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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id k11si11361682pga.340.2017.12.12.02.38.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=akSdxwqz; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C195C220EE119; Tue, 12 Dec 2017 02:33:52 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA6BC220EE115 for ; Tue, 12 Dec 2017 02:33:51 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id x49so20562434wrb.13 for ; Tue, 12 Dec 2017 02:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=akSdxwqzUugnEqQbLOIMDNr9IKV2vo+VCWY8nWoczdD+bw6UNSQvZ3tRgfrRT/11e8 0Aq9mYkIeb9bN5HoclRq4eoFitAazUhXdq+2JEBiRLYofY03TXVr6vPonBX138rQJRGx Q6uWer02cRAIuczaerN3dWH4bRDtLUqOypZ5o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PU7ms/RrRVJMKOJrexx0EuB55mzzfnUUIroAJi4CSqY=; b=Gjkk9oMZ2Ydk7Z+animfgB2gI04Om+TfsW+OLAow67xdYqmZFVX/c3w8ubm0n7Yfpr 12uFGG84LHHirYcC/Y/7BxkOpNuIVXXi/CYMrHZwan3fd5Y+FSSFDTCSrv+YZVpDW2ev vu1UBAWWmel6pWxrpRU2NKHMGWkSZVgoGzYPUoq1vn+YriuPXU3ngaBi7u6b4zvMiFbk myX8pt8kKZwLc7LUXU1rnXagAbMbbl8NjVScRQ6EF2cFMF4RnkKcUWPzsomWb5WAvCc3 HKiEt94PZ1u1PA4vU8P8aPot8mYiNv/PbGFRXpwS38R9mAhBRlcII8EUf2e8HnoUNXPq /nIA== X-Gm-Message-State: AKGB3mIDoWq+QY6dVTK+mZY6oovHoIy2sBqBwShiQqBrtUm/AMsOhOwV pd9cGr66ZNj1i+Eok97H8rFCh0zo4CA= X-Received: by 10.223.175.49 with SMTP id z46mr3387635wrc.12.1513075108814; Tue, 12 Dec 2017 02:38:28 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:27 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:05 +0000 Message-Id: <20171212103807.18836-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 6/8] Silicon/SynQuacerEvalBoard: enable PCI #0 only when card is detected X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The EVB does not boot if PCI RC #0 has no card inserted, and will hang in the PCIe initialization code. So let's check the presence detect GPIO, and only enable PCI RC #0 if it is asserted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 70 ++++++++++++++------ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 1 + 4 files changed, 59 insertions(+), 21 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index c71425664bdc..917632c2b4c1 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -374,6 +374,10 @@ [PcdsFixedAtBuild.common] # set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + # On the EVB, PCIe RC #0 should not be enabled from software if no card + # was inserted, or the boot will hang. + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|15 + !if $(BUILD_NUMBER) > 1 gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(BUILD_NUMBER)" !endif @@ -395,6 +399,9 @@ [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF + # enable RC #1 only by default, RC #0 will be enabled if an endpoint is detected + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x2 + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c index e4aec8b09169..7c529a22c6ef 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -24,7 +24,10 @@ #include #include -#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8 +#define GPIO_NOT_IMPLEMENTED MAX_UINT8 + +#define CLEAR_SETTINGS_GPIO_ASSERTED 1 +#define PCIE_GPIO_CARD_PRESENT 0 STATIC CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); @@ -100,6 +103,35 @@ STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescriptor = { &mDramInfoPpi }; +STATIC +EFI_STATUS +ReadGpioInput ( + IN EMBEDDED_GPIO_PPI *Gpio, + IN UINT8 Pin, + OUT UINTN *Value + ) +{ + EFI_STATUS Status; + + if (Pin == GPIO_NOT_IMPLEMENTED) { + return EFI_NOT_FOUND; + } + + Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to set GPIO %d as input - %r\n", + __FUNCTION__, Pin, Status)); + return Status; + } + + Status = Gpio->Get (Gpio, Pin, Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to get GPIO %d state - %r\n", + __FUNCTION__, Pin, Status)); + } + return Status; +} + EFI_STATUS EFIAPI PlatformPeim ( @@ -109,30 +141,26 @@ PlatformPeim ( EMBEDDED_GPIO_PPI *Gpio; EFI_STATUS Status; UINTN Value; - UINT8 Pin; ASSERT (mDramInfo->NumRegions > 0); - Pin = FixedPcdGet8 (PcdClearSettingsGpioPin); - if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) { - Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, - (VOID **)&Gpio); - ASSERT_EFI_ERROR (Status); + Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL, + (VOID **)&Gpio); + ASSERT_EFI_ERROR (Status); - Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n", - __FUNCTION__, Status)); - } else { - Status = Gpio->Get (Gpio, Pin, &Value); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n", - __FUNCTION__, Status)); - } else if (Value > 0) { - DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); - PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); - } - } + Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdClearSettingsGpioPin), &Value); + if (!EFI_ERROR (Status) && Value == CLEAR_SETTINGS_GPIO_ASSERTED) { + DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__)); + PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS); + } + + Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdPcie0PresenceDetectGpioPin), + &Value); + if (!EFI_ERROR (Status) && Value == PCIE_GPIO_CARD_PRESENT) { + DEBUG ((DEBUG_INFO, + "%a: card detected in PCIe RC #0, enabling\n", __FUNCTION__)); + Status = PcdSet8S (PcdPcieEnableMask, PcdGet8 (PcdPcieEnableMask) | BIT0); + ASSERT_EFI_ERROR (Status); } // diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf index a6501fb205e1..eb6a5bf9ac1a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf @@ -43,6 +43,7 @@ [FixedPcd] gArmTokenSpaceGuid.PcdFvSize gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin gSynQuacerTokenSpaceGuid.PcdDramInfoBase + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin [Ppis] gEdkiiEmbeddedGpioPpiGuid ## CONSUMES @@ -51,6 +52,7 @@ [Ppis] [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask [Depex] gEdkiiEmbeddedGpioPpiGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 2e18cb33346d..a21f12b5bc32 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -36,6 +36,7 @@ [PcdsFixedAtBuild] # GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|0xFF|UINT8|0x00000006 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005