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[198.145.21.10]) by mx.google.com with ESMTPS id c196-v6si405423pga.494.2018.05.15.10.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fbJIJPfB; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3BA6C2034862C; Tue, 15 May 2018 10:37:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B74F2209603DA for ; Tue, 15 May 2018 10:37:47 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id o4-v6so1020795wrm.0 for ; Tue, 15 May 2018 10:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YeTrVhslB5MjKv/QGsjKNe9ONYfEeO/pFgzZU8S9vvA=; b=fbJIJPfBQvpBHSQxbgyaQePINAr0maKcZCPiI9SdP+1ls1xk22fzID6Y3W+BHsJbFq z7jTvX9krQr873DOV8S3mPRSXU2KzIqRjj1/adL8Dc6oYV9UpNFMUytExSyv7+2QYjX1 Ce7uUCU608vJdGCAnzjvII2O1TnH9zHdy5+O8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YeTrVhslB5MjKv/QGsjKNe9ONYfEeO/pFgzZU8S9vvA=; b=MzEt9vP9mZXhBl1yAEoZOXsuif1T75lOhJd8BT69s8nzEID7USMb5b7Sq+A8Jw2Dad 3pWOD5red/suDNgtNV/HzZN1DvQZIC7rcQ8/f203ciepcZ0cUy33yF1SSpA3vVVmfswF IkDMPnRVJWcAx6eGofZjx7Yq+eGQi4ZuuQcr+qFujG9ymasO3cjUTs0eNUSOLESjLVPD AZuqUhn9ssBgM+j0p5gKbXW8xFnXP4uMXQ+Wx3sAAZxhYp+372QKz3ikX2na/lgEv2Cb UGOwioIxBynvzQQm1LqqMjl7gRMOLcyhALHwazBcOG7sjdVRHA3ywtgA3vk739Kv8e+f fXkA== X-Gm-Message-State: ALKqPwfhYA8nixUGNWqdJ0VXKfZ+taRJ2WNoIjTqQqHyW2oC63zCd4hz TB5xwZbOy48eOPyx9vqciBGhGPD+KiU= X-Received: by 2002:adf:dd03:: with SMTP id a3-v6mr12401057wrm.0.1526405865806; Tue, 15 May 2018 10:37:45 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:45 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:32 +0200 Message-Id: <20180515173736.29639-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/5] Silicon/AMD/Styx: make ARM-TF and PSCI dependencies unconditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The Styx platform theoretically supports running in an environment where no ARM Trusted Firmware is running in EL3 and PSCI is not implemented. This is not a configuration that we aim to support, and so let's remove the code that implements this, especially because it is essentially dead code and unmaintained. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 7 -- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 1 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 7 -- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 2 - Silicon/AMD/Styx/AcpiTables/Fadt.c | 5 +- Silicon/AMD/Styx/AmdStyx.dec | 5 -- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c | 70 -------------------- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf | 6 -- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf | 1 - Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 58 ++++++++-------- Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 1 - Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf | 3 - Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 - 13 files changed, 29 insertions(+), 139 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 348828e18d44..86061cd4606f 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -19,7 +19,6 @@ [Defines] DEFINE DO_XGBE = 1 DEFINE NUM_CORES = 8 -DEFINE DO_PSCI = 1 DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -457,12 +456,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 -!if $(DO_PSCI) - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE -!endif - !if $(DO_ISCP) gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE !else diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 007c36412b93..80b096ba5587 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -431,7 +431,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE # SMBIOS 3.0 only diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 3f4c7c8a3eef..72eb943a8bfd 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -18,7 +18,6 @@ [Defines] DEFINE NUM_CORES = 4 -DEFINE DO_PSCI = 1 DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -428,12 +427,6 @@ [PcdsFixedAtBuild.common] ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -!if $(DO_PSCI) - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE -!endif - !if $(DO_ISCP) gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE !else diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index 057c52512e4e..bff5be4673a4 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -82,8 +82,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion gAmdStyxTokenSpaceGuid.PcdSata1PortCount diff --git a/Silicon/AMD/Styx/AcpiTables/Fadt.c b/Silicon/AMD/Styx/AcpiTables/Fadt.c index bcbff3798883..bdf88a9c8e32 100644 --- a/Silicon/AMD/Styx/AcpiTables/Fadt.c +++ b/Silicon/AMD/Styx/AcpiTables/Fadt.c @@ -73,7 +73,7 @@ STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = { FADT_FLAGS, // UINT32 Flags NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - 0, // UINT16 ArmBootArch + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch 1, // UINT8 MinorVersion 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt @@ -96,9 +96,6 @@ FadtTable ( VOID ) { - if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) { - AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT; - } return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt; } diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index 0d7e82f2d768..cffe1cafde8b 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -89,17 +89,12 @@ [PcdsFixedAtBuild] gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV|369|UINT32|0x00050008 # Trusted-Firmware - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport|TRUE|BOOLEAN|0x00060000 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002 # ISCP gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000 - # PSCI - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE|BOOLEAN|0x00080000 - gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext|0|UINT64|0x00080001 - # Cores Per cluster gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000 diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c index fd5bb96f7c98..e713d5581925 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -33,7 +33,6 @@ STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 }; -STATIC AMD_MP_BOOT_PROTOCOL mAmdMpBootProtocol = { 0 }; STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 }; @@ -56,13 +55,6 @@ AmdStyxGetMpParkingBase ( OUT UINTN *MpParkingSize ); -STATIC -VOID -AmdStyxParkSecondaryCore ( - ARM_CORE_INFO *ArmCoreInfo, - EFI_PHYSICAL_ADDRESS SecondaryEntry - ); - #pragma pack(push, 1) typedef struct _PMU_INFO { @@ -94,8 +86,6 @@ PlatInitDxeEntryPoint ( ) { EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; ARM_CORE_INFO *ArmCoreInfoTable; UINTN ArmCoreCount; EFI_HANDLE Handle = NULL; @@ -120,39 +110,6 @@ PlatInitDxeEntryPoint ( ); ASSERT_EFI_ERROR (Status); - // Install MP-Boot Protocol - if (!FixedPcdGetBool (PcdPsciOsSupport) && - FixedPcdGetBool (PcdTrustedFWSupport)) { - // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory - MpParkingBase = 0; - MpParkingSize = ArmCoreCount * SIZE_4KB; - Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (MpParkingSize), - &MpParkingBase); - if (EFI_ERROR (Status) || MpParkingBase == 0) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase.")); - } else { - mAmdMpBootInfo.MpParkingBase = MpParkingBase; - mAmdMpBootInfo.MpParkingSize = MpParkingSize; - mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable; - mAmdMpBootInfo.ArmCoreCount = ArmCoreCount; - - mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore; - mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo; - - Status = gBS->InstallProtocolInterface ( - &Handle, - &gAmdMpBootProtocolGuid, - EFI_NATIVE_INTERFACE, - (VOID *)&mAmdMpBootProtocol - ); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol.")); - gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize)); - } - } - } - return Status; } @@ -208,30 +165,3 @@ AmdStyxGetMpParkingBase ( *MpParkingSize = mAmdMpBootInfo.MpParkingBase; return mAmdMpBootInfo.MpParkingBase; } - - -STATIC -VOID -AmdStyxParkSecondaryCore ( - ARM_CORE_INFO *ArmCoreInfo, - EFI_PHYSICAL_ADDRESS SecondaryEntry - ) -{ - ARM_SMC_ARGS SmcRegs = {0}; - UINTN MpId; - - MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId); - - SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64; - SmcRegs.Arg1 = MpId; - SmcRegs.Arg2 = SecondaryEntry; - SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext); - ArmCallSmc (&SmcRegs); - - if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS || - SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) { - DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId)); - } else { - DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId)); - } -} diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf index 15f46be651b7..1ebde2723355 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -51,12 +51,6 @@ [Guids] [Protocols] gAmdMpCoreInfoProtocolGuid ## PRODUCER - gAmdMpBootProtocolGuid ## PRODUCER - -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport [Depex] TRUE diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf index 9f141946aea5..ccc079bebab2 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -68,7 +68,6 @@ [Pcd] [FixedPcd] gAmdStyxTokenSpaceGuid.PcdIscpSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdCpuIdRegister [Depex] diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 70821d1b120b..67f90efdcb3f 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -127,36 +127,34 @@ MemoryPeim ( Base = PcdGet64 (PcdSystemMemoryBase); Size = PcdGet64 (PcdSystemMemorySize); - if (FixedPcdGetBool (PcdTrustedFWSupport)) { - - // - // For now, we assume that the trusted firmware region is at the base of - // system memory, since that is much easier to deal with. - // - ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase)); - - Base += PcdGet64 (PcdTrustedFWMemorySize); - Size -= PcdGet64 (PcdTrustedFWMemorySize); - - // Reserved Trusted Firmware region - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ( EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED ), - PcdGet64 (PcdTrustedFWMemoryBase), - PcdGet64 (PcdTrustedFWMemorySize) - ); - - BuildMemoryAllocationHob ( - PcdGet64 (PcdTrustedFWMemoryBase), - PcdGet64 (PcdTrustedFWMemorySize), - EfiReservedMemoryType - ); - } + + // + // For now, we assume that the trusted firmware region is at the base of + // system memory, since that is much easier to deal with. + // + ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase)); + + Base += PcdGet64 (PcdTrustedFWMemorySize); + Size -= PcdGet64 (PcdTrustedFWMemorySize); + + // Reserved Trusted Firmware region + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED ), + PcdGet64 (PcdTrustedFWMemoryBase), + PcdGet64 (PcdTrustedFWMemorySize) + ); + + BuildMemoryAllocationHob ( + PcdGet64 (PcdTrustedFWMemoryBase), + PcdGet64 (PcdTrustedFWMemorySize), + EfiReservedMemoryType + ); // Declare system memory BuildResourceDescriptorHob ( diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index 724d71645d5a..d17e6c26feb5 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -69,7 +69,6 @@ [FixedPcd] gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize diff --git a/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf index 5a99fd79384a..d9faf3abb09a 100644 --- a/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf +++ b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf @@ -42,6 +42,3 @@ [LibraryClasses] PcdLib BaseLib ArmSmcLib - -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index fc8b25c92873..3f36799f5df1 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -51,8 +51,6 @@ [Pcd] [FixedPcd] gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Guids]