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[198.145.21.10]) by mx.google.com with ESMTPS id 33-v6si497340plf.308.2018.05.15.10.37.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDxPeqmp; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6675520348635; Tue, 15 May 2018 10:37:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1E197209603D9 for ; Tue, 15 May 2018 10:37:49 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id y15-v6so987177wrg.11 for ; Tue, 15 May 2018 10:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RGF7sqd+567yVouByADXvhOOhLGBBsdPB2axphSHZ80=; b=aDxPeqmpS/TVmdlXz2T0ub3BN1qqGq5Q7pXPENDPH24ERrkO9ghnFK2lYkwefrS3SG FvBWRMP6ZnoTz75Lp9bf4+R2n/aIOWLD4UpjMdXOUdSOrgnEyZmejsV4KJBWjBvbwHAV 5JAGMSe5hOTHMF+jXBE/UY02O9fVAATDZbjVo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RGF7sqd+567yVouByADXvhOOhLGBBsdPB2axphSHZ80=; b=Lq0Etd91BUavYH3H69dUzY9vPPKyFCX1Nj7QsVelVIo4Xk4hnayN82Lg9BADPgK2PO vI4I7vjwffM6uQd8/T6NZwAPPcguoUyvUAsl6pE3LMosyt1TJM9DGfogjlw4gyajF7cm w44sytDDHWXKrCw3d0O6bC+x7VvVJX+AIPZ3h8xV4EMLU7jHLIZr3uvkHtRK833kwcF4 ld2FzwsdA7Qk9mSmPfkSOF0Sv/nwjFKrPn/Tu1nXi54i7JYvtSJQav6qax59nozjx1yE yvcz67FkNBN1T6Z55UaxcNsb/1Vb4qRXGYqhIybUdY1G86ft07TNU8MCDeUJ3G0vr7ib Iz7w== X-Gm-Message-State: ALKqPwdIlnIEIWbhf+1u+f0vC78HnCuZYfvlPQHaeUepaom1XCSIH5Z0 qkejKIvYW4Gd4dCMExYUy5svB0/ojc0= X-Received: by 2002:adf:88b6:: with SMTP id f51-v6mr10617935wrf.55.1526405867871; Tue, 15 May 2018 10:37:47 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:33 +0200 Message-Id: <20180515173736.29639-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/5] Silicon/AMD/Styx: remove MpBootDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" MpBootDxe implements support for the ACPI Parking Protocol and the DT based spintable protocol to bring up secondaries, neither of which are recommended on systems implementing EL3, are not enabled in the default build configuration of the platforms that include it and is therefore essentially dead code. (Note that this driver DEPEXes on a protocol that never gets installed when building this platform with ARM-TF and PSCI support, which we now do unconditionally) So let's remove it from the platform descriptions that refer to it, and remove the code altogether as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 5 - Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 5 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 5 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 5 - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c | 170 -------------------- Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf | 53 ------ Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S | 87 ---------- 7 files changed, 330 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 86061cd4606f..26b91ca88a2c 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -629,11 +629,6 @@ [Components.common] MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # AHCI Support # diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index 541d65ef753e..1ed32f68ef9d 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -222,11 +222,6 @@ [FV.FvMain] INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # SMBIOS Support # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 72eb943a8bfd..8d50d78c30cd 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -563,11 +563,6 @@ [Components.common] MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # AHCI Support # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index 38344fa406a3..e23533d1bddb 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -220,11 +220,6 @@ [FV.FvMain] INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # SMBIOS Support # diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c deleted file mode 100644 index bd7244648ab0..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c +++ /dev/null @@ -1,170 +0,0 @@ -/** @file - - Copyright (c) 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - -/* These externs are used to relocate our Pen code into pre-allocated memory */ -extern VOID *SecondariesPenStart; -extern VOID *SecondariesPenEnd; -extern UINTN *AsmParkingBase; -extern UINTN *AsmMailboxBase; - - -STATIC -EFI_PHYSICAL_ADDRESS -ConfigurePen ( - IN EFI_PHYSICAL_ADDRESS MpParkingBase, - IN UINTN MpParkingSize, - IN ARM_CORE_INFO *ArmCoreInfoTable, - IN UINTN ArmCoreCount - ) -{ - EFI_PHYSICAL_ADDRESS PenBase; - UINTN PenSize; - UINTN MailboxBase; - UINTN CoreNum; - UINTN CoreMailbox; - UINTN CoreParking; - - // - // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#. - // For details, refer to the "Multi-processor Startup for ARM Platforms" document: - // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx - // - PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64)); - PenSize = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart; - - // Relocate the Pen code - CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize); - - // Put spin-table mailboxes below the pen code so we know where they are relative to code. - // Make sure this is 8 byte aligned. - MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart); - if (MailboxBase % sizeof(UINT64) != 0) { - MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64); - } - - // Update variables used in the Pen code - *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase; - *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase; - - for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) { - // Clear the jump address at spin-table slot - CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64); - *((UINTN*)(CoreMailbox)) = 0x0; - - // Clear the jump address and set Core# at mp-parking slot - CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB; - *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0; - *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum; - - // Update table entry to be consumed by FDT parser - ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox; - } - - // flush the cache before launching secondary cores - WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize); - - return PenBase; -} - - -EFI_STATUS -EFIAPI -MpBootDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - AMD_MP_BOOT_PROTOCOL *MpBootProtocol; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; - ARM_CORE_INFO *ArmCoreInfoTable; - UINTN ArmCoreCount; - UINTN CoreNum; - EFI_PHYSICAL_ADDRESS PenBase; - - DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n")); - - MpBootProtocol = NULL; - Status = gBS->LocateProtocol ( - &gAmdMpBootProtocolGuid, - NULL, - (VOID **)&MpBootProtocol - ); - if (EFI_ERROR (Status) || MpBootProtocol == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n")); - return EFI_UNSUPPORTED; - } - - if ((VOID *)MpBootProtocol->MpBootInfo == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n")); - return EFI_UNSUPPORTED; - } - - MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase; - if ((VOID *)MpParkingBase == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n")); - return EFI_UNSUPPORTED; - } - if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n")); - return EFI_UNSUPPORTED; - } - - ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable; - if (ArmCoreInfoTable == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n")); - return EFI_UNSUPPORTED; - } - - ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount; - if (ArmCoreCount < 2) { - DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount)); - return EFI_UNSUPPORTED; - } - - MpParkingSize = ArmCoreCount * SIZE_4KB; - if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n", - MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount)); - return EFI_UNSUPPORTED; - } - - if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n")); - return EFI_UNSUPPORTED; - } - - // Move secondary cores to our new Pen - PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount); - for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) { - MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase); - } - - return EFI_SUCCESS; -} - - diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf deleted file mode 100644 index ec63cd36e804..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf +++ /dev/null @@ -1,53 +0,0 @@ -#/* @file -# -# Copyright (c) 2016, AMD Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = MpBootDxe - FILE_GUID = ff3f9c9b-6d36-4787-9144-6b22acba5e9b - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = MpBootDxeEntryPoint - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = AARCH64 -# -# - -[Sources.common] - MpBootDxe.c - -[Sources.AARCH64] - MpBootHelper.S - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec - Silicon/AMD/Styx/AmdStyx.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - CacheMaintenanceLib - BaseMemoryLib - DebugLib - -[Protocols] - gAmdMpBootProtocolGuid ## CONSUMED - -[Depex] - gAmdMpBootProtocolGuid diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S deleted file mode 100644 index c16cc59a1e5e..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S +++ /dev/null @@ -1,87 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//** -// Derived from: -// ArmPkg/Library/BdsLib/AArch64/BdsLinuxLoaderHelper.S -// -//** - -/* Secondary core pens for AArch64 Linux booting. - - This code is placed in Linux kernel memory and marked reserved. UEFI ensures - that the secondary cores get to this pen and the kernel can then start the - cores from here. - NOTE: This code must be self-contained. -*/ - -#include - -.text -.align 3 - -GCC_ASM_EXPORT(SecondariesPenStart) -ASM_GLOBAL SecondariesPenEnd - -ASM_PFX(SecondariesPenStart): - // Registers x0-x3 are reserved for future use and should be set to zero. - mov x0, xzr - mov x1, xzr - mov x2, xzr - mov x3, xzr - - mrs x4, mpidr_el1 // Get MPCore register - and x5, x4, #ARM_CORE_MASK // Get core number - and x4, x4, #ARM_CLUSTER_MASK // Get cluster number - - add x4, x5, x4, LSR #7 // Add scaled cluster number to core number - mov x6, x4 // Save a copy to compute mp-parking offset - - ldr x5, AsmMailboxBase // Get mailbox addr relative to PC - lsl x4, x4, 3 // Add 8-byte offset for this core - add x4, x4, x5 // - - ldr x5, AsmParkingBase // Get mp-parking addr relative to PC - lsl x6, x6, 12 // Add 4K-byte offset for this core - add x6, x6, x5 // - - mov x5, 1 // Get mp-parking id# at 2K offset - lsl x5, x5, 11 // - add x5, x5, x6 // - ldr x10, [x5] // - -1: ldr x5, [x4] // Load jump-addr from spin-table mailbox - cmp xzr, x5 // Has the value been set? - b.ne 4f // If so, break out of loop - - ldr x5, [x6] // Load mp-parking id# - cmp w10, w5 // Is it my id? - b.ne 2f // If not, continue polling - - ldr x5, [x6, 8] // Load jump-addr from mp-parking - cmp xzr, x5 // Has the value been set? - b.ne 3f // If so, break out of loop - -2: wfe // Wait a bit - b 1b // Wait over, check again - -3: str xzr, [x6, 8] // Clear to acknowledge - mov x0, x6 // Return mp-parking address -4: br x5 // Jump to new addr - -.align 3 // Make sure the variable below is 8 byte aligned. - .global AsmParkingBase -AsmParkingBase: .xword 0xdeaddeadbeefbeef - .global AsmMailboxBase -AsmMailboxBase: .xword 0xdeaddeadbeefbeef - -SecondariesPenEnd: