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[198.145.21.10]) by mx.google.com with ESMTPS id 95-v6si36328983plc.383.2018.05.30.11.19.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dvsDysyT; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A2981210C998E; Wed, 30 May 2018 11:19:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1AEBE210C997A for ; Wed, 30 May 2018 11:19:37 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id i12-v6so30496480wrc.4 for ; Wed, 30 May 2018 11:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=dvsDysyT6UTseVQ853f0Oo+JTyKhNRbxXAqdBa/NmbszfeH7uaJdazTvmL0pOWVoOL nHuoXdv0BYLiIDkqliPQ7V/ecbuvNzGTSDF9mTXFmxjeMTjXAlCwDLbJQzzZCjed5jN5 2dEixtjNZGp/nUMGfGDBJVlJ/MYo13IajO0Bc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=ns1jsUWL4ZVHzE0GQ7uJseCJvlVIXkJVXY6Irf82TnUE9nMqSzKWbTC3JG3mpFMsYq Es+StDfiI1UXV5YU/r/x/pZeorAD2k2xEt8LyKCXKTFGO5gYWbwd7/r22LB4QIVC66FK kS3WsgNOPG6UkG3awup1VzDZkTUMmn1tNGxk/EkUoI6nTWJ3QxLpYTFbZVniL66Lucyo oPjt7K6/MC4r6PPCMU2QU+jRU0QOlZPwd61I+4h7cX2d2Ar60LfNviAHySUSHKOxXP8k BUZdseAPAeivR3LVvAt+U4Qh41cN6Jgy7IXWDg9ESPeNKqDhQ7oy7IWYwztke8q0BYBE Vygg== X-Gm-Message-State: ALKqPwdYpwHxR+E32WxGSdmYSw+pS9Y2NTGYzsdf1zzyWr4NcEGTkcqb wQ8xtWD2ccvkB+opt9XeYjW9ptl225s= X-Received: by 2002:adf:9f4a:: with SMTP id f10-v6mr2895278wrg.216.1527704375304; Wed, 30 May 2018 11:19:35 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:34 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:27 +0200 Message-Id: <20180530181929.5066-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Masahisa KOJIMA The current revision of SC2A11 contains PCIe bus issue. In MRd transaction, 1st/Last DW BE fields are not correctly set by hardware. As a workaround, set TH bit and specify MSG_CODE in iATU. With this setup, the value specified as MSG_CODE is set to the 1st/Last DW BE fields and PCIe controller can emit the correct MRd TLP header. Same workaround was already included for MMIO32 region, MMIO64 region also requires this workaround. Some deivices, such as Samsong SSD 970 EVO, do not work without this modification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Masahisa KOJIMA --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e4679543cc66..227f9a725ce8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -359,8 +359,9 @@ PciInitControllerPost ( RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); } // enable link