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[198.145.21.10]) by mx.google.com with ESMTPS id w24si12144722plp.304.2018.12.11.07.02.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YXrX0cWY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0142821199B3E; Tue, 11 Dec 2018 07:02:47 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3548021199539 for ; Tue, 11 Dec 2018 07:02:46 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id y1so2534798wmi.3 for ; Tue, 11 Dec 2018 07:02:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9q9xw+RZi0Rq4s3x7ACklVnt+F41m4B82wsORlKqTHY=; b=YXrX0cWYZ48TTOU+UYZuondzNdCMcaI816zwUtGdzaLxVqW6oSvT3yz1fKWXMSfmib Q/6pkurE2AOKniYWzXDGpOkmO8+iF1VcDycgg8x8cXzLFsGnsNwSSwb4ku1BS1w6tM4y Ocv/vgtNJYsXFo3P807OeeRoBhy8n2yl8Hvuc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9q9xw+RZi0Rq4s3x7ACklVnt+F41m4B82wsORlKqTHY=; b=encjZ3nX+cmkTT1ZyX/6VCGLczzmixB0wj1RuyrUrZYSkADdbr0EIuIs38hvF/q4cZ C2ru9kxklJOe/O1SJr79ey0vaQjAfo9pPz5XJYhOFt/33csFLEOgEZABxHk4GxUgXTn/ VHQOmnODY8RxHVVH4Cha7v83WlVspjdSW92weJWEwXSGbnN3tYlrw/Jy+JnTbkR5HNoC ds2p2B0Oa1JEYBfFiTQRmZn4ACWn8XYAGVWYrJrF/nNhbSWRfmF5oK6NzwVBm+mAr62Q bWTlmI5nm66njce/XyaT7oE29arynknFT/IGm+A/P+CwJY27/m7QIAvQEWEB8578B7e5 aX+A== X-Gm-Message-State: AA+aEWYBo4wbYizvMysyT1BFBZ07YFI8IBtMWImWaCiFWHiwAYwHHTE9 ru0J8QrGdF4CX8zUpIG9Jmlmz6wgobHlJw== X-Received: by 2002:a1c:8acd:: with SMTP id m196mr2716604wmd.120.1544540564297; Tue, 11 Dec 2018 07:02:44 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:42 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:33 +0100 Message-Id: <20181211150237.32275-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/6] Silicon/Styx: drop ARM_CPU_AARCH64 define X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The define ARM_CPU_AARCH64 is only tested once, in the SMBIOS driver, to decide whether to emit 'v8' or 'v7' as processor architecture. However, this platform has no 32-bit addressable DRAM, and so it cannot be built or executed in 32-bit mode anyway, making the test rather pointless. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 4 ++-- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 4 ++-- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 4 ++-- Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 4 ---- 4 files changed, 6 insertions(+), 10 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 3b9d70de2751..9172c82fdeba 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -268,8 +268,8 @@ DEFINE DO_CAPSULE = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 29e740695366..f556591b9e25 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -260,8 +260,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index f342cf82d251..5abf1d52f916 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -258,8 +258,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index bcb6e020a5fd..8fe806c18ac3 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -309,11 +309,7 @@ STATIC SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { STATIC CHAR8 CONST * CONST mProcessorInfoType4Strings[] = { "Socket", "ARM", -#ifdef ARM_CPU_AARCH64 "v8", -#else - "v7", -#endif "1.0", "1.0", "1.0",