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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id r58si1039920qtr.208.2018.03.19.23.50.07 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 19 Mar 2018 23:50:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@cisco.com header.s=iport header.b=CyJdjaIh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=cisco.com Received: from localhost ([::1]:46483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyB5y-0004pv-T0 for patch@linaro.org; Tue, 20 Mar 2018 02:50:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32982) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyAWN-00056h-1t for qemu-devel@nongnu.org; Tue, 20 Mar 2018 02:13:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eyAWM-0003WK-25 for qemu-devel@nongnu.org; Tue, 20 Mar 2018 02:13:19 -0400 Received: from alln-iport-7.cisco.com ([173.37.142.94]:17023) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1eyAWG-0003PB-Uh; Tue, 20 Mar 2018 02:13:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=@cisco.com; l=2177; q=dns/txt; s=iport; t=1521526392; x=1522735992; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RZ4Lsc4IfHUkBkgkiIS4Hj46WC1aCZ3eCG8wp2jxxyo=; b=CyJdjaIhX8myDQTZn5cvrzTO2dts+rsYHek4pk1XKdPqkaQFX3a+1GAi +lHRsn8m6djFZ8haZZLhigX1TYLc9+bMCWoOHI+/tiU31mk8Vu9QieQ1o UWA3FuD5+Si/5mbBB2SbtfGEBwDO9diSRTGqV5/p+9l7pEGSEkGCkmW5I g=; X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DkAwBzpbBa/5tdJa1eGQEBAQEBAQEBAQEBAQcBAQEBAYNQgVgog12YGoMZlhQLhRGDRiE4FAECAQEBAQEBAmsohU8ECwFGNQImAnKFGqhagWw6iGCCDoEMhCeCFYYWhgWCPIJhA40pixIJjzYCjTABMI9iAhETAYEqNSGBUk0jFYJ9gjIbjh0hIDSQYgEBAQ X-IronPort-AV: E=Sophos;i="5.48,333,1517875200"; d="scan'208";a="85963202" Received: from rcdn-core-4.cisco.com ([173.37.93.155]) by alln-iport-7.cisco.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Mar 2018 06:13:10 +0000 Received: from kamensky-w541.cisco.com ([10.24.8.216]) (authenticated bits=0) by rcdn-core-4.cisco.com (8.14.5/8.14.5) with ESMTP id w2K6CnoM006241 (version=TLSv1/SSLv3 cipher=AES128-SHA256 bits=128 verify=NO); Tue, 20 Mar 2018 06:13:09 GMT From: Victor Kamensky To: qemu-devel@nongnu.org Date: Mon, 19 Mar 2018 23:12:48 -0700 Message-Id: <1521526368-1996-1-git-send-email-kamensky@cisco.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Authenticated-User: kamensky@cisco.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 173.37.142.94 X-Mailman-Approved-At: Tue, 20 Mar 2018 02:47:25 -0400 Subject: [Qemu-devel] [PATCH] arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXIT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In OE project 4.15 linux kernel boot hang was observed under single cpu aarch64 qemu. Kernel code was in a loop waiting for vtimer arrival, spinning in TC generated blocks, while interrupt was pending unprocessed. This happened because when qemu tried to handle vtimer interrupt target had interrupts disabled, as result flag indicating TCG exit, cpu->icount_decr.u16.high, was cleared but arm_cpu_exec_interrupt function did not call arm_cpu_do_interrupt to process interrupt. Latter when target reenabled interrupts, it happened without exit into main loop, so following code that waited for result of interrupt execution run in infinite loop. To solve the problem instructions that operate on CPU sys state (i.e enable/disable interrupt), and marked as DISAS_UPDATE, should be considered as DISAS_EXIT variant, and should be forced to exit back to main loop so qemu will have a chance processing pending CPU state updates, including pending interrupts. This change brings consistency with how DISAS_UPDATE is treated in aarch32 case. CC: Peter Maydell CC: Alex Bennée CC: qemu-stable@nongnu.org Suggested-by: Peter Maydell Signed-off-by: Victor Kamensky Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 31ff047..327513e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13378,12 +13378,12 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); /* fall through */ - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(); - break; case DISAS_EXIT: tcg_gen_exit_tb(0); break; + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_NORETURN: case DISAS_SWI: break;