From patchwork Mon Mar 26 05:42:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Victor Kamensky \(kamensky\)" X-Patchwork-Id: 132395 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3430525ljb; Sun, 25 Mar 2018 22:42:27 -0700 (PDT) X-Google-Smtp-Source: AG47ELuo9ZQibdp5O8vh1JB6Ivr5vXpiMY9fYifeeq+vyQim6CyXl3syZDotDpdwCez/DejyttWm X-Received: by 10.98.170.13 with SMTP id e13mr19631014pff.137.1522042947628; Sun, 25 Mar 2018 22:42:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522042947; cv=none; d=google.com; s=arc-20160816; b=J5ZKLhLoPPxNPbL1jtix26GVD2mknXrRmOkyUxLTQJyhr+ZZWQbGrkL54oGE6wjzza BRj0A6QjWkZAvj2bEki7LZ9TKJdiDEig1/SKWf5fDQxoDKhSBJoHH5+mfpxljGujevdF CB/Ejht+mLE3sdQQnkxQW+gKwDD4/Qr8qCbt+K3WrSDI9k5BBruu5mOd0iJXJjD5NsWP aU9P9DAmBY7byDHXmTP49JRdg25tY/kFepeKZtLNkQ9WdKwG4Ri9R4bQkieZgar7OHd8 6mh5yT0U2O8UI+f7RqvGw3CDWKPPviVqv9H24BVJ5RHxCCGjECl0xSDuAzCgp3S2Sv4q pACA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :mime-version:message-id:date:to:from:dkim-signature:delivered-to :arc-authentication-results; bh=/O2VruWOeQNBYmZNVKf6CyneIo4IAZjKdVGQdU86ahM=; b=sYW8fiBy+JVhOC6umIjGgHAD/O/d0+MDyTnBmswqM7Yuwgh8VWrGVcbBClOaHOIoAg DYDQLUJzLBZ78UrcEEO7Dy3OVmatUY8kXLildoaTEHnO97EaqH4mvxVaKX+SSBMVcSKp hrdU4qVrdkShxqWxw7R7AIwFqHywhC/5+gErT/Fremi807SQOj8qXYN5th4lFG/5cjMI 1rWwF26nf24arwdTLlZKWG9T/B1BOAKhN6aCmQA4qyx32j82LZlWAMPQOQHQfH6t9WbO wwHj/ldVBnwQx7l+zi0/JCjA5D1S3O+ohtSfl0xGRHdkYGZb86eAIPma+DZxoUqQ+Hw+ a0Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@cisco.com header.s=iport header.b=KvPk2LtJ; spf=pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) smtp.mailfrom=openembedded-core-bounces@lists.openembedded.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=cisco.com Return-Path: Received: from mail.openembedded.org (mail.openembedded.org. [140.211.169.62]) by mx.google.com with ESMTP id t2-v6si15055621plj.651.2018.03.25.22.42.26; Sun, 25 Mar 2018 22:42:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) client-ip=140.211.169.62; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@cisco.com header.s=iport header.b=KvPk2LtJ; spf=pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) smtp.mailfrom=openembedded-core-bounces@lists.openembedded.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=cisco.com Received: from layers.openembedded.org (localhost [127.0.0.1]) by mail.openembedded.org (Postfix) with ESMTP id F01F378596; Mon, 26 Mar 2018 05:42:21 +0000 (UTC) X-Original-To: openembedded-core@lists.openembedded.org Delivered-To: openembedded-core@lists.openembedded.org Received: from rcdn-iport-3.cisco.com (rcdn-iport-3.cisco.com [173.37.86.74]) by mail.openembedded.org (Postfix) with ESMTP id 0346A78226 for ; Mon, 26 Mar 2018 05:42:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=cisco.com; i=@cisco.com; l=3681; q=dns/txt; s=iport; t=1522042941; x=1523252541; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DjPou3zojY6MrIk6CduBDIdnBS+MxorGSYPw5Re6FVE=; b=KvPk2LtJvw5ycQKPsfyFb59CIoESN1JbnLWH3r+Q2+Soj0WG21Irtd48 FpzVdKM5dheo/kPgjzLVq7zPFpxl3OQW0X4BPg5G0xc8xKzg1Wxbgrqgd Ew4p8zff1QlH4v21ouXCM6VQIHBTosdgi8R6JdUo8qnAKs8LsBsZzH0JF k=; X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DtAAD3hrha/5tdJa1eGQEBAQEBAQEBAQEBAQcBAQEBAYNBgVEog1yIAI0Ngmkcjj6EExSBcguFBQKDdiE0GAECAQEBAQEBAmsohSUBKQQLAUYsAwECAwImAkgJGAmFDqtXgWs1hFiDZ4IagQiGUIIUgQyCU4R0ARIBgyCCVAOMV4poCI4xAow2ASuPJAIREwGBJRw4YXFNIxWCfROCDhiOFiEfMI1tgjcBAQ X-IronPort-AV: E=Sophos;i="5.48,363,1517875200"; d="scan'208";a="361949754" Received: from rcdn-core-4.cisco.com ([173.37.93.155]) by rcdn-iport-3.cisco.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Mar 2018 05:42:20 +0000 Received: from kamensky-w541.cisco.com ([10.24.23.119]) (authenticated bits=0) by rcdn-core-4.cisco.com (8.14.5/8.14.5) with ESMTP id w2Q5g7Sq025286 (version=TLSv1/SSLv3 cipher=AES128-SHA256 bits=128 verify=NO); Mon, 26 Mar 2018 05:42:20 GMT From: Victor Kamensky To: openembedded-core@lists.openembedded.org Date: Sun, 25 Mar 2018 22:42:07 -0700 Message-Id: <1522042927-29046-1-git-send-email-kamensky@cisco.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Authenticated-User: kamensky@cisco.com Subject: [OE-core] [PATCH] qemu: fix qemuarm64 intermediate kernel hang in raid6_select_algo func X-BeenThere: openembedded-core@lists.openembedded.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Patches and discussions about the oe-core layer List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org Backport fix from qemu mainline for intermediate qemuarm64 hang issue. Root caused in OE environment, issue with aarch64 qemu logic of executing instructions that reenabe interrupts. See patch commit message for more details. Upstream-Status: Backport Signed-off-by: Victor Kamensky --- ...te-a64-treat-DISAS_UPDATE-as-variant-of-D.patch | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 meta/recipes-devtools/qemu/qemu/0001-arm-translate-a64-treat-DISAS_UPDATE-as-variant-of-D.patch diff --git a/meta/recipes-devtools/qemu/qemu/0001-arm-translate-a64-treat-DISAS_UPDATE-as-variant-of-D.patch b/meta/recipes-devtools/qemu/qemu/0001-arm-translate-a64-treat-DISAS_UPDATE-as-variant-of-D.patch new file mode 100644 index 0000000..f90cae6 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu/0001-arm-translate-a64-treat-DISAS_UPDATE-as-variant-of-D.patch @@ -0,0 +1,67 @@ +From a75a52d62418dafe462be4fe30485501d1010bb9 Mon Sep 17 00:00:00 2001 +From: Victor Kamensky +Date: Fri, 23 Mar 2018 18:26:45 +0000 +Subject: [PATCH] arm/translate-a64: treat DISAS_UPDATE as variant of + DISAS_EXIT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In OE project 4.15 linux kernel boot hang was observed under +single cpu aarch64 qemu. Kernel code was in a loop waiting for +vtimer arrival, spinning in TC generated blocks, while interrupt +was pending unprocessed. This happened because when qemu tried to +handle vtimer interrupt target had interrupts disabled, as +result flag indicating TCG exit, cpu->icount_decr.u16.high, +was cleared but arm_cpu_exec_interrupt function did not call +arm_cpu_do_interrupt to process interrupt. Later when target +reenabled interrupts, it happened without exit into main loop, so +following code that waited for result of interrupt execution +run in infinite loop. + +To solve the problem instructions that operate on CPU sys state +(i.e enable/disable interrupt), and marked as DISAS_UPDATE, +should be considered as DISAS_EXIT variant, and should be +forced to exit back to main loop so qemu will have a chance +processing pending CPU state updates, including pending +interrupts. + +This change brings consistency with how DISAS_UPDATE is treated +in aarch32 case. + +CC: Peter Maydell +CC: Alex Bennée +CC: qemu-stable@nongnu.org +Suggested-by: Peter Maydell +Signed-off-by: Victor Kamensky +Reviewed-by: Richard Henderson +Message-id: 1521526368-1996-1-git-send-email-kamensky@cisco.com +Signed-off-by: Peter Maydell +Upstream-Status: Backport +--- + target/arm/translate-a64.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c +index 31ff047..327513e 100644 +--- a/target/arm/translate-a64.c ++++ b/target/arm/translate-a64.c +@@ -13378,12 +13378,12 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ +- case DISAS_JUMP: +- tcg_gen_lookup_and_goto_ptr(); +- break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; ++ case DISAS_JUMP: ++ tcg_gen_lookup_and_goto_ptr(); ++ break; + case DISAS_NORETURN: + case DISAS_SWI: + break; +-- +2.7.4 +