From patchwork Thu Apr 6 13:15:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 96957 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726357qgd; Thu, 6 Apr 2017 06:16:13 -0700 (PDT) X-Received: by 10.99.232.21 with SMTP id s21mr36736275pgh.67.1491484572641; Thu, 06 Apr 2017 06:16:12 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id c11si1827360pgn.360.2017.04.06.06.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A81DE20D77DB5; Thu, 6 Apr 2017 06:16:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 35E7121A18AA9 for ; Thu, 6 Apr 2017 06:16:09 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id t189so8825499wmt.1 for ; Thu, 06 Apr 2017 06:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yntV8JR7Qedy6lfVbKLklwBn0TCaGGzxSRflo1jlGUc=; b=QHyFyoYYE/pyJrl7DLE1JpsHTyaaHV31fQV8j0zi359NZcgyb2+eG9SS837lfblHOq yUPXp8Dp/CQXyOApDdmD5jBWUcW3V9MHrLEn49fh3XoHGYYviMN4RxVArxlSVDvVaP3i q/yBOOyFhmkYYSyjkLOrZVPc8hem36O+Uq/CU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yntV8JR7Qedy6lfVbKLklwBn0TCaGGzxSRflo1jlGUc=; b=p8dgZ7UCtpiNhwuqTx0sxwDoz7M25lLGY0nV//EDug1VekoU4U8GhEQO62r8KO3HvK czm1sN5WIIna1Fai2bJHiT0WGSNTYXww3A/49LQx6cym2UcYT7Jp7D8w+zmwNTO3ghu2 VxjKRTxxfZFlNT4gYUHkZIaY2oZZtdabunU22YWVGp2M6nu6EmUKItLe/oY5Z+jDSTk/ ZiFom/7Zl5xKNBNmq0pigSYNq6TYWAKWeO5ItIuwMoL3YnOQV0YI45wcvAqLM+fBYFYU YIH194cEONjtFf8iMeJrmGYgkG/bTBHfLttiYomSnh+Ls1FkPPDURmqdfGLr8oZ5Nxj1 CkBQ== X-Gm-Message-State: AFeK/H3l/E92neJ41PuIkLjazHQq/FNN9diE+DrvbRVPSdgi2/JxGPc85Bf2kuDL+quJ7KjC X-Received: by 10.28.220.212 with SMTP id t203mr24693383wmg.62.1491484567771; Thu, 06 Apr 2017 06:16:07 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:07 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Date: Thu, 6 Apr 2017 14:15:47 +0100 Message-Id: <20170406131551.3322-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 ++++++---- ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 +++++++- 2 files changed, 13 insertions(+), 5 deletions(-) -- 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h index 06414e6e7208..4e17c800a34f 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h @@ -40,9 +40,11 @@ #define ARM_VE_SMB_SRAM_BASE 0x2E000000 #define ARM_VE_SMB_SRAM_SZ SIZE_64KB // USB, Ethernet, VRAM -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) + +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB // DRAM #define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) @@ -75,6 +77,6 @@ #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 // VRAM offset for the PL111 Colour LCD Controller on the motherboard -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) +#define VRAM_MOTHERBOARD_BASE (PL111_CLCD_VRAM_MOTHERBOARD_BASE) #endif diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 14c7e8e1d672..70c17ae70478 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -21,7 +21,7 @@ #include // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // VRAM + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; From patchwork Thu Apr 6 13:15:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 96958 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726376qgd; Thu, 6 Apr 2017 06:16:15 -0700 (PDT) X-Received: by 10.84.214.15 with SMTP id h15mr2182850pli.65.1491484575030; Thu, 06 Apr 2017 06:16:15 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 31si1858403plz.70.2017.04.06.06.16.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E405821DFA903; Thu, 6 Apr 2017 06:16:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2B29321A18AA9 for ; Thu, 6 Apr 2017 06:16:11 -0700 (PDT) Received: by mail-wm0-x229.google.com with SMTP id y18so14258wmh.0 for ; Thu, 06 Apr 2017 06:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wBGxrj+uXaMQkdrtDV0kUgo4CGp2R4urP0FQkP5YUXY=; b=GJCNaUaDhwwyJ1EJCuolVcMB2uAslScngA9LgxTwWOtFr435TmuMvu4anOQP4tu4Ya BNy+b3/KRc+Pm8ihGF93Z9DLDoFYwhz2GJR/xcy/cOQW7ekeQ9xuegcsQGuvDhbH017w uN0XvEchpcK8m5x9amWic5IGDqTWVF6hc65wU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wBGxrj+uXaMQkdrtDV0kUgo4CGp2R4urP0FQkP5YUXY=; b=hGiOfvpiHeenyALzgwaUM4DeJeOrrYabnvQBiJvHZ26vi4njKz4Gssln562ZssSvWb hPdCJ71GcFM4vtaI5cjIr8qLZVR9W+2fz4TnJ3ZaMSRewG7SAZ574u37GphFXLhvYuTq E5bZhTrx5wI//VI9jW2+wQJuJo12/xYUN/IB1Gx+AxCsOzSGTkcnbJ6BUlxYTZFLF48q JJxm0XvtVkWiS5MN2HmGQXv4yzMyZ8ELHNaQ9hbtB61Ydto6tj5WJbomWTh82MXVXfNY gxF9H66jH0t6t3XSgDuqLHdf6CEVoGDLvAueaZ4hpf+9vG69VtEosVcQ7OGGippq4PKC 5btQ== X-Gm-Message-State: AFeK/H29OHce7oyUbShv69xM995w+BGr/2QkGb9eiViR+5GYogXlwsUU1IpgqFKlOWnhf5Jn X-Received: by 10.28.66.74 with SMTP id p71mr24455603wma.131.1491484569782; Thu, 06 Apr 2017 06:16:09 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:09 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Date: Thu, 6 Apr 2017 14:15:48 +0100 Message-Id: <20170406131551.3322-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 2/5] ArmPlatformPkg/HdLcdArmVExpressLib: fix incorrect FreePool () call X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index a57846715ed7..67b2f14beee3 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -146,7 +146,7 @@ LcdPlatformGetVram ( Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { - gBS->FreePool (VramBaseAddress); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } From patchwork Thu Apr 6 13:15:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 96959 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726402qgd; Thu, 6 Apr 2017 06:16:17 -0700 (PDT) X-Received: by 10.98.223.133 with SMTP id d5mr12925447pfl.222.1491484577485; Thu, 06 Apr 2017 06:16:17 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id h1si1843106pfg.225.2017.04.06.06.16.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2D49721A0480E; Thu, 6 Apr 2017 06:16:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wr0-x22c.google.com (mail-wr0-x22c.google.com [IPv6:2a00:1450:400c:c0c::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9833521A0480E for ; Thu, 6 Apr 2017 06:16:13 -0700 (PDT) Received: by mail-wr0-x22c.google.com with SMTP id t20so61702279wra.1 for ; Thu, 06 Apr 2017 06:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FmqolnnYwGoGv5HaGK9zKXUVK4PFXtsvwaBl8IkU4mc=; b=O4pwHuD4J2ZxJ/mGGSFL+A5v82ooDj38Vmr7g7NaIpz4CFjKEf6V2Ja+MohjKUwmka eA2vzXq9p6yPWmKPeUVAEZ9fcYHoZjo6XHeQ7noUxzTEQSddr6Cm8ityfVcxRnyTlV39 UpZggFfAZAVat6ip6H63DRW6b3bIgfmDjttfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FmqolnnYwGoGv5HaGK9zKXUVK4PFXtsvwaBl8IkU4mc=; b=Yeb8b6eLKMkc/QAo7LaBkU59Z2TmndgGqAsvwkQEtz5z9UUFlsWdNHAQ4nVYUmIMeu mTz1Vb3aT+E/1xt1Oq+nhs0Qymg5CWPg7neVElmSH3E0IzVeZhgWSnAyBJwL988110s5 Cl/gUSJHGbtWwGhKOVvdPWCW+aIhLWwx1Bn0IGa/bV0NaQplIpXe2LgzaLkpXp4jlgtu qBY3AIByiVsZbAiKhSa10wlrRKFsBDHl2vSZbXdBwyFIz/ql4MQkXV1oKdWbU5ELUtcP YxKgYD1Pdy+gWG+xYwvuizlHBRZeRGWPRtB5k+z6UkeESDUs2RrSgiguNeILvmf0hcx1 YtKg== X-Gm-Message-State: AFeK/H1906Tw8XlXFIUJE3K+2PMMKuoHFMe3qQwnePV2FzcNHRuMmCfOwbdB6BRGRsMQHGxj X-Received: by 10.223.171.84 with SMTP id r20mr28233947wrc.159.1491484572116; Thu, 06 Apr 2017 06:16:12 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:11 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Date: Thu, 6 Apr 2017 14:15:49 +0100 Message-Id: <20170406131551.3322-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 3/5] ArmPlatformPkg/PL111LcdArmVExpressLib: fix incorrect FreePool () call X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c index 2000c9bdf436..a8125e81daac 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -195,7 +195,7 @@ LcdPlatformGetVram ( Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { - gBS->FreePool(VramBaseAddress); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); return Status; } break; From patchwork Thu Apr 6 13:15:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 96960 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726422qgd; Thu, 6 Apr 2017 06:16:20 -0700 (PDT) X-Received: by 10.84.229.2 with SMTP id b2mr43798345plk.154.1491484580425; Thu, 06 Apr 2017 06:16:20 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id d10si1829732plj.322.2017.04.06.06.16.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5E79520D77DCF; Thu, 6 Apr 2017 06:16:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BE74820D77DD1 for ; Thu, 6 Apr 2017 06:16:15 -0700 (PDT) Received: by mail-wm0-x231.google.com with SMTP id o81so45328612wmb.1 for ; Thu, 06 Apr 2017 06:16:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JzjCA8YmvF/IBZAkTgf5WNcTCS+T1mp3sZ6R3pHEtWk=; b=akbzG64AhUVt2yBZxfgoZwb9ANUovfKwMhBXd42kVBpJO6l97BZKbAhyhzKaTuQy2+ OXrGg0I5UAC7L6m1JIH/rwlJEA4RrIuic3m1lEMcCG+dIhWCzDDTH0DoU8aK32Tug71c waT1pRo10mChI3ezScmjESYKt9nhHzP6t7kbM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JzjCA8YmvF/IBZAkTgf5WNcTCS+T1mp3sZ6R3pHEtWk=; b=JSp+c/aS66MZK099C73YPN8UKO3NdP4HXIPqd7ZhMtI/YObmNatnGvNqfuQfRz0apc pW/tUxLWGvMohHlE83HkbfF8wckN2NAHTlRQ5Faq5rdM4ary6uP5EuyRnybFFfrPX8+E vuplODqZaNnlxoKn1/Gy080KIfuQINd+9QXl3hOAv2ALQ63LPCoyVOwXU2NBYTb4C9Ib du2eCL4lH+Ony0DxfCsK8K6Ayw7Up/mmWw7N6Hvm6rWm9qaAuFUlSCMyhyjOcKVO2If3 Zb6fIgAiJYUwDInToGzqblFq5GMAuwR/x2+xbSSoJbk2TtHlnmjMNstDWdiSC+CgxoH4 iQgw== X-Gm-Message-State: AFeK/H1vQ/dDeJzyRBPOTYIVBntRb9ZaGFvr+DIo36BG7H/6k2llwHJRx6/hdoW5WB0l8FOb X-Received: by 10.28.69.68 with SMTP id s65mr24652240wma.13.1491484574333; Thu, 06 Apr 2017 06:16:14 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:13 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Date: Thu, 6 Apr 2017 14:15:50 +0100 Message-Id: <20170406131551.3322-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 4/5] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 12 ++++-------- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf | 3 ++- 2 files changed, 6 insertions(+), 9 deletions(-) -- 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index 67b2f14beee3..b1106ee19b98 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -119,7 +119,6 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; EFI_ALLOCATE_TYPE AllocationType; // Set the vram size @@ -138,12 +137,9 @@ LcdPlatformGetVram ( return Status; } - // Ensure the Cpu architectural protocol is already installed - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable. + Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf index 780724737929..dff17e86fd3e 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf @@ -32,8 +32,9 @@ [Packages] ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec [LibraryClasses] - BaseLib ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced From patchwork Thu Apr 6 13:15:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 96962 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp726456qgd; Thu, 6 Apr 2017 06:16:25 -0700 (PDT) X-Received: by 10.84.199.194 with SMTP id d2mr10298252plh.33.1491484585062; Thu, 06 Apr 2017 06:16:25 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id t68si1847271pfi.167.2017.04.06.06.16.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AD2BA20D77DD6; Thu, 6 Apr 2017 06:16:19 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07C1620D77DD6 for ; Thu, 6 Apr 2017 06:16:18 -0700 (PDT) Received: by mail-wm0-x236.google.com with SMTP id o81so45329564wmb.1 for ; Thu, 06 Apr 2017 06:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nyu5gvclC7SseCmFnQyvFoZkMEMf+RAQZpDb1gXEJgI=; b=ONZQdetIDSGH2hgP7VC1USiq4CJ+aetCqeG4ZvgTqhU05k6CU6bO8nu0ihSyc7I+d0 1+1oSnexF77knb4UrZWsT5NejtOGSe208xZHX5EI7ChXBnMAE8teQWxqTcs6lmQz/9j4 t2QTthAhaCHxIihYmrUPVueNRKE5c5DU+q5/I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nyu5gvclC7SseCmFnQyvFoZkMEMf+RAQZpDb1gXEJgI=; b=qq7LCNBGaTYbtpc31VDxCwvDQmiotizHJ6qkmhA0AFzLck4XB0ArwKK/hF02zFiTvX B3CdfKn0NqbKf97hwY+rZFdUKq3tdYDR9BE8Onm77VGS6twFkiCI4nb9+N4p8vtDzO6I NoCuLHTqutkB7aOlEfbTUK2TXZIV3UqsYQEopdrV8WCGfJYqnEvrb827EXRPVuIiZid+ z4STYkNNH2j60IZpSINJRpDiG8bmnetxclvITneUhpx+xpIvZsWcE02YmH3bxj63l3GU sYM7byva+/5529Kslw3UUV6GzvtGce8iC8nQbSutXV6LfMJjaZC+U0hfLHYf8NNO5Z1Z ZgQA== X-Gm-Message-State: AFeK/H15R7LDAIN804Orruf0w+lqpUvrHsu81FVXpmkkjIexoDlCi98fAtkI5j/aeHFzOJpi X-Received: by 10.28.64.135 with SMTP id n129mr18516268wma.45.1491484576376; Thu, 06 Apr 2017 06:16:16 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:15 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Date: Thu, 6 Apr 2017 14:15:51 +0100 Message-Id: <20170406131551.3322-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 5/5] ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 12 ++++-------- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf | 3 ++- 2 files changed, 6 insertions(+), 9 deletions(-) -- 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c index a8125e81daac..3f3ceb3d2fa8 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -17,10 +17,10 @@ #include #include #include +#include #include #include -#include #include #include @@ -165,7 +165,6 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; Status = EFI_SUCCESS; @@ -187,12 +186,9 @@ LcdPlatformGetVram ( return Status; } - // Ensure the Cpu architectural protocol is already installed - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable. - Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable. + Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf index d1978e7110d5..658558ab1523 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf @@ -31,8 +31,9 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec [LibraryClasses] - BaseLib ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced