From patchwork Mon Apr 10 12:33:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 97103 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1341681qgd; Mon, 10 Apr 2017 05:37:05 -0700 (PDT) X-Received: by 10.107.168.90 with SMTP id r87mr4389367ioe.45.1491827825072; Mon, 10 Apr 2017 05:37:05 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id d74si14109982iod.75.2017.04.10.05.37.04; Mon, 10 Apr 2017 05:37:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 35CD862E7C; Mon, 10 Apr 2017 12:37:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2BD4E62B8D; Mon, 10 Apr 2017 12:37:02 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BB0B062F36; Mon, 10 Apr 2017 12:37:00 +0000 (UTC) Received: from mail-pf0-f170.google.com (mail-pf0-f170.google.com [209.85.192.170]) by lists.linaro.org (Postfix) with ESMTPS id 8F3EE62D82 for ; Mon, 10 Apr 2017 12:36:58 +0000 (UTC) Received: by mail-pf0-f170.google.com with SMTP id i5so32787025pfc.2 for ; Mon, 10 Apr 2017 05:36:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L0+Ne374DKNctKLtINwROo8GcRlzE5Pp6m61hzsLGE0=; b=dnMfjpVAnqHLhsAT4Ztc+gkYsCGd+8xTg/BXFPybfPxwp9cAeuyG+OT0ADmjgBOK6/ RNM5Cpn5+Nn1o6VA9Pjdq7Yt765enArKAMHC+1m+VMeeO6tt1+YJ8T4jpMSjnTy29eRC /xR8qCYW6H69cBSh2dE/uETuLSDl/SL12dZw6qfxtYtfKT53EGu3WfpBpTNz6QLP+h1S 8Dkavb7Ml39OGjsHf1FrIarXdYCJqlmHD6HzigU3VPGRb2DJ3qrlRcn+heLk/oNR1gp1 UA+uOqq9qQPg78tOsWxr1gsn/UY4TqgkKs2I1c0wk+XFdvdDhVPzaRoFFLaQaMxChYp4 nshw== X-Gm-Message-State: AN3rC/5d8yUlFFkAxlbX5ISPSDxP/CnhdK+mHFCL6C4fn/Yh1sr7Lb65rkO3Vr34J0ygDarSsLY= X-Received: by 10.84.238.143 with SMTP id v15mr20193323plk.102.1491827817779; Mon, 10 Apr 2017 05:36:57 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 128sm24645352pgi.49.2017.04.10.05.36.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Apr 2017 05:36:57 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Mon, 10 Apr 2017 20:33:13 +0800 Message-Id: <1491827595-84884-2-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> References: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v3 1/3] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++ Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..a9b3d74 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \ + CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9671c57..9a0f636 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -70,6 +70,10 @@ #define PCS_SDS_CFG_REG 0x204 #define SDS_CFG_STRIDE 0x4 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define MUX_CFG_STRIDE 0x4 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) From patchwork Mon Apr 10 12:33:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 97104 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1341694qgd; Mon, 10 Apr 2017 05:37:07 -0700 (PDT) X-Received: by 10.107.136.143 with SMTP id s15mr4180362ioi.224.1491827827102; Mon, 10 Apr 2017 05:37:07 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i203si14155198ioi.179.2017.04.10.05.37.06; Mon, 10 Apr 2017 05:37:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8BD4260F28; Mon, 10 Apr 2017 12:37:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 6F9BA63A34; Mon, 10 Apr 2017 12:37:04 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 38D2D62D96; Mon, 10 Apr 2017 12:37:03 +0000 (UTC) Received: from mail-pg0-f43.google.com (mail-pg0-f43.google.com [74.125.83.43]) by lists.linaro.org (Postfix) with ESMTPS id 0C83E60F28 for ; Mon, 10 Apr 2017 12:37:01 +0000 (UTC) Received: by mail-pg0-f43.google.com with SMTP id x125so105284969pgb.0 for ; Mon, 10 Apr 2017 05:37:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3zCithuUcb7ai8bZObf0R5TodwDzLqyHie1O5omR2lw=; b=Ov81ZKTtoTSWWU9e4j/C1WuqqEtNbJ2QcWu9k5MV5+wmC0yOSXt8hvfEaOtfiydGUk guROlHcXJ13+CzwvgxlotXnVC1ZGoJZ08GrBwQzkV3WCnLYwdo0dMSxwBsexWt6Eined LoXoOxQta2487i43OqL3PNPJBr4hGLDHyzDyaySU8G11uu9/ETP6JKH1di1jNYmd6N7q dOfbc44bZ1uI6T02zzMrUMAbgeyTVYnx0enWo/KqLLlF+Ko1aYYp4UAzI0xkf//v4LhL YFg1tfSDtMvvUOpQRFhk2PIenT1WmRJhaZPFaMu0cx13ZEHyQ/cNSUAAJDlvHCYP5jt2 JIwg== X-Gm-Message-State: AFeK/H0mVsPnX0PmxoWcwcjAmkQPFsiRtPl9lAsLC5KOwryXE9BUzQRjPw+pi5SAL8DK5Ud8Rzo= X-Received: by 10.99.156.2 with SMTP id f2mr34229973pge.65.1491827820293; Mon, 10 Apr 2017 05:37:00 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 128sm24645352pgi.49.2017.04.10.05.36.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Apr 2017 05:36:59 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Mon, 10 Apr 2017 20:33:14 +0800 Message-Id: <1491827595-84884-3-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> References: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v3 2/3] Hisilicon: disable RC Option Rom X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The M3(the coprocessor)PCIe driver will read Option Rom header durning enumeration, this operation will cause a completion error when there is no device inserted to the RC port, and the Option rom is uesless now. So we need to disable the RC Option Rom. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index a9b3d74..1df7a90 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -901,6 +901,50 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return; } +UINT32 +SysRegRead ( + IN UINT32 SocType, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINTN Reg + ) +{ + UINT32 Value; + if (SocType == 0x1610) { + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); + } else { + //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE + //in the same hostbridge. + RegRead (PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); + } + return Value; +} + +VOID +DisableRcOptionRom ( + IN UINT32 Soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_PORT_TYPE PcieType +) +{ + UINT32 Value = 0; + if (PcieType == PCIE_ROOT_COMPLEX) { + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value |= BIT2; //cs2 enable + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG); + Value &= ~BIT0; //disable option rom + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value); + + Value = SysRegRead (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value &= ~BIT2; //cs2 disable + SysRegWrite (Soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + } + return; +} + EFI_STATUS EFIAPI PciePortInit ( @@ -961,6 +1005,8 @@ PciePortInit ( /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); + /* Disable RC Option Rom */ + DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { From patchwork Mon Apr 10 12:33:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 97105 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1341715qgd; Mon, 10 Apr 2017 05:37:11 -0700 (PDT) X-Received: by 10.107.173.22 with SMTP id w22mr50784816ioe.119.1491827831173; Mon, 10 Apr 2017 05:37:11 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 17si14127241iob.248.2017.04.10.05.37.09; Mon, 10 Apr 2017 05:37:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A6FC061FC4; Mon, 10 Apr 2017 12:37:09 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 9A2F362B8D; Mon, 10 Apr 2017 12:37:07 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0E63062B8D; Mon, 10 Apr 2017 12:37:06 +0000 (UTC) Received: from mail-pg0-f45.google.com (mail-pg0-f45.google.com [74.125.83.45]) by lists.linaro.org (Postfix) with ESMTPS id D440060F28 for ; Mon, 10 Apr 2017 12:37:03 +0000 (UTC) Received: by mail-pg0-f45.google.com with SMTP id g2so103919116pge.3 for ; Mon, 10 Apr 2017 05:37:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G+5T7rZL/eUSm3ogYfHH/GTPVlTfF8oNt6K9jQzmf2Q=; b=rqNMY+1QuDeh5D0qCVrbnKu65wDCS4YQQ97uiq20yc3kUSxHmXLuHYyGVBRUhk3vpm QrkejPwRp9sYrQph4XMZ7c+GoltnRbQuUpG7oVzezzh2ZausVj+WtPXpil7COxgBAYfX /Kw+CSCtKLZLrq9S3xv0JuuJzM2lYJKwhwRJk+Ef+yEZQ7ND3Nus2TSUS944R4HTe01p sAz3W4pVwZEWPtc9WbxWlxMLnUTkV0HiPtTdKQ4qsmckq8fGrNxIAcpHqOJFw3D9uRv2 TnpAK42/OJa2MvVb18UGKSirmTM00IbiFDcmL4otjat7mxIvcftDTGSyUmNRu7KXoPJw K1Pg== X-Gm-Message-State: AFeK/H1QfxHCcRL7TNeb/TTxP30b/5mxk6Sqz5qvaODPAXGD7OzCNZyuZ10hcYlhv/Wb62Jdm7kmfcju X-Received: by 10.99.127.12 with SMTP id a12mr55915259pgd.5.1491827823044; Mon, 10 Apr 2017 05:37:03 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 128sm24645352pgi.49.2017.04.10.05.37.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Apr 2017 05:37:02 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Mon, 10 Apr 2017 20:33:15 +0800 Message-Id: <1491827595-84884-4-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> References: <1491827595-84884-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v3 3/3] Hisilicon: Add reconfig lane number feature X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" In some cases, the PCIe device may close part of lanes in config state of LTSSM, the hip06 RC should reconfig lane number and try to linkup again. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 136 ++++++++++++++++++++- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 5 + 2 files changed, 139 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 1df7a90..8ab7fa3 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -39,6 +39,14 @@ extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; extern PCIE_IATU gastr_pcie_iatu_cfg; extern PCIE_IATU_VA mPcieIatuTable; +EFI_STATUS +EFIAPI +PciePortInit ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN PCIE_DRIVER_CFG *PcieCfg + ); + VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) { RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); @@ -149,8 +157,131 @@ VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN } } } +/* + * The ltssm register is assigned in an asynchronous way, the value + * of register may not right in metastable state. + * Read the register twice to get stable value. + */ +VOID PcieGetLtssmValue ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT32 *Value + ) +{ + UINT32 ValueA; + UINT32 ValueB = 0; + UINT32 Count; + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA); + ValueA = ValueA & PCIE_LTSSM_STATE_MASK; + + Count = 0; + while (Count < 2) { + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB); + ValueB = ValueB & PCIE_LTSSM_STATE_MASK; + + /* Get the same state in continuous two times*/ + if (ValueA == ValueB) { + break; + } + + //If the second value not equal to the first, we return the second one as the stable + ValueA = ValueB; + Count++; + } + + *Value = ValueB; + + return; + +} + +/* + * In some cases, the PCIe device may close part of lanes in + * config state of LTSSM, the hip06 RC should reconfig lane num + * and try to linkup again. + */ +VOID PcieReconfigLaneNum ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_DRIVER_CFG *PcieCfg + ) +{ + EFI_STATUS Status; + UINT32 LtssmStatus; + UINT32 RegVal; + UINT32 LoopCnt = 0; + UINT32 LaneNumCnt = 0; + PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth; + + // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers + while (LoopCnt < 500) { + + /* + * The minimum lanenum is 1, no need to try any more. + */ + if (PortWidth <= 1) { + DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n")); + return; + } + + /* + * Check the lane num config state is normal or not. + */ + PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); + if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) { + LaneNumCnt++; + } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + PcieGetLtssmValue (HostBridgeNum, Port, &LtssmStatus); + if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + break; + } + } else { + LaneNumCnt = 0; + } + + /* + * The lane num config state is abnormal, need to reconfig + * the lane num and try to establish link again. + */ + if (LaneNumCnt > MAX_TRY_LINK_NUM) { + /* Disable LTSSM */ + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + RegVal &= ~(LTSSM_ENABLE); + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + /* + * Decrease the PortWidth and try to link again, + * the value of PortWidth 0xf (X8), 0x7(x4), 0x3(X2), 0x1(X1) + */ + PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1); + + Status = PciePortInit (soctype, HostBridgeNum, PcieCfg); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); + } + return; + } + + LoopCnt++; + /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted + * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept. + * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range. + */ + MicroSecondDelay (200); + } + + return ; +} -EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +EFI_STATUS +PcieEnableItssm ( + IN UINT32 soctype, + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN PCIE_DRIVER_CFG *PcieCfg + ) { PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0; @@ -165,6 +296,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= BIT11|BIT30|BIT31; RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); + PcieReconfigLaneNum (soctype, HostBridgeNum, Port, PcieCfg); return EFI_SUCCESS; } else @@ -1008,7 +1140,7 @@ PciePortInit ( /* Disable RC Option Rom */ DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ - (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { //PCIe will still work even if performance tuning fails, //and there is warning message inside the function to print diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index 539d567..bf57652 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8982,6 +8982,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) #define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) +#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) @@ -12694,7 +12695,11 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) #define PCIE_LTSSM_STATE_MASK (0x3f) +#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a +#define PCIE_LTSSM_CFG_COMPLETE 0x0b #define PCIE_LTSSM_LINKUP_STATE (0x11) +#define LTSSM_ENABLE BIT11 +#define MAX_TRY_LINK_NUM 5 #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_RD_STS0_REG (PCIE_SUBCTRL_BASE + 0x6890)