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[198.145.21.10]) by mx.google.com with ESMTPS id c196-v6si405423pga.494.2018.05.15.10.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fbJIJPfB; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3BA6C2034862C; Tue, 15 May 2018 10:37:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B74F2209603DA for ; Tue, 15 May 2018 10:37:47 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id o4-v6so1020795wrm.0 for ; Tue, 15 May 2018 10:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YeTrVhslB5MjKv/QGsjKNe9ONYfEeO/pFgzZU8S9vvA=; b=fbJIJPfBQvpBHSQxbgyaQePINAr0maKcZCPiI9SdP+1ls1xk22fzID6Y3W+BHsJbFq z7jTvX9krQr873DOV8S3mPRSXU2KzIqRjj1/adL8Dc6oYV9UpNFMUytExSyv7+2QYjX1 Ce7uUCU608vJdGCAnzjvII2O1TnH9zHdy5+O8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YeTrVhslB5MjKv/QGsjKNe9ONYfEeO/pFgzZU8S9vvA=; b=MzEt9vP9mZXhBl1yAEoZOXsuif1T75lOhJd8BT69s8nzEID7USMb5b7Sq+A8Jw2Dad 3pWOD5red/suDNgtNV/HzZN1DvQZIC7rcQ8/f203ciepcZ0cUy33yF1SSpA3vVVmfswF IkDMPnRVJWcAx6eGofZjx7Yq+eGQi4ZuuQcr+qFujG9ymasO3cjUTs0eNUSOLESjLVPD AZuqUhn9ssBgM+j0p5gKbXW8xFnXP4uMXQ+Wx3sAAZxhYp+372QKz3ikX2na/lgEv2Cb UGOwioIxBynvzQQm1LqqMjl7gRMOLcyhALHwazBcOG7sjdVRHA3ywtgA3vk739Kv8e+f fXkA== X-Gm-Message-State: ALKqPwfhYA8nixUGNWqdJ0VXKfZ+taRJ2WNoIjTqQqHyW2oC63zCd4hz TB5xwZbOy48eOPyx9vqciBGhGPD+KiU= X-Received: by 2002:adf:dd03:: with SMTP id a3-v6mr12401057wrm.0.1526405865806; Tue, 15 May 2018 10:37:45 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:45 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:32 +0200 Message-Id: <20180515173736.29639-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/5] Silicon/AMD/Styx: make ARM-TF and PSCI dependencies unconditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The Styx platform theoretically supports running in an environment where no ARM Trusted Firmware is running in EL3 and PSCI is not implemented. This is not a configuration that we aim to support, and so let's remove the code that implements this, especially because it is essentially dead code and unmaintained. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 7 -- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 1 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 7 -- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 2 - Silicon/AMD/Styx/AcpiTables/Fadt.c | 5 +- Silicon/AMD/Styx/AmdStyx.dec | 5 -- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c | 70 -------------------- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf | 6 -- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf | 1 - Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 58 ++++++++-------- Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 1 - Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf | 3 - Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 - 13 files changed, 29 insertions(+), 139 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 348828e18d44..86061cd4606f 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -19,7 +19,6 @@ [Defines] DEFINE DO_XGBE = 1 DEFINE NUM_CORES = 8 -DEFINE DO_PSCI = 1 DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -457,12 +456,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 -!if $(DO_PSCI) - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE -!endif - !if $(DO_ISCP) gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE !else diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 007c36412b93..80b096ba5587 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -431,7 +431,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE # SMBIOS 3.0 only diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 3f4c7c8a3eef..72eb943a8bfd 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -18,7 +18,6 @@ [Defines] DEFINE NUM_CORES = 4 -DEFINE DO_PSCI = 1 DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -428,12 +427,6 @@ [PcdsFixedAtBuild.common] ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -!if $(DO_PSCI) - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|FALSE -!endif - !if $(DO_ISCP) gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE !else diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index 057c52512e4e..bff5be4673a4 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -82,8 +82,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion gAmdStyxTokenSpaceGuid.PcdSata1PortCount diff --git a/Silicon/AMD/Styx/AcpiTables/Fadt.c b/Silicon/AMD/Styx/AcpiTables/Fadt.c index bcbff3798883..bdf88a9c8e32 100644 --- a/Silicon/AMD/Styx/AcpiTables/Fadt.c +++ b/Silicon/AMD/Styx/AcpiTables/Fadt.c @@ -73,7 +73,7 @@ STATIC EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE AcpiFadt = { FADT_FLAGS, // UINT32 Flags NULL_GAS, // EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - 0, // UINT16 ArmBootArch + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch 1, // UINT8 MinorVersion 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt @@ -96,9 +96,6 @@ FadtTable ( VOID ) { - if (FixedPcdGetBool (PcdPsciOsSupport) && FixedPcdGetBool (PcdTrustedFWSupport)) { - AcpiFadt.ArmBootArch = EFI_ACPI_5_1_ARM_PSCI_COMPLIANT; - } return (EFI_ACPI_DESCRIPTION_HEADER *) &AcpiFadt; } diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index 0d7e82f2d768..cffe1cafde8b 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -89,17 +89,12 @@ [PcdsFixedAtBuild] gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV|369|UINT32|0x00050008 # Trusted-Firmware - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport|TRUE|BOOLEAN|0x00060000 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002 # ISCP gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000 - # PSCI - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE|BOOLEAN|0x00080000 - gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext|0|UINT64|0x00080001 - # Cores Per cluster gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000 diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c index fd5bb96f7c98..e713d5581925 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -33,7 +33,6 @@ STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 }; -STATIC AMD_MP_BOOT_PROTOCOL mAmdMpBootProtocol = { 0 }; STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 }; @@ -56,13 +55,6 @@ AmdStyxGetMpParkingBase ( OUT UINTN *MpParkingSize ); -STATIC -VOID -AmdStyxParkSecondaryCore ( - ARM_CORE_INFO *ArmCoreInfo, - EFI_PHYSICAL_ADDRESS SecondaryEntry - ); - #pragma pack(push, 1) typedef struct _PMU_INFO { @@ -94,8 +86,6 @@ PlatInitDxeEntryPoint ( ) { EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; ARM_CORE_INFO *ArmCoreInfoTable; UINTN ArmCoreCount; EFI_HANDLE Handle = NULL; @@ -120,39 +110,6 @@ PlatInitDxeEntryPoint ( ); ASSERT_EFI_ERROR (Status); - // Install MP-Boot Protocol - if (!FixedPcdGetBool (PcdPsciOsSupport) && - FixedPcdGetBool (PcdTrustedFWSupport)) { - // Allocate Parking area (4KB-aligned, 4KB per core) as Reserved memory - MpParkingBase = 0; - MpParkingSize = ArmCoreCount * SIZE_4KB; - Status = gBS->AllocatePages (AllocateAnyPages, EfiReservedMemoryType, - EFI_SIZE_TO_PAGES (MpParkingSize), - &MpParkingBase); - if (EFI_ERROR (Status) || MpParkingBase == 0) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to allocate MpParkingBase.")); - } else { - mAmdMpBootInfo.MpParkingBase = MpParkingBase; - mAmdMpBootInfo.MpParkingSize = MpParkingSize; - mAmdMpBootInfo.ArmCoreInfoTable = ArmCoreInfoTable; - mAmdMpBootInfo.ArmCoreCount = ArmCoreCount; - - mAmdMpBootProtocol.ParkSecondaryCore = AmdStyxParkSecondaryCore; - mAmdMpBootProtocol.MpBootInfo = &mAmdMpBootInfo; - - Status = gBS->InstallProtocolInterface ( - &Handle, - &gAmdMpBootProtocolGuid, - EFI_NATIVE_INTERFACE, - (VOID *)&mAmdMpBootProtocol - ); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to install MP-Boot Protocol.")); - gBS->FreePages (MpParkingBase, EFI_SIZE_TO_PAGES (MpParkingSize)); - } - } - } - return Status; } @@ -208,30 +165,3 @@ AmdStyxGetMpParkingBase ( *MpParkingSize = mAmdMpBootInfo.MpParkingBase; return mAmdMpBootInfo.MpParkingBase; } - - -STATIC -VOID -AmdStyxParkSecondaryCore ( - ARM_CORE_INFO *ArmCoreInfo, - EFI_PHYSICAL_ADDRESS SecondaryEntry - ) -{ - ARM_SMC_ARGS SmcRegs = {0}; - UINTN MpId; - - MpId = GET_MPID (ArmCoreInfo->ClusterId, ArmCoreInfo->CoreId); - - SmcRegs.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64; - SmcRegs.Arg1 = MpId; - SmcRegs.Arg2 = SecondaryEntry; - SmcRegs.Arg3 = FixedPcdGet64 (PcdPsciCpuOnContext); - ArmCallSmc (&SmcRegs); - - if (SmcRegs.Arg0 == ARM_SMC_PSCI_RET_SUCCESS || - SmcRegs.Arg0 == ARM_SMC_PSCI_RET_ALREADY_ON) { - DEBUG ((EFI_D_ERROR, "CPU[MpId] = 0x%X at RUN state.\n", MpId)); - } else { - DEBUG ((EFI_D_ERROR, "Warning: Could not transition CPU[MpId] = 0x%X to RUN state.\n", MpId)); - } -} diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf index 15f46be651b7..1ebde2723355 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -51,12 +51,6 @@ [Guids] [Protocols] gAmdMpCoreInfoProtocolGuid ## PRODUCER - gAmdMpBootProtocolGuid ## PRODUCER - -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdPsciCpuOnContext - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport [Depex] TRUE diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf index 9f141946aea5..ccc079bebab2 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -68,7 +68,6 @@ [Pcd] [FixedPcd] gAmdStyxTokenSpaceGuid.PcdIscpSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdCpuIdRegister [Depex] diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 70821d1b120b..67f90efdcb3f 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -127,36 +127,34 @@ MemoryPeim ( Base = PcdGet64 (PcdSystemMemoryBase); Size = PcdGet64 (PcdSystemMemorySize); - if (FixedPcdGetBool (PcdTrustedFWSupport)) { - - // - // For now, we assume that the trusted firmware region is at the base of - // system memory, since that is much easier to deal with. - // - ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase)); - - Base += PcdGet64 (PcdTrustedFWMemorySize); - Size -= PcdGet64 (PcdTrustedFWMemorySize); - - // Reserved Trusted Firmware region - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - ( EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED ), - PcdGet64 (PcdTrustedFWMemoryBase), - PcdGet64 (PcdTrustedFWMemorySize) - ); - - BuildMemoryAllocationHob ( - PcdGet64 (PcdTrustedFWMemoryBase), - PcdGet64 (PcdTrustedFWMemorySize), - EfiReservedMemoryType - ); - } + + // + // For now, we assume that the trusted firmware region is at the base of + // system memory, since that is much easier to deal with. + // + ASSERT (Base == PcdGet64 (PcdTrustedFWMemoryBase)); + + Base += PcdGet64 (PcdTrustedFWMemorySize); + Size -= PcdGet64 (PcdTrustedFWMemorySize); + + // Reserved Trusted Firmware region + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED ), + PcdGet64 (PcdTrustedFWMemoryBase), + PcdGet64 (PcdTrustedFWMemorySize) + ); + + BuildMemoryAllocationHob ( + PcdGet64 (PcdTrustedFWMemoryBase), + PcdGet64 (PcdTrustedFWMemorySize), + EfiReservedMemoryType + ); // Declare system memory BuildResourceDescriptorHob ( diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index 724d71645d5a..d17e6c26feb5 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -69,7 +69,6 @@ [FixedPcd] gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize diff --git a/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf index 5a99fd79384a..d9faf3abb09a 100644 --- a/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf +++ b/Silicon/AMD/Styx/Library/ResetSystemLib/ResetSystemLib.inf @@ -42,6 +42,3 @@ [LibraryClasses] PcdLib BaseLib ArmSmcLib - -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index fc8b25c92873..3f36799f5df1 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -51,8 +51,6 @@ [Pcd] [FixedPcd] gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment - gAmdStyxTokenSpaceGuid.PcdPsciOsSupport - gAmdStyxTokenSpaceGuid.PcdTrustedFWSupport gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Guids] From patchwork Tue May 15 17:37:33 2018 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id 33-v6si497340plf.308.2018.05.15.10.37.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDxPeqmp; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6675520348635; Tue, 15 May 2018 10:37:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1E197209603D9 for ; Tue, 15 May 2018 10:37:49 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id y15-v6so987177wrg.11 for ; Tue, 15 May 2018 10:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RGF7sqd+567yVouByADXvhOOhLGBBsdPB2axphSHZ80=; b=aDxPeqmpS/TVmdlXz2T0ub3BN1qqGq5Q7pXPENDPH24ERrkO9ghnFK2lYkwefrS3SG FvBWRMP6ZnoTz75Lp9bf4+R2n/aIOWLD4UpjMdXOUdSOrgnEyZmejsV4KJBWjBvbwHAV 5JAGMSe5hOTHMF+jXBE/UY02O9fVAATDZbjVo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RGF7sqd+567yVouByADXvhOOhLGBBsdPB2axphSHZ80=; b=Lq0Etd91BUavYH3H69dUzY9vPPKyFCX1Nj7QsVelVIo4Xk4hnayN82Lg9BADPgK2PO vI4I7vjwffM6uQd8/T6NZwAPPcguoUyvUAsl6pE3LMosyt1TJM9DGfogjlw4gyajF7cm w44sytDDHWXKrCw3d0O6bC+x7VvVJX+AIPZ3h8xV4EMLU7jHLIZr3uvkHtRK833kwcF4 ld2FzwsdA7Qk9mSmPfkSOF0Sv/nwjFKrPn/Tu1nXi54i7JYvtSJQav6qax59nozjx1yE yvcz67FkNBN1T6Z55UaxcNsb/1Vb4qRXGYqhIybUdY1G86ft07TNU8MCDeUJ3G0vr7ib Iz7w== X-Gm-Message-State: ALKqPwdIlnIEIWbhf+1u+f0vC78HnCuZYfvlPQHaeUepaom1XCSIH5Z0 qkejKIvYW4Gd4dCMExYUy5svB0/ojc0= X-Received: by 2002:adf:88b6:: with SMTP id f51-v6mr10617935wrf.55.1526405867871; Tue, 15 May 2018 10:37:47 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:46 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:33 +0200 Message-Id: <20180515173736.29639-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/5] Silicon/AMD/Styx: remove MpBootDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" MpBootDxe implements support for the ACPI Parking Protocol and the DT based spintable protocol to bring up secondaries, neither of which are recommended on systems implementing EL3, are not enabled in the default build configuration of the platforms that include it and is therefore essentially dead code. (Note that this driver DEPEXes on a protocol that never gets installed when building this platform with ARM-TF and PSCI support, which we now do unconditionally) So let's remove it from the platform descriptions that refer to it, and remove the code altogether as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 5 - Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 5 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 5 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf | 5 - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c | 170 -------------------- Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf | 53 ------ Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S | 87 ---------- 7 files changed, 330 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 86061cd4606f..26b91ca88a2c 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -629,11 +629,6 @@ [Components.common] MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # AHCI Support # diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index 541d65ef753e..1ed32f68ef9d 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -222,11 +222,6 @@ [FV.FvMain] INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # SMBIOS Support # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 72eb943a8bfd..8d50d78c30cd 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -563,11 +563,6 @@ [Components.common] MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # AHCI Support # diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf index 38344fa406a3..e23533d1bddb 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.fdf @@ -220,11 +220,6 @@ [FV.FvMain] INF RuleOverride=ACPITABLE Silicon/AMD/Styx/AcpiTables/AcpiAml.inf INF Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf - # - # MP-Boot: ACPI[Parking Protocol] + FDT[Spin-Table] - # - INF Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf - # # SMBIOS Support # diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c deleted file mode 100644 index bd7244648ab0..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.c +++ /dev/null @@ -1,170 +0,0 @@ -/** @file - - Copyright (c) 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - - -/* These externs are used to relocate our Pen code into pre-allocated memory */ -extern VOID *SecondariesPenStart; -extern VOID *SecondariesPenEnd; -extern UINTN *AsmParkingBase; -extern UINTN *AsmMailboxBase; - - -STATIC -EFI_PHYSICAL_ADDRESS -ConfigurePen ( - IN EFI_PHYSICAL_ADDRESS MpParkingBase, - IN UINTN MpParkingSize, - IN ARM_CORE_INFO *ArmCoreInfoTable, - IN UINTN ArmCoreCount - ) -{ - EFI_PHYSICAL_ADDRESS PenBase; - UINTN PenSize; - UINTN MailboxBase; - UINTN CoreNum; - UINTN CoreMailbox; - UINTN CoreParking; - - // - // Set Pen at the 2K-offset of the Parking area, skipping an 8-byte slot for the Core#. - // For details, refer to the "Multi-processor Startup for ARM Platforms" document: - // https://acpica.org/sites/acpica/files/MP%20Startup%20for%20ARM%20platforms.docx - // - PenBase = (EFI_PHYSICAL_ADDRESS)((UINTN)MpParkingBase + SIZE_2KB + sizeof(UINT64)); - PenSize = (UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart; - - // Relocate the Pen code - CopyMem ((VOID*)(PenBase), (VOID*)&SecondariesPenStart, PenSize); - - // Put spin-table mailboxes below the pen code so we know where they are relative to code. - // Make sure this is 8 byte aligned. - MailboxBase = (UINTN)PenBase + ((UINTN)&SecondariesPenEnd - (UINTN)&SecondariesPenStart); - if (MailboxBase % sizeof(UINT64) != 0) { - MailboxBase += sizeof(UINT64) - MailboxBase % sizeof(UINT64); - } - - // Update variables used in the Pen code - *(UINTN*)(PenBase + ((UINTN)&AsmMailboxBase - (UINTN)&SecondariesPenStart)) = MailboxBase; - *(UINTN*)(PenBase + ((UINTN)&AsmParkingBase - (UINTN)&SecondariesPenStart)) = (UINTN)MpParkingBase; - - for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) { - // Clear the jump address at spin-table slot - CoreMailbox = MailboxBase + CoreNum * sizeof (UINT64); - *((UINTN*)(CoreMailbox)) = 0x0; - - // Clear the jump address and set Core# at mp-parking slot - CoreParking = (UINTN)MpParkingBase + CoreNum * SIZE_4KB; - *((UINTN*)(CoreParking + sizeof (UINT64))) = 0x0; - *((UINTN*)(CoreParking + SIZE_2KB)) = CoreNum; - - // Update table entry to be consumed by FDT parser - ArmCoreInfoTable[CoreNum].MailboxSetAddress = CoreMailbox; - } - - // flush the cache before launching secondary cores - WriteBackDataCacheRange ((VOID *)MpParkingBase, MpParkingSize); - - return PenBase; -} - - -EFI_STATUS -EFIAPI -MpBootDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - AMD_MP_BOOT_PROTOCOL *MpBootProtocol; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; - ARM_CORE_INFO *ArmCoreInfoTable; - UINTN ArmCoreCount; - UINTN CoreNum; - EFI_PHYSICAL_ADDRESS PenBase; - - DEBUG ((EFI_D_ERROR, "MpBootDxe Loaded\n")); - - MpBootProtocol = NULL; - Status = gBS->LocateProtocol ( - &gAmdMpBootProtocolGuid, - NULL, - (VOID **)&MpBootProtocol - ); - if (EFI_ERROR (Status) || MpBootProtocol == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: Failed to locate MP-Boot Protocol.\n")); - return EFI_UNSUPPORTED; - } - - if ((VOID *)MpBootProtocol->MpBootInfo == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: MpBootInfo not allocated.\n")); - return EFI_UNSUPPORTED; - } - - MpParkingBase = MpBootProtocol->MpBootInfo->MpParkingBase; - if ((VOID *)MpParkingBase == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not allocated.\n")); - return EFI_UNSUPPORTED; - } - if (((UINTN)MpParkingBase & (SIZE_4KB -1)) != 0) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingBase not 4K aligned.\n")); - return EFI_UNSUPPORTED; - } - - ArmCoreInfoTable = MpBootProtocol->MpBootInfo->ArmCoreInfoTable; - if (ArmCoreInfoTable == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: ArmCoreInfoTable not allocated.\n")); - return EFI_UNSUPPORTED; - } - - ArmCoreCount = MpBootProtocol->MpBootInfo->ArmCoreCount; - if (ArmCoreCount < 2) { - DEBUG ((EFI_D_ERROR, "Warning: Found %d cores.\n", ArmCoreCount)); - return EFI_UNSUPPORTED; - } - - MpParkingSize = ArmCoreCount * SIZE_4KB; - if (MpParkingSize > MpBootProtocol->MpBootInfo->MpParkingSize) { - DEBUG ((EFI_D_ERROR, "Warning: MpParkingSize = 0x%lX, not large enough for %d cores.\n", - MpBootProtocol->MpBootInfo->MpParkingSize, ArmCoreCount)); - return EFI_UNSUPPORTED; - } - - if ((VOID *)MpBootProtocol->ParkSecondaryCore == NULL) { - DEBUG ((EFI_D_ERROR, "Warning: ParkSecondaryCore() not supported.\n")); - return EFI_UNSUPPORTED; - } - - // Move secondary cores to our new Pen - PenBase = ConfigurePen (MpParkingBase, MpParkingSize, ArmCoreInfoTable, ArmCoreCount); - for (CoreNum = 0; CoreNum < ArmCoreCount; CoreNum++) { - MpBootProtocol->ParkSecondaryCore (&ArmCoreInfoTable[CoreNum], PenBase); - } - - return EFI_SUCCESS; -} - - diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf deleted file mode 100644 index ec63cd36e804..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootDxe.inf +++ /dev/null @@ -1,53 +0,0 @@ -#/* @file -# -# Copyright (c) 2016, AMD Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = MpBootDxe - FILE_GUID = ff3f9c9b-6d36-4787-9144-6b22acba5e9b - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = MpBootDxeEntryPoint - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = AARCH64 -# -# - -[Sources.common] - MpBootDxe.c - -[Sources.AARCH64] - MpBootHelper.S - -[Packages] - ArmPkg/ArmPkg.dec - MdePkg/MdePkg.dec - Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec - Silicon/AMD/Styx/AmdStyx.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - CacheMaintenanceLib - BaseMemoryLib - DebugLib - -[Protocols] - gAmdMpBootProtocolGuid ## CONSUMED - -[Depex] - gAmdMpBootProtocolGuid diff --git a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S b/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S deleted file mode 100644 index c16cc59a1e5e..000000000000 --- a/Silicon/AMD/Styx/Drivers/MpBootDxe/MpBootHelper.S +++ /dev/null @@ -1,87 +0,0 @@ -// -// Copyright (c) 2011-2013, ARM Limited. All rights reserved. -// Copyright (c) 2014 - 2016, AMD Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//** -// Derived from: -// ArmPkg/Library/BdsLib/AArch64/BdsLinuxLoaderHelper.S -// -//** - -/* Secondary core pens for AArch64 Linux booting. - - This code is placed in Linux kernel memory and marked reserved. UEFI ensures - that the secondary cores get to this pen and the kernel can then start the - cores from here. - NOTE: This code must be self-contained. -*/ - -#include - -.text -.align 3 - -GCC_ASM_EXPORT(SecondariesPenStart) -ASM_GLOBAL SecondariesPenEnd - -ASM_PFX(SecondariesPenStart): - // Registers x0-x3 are reserved for future use and should be set to zero. - mov x0, xzr - mov x1, xzr - mov x2, xzr - mov x3, xzr - - mrs x4, mpidr_el1 // Get MPCore register - and x5, x4, #ARM_CORE_MASK // Get core number - and x4, x4, #ARM_CLUSTER_MASK // Get cluster number - - add x4, x5, x4, LSR #7 // Add scaled cluster number to core number - mov x6, x4 // Save a copy to compute mp-parking offset - - ldr x5, AsmMailboxBase // Get mailbox addr relative to PC - lsl x4, x4, 3 // Add 8-byte offset for this core - add x4, x4, x5 // - - ldr x5, AsmParkingBase // Get mp-parking addr relative to PC - lsl x6, x6, 12 // Add 4K-byte offset for this core - add x6, x6, x5 // - - mov x5, 1 // Get mp-parking id# at 2K offset - lsl x5, x5, 11 // - add x5, x5, x6 // - ldr x10, [x5] // - -1: ldr x5, [x4] // Load jump-addr from spin-table mailbox - cmp xzr, x5 // Has the value been set? - b.ne 4f // If so, break out of loop - - ldr x5, [x6] // Load mp-parking id# - cmp w10, w5 // Is it my id? - b.ne 2f // If not, continue polling - - ldr x5, [x6, 8] // Load jump-addr from mp-parking - cmp xzr, x5 // Has the value been set? - b.ne 3f // If so, break out of loop - -2: wfe // Wait a bit - b 1b // Wait over, check again - -3: str xzr, [x6, 8] // Clear to acknowledge - mov x0, x6 // Return mp-parking address -4: br x5 // Jump to new addr - -.align 3 // Make sure the variable below is 8 byte aligned. - .global AsmParkingBase -AsmParkingBase: .xword 0xdeaddeadbeefbeef - .global AsmMailboxBase -AsmMailboxBase: .xword 0xdeaddeadbeefbeef - -SecondariesPenEnd: From patchwork Tue May 15 17:37:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 135910 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1321182lji; Tue, 15 May 2018 10:37:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZodVtY37OLHE1/l64zXxaNzrvW47NFDJgAWoicXjSAl2iVLAYM69OmuBfNwS2HcFvG5VT9F X-Received: by 2002:a63:7043:: with SMTP id a3-v6mr12847067pgn.206.1526405875701; Tue, 15 May 2018 10:37:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526405875; cv=none; d=google.com; s=arc-20160816; b=jBaPLQMqH+xagtaFZwBeIxa5tLhTu2K8VmIT3RezCslfAOUpkya4JR3502SI3CE9T+ jSuhTFCj3Z+kPdIqEDGZDLA9dUPll4LbzJ+h6wdk+qWUsJVQL5a414e21KwUyZMdpXTM iS5HzIhvSjM9O1JeF2TZZsuuILSmcP8mD7Ljv5WLRvK/qaEqkreOiHzXusglPX8lxTLp picHa4dVvSyx6ELteianKYcaI1PEM/IkAIEu1RhYP0jVPNbLbU+VsIQzNSSQNDJ42VeE JOYX/KGQmNMzEk8F1AeUrbU8R9m8ga/TVYNCVyfgZlI+ehAlx6c631T/xsicNGXgJcMU hBRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=XXBWMoyys5We6GAVBFnURS7XYo5OYm9Gsm4el7ExWas=; b=aCm8WecCaXHDMjCYGoPvoMH6FgRdhaR9gsLph5Rqqjcy3DYhFP7PxE2WjSki/3SXzZ SzOOZ2hdesUCCqK81ig0PISejNL6T1/072hSpcYbOYSX/T4VQtQa7qXT6kkjWGYpXIG8 WIkRuwJ40lvo96rBoEbRWhDuFav6OVta3/bR/VDpKdJZa/BrtwNPIg/REyjBeZu9TGEn LfGsgkyCPZBq4B+kwtB5nZKtz+VKhNQQ/koF3EHq+XvwZ4jVka88V5nZMaj2bLBupG4L vTfqZt/xUffzMylyEnf75ktsUJc6U8nrE2VaxkoB96eBu/OJrcVycHIaOsRtGfM+BoNt /rcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EFHtlTNG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t18-v6si496750plr.240.2018.05.15.10.37.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EFHtlTNG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 92030209603E7; Tue, 15 May 2018 10:37:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 500FE20348632 for ; Tue, 15 May 2018 10:37:51 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id v60-v6so1003120wrc.7 for ; Tue, 15 May 2018 10:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z6UIXSs8PNpFoSJO2TkFmet98acvG2q4F3jghyfpuqA=; b=EFHtlTNGww9xbfcUUEfB4jGvmNfdwo3FSgCRwIP+Oo2h3tpDVOrxyGSJtfrgZd0Tu3 pT0vHp8i0LIaClKN6Rekh2+PkOYBYEQWDxmAwf2qsmrquZsiQ75g+tzzoMd7fDK1S8ni iqfl3X7ZIMsZrZZhTEPszPjMSstQbhDzmfQQ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z6UIXSs8PNpFoSJO2TkFmet98acvG2q4F3jghyfpuqA=; b=DSc/YGPUW7sCYK3EfepgPkgut6Iay9B7BFzHmQ+icCXqnc8yVA/ENY/ie0bXIg3vgr 9sJIAeFmt9xU5VExweZE2GZ4+3/baoWdqnSwQtD/Dqr+x38jYWQ6QZxsAjQFHVN4i0+f JSnEwrbzpMHfGivuvmD2KHOId7MtHU7fMrMSGrRvzKJnQjPKheIqqCbq1oVDl7RzFFmQ shSYjlpLBbpLk+G80qhhsGNH7tw7We1Gteh/OuwFN1uFtaRccbpWQJzFyBhXoqCukHb9 P9Ot41A21pGkjz3W3k2aMH5f/QMZaMmBd/2oAW33h6z4pf8GKXt+cGCP379Ol3L6pExj /0Vw== X-Gm-Message-State: ALKqPwfZNY1GppgtcgJNs9P1jlapzke8ivt6UzJ+pCPdDq6jV3JYHBX4 ns3Dw9URamocG8AbcDcE2CutLWJwQL4= X-Received: by 2002:adf:abab:: with SMTP id s40-v6mr12033178wrc.259.1526405869581; Tue, 15 May 2018 10:37:49 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:48 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:34 +0200 Message-Id: <20180515173736.29639-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/5] Silicon/AMD/Styx: remove support for the ACPI parking protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The ACPI parking protocol is a kludge to allow SOC implementations that lack EL3 support to bring up secondaries in a standardized manner. Since our UEFI implementation unconditionally relies on ARM Trusted Firmware and PSCI now, there is no point in supporting the parking protocol any longer so let's remove it. (Note also that the implementation of AmdStyxGetMpParkingBase is flawed, so it is unsure whether it has ever worked in reality) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 - Silicon/AMD/Styx/AcpiTables/Madt.c | 24 ++---------- Silicon/AMD/Styx/AmdStyx.dec | 4 -- Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h | 39 -------------------- Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h | 7 ---- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c | 21 ----------- 6 files changed, 3 insertions(+), 93 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index bff5be4673a4..4ae64ac22665 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -82,7 +82,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster - gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Depex] diff --git a/Silicon/AMD/Styx/AcpiTables/Madt.c b/Silicon/AMD/Styx/AcpiTables/Madt.c index 96182e790f98..43d415c8bc32 100644 --- a/Silicon/AMD/Styx/AcpiTables/Madt.c +++ b/Silicon/AMD/Styx/AcpiTables/Madt.c @@ -57,12 +57,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields #endif -#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion)) -#define PARKED_OFFSET ( 4096 ) - #define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster)) -#define PARKED_ADDRESS(Base, ClusterId, CoreId) \ - ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET) /* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */ @@ -73,7 +68,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; CpuNum, /* UINT32 CPUInterfaceNumber */ \ (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \ EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \ - PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ PerfInt, /* UINT32 PerformanceInterruptGsiv */ \ 0, /* UINT64 ParkedAddress */ \ GIC_BASE, /* UINT64 PhysicalBaseAddress */ \ @@ -194,8 +189,7 @@ BuildGicC ( EFI_ACPI_5_1_GIC_STRUCTURE *GicC, UINT32 CpuNum, UINT32 ClusterId, - UINT32 CoreId, - EFI_PHYSICAL_ADDRESS MpParkingBase + UINT32 CoreId ) { UINT32 MpId, PmuSpi; @@ -212,8 +206,6 @@ BuildGicC ( GicC->CPUInterfaceNumber = CpuNum; GicC->AcpiProcessorUid = MpId; GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED; - GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION; - GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId); GicC->PhysicalBaseAddress = GIC_BASE; GicC->GICV = GICV_BASE; GicC->GICH = GICH_BASE; @@ -281,8 +273,6 @@ MadtHeader ( ARM_CORE_INFO *ArmCoreInfoTable; UINTN CoreCount, CpuNum; EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; Status = gBS->LocateProtocol ( &gAmdMpCoreInfoProtocolGuid, @@ -299,13 +289,6 @@ MadtHeader ( ASSERT (CoreCount <= NUM_CORES); ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount)); - MpParkingSize = 0; - MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize); - if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) { - DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n")); - MpParkingBase = 0; - } - GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0]; AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); @@ -315,8 +298,7 @@ MadtHeader ( Status = BuildGicC (GicC, CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, - ArmCoreInfoTable[CpuNum].CoreId, - MpParkingBase + ArmCoreInfoTable[CpuNum].CoreId ); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index cffe1cafde8b..1eb1ce801e0b 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -28,7 +28,6 @@ [Ppis] gAmdStyxPlatInitPpiGuid = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } } [Protocols] - gAmdMpBootProtocolGuid = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } } gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } } [Guids] @@ -101,9 +100,6 @@ [PcdsFixedAtBuild] # UEFI entry point gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000 - # Parking Protocol - gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000 - # The original offset in memory of the NV store firmware volume, before # relocating it to a dynamically allocated buffer. We need this to correlate # flash accesses to the in-memory copy with LBAs in the actual SPI flash diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h deleted file mode 100644 index 2aa4c55ccbaf..000000000000 --- a/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @file - - Copyright (c) 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _AMD_MP_BOOT_H_ -#define _AMD_MP_BOOT_H_ - -extern EFI_GUID gAmdMpBootProtocolGuid; - -typedef -VOID -(EFIAPI *PARK_SECONDARY_CORE) ( - IN ARM_CORE_INFO *ArmCoreInfo, - IN EFI_PHYSICAL_ADDRESS SecondaryEntry - ); - -typedef struct _AMD_MP_BOOT_INFO { - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; - ARM_CORE_INFO *ArmCoreInfoTable; - UINTN ArmCoreCount; -} AMD_MP_BOOT_INFO; - -typedef struct _AMD_MP_BOOT_PROTOCOL { - PARK_SECONDARY_CORE ParkSecondaryCore; - AMD_MP_BOOT_INFO *MpBootInfo; -} AMD_MP_BOOT_PROTOCOL; - -#endif // _AMD_MP_BOOT_H_ diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h index 95f46e8af962..e6aa8fb1bec9 100644 --- a/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h +++ b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h @@ -30,16 +30,9 @@ EFI_STATUS OUT UINT32 *PmuSpi ); -typedef -EFI_PHYSICAL_ADDRESS -(EFIAPI *GET_MP_PARKING_BASE) ( - OUT UINTN *MpParkingSize - ); - typedef struct _AMD_MP_CORE_INFO_PROTOCOL { GET_ARM_CORE_INFO_TABLE GetArmCoreInfoTable; GET_PMU_SPI_FROM_MPID GetPmuSpiFromMpId; - GET_MP_PARKING_BASE GetMpParkingBase; } AMD_MP_CORE_INFO_PROTOCOL; #endif // _AMD_MP_CORE_INFO_H_ diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c index e713d5581925..68f97fb89148 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -29,11 +29,9 @@ #include #include -#include STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 }; -STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 }; STATIC @@ -49,12 +47,6 @@ AmdStyxGetPmuSpiFromMpId ( OUT UINT32 *PmuSpi ); -STATIC -EFI_PHYSICAL_ADDRESS -AmdStyxGetMpParkingBase ( - OUT UINTN *MpParkingSize - ); - #pragma pack(push, 1) typedef struct _PMU_INFO { @@ -101,7 +93,6 @@ PlatInitDxeEntryPoint ( // Install CoreInfo Protocol mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable; mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId; - mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase; Status = gBS->InstallProtocolInterface ( &Handle, &gAmdMpCoreInfoProtocolGuid, @@ -153,15 +144,3 @@ AmdStyxGetPmuSpiFromMpId ( return EFI_INVALID_PARAMETER; } - -STATIC -EFI_PHYSICAL_ADDRESS -AmdStyxGetMpParkingBase ( - OUT UINTN *MpParkingSize - ) -{ - ASSERT (MpParkingSize != NULL); - - *MpParkingSize = mAmdMpBootInfo.MpParkingBase; - return mAmdMpBootInfo.MpParkingBase; -} From patchwork Tue May 15 17:37:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 135911 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1321263lji; Tue, 15 May 2018 10:37:59 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpesZ+GbUHI3YcwN7ycZnXJNQuVELflq3SliUkPbtUwFDGN3EG6mBt3DvrFgjmrdTuGdZUg X-Received: by 2002:a17:902:7615:: with SMTP id k21-v6mr15037687pll.97.1526405879364; Tue, 15 May 2018 10:37:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526405879; cv=none; d=google.com; s=arc-20160816; b=KP7psxytF18jpcAUH2+DoRngpEcUlAlIu68EiLokih/fO+ZsGqY/bD9Hjw/et6QYg2 NXuCkr7bPxly80SHKhW9obgPb96XNEIhGKKA7ulzqN4KuQ2eqFMmR53OjHfNNwXu5mWs Q+uhfV0WMcZJ+B62rZa09+gv+Rwwxwfybd2bC26JL42GYAEvGYCi9JmL2nAga5hcdfrt gLzbLrv6Y7J+LixvcbRr/d0O8vDu4U7JN21xgCbowiTVyyLLTlUmKu1th7cBQhJz7ETk BD+y7967zNqq240fhQ5DT/059Uqs5uqZt5YTcpDUqPMrP2K8vY1pGQN4u4wnD89lDoQE WOcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=/YDcB38UtCndfmO0uAsm2OgrpwzDGITVBoiol1qiV6Y=; b=f10y7DbePF8ljeetnSwTpm8+DONUcl1IwOx+GSq/CWFb5O9s4bAhoR/o6EK36tpTcl AZRASyGjYMNoJYXdqK19VIkuOuH/Fk6G5QvFueyrbPvc3yweSi4o4Eb2KolhnHKIVO76 82warVXWN+q740REARXJfeBHQ4gZZ8d+ucDZ8hoSC8vLZCVhfqvcdNTmzHLvnFYLopWc a5ZYKx1SawwdjVTknbwInXNSdETdu7iseu8c9OwUzmn1bo+j4GgszTkLi130SeoNbaLx N6vu9MBVxpYccIkwhKdkrc//gp6PZNdT0OsQaA0+SgWZkhP3SXb/7xnTe16QgUhLmlkV Rf8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RZDIFtGG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id v20-v6si475062pff.363.2018.05.15.10.37.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RZDIFtGG; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BEAE42034863B; Tue, 15 May 2018 10:37:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B7909209603D9 for ; Tue, 15 May 2018 10:37:53 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id f8-v6so2641502wmc.4 for ; Tue, 15 May 2018 10:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jn0im5+tXL8rl51MlKrQb1X7aGSjULzplqKXrDuOk88=; b=RZDIFtGGqhQiQJpxIQ2WQtPj+pwJKeLP8WHEfwjeF8ijqcnxBArv3+7dXxJJdiitMY p0tT/WB1UAol4sV/xlPBWu7YZgGpHFm8yGT58/I34cNCH2CaEgRGI3vfiVIHwUer9T5E vmcaPoivgZ4tX63fG6S/EXbxRVa4KAchnxcBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jn0im5+tXL8rl51MlKrQb1X7aGSjULzplqKXrDuOk88=; b=H7wVqcklUBzKAXF2k2oGycK6SN9OXFz0bSWht9EFNkL8NQ1LjefORTgag6Y4vqkx6M ZrNTZZ4luh+eFHRZG2HstnHfD7i2TdTEKzBL72VQ4nOJcNHxygciKAqpYkjkoQJRQ0Ma 2fHWf3OXxOZCqxqCV//FJIAYJYg4q64hDlAQUFl94FjniWCGUjBixj++0pPbKdP1CuAL nD2n2TMQQj2Nwk6sxmBp6INRvzAifdvsdXKDq/UhQgEa+qjEAbzOE6Cgxe6jLvcYKvov c4hdetBRAGStpEwbAnVUmYFbzAto847yiDgRjsn3LFFlhbqjQPyoEB61Uq7ZYJPK2f8u gSbQ== X-Gm-Message-State: ALKqPwe53KcQ8y8TNwQAspVdq/xKLftSaW9tOFxQK7n/1zv/EhF8j4JQ 8g/a4nq6lOkIhmdIuZX8I+kJfMwgfZ4= X-Received: by 2002:a1c:e854:: with SMTP id f81-v6mr2037602wmh.14.1526405871517; Tue, 15 May 2018 10:37:51 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:50 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:35 +0200 Message-Id: <20180515173736.29639-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/5] Silicon/AMD/Styx: make ISCP dependency unconditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The Styx code can be built without relying on the ISCP, but doing so is rather pointless, and is essentially dead code because nobody ever does that. Let's just remove this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 7 -- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 2 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 7 -- Silicon/AMD/Styx/AmdStyx.dec | 3 - Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 120 +++++++++----------- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf | 1 - Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 40 ------- Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf | 1 - Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 2 - Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c | 16 +-- Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf | 3 - 11 files changed, 55 insertions(+), 147 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 26b91ca88a2c..7bc1ab937813 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -19,7 +19,6 @@ [Defines] DEFINE DO_XGBE = 1 DEFINE NUM_CORES = 8 -DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE DEFINE DO_CAPSULE = FALSE @@ -456,12 +455,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 -!if $(DO_ISCP) - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE -!endif - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 80b096ba5587..1acfe7e93fad 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -431,8 +431,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 8d50d78c30cd..8d0a5bdc5270 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -18,7 +18,6 @@ [Defines] DEFINE NUM_CORES = 4 -DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -427,12 +426,6 @@ [PcdsFixedAtBuild.common] ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -!if $(DO_ISCP) - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE -!endif - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index 1eb1ce801e0b..eeded93a32e2 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -91,9 +91,6 @@ [PcdsFixedAtBuild] gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002 - # ISCP - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000 - # Cores Per cluster gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000 diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 61e373406bcc..4ea1dd4b3577 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -140,64 +140,56 @@ PlatInitPeiEntryPoint ( mAmdCoreCount = PcdGet32 (PcdSocCoreCount); } - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi); - ASSERT_EFI_ERROR (Status); + Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi); + ASSERT_EFI_ERROR (Status); - // Get fuse information from ISCP - Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo); - ASSERT_EFI_ERROR (Status); + // Get fuse information from ISCP + Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo); + ASSERT_EFI_ERROR (Status); - CpuMap = IscpFuseInfo.SocConfiguration.CpuMap; - CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount; - CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8; + CpuMap = IscpFuseInfo.SocConfiguration.CpuMap; + CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount; + CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8; - ASSERT (CpuMap != 0); - ASSERT (CpuCoreCount != 0); - ASSERT (CpuCoreCount <= CpuMapSize); + ASSERT (CpuMap != 0); + ASSERT (CpuCoreCount != 0); + ASSERT (CpuCoreCount <= CpuMapSize); - // Update core count based on fusing - if (mAmdCoreCount > CpuCoreCount) { - mAmdCoreCount = CpuCoreCount; - } + // Update core count based on fusing + if (mAmdCoreCount > CpuCoreCount) { + mAmdCoreCount = CpuCoreCount; } // // Update per-core information from ISCP + // Walk CPU map to enumerate active cores // - if (!FixedPcdGetBool (PcdIscpSupport)) { - DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n")); - } else { - // - // Walk CPU map to enumerate active cores - // - for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) { - if (CpuMap & 1) { - CpuResetInfo.CoreNum = CoreNum; - Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction ( - PeiServices, &CpuResetInfo ); - ASSERT_EFI_ERROR (Status); - ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED); - ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED); - - mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId; - mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId; - - DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n", - Index, mAmdMpCoreInfoTable[Index].ClusterId, - mAmdMpCoreInfoTable[Index].CoreId)); - - // Next core in Table - ++Index; - } - // Next core in Map - CpuMap >>= 1; + for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) { + if (CpuMap & 1) { + CpuResetInfo.CoreNum = CoreNum; + Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction ( + PeiServices, &CpuResetInfo ); + ASSERT_EFI_ERROR (Status); + ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED); + ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED); + + mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId; + mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId; + + DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n", + Index, mAmdMpCoreInfoTable[Index].ClusterId, + mAmdMpCoreInfoTable[Index].CoreId)); + + // Next core in Table + ++Index; } + // Next core in Map + CpuMap >>= 1; + } - // Update core count based on CPU map - if (mAmdCoreCount > Index) { - mAmdCoreCount = Index; - } + // Update core count based on CPU map + if (mAmdCoreCount > Index) { + mAmdCoreCount = Index; } // Update SocCoreCount on Dynamic PCD @@ -212,14 +204,12 @@ PlatInitPeiEntryPoint ( // Get SystemMemorySize from ISCP IscpMemDescriptor.Size0 = 0; - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor); - ASSERT_EFI_ERROR (Status); + Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor); + ASSERT_EFI_ERROR (Status); - // Update SystemMemorySize on Dynamic PCD - if (IscpMemDescriptor.Size0) { - PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0); - } + // Update SystemMemorySize on Dynamic PCD + if (IscpMemDescriptor.Size0) { + PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0); } if (IscpMemDescriptor.Size0 == 0) { DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n")); @@ -229,19 +219,17 @@ PlatInitPeiEntryPoint ( #if DO_XGBE == 1 // Get MAC Address from ISCP - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiIscpPpi->ExecuteGetMacAddressTransaction ( - PeiServices, &MacAddrInfo ); - ASSERT_EFI_ERROR (Status); - - MacAddr0 = MacAddr1 = 0; - for (Index = 0; Index < 6; ++Index) { - MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8); - MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8); - } - PcdSet64 (PcdEthMacA, MacAddr0); - PcdSet64 (PcdEthMacB, MacAddr1); + Status = PeiIscpPpi->ExecuteGetMacAddressTransaction ( + PeiServices, &MacAddrInfo ); + ASSERT_EFI_ERROR (Status); + + MacAddr0 = MacAddr1 = 0; + for (Index = 0; Index < 6; ++Index) { + MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8); + MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8); } + PcdSet64 (PcdEthMacA, MacAddr0); + PcdSet64 (PcdEthMacB, MacAddr1); DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA))); DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB))); diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf index ccc079bebab2..b8829a4a9c3e 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -67,7 +67,6 @@ [Pcd] gAmdStyxTokenSpaceGuid.PcdEthMacB [FixedPcd] - gAmdStyxTokenSpaceGuid.PcdIscpSupport gAmdStyxTokenSpaceGuid.PcdCpuIdRegister [Depex] diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 4bf9fc39942f..bcb6e020a5fd 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -455,16 +455,7 @@ STATIC SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { 0, // ConfiguredMemoryClockSpeed; }; -#if (FixedPcdGetBool (PcdIscpSupport)) STATIC CHAR8 CONST *mMemDevInfoType17Strings[ 7 ] = {0}; -#else -STATIC CHAR8 CONST * CONST mMemDevInfoType17Strings[] = { - "OS Virtual Memory", - "malloc", - "OSV", - NULL -}; -#endif /*********************************************************************** SMBIOS data definition TYPE19 Memory Array Mapped Address Information @@ -648,7 +639,6 @@ ProcessorInfoUpdateSmbiosType4 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE4_SMBIOS_INFO *SmbiosT4 = &mSmbiosInfo.SmbiosCpuBuffer.T4[0]; DEBUG ((EFI_D_ERROR, "Logging SmbiosType4 from ISCP.\n")); @@ -671,22 +661,6 @@ ProcessorInfoUpdateSmbiosType4 ( &SmbiosT4->T4ProcId.ProcIDMsd, sizeof(UINT32)); CopyMem (&mProcessorInfoType4.Voltage, &SmbiosT4->T4Voltage, sizeof(UINT8)); -#else - mProcessorInfoType4.ProcessorType = CentralProcessor; - mProcessorInfoType4.ProcessorFamily = ProcessorFamilyIndicatorFamily2; - mProcessorInfoType4.ProcessorFamily2 = ProcessorFamilyARM; - #ifdef ARM_CPU_AARCH64 - mProcessorInfoType4.ProcessorCharacteristics = 0x6C; - #else - mProcessorInfoType4.ProcessorCharacteristics = 0x68; - #endif - mProcessorInfoType4.MaxSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz - mProcessorInfoType4.CurrentSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz - mProcessorInfoType4.CoreCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.EnabledCoreCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.ThreadCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.ProcessorUpgrade = ProcessorUpgradeDaughterBoard; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings); } @@ -700,7 +674,6 @@ CacheInfoUpdateSmbiosType7 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE7_SMBIOS_INFO *SmbiosT7; SMBIOS_TABLE_TYPE7 dstType7 = {{0}}; @@ -756,9 +729,6 @@ CacheInfoUpdateSmbiosType7 ( dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; dstType7.Associativity = SmbiosT7->T7Associativity; LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); -#else - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings); -#endif } /*********************************************************************** @@ -782,7 +752,6 @@ PhyMemArrayInfoUpdateSmbiosType16 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE16_SMBIOS_INFO *SmbiosT16 = &mSmbiosInfo.SmbiosMemBuffer.T16; DEBUG ((EFI_D_ERROR, "Logging SmbiosType16 from ISCP.\n")); @@ -791,7 +760,6 @@ PhyMemArrayInfoUpdateSmbiosType16 ( mPhyMemArrayInfoType16.Use = SmbiosT16->Use; mPhyMemArrayInfoType16.MemoryErrorCorrection = SmbiosT16->MemoryErrorCorrection; mPhyMemArrayInfoType16.NumberOfMemoryDevices = SmbiosT16->NumberOfMemoryDevices; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings); } @@ -805,7 +773,6 @@ MemDevInfoUpdatedstType17 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) SMBIOS_TABLE_TYPE17 dstType17 = {{0}}; ISCP_TYPE17_SMBIOS_INFO *srcType17; UINTN i, j, StrIndex, LastIndex; @@ -874,9 +841,6 @@ MemDevInfoUpdatedstType17 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType17, mMemDevInfoType17Strings); } } -#else - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings); -#endif } /*********************************************************************** @@ -888,7 +852,6 @@ MemArrMapInfoUpdateSmbiosType19 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE19_SMBIOS_INFO *SmbiosT19 = &mSmbiosInfo.SmbiosMemBuffer.T19; DEBUG ((EFI_D_ERROR, "Logging SmbiosType19 from ISCP.\n")); @@ -899,7 +862,6 @@ MemArrMapInfoUpdateSmbiosType19 ( mMemArrMapInfoType19.PartitionWidth = SmbiosT19->PartitionWidth; mMemArrMapInfoType19.ExtendedStartingAddress = SmbiosT19->ExtStartingAddr; mMemArrMapInfoType19.ExtendedEndingAddress = SmbiosT19->ExtEndingAddr; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings); } @@ -946,7 +908,6 @@ PlatformSmbiosDriverEntryPoint ( return Status; } -#if (FixedPcdGetBool (PcdIscpSupport)) Status = gBS->LocateProtocol ( &gAmdIscpDxeProtocolGuid, NULL, @@ -966,7 +927,6 @@ PlatformSmbiosDriverEntryPoint ( DEBUG ((EFI_D_ERROR, "Failed to get SMBIOS data via ISCP")); return Status; } -#endif BIOSInfoUpdateSmbiosType0(); diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf index 0027d79031d7..76521cbde59e 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -52,7 +52,6 @@ [Guids] [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz - gAmdStyxTokenSpaceGuid.PcdIscpSupport [Depex] gEfiSmbiosProtocolGuid AND diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index d17e6c26feb5..db7ce6af33d1 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -72,8 +72,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize - gAmdStyxTokenSpaceGuid.PcdIscpSupport - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c index 1b926242b5bb..11f398ad29e2 100644 --- a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c @@ -60,10 +60,6 @@ LibGetTime ( ISCP_RTC_INFO RtcInfo; EFI_STATUS Status; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_DEVICE_ERROR; - } - if (mRtcIscpDxeProtocol == NULL) { DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n")); return EFI_DEVICE_ERROR; @@ -111,10 +107,6 @@ LibSetTime ( EFI_STATUS Status; ISCP_RTC_INFO RtcInfo; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_DEVICE_ERROR; - } - // // Use Time, to set the time in your RTC hardware // @@ -213,10 +205,6 @@ LibRtcInitialize ( { EFI_STATUS Status; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_SUCCESS; - } - // // Do some initialization if required to turn on the RTC // @@ -268,9 +256,7 @@ LibRtcVirtualNotifyEvent ( // to virtual address. After the OS transistions to calling in virtual mode, all future // runtime calls will be made in virtual mode. // - if (FixedPcdGetBool (PcdIscpSupport)) { - EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol); - } + EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol); } diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf index cd9418c9b732..5392bd076cf0 100644 --- a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -41,9 +41,6 @@ [LibraryClasses] UefiRuntimeLib DxeServicesTableLib -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdIscpSupport - [Guids] gEfiEventVirtualAddressChangeGuid From patchwork Tue May 15 17:37:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 135912 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1321330lji; Tue, 15 May 2018 10:38:03 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoIbnwR2T6XzW9KpyElzvuq6fE/ZIxolB3DsSazuV4YVa4GAQoH/f5/op1bMrV36ZBL8kE+ X-Received: by 2002:a63:990a:: with SMTP id d10-v6mr13026172pge.166.1526405882922; Tue, 15 May 2018 10:38:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526405882; cv=none; d=google.com; s=arc-20160816; b=eqV2XCFFikv/4ciAjzx9VZpbf/55lqGbyZdpbMJW00XGUlVAkhSM3R3kcBAVZUBH+J WeTd06jsjSf5psr4i5k0FYLU2sSwVhJyE5YfMztmp+UvxXBSaJglsTh7p4sV6pnp1FIr LQ3VqEZZS+GuZVDNvoPEKFzIwBc88BQalYIXU0O019/EL0kj1oWNkyMUgwBMzEM9nlQK AGfYoDz+yFNtkf64fd8JRYLP+upZ/9dONEA4YWqxY5EKEp1WtiWR272iSZ+DHwncS9Qi FO63ArAkG3iZJAmYnuN32VRplzqVGKf8L8AwIXCBtGYeCoqBWGrjZYDgM/ErAELvIrY8 RfYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=/Ef8NayOLNXPRPp5VuRjLkZRZ8WyAblimF9SEBlZxVM=; b=pP1i+ACEWXNAViB12t3TzE3dKKgZkDCUiHObuFZU/ctI0HPGox/CMh9OfwpTJIzwZi O/uHkPnn2/VbLtmCISYe8v9y0a+8JcZmhPYaR+v2vognXVc5WvegcbpfUJSNNyzvYZv7 +wl9sSVEhnWJhjh5jW7wKEIBnUJye+S9d/t3jZKwAZPydqys5NTB+CBFmqm8KfeRkQWk 7XtAYxRgycIyCzou0CVHbdEnK1LAd90m6V9v66W0LtrHSFGaOerErWllpLxlk/xN9zeJ IbfvTL5UZxr/g4Vih1XbqxPpRuo+oq3kWi1cATS8fmL8IpM3KrfLX3RAuSWktOSzxav3 alRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=F2wumNv6; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id p7-v6si409158pgd.96.2018.05.15.10.38.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:38:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=F2wumNv6; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E5167203B8583; Tue, 15 May 2018 10:37:56 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 36F5F2034863A for ; Tue, 15 May 2018 10:37:55 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id g21-v6so998480wrb.8 for ; Tue, 15 May 2018 10:37:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=88jViZIedGxsLt7kELXLByYVGB9glpj7OGD31URZKLs=; b=F2wumNv6dhxGv6zIqg07tlWF2OtI7pgfkmCLH5MsciKy9dnT6tmJJPJuQ2Cz5ZbPgN AHzxU/tvAFlPA4nYJ6B/SoxUQF1I2ildlADIRuhqMt7tCyx0dFGOlM5LCBaROrStaNts bGRkp091gOPt/T6eLRWUW5TQaYOr+u/xz2ml8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=88jViZIedGxsLt7kELXLByYVGB9glpj7OGD31URZKLs=; b=A1ZLA4DRKMUEUKcSdM8aYFReq+LajwgdackXnuTUUBitu1NEhk9Knd0qRbCyUetw2V wzznkxyua732FMGgF1btvYP7Nq/rhuUR0v4wcHQglFZssM4TX1/nqpSpW/Bajr09hpGU No43CgYihcx4XJtilpFRviRz3M+mEYY1QjXbRia3Q4KwUx/mLykWBsT6TL7yWOEqGHjb AcfMrQplxSLt3dSgE6uCopsFSjGY8fxTORMl9swGGHa2PrlJog6ou62hRYto0krI9ZmF dr7ucZHpuK4WTFSstDJwdEaJZHxsGr2h6W91JwVFAdU9T8CUT5Bq0o220gUYlV2XRkx6 7t5Q== X-Gm-Message-State: ALKqPwf7aCxkIYMZIFk4AIl2RtllF6ouuXeeNhZBfPWCm2R9kUaltJn3 rVOVjO1xIilnVyJ4ycSJZHZjjmC+feQ= X-Received: by 2002:adf:87d4:: with SMTP id c20-v6mr11298983wrc.197.1526405873607; Tue, 15 May 2018 10:37:53 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:52 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 15 May 2018 19:37:36 +0200 Message-Id: <20180515173736.29639-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/5] Platform/AMD/Overdrive: enable support for NVME PCIe devices X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk, neko@bakuhatsu.net, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Upon request, add the generic NvmExpress driver to the Overdrive build so plugin NVME SSDs can be supported at boot. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 1 + Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 1 + 2 files changed, 2 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 7bc1ab937813..5e564f66b824 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -621,6 +621,7 @@ [Components.common] ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf # # AHCI Support diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index 1ed32f68ef9d..97894aa8482d 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -161,6 +161,7 @@ [FV.FvMain] INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf # # AHCI Support