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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t127-v6si28093759pgc.519.2018.05.30.20.10.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LCSltt6t; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 73DFF210C999E; Wed, 30 May 2018 20:10:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4ADD420965DC7 for ; Wed, 30 May 2018 20:10:23 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id v24-v6so12312416plo.3 for ; Wed, 30 May 2018 20:10:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T6Tcq4WtZva2i/n5lhRAHiNmunOsRktJ3uTaebKCPvI=; b=LCSltt6tgxV+m03bFrbB/aywPF3XX8jlnZEJAYE6grZAAvOzA9LT1ySi+DJ+Yd7bvr kJqCZUSZkdmbafBLc6CFBbQavdxi6lwWjWYhPhcphxpziiTrBtNX5GP92MnOZ1NcO7vK 2hWTssQk34gAnbCPGuVg+mPMYgPEph2CerxIE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T6Tcq4WtZva2i/n5lhRAHiNmunOsRktJ3uTaebKCPvI=; b=TLyStrQdizYc6C5dOBx8Ahno89/tkFK1fz8cYcXqxfjVTwfMajWZc80rV6ZNhAuNMc /kAOF5wLDKi8FioFYIZQR9btgmsVIvrjX5eDPUO8vnMIocLMMvM/6vT5TW9SPhtcYHw+ U6rV+Isbjv4MHukAoQH5NcFdjQ1moyFy6l5i2umYJpOxreQmsxWybHgUtsCIkdfpWLJr BSZDbF68EyMzsAXV/3N9IEI5bMmM+g++crnekA3whkjJ4GgobNjEgxOpAaREqBOto2bX 7F5RfaiaLntEyACoH9HZvQleKNb82n52+853FpVt0PzRSXVktZ0ddc4UqsqhXeX/bj6c QDDA== X-Gm-Message-State: ALKqPwerGCS1SqPWo4GHpGAZVp9+5ryCznlszkvIjiVLcGeXFLnqpIRx TpIzqv1CH8Uj2lm3FWS87LMTxMnboao= X-Received: by 2002:a17:902:8:: with SMTP id 8-v6mr5188130pla.287.1527736222598; Wed, 30 May 2018 20:10:22 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:21 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:05 +0800 Message-Id: <1527736210-17133-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 1/6] Platform/Hisilicon/HiKey960: add gpio platform driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add gpio platform driver to enable GPIO in HiKey960 platform. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 1 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 1 + Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf | 35 +++++++++ Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c | 83 ++++++++++++++++++++ 4 files changed, 120 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 36f43956ab40..3da1b8556321 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -179,6 +179,7 @@ [Components.common] # # GPIO # + Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index 655032a36c53..162dbaaf2646 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -120,6 +120,7 @@ [FV.FvMain] # # GPIO # + INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf new file mode 100644 index 000000000000..5ea3747321d8 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2018, Linaro. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKey960GpioDxe + FILE_GUID = 6aa12592-7e36-4aec-acf8-2ac2fd13815c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKey960GpioEntryPoint + +[Sources] + HiKey960GpioDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + +[Protocols] + gPlatformGpioProtocolGuid + +[Depex] + TRUE diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c new file mode 100644 index 000000000000..b196455072cc --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c @@ -0,0 +1,83 @@ +/** @file +* +* Copyright (c) 2018, Linaro. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +GPIO_CONTROLLER gGpioDevice[] = { + // + // { base address, gpio index, gpio count } + // + { 0xe8a0b000, 0, 8 }, // GPIO0 + { 0xe8a0c000, 8, 8 }, // GPIO1 + { 0xe8a0d000, 16, 8 }, // GPIO2 + { 0xe8a0e000, 24, 8 }, // GPIO3 + { 0xe8a0f000, 32, 8 }, // GPIO4 + { 0xe8a10000, 40, 8 }, // GPIO5 + { 0xe8a11000, 48, 8 }, // GPIO6 + { 0xe8a12000, 56, 8 }, // GPIO7 + { 0xe8a13000, 64, 8 }, // GPIO8 + { 0xe8a14000, 72, 8 }, // GPIO9 + { 0xe8a15000, 80, 8 }, // GPIO10 + { 0xe8a16000, 88, 8 }, // GPIO11 + { 0xe8a17000, 96, 8 }, // GPIO12 + { 0xe8a18000, 104, 8 }, // GPIO13 + { 0xe8a19000, 112, 8 }, // GPIO14 + { 0xe8a1a000, 120, 8 }, // GPIO15 + { 0xe8a1b000, 128, 8 }, // GPIO16 + { 0xe8a1c000, 136, 8 }, // GPIO17 + { 0xff3b4000, 144, 8 }, // GPIO18 + { 0xff3b5000, 152, 8 }, // GPIO19 + { 0xe8a1f000, 160, 8 }, // GPIO20 + { 0xe8a20000, 168, 8 }, // GPIO21 + { 0xfff0b000, 176, 8 }, // GPIO22 + { 0xfff0c000, 184, 8 }, // GPIO23 + { 0xfff0d000, 192, 8 }, // GPIO24 + { 0xfff0e000, 200, 8 }, // GPIO25 + { 0xfff0f000, 208, 8 }, // GPIO26 + { 0xfff10000, 216, 8 }, // GPIO27 + { 0xfff1d000, 224, 8 }, // GPIO28 +}; + +PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { + // + // { global gpio count, gpio controller count, GPIO_CONTROLLER } + // + 232, 29, gGpioDevice +}; + +EFI_STATUS +EFIAPI +HiKey960GpioEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // Install the Embedded Platform GPIO Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, + NULL + ); + if (EFI_ERROR(Status)) { + Status = EFI_OUT_OF_RESOURCES; + } + + return Status; +} From patchwork Thu May 31 03:10:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 137312 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp6067604lji; Wed, 30 May 2018 20:10:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIai7k3ctzm56GM9f+YrKsiB5DbQEt3sARPLpe1/tiO2X/YEv5LsF8X4gfC5HDPJL1crQGD X-Received: by 2002:a17:902:aa4b:: with SMTP id c11-v6mr5266500plr.17.1527736229090; Wed, 30 May 2018 20:10:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527736229; cv=none; d=google.com; s=arc-20160816; b=cjAwXgz4T7GHtLnZpVcH56iO/sxTDhWzIk4tmxwjnk8ggRMHcwbhXpzfnJd5er4dNy x8+USZAfSUdo4IRrxhS/eX/+oSX8OEzWHmbMn3R0JmzANg1AzQOko//2kS76hs3+Tsvm CPcVRPDU4Gj3vtie2sf5GmDYk0skTUFrj8LEvm9dGtDH6ixhmuIbYQbpZSmD71Uftst4 8idivvY8+lrMtm7cajPJbbqWHFMZhvua68C55UotWcLKOTtLXqXsaD2+ktFydYHiIIqT mOC/Yd3QPf3t/DlbF3i41Eol76g2MUNT4Sgw8IliFSJrY9Gwf2O40tRn1+ookXPkfgVt r36A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=Kl+hs7T8punOC08iNl54dWTAZbX5NVLvkz/pVp1FmJY=; b=GT3phQS8MyD6ZnWDhlbnUjZTc4bZO4aNlHZkmMU8zUg5W2M8SN0sN70B52URHoxCm+ aKPbjlvICYaLk2eIPH81Lvm02ewEYmhPvgTwL6KS/yvTD/CVdvRtEeeFpSvVSSKOLzf2 vnr4EzDMHqoLurfQPSHI+rqFS0izWC2aSZSq9E0JRyUQZ6IvRgr2betWJlIEwbklTvT3 ruH8hqVYaURl+RIED9VHCRK+exu0e66ceTIk66b2rqjfSKOLply36UVwbzv2Fka0QbmI Ly2qxAJWx+Q+1o2frrzH0X+iS5jI7uYFcjaF+eshHf7aCub4ac5Sm1OLK53dBADvmPl0 vvSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RVytGp+H; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id i13-v6si8519006pgp.341.2018.05.30.20.10.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RVytGp+H; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AD355210CEA20; Wed, 30 May 2018 20:10:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D469C20965DC7 for ; Wed, 30 May 2018 20:10:26 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id 30-v6so12294222pld.13 for ; Wed, 30 May 2018 20:10:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KU2IRD2VqWFosbXLlqhF5xX4zdWBUgqlTv71oISv4sg=; b=RVytGp+Hx3Qlvxh9ciZy9/v3M4PHC11UJMyGTGLafvZaUhmxrMM5/ZdGnHvHU24UKb 9jlwOF2dvAI5+IIbobI3e86jVEhdTTThRrEYgHbQYiZtH+nAdf4BftVKBV5eO2Ik7FVD 3KpIRSLCD72VKvLisidg8HrgBiglDXW/E/ij8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KU2IRD2VqWFosbXLlqhF5xX4zdWBUgqlTv71oISv4sg=; b=BaY9t7ydKt86bYHj329BPO8pJH2MriDxaF4kWqKu96MdKb4wPyYbHxMQiIMHMQ4N2A iTAmFoNUKPL9/WrB/k8/jkeYRhiExHqyd923ox8Q2bF5hQKjMjiAgTJppRNkAOVq8+33 uBf8FlA/8dryjSfYDwt7JV1cnxLKuO8vZMEdBRY4byL+tVWHmNcVNR+S+SLwlZ5Zk3T/ YW1sJTKYKx6gIo20z2xW/KmUUX4oEcHJ3w+nrX2ssYPpVPND+3+9Ey/ysJD5+dt1HINU FziKfO6bSVreENR/tpoX1ojEUHVJGbTJs1OyW/3l9uPRdxTg42fHTNcDgRii+TwOZ/ME NrRw== X-Gm-Message-State: ALKqPwf4Gc+iKXY3Y84nLTqSwiZSsTLgnunxWy2iSNn3x1TvxqfXGwYT T3IIzmcECFSNaUn33xgNB4xqdxZbS2w= X-Received: by 2002:a17:902:780a:: with SMTP id p10-v6mr5280661pll.281.1527736225900; Wed, 30 May 2018 20:10:25 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:24 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:06 +0800 Message-Id: <1527736210-17133-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 2/6] Platform/HiKey960: do basic initialization X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Do some basic initliazation on peripherals, such as pins and regulators. The hardcoding code is taken from non-open reference code. Can't fix it for lack of documents. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Silicon/Hisilicon/Hi3660/Hi3660.dec | 32 +++ Platform/Hisilicon/HiKey960/HiKey960.dsc | 2 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 2 + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 47 +++++ Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h | 23 +++ Silicon/Hisilicon/Hi3660/Include/Hi3660.h | 195 ++++++++++++++++++ Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 212 ++++++++++++++++++++ 7 files changed, 513 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Hi3660/Hi3660.dec b/Silicon/Hisilicon/Hi3660/Hi3660.dec new file mode 100644 index 000000000000..72de61e0635c --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Hi3660.dec @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x0001001a + PACKAGE_NAME = Hi3660 + PACKAGE_GUID = e457ba7c-faba-4dea-b274-f5962d016c79 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gHi3660TokenSpaceGuid = { 0x4abc73fa, 0x8a49, 0x4d2c, { 0x95, 0x44, 0x17, 0x87, 0x29, 0x06, 0x20, 0xb4 } } diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 3da1b8556321..6cc1c1edf453 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -182,6 +182,8 @@ [Components.common] Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index 162dbaaf2646..b7d70b010598 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -123,6 +123,8 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf new file mode 100644 index 000000000000..a1a7d005ce8b --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -0,0 +1,47 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKey960Dxe + FILE_GUID = 6d824b2c-640e-4643-b9f2-9c09e8bff429 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKey960EntryPoint + +[Sources.common] + HiKey960Dxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/Hi3660/Hi3660.dec + +[LibraryClasses] + BaseMemoryLib + CacheMaintenanceLib + DxeServicesTableLib + IoLib + PcdLib + TimerLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h new file mode 100644 index 000000000000..ae8bdd5c8140 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h @@ -0,0 +1,23 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HIKEY960DXE_H__ +#define __HIKEY960DXE_H__ + +enum { + BOOT_MODE_RECOVERY = 0, + BOOT_MODE_MASK = 1, +}; + +#endif /* __HIKEY960DXE_H__ */ diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h new file mode 100644 index 000000000000..5fbf32267657 --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h @@ -0,0 +1,195 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HI3660_H__ +#define __HI3660_H__ + +#define HKADC_SSI_REG_BASE 0xE82B8000 + +#define PCTRL_REG_BASE 0xE8A09000 + +#define PCTRL_CTRL3 (PCTRL_REG_BASE + 0x010) +#define PCTRL_CTRL24 (PCTRL_REG_BASE + 0x064) + +#define PCTRL_CTRL3_USB_TXCO_EN (1 << 1) +#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL (1 << 25) + +#define SCTRL_REG_BASE 0xFFF0A000 + +#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) +#define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0) + +#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C) + +#define USB3OTG_BC_REG_BASE 0xFF200000 + +#define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000) +#define USB3OTG_CTRL2 (USB3OTG_BC_REG_BASE + 0x008) +#define USB3OTG_CTRL3 (USB3OTG_BC_REG_BASE + 0x00C) +#define USB3OTG_CTRL4 (USB3OTG_BC_REG_BASE + 0x010) +#define USB3OTG_CTRL6 (USB3OTG_BC_REG_BASE + 0x018) +#define USB3OTG_CTRL7 (USB3OTG_BC_REG_BASE + 0x01C) +#define USB3OTG_PHY_CR_STS (USB3OTG_BC_REG_BASE + 0x050) +#define USB3OTG_PHY_CR_CTRL (USB3OTG_BC_REG_BASE + 0x054) + +#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN (1 << 15) +#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP (1 << 1) +#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP (1 << 0) +#define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6) +#define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5) +#define USB3OTG_CTRL7_REF_SSP_EN (1 << 16) +#define USB3OTG_PHY_CR_DATA_OUT(x) (((x) & 0xFFFF) << 1) +#define USB3OTG_PHY_CR_ACK (1 << 0) +#define USB3OTG_PHY_CR_DATA_IN(x) (((x) & 0xFFFF) << 4) +#define USB3OTG_PHY_CR_WRITE (1 << 3) +#define USB3OTG_PHY_CR_READ (1 << 2) +#define USB3OTG_PHY_CR_CAP_DATA (1 << 1) +#define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) + +#define PMU_REG_BASE 0xFFF34000 +#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x068 << 2)) +#define LDO9_VSET_MASK (7 << 0) + +#define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2)) +#define LDO16_ONOFF_ECO_LDO16_ENABLE BIT1 +#define LDO16_ONOFF_ECO_ECO_ENABLE BIT0 + +#define PMIC_LDO16_VSET_REG (PMU_REG_BASE + (0x079 << 2)) +#define LDO16_VSET_MASK (7 << 0) + +#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) +#define PMIC_OSC32K_ONOFF_CTRL (PMU_REG_BASE + (0x0CC << 2)) + +#define PMIC_HARDWARE_CTRL0_WIFI_CLK (1 << 5) +#define PMIC_OSC32K_ONOFF_CTRL_EN_32K (1 << 1) + + +#define CRG_REG_BASE 0xFFF35000 + +#define CRG_PEREN0 (CRG_REG_BASE + 0x000) +#define CRG_PEREN2 (CRG_REG_BASE + 0x020) +#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) +#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) +#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) +#define CRG_PEREN4 (CRG_REG_BASE + 0x040) +#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) +#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) +#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) +#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) +#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) +#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) +#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) +#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) +#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) +#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) +#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) +#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) +#define CRG_CLKDIV4 (CRG_REG_BASE + 0x0B8) +#define CRG_ISOEN (CRG_REG_BASE + 0x144) +#define CRG_ISODIS (CRG_REG_BASE + 0x148) +#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) + +#define PERI_UFS_BIT (1 << 12) +#define PERI_ARST_UFS_BIT (1 << 7) + +#define PEREN0_GT_HCLK_SD BIT30 + +#define PEREN2_HKADCSSI BIT24 + +#define PEREN4_GT_CLK_SD BIT17 +#define PEREN4_GT_ACLK_USB3OTG (1 << 1) +#define PEREN4_GT_CLK_USB3OTG_REF (1 << 0) + +#define PERRSTEN2_HKADCSSI BIT24 + +#define PERRSTEN4_SD BIT18 + +#define PERRSTEN4_USB3OTG_MUX (1 << 8) +#define PERRSTEN4_USB3OTG_AHBIF (1 << 7) +#define PERRSTEN4_USB3OTG_32K (1 << 6) +#define PERRSTEN4_USB3OTG (1 << 5) +#define PERRSTEN4_USB3OTGPHY_POR (1 << 3) + +#define PERISOEN_USB_REFCLK_ISO_EN (1 << 25) + +#define CLKDIV4_SC_SEL_SD_MASK (7 << 4) +#define CLKDIV4_SC_DIV_SD_MASK 0xf +#define CLKDIV4_SC_MASK_SHIFT 16 +#define CLKDIV4_SC_SEL_SD(x) (((x) & 0x7) << 4) +#define CLKDIV4_SC_DIV_SD(x) ((x) & 0xf) + +#define CRG_CLKDIV16_OFFSET 0x0E8 +#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9) +#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) + +#define CRG_CLKDIV17_OFFSET 0x0EC +#define SC_DIV_UFS_PERIBUS (1 << 14) + +#define IOMG_MMC0_REG_BASE 0xFF37E000 +#define IOMG_MMC0_000_REG (IOMG_MMC0_REG_BASE + 0x000) +#define IOMG_MMC0_001_REG (IOMG_MMC0_REG_BASE + 0x004) +#define IOMG_MMC0_002_REG (IOMG_MMC0_REG_BASE + 0x008) +#define IOMG_MMC0_003_REG (IOMG_MMC0_REG_BASE + 0x00C) +#define IOMG_MMC0_004_REG (IOMG_MMC0_REG_BASE + 0x010) +#define IOMG_MMC0_005_REG (IOMG_MMC0_REG_BASE + 0x014) + +#define IOCG_MMC0_REG_BASE 0xFF37E800 +#define IOCG_MMC0_000_REG (IOCG_MMC0_REG_BASE + 0x000) +#define IOCG_MMC0_001_REG (IOCG_MMC0_REG_BASE + 0x004) +#define IOCG_MMC0_002_REG (IOCG_MMC0_REG_BASE + 0x008) +#define IOCG_MMC0_003_REG (IOCG_MMC0_REG_BASE + 0x00C) +#define IOCG_MMC0_004_REG (IOCG_MMC0_REG_BASE + 0x010) +#define IOCG_MMC0_005_REG (IOCG_MMC0_REG_BASE + 0x014) + +#define IOMG_AO_REG_BASE 0xFFF11000 +#define IOMG_AO_006_REG (IOMG_AO_REG_BASE + 0x018) + +#define IOMG_FUNC0 0 +#define IOMG_FUNC1 1 +#define IOCG_PULLUP BIT0 +#define IOCG_PULLDOWN BIT1 +#define IOCG_DRIVE(x) ((x) << 4) + +#define UFS_SYS_REG_BASE 0xFF3B1000 + +#define UFS_SYS_PSW_POWER_CTRL_OFFSET 0x004 +#define UFS_SYS_PHY_ISO_EN_OFFSET 0x008 +#define UFS_SYS_HC_LP_CTRL_OFFSET 0x00C +#define UFS_SYS_PHY_CLK_CTRL_OFFSET 0x010 +#define UFS_SYS_PSW_CLK_CTRL_OFFSET 0x014 +#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET 0x018 +#define UFS_SYS_RESET_CTRL_EN_OFFSET 0x01C +#define UFS_SYS_MONITOR_HH_OFFSET 0x03C +#define UFS_SYS_UFS_SYSCTRL_OFFSET 0x05C +#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET 0x060 +#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET 0x064 + +#define BIT_UFS_PSW_ISO_CTRL (1 << 16) +#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) +#define BIT_UFS_REFCLK_ISO_EN (1 << 16) +#define BIT_UFS_PHY_ISO_CTRL (1 << 0) +#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) +#define BIT_SYSCTRL_PWR_READY (1 << 8) +#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_SYSCTRL_LP_RESET_N (1 << 0) +#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0) +#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET (1 << 16) +#define BIT_UFS_DEVICE_RESET (1 << 0) + +#endif /* __HI3660_H__ */ diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c new file mode 100644 index 000000000000..e88bad2167c6 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -0,0 +1,212 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "HiKey960Dxe.h" + +STATIC +VOID +InitSdCard ( + IN VOID + ) +{ + UINT32 Data; + + // + // LDO16 + // 000: 1.75V, 001: 1.8V, 010: 2.4V, 011: 2.6V, 100: 2.7V, + // 101: 2.85V, 110: 2.95V, 111: 3.0V. + // + Data = MmioRead32 (PMIC_LDO16_VSET_REG) & LDO16_VSET_MASK; + Data |= 6; + MmioWrite32 (PMIC_LDO16_VSET_REG, Data); + MmioOr32 (PMIC_LDO16_ONOFF_ECO_REG, LDO16_ONOFF_ECO_LDO16_ENABLE); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // LDO9 + // 000: 1.75V, 001: 1.8V, 010: 1.825V, 011: 2.8V, 100: 2.85V, + // 101: 2.95V, 110: 3.0V, 111: 3.3V. + // + Data = MmioRead32 (PMIC_LDO9_VSET_REG) & LDO9_VSET_MASK; + Data |= 5; + MmioWrite32 (PMIC_LDO9_VSET_REG, Data); + MmioOr32 (PMU_REG_BASE + (0x6a << 2), 2); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // GPIO203 + // + MmioWrite32 (IOMG_AO_REG_BASE + (24 << 2), 0); // GPIO function + + // + // SD pinmux + // + MmioWrite32 (IOMG_MMC0_000_REG, IOMG_FUNC1); // SD_CLK + MmioWrite32 (IOMG_MMC0_001_REG, IOMG_FUNC1); // SD_CMD + MmioWrite32 (IOMG_MMC0_002_REG, IOMG_FUNC1); // SD_DATA0 + MmioWrite32 (IOMG_MMC0_003_REG, IOMG_FUNC1); // SD_DATA1 + MmioWrite32 (IOMG_MMC0_004_REG, IOMG_FUNC1); // SD_DATA2 + MmioWrite32 (IOMG_MMC0_005_REG, IOMG_FUNC1); // SD_DATA3 + MmioWrite32 (IOCG_MMC0_000_REG, IOCG_DRIVE (15)); // SD_CLK float with 32mA + MmioWrite32 (IOCG_MMC0_001_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_CMD + MmioWrite32 (IOCG_MMC0_002_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA0 + MmioWrite32 (IOCG_MMC0_003_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA1 + MmioWrite32 (IOCG_MMC0_004_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA2 + MmioWrite32 (IOCG_MMC0_005_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA3 + + // + // SC_SEL_SD: + // 0xx: 3.2MHz, 100: PPLL0, 101: PPLL1, 11x: PPLL2. + // SC_DIV_SD: + // divider = value + 1 + // + do { + MmioOr32 ( + CRG_CLKDIV4, + CLKDIV4_SC_SEL_SD (7) | + (CLKDIV4_SC_SEL_SD_MASK << CLKDIV4_SC_MASK_SHIFT) + ); + Data = MmioRead32 (CRG_CLKDIV4) & CLKDIV4_SC_SEL_SD_MASK; + } while (Data != CLKDIV4_SC_SEL_SD (7)); + + // + // Unreset SD controller + // + MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_SD); + do { + Data = MmioRead32 (CRG_PERRSTSTAT4); + } while ((Data & PERRSTEN4_SD) == PERRSTEN4_SD); + // + // Enable SD controller clock + // + MmioOr32 (CRG_PEREN0, PEREN0_GT_HCLK_SD); + MmioOr32 (CRG_PEREN4, PEREN4_GT_CLK_SD); + do { + Data = MmioRead32 (CRG_PERCLKEN4); + } while ((Data & PEREN4_GT_CLK_SD) != PEREN4_GT_CLK_SD); +} + +VOID +InitPeripherals ( + IN VOID + ) +{ + // + // Enable FPLL0 + // + MmioOr32 (SCTRL_SCFPLLCTRL0, SCTRL_SCFPLLCTRL0_FPLL0_EN); + + InitSdCard (); + + // + // Enable wifi clock + // + MmioOr32 (PMIC_HARDWARE_CTRL0, PMIC_HARDWARE_CTRL0_WIFI_CLK); + MmioOr32 (PMIC_OSC32K_ONOFF_CTRL, PMIC_OSC32K_ONOFF_CTRL_EN_32K); +} + +/** + Notification function of the event defined as belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in + the entry point of the driver. + + This function is called when an event belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an + event is signalled once at the end of the dispatching of all + drivers (end of the so called DXE phase). + + @param[in] Event Event declared in the entry point of the driver whose + notification function is being invoked. + @param[in] Context NULL +**/ +STATIC +VOID +OnEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINT32 BootMode; + CHAR8 Buf[64]; + UINTN Count; + + BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK; + if (BootMode == BOOT_MODE_RECOVERY) { + Count = AsciiSPrint ( + Buf, + 64, + "WARNING: CAN NOT BOOT KERNEL IN RECOVERY MODE!\n" + ); + SerialPortWrite ((UINT8 *)Buf, Count); + Count = AsciiSPrint ( + Buf, + 64, + "Switch to normal boot mode, then reboot to boot kernel.\n" + ); + SerialPortWrite ((UINT8 *)Buf, Count); + } +} + +EFI_STATUS +EFIAPI +HiKey960EntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + InitPeripherals (); + + // + // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. + // The "OnEndOfDxe()" function is declared as the call back function. + // It will be called at the end of the DXE phase when an event of the + // same group is signalled to inform about the end of the DXE phase. + // Install the INSTALL_FDT_PROTOCOL protocol. + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} From patchwork Thu May 31 03:10:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 137313 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp6067627lji; Wed, 30 May 2018 20:10:32 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKtQ1EUhS7U8Ee1btRGZSTBpeYw8szEMhF9uhjp/aM9agnNL6M47FMS7SvkIldLZByX3g9g X-Received: by 2002:a63:85c8:: with SMTP id u191-v6mr3944557pgd.300.1527736232268; Wed, 30 May 2018 20:10:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527736232; cv=none; d=google.com; s=arc-20160816; b=f8uER+vYzfoYQ6u6Ir3cFPGL+D05h/5Q0679oE3DSGH6uOK3x+pqx3VofATx6M/icH nBwGwhBPHUmRp0Q59ayCQv2Pw1ph/aXhzLAe252t+m9hH6gm44rv10Wy5kwycFta0eYg 7XrOf3ecWLQkQO0tBlQ1jymrJgpi6IuCOnOHa3RTLozwiCCgYrz1lAZOfjLKF+2FMoWM WggXahgFLeqM1js5UsuZGlDxEbueYRDe9hU2X+TjIWz0/NJqSIcKrWn/nNW227T9JDlD pS7fEd9AqB4/leHvJxFaqf2THCYJQs0eSueZBWnwO5TFNabNob/nrWx8yDslmPIj357b jsQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=5rA4bjWm0CYBG4yGIWUToV0pqbJg+Y6AyCkOKPz6zF4=; b=AK/8MztrOpwWP6RfbzAHHbKMMU2pqta6lCgHrTyVdw8H6sPxArhx4sHSEJXnV36iyu 2l7FXdkvt2nWuJQA6ZPKPte3+LIduuSq8wn0b9bF7amYtTptJ1O+gdywYu+uQH1Bogz0 K5WxseVfynIi4KICLoiXEW6S3ayYNZSp1nmSqsWFSyaf4QVjaxr9XihDjAPzhuuG14oU MMKuHsrSF0EC/zp0lrWH19SFmCS2cxDeu3hU/b0UpcZjKEDlAeJYYtseB2hlUMWLPXHB TN/7Qt3GLakOp69Q01Ug4AoD84rBs0U75ZSp55JnPnDRoi291+YW1+G0zy33powXWbrV HvXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O8d/y9gw; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id q28-v6si14184945pgc.672.2018.05.30.20.10.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O8d/y9gw; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DD011210CEA2D; Wed, 30 May 2018 20:10:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 70A6520965DC7 for ; Wed, 30 May 2018 20:10:30 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id 30-v6so12294306pld.13 for ; Wed, 30 May 2018 20:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nv4iC6LHzM7SAQ3TkxuB5XSpLwelhxdA0ihcL47IQKs=; b=O8d/y9gwlqmCnP4V/B9iKaHA6PzOhN4rkj5YuJTBcg/xPdwUQVUoHM2nvG0vTupdqv PzjBH5OiAWaYNTlTJNOy+Utyh8xKIKZs8Qlh5bjisGJ15UV+6uwjSpClvuYVkgEthzR8 J4vSAQQcKTJCnPEXAoMbFNRRZVjggEp5cYvWk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nv4iC6LHzM7SAQ3TkxuB5XSpLwelhxdA0ihcL47IQKs=; b=Ygu/oFUIsAxBN63CGAP6MCCORT9gWfkLa4vJIUgT5dHnFaAPeODyRq0RzID6SF0zHM X9mWd5bQN0+puUBz/jwvJUNB1OKPVvhFU1Lh56DYIllC1mEyzs4GPGfoWY0ektBqyglB OHX6bGFVJAG/7x9nPJvaecILe71tGYEIW28dslYz6+rBgoPoz1oa7hg1478f5zXQlGVE VEHibLBaV9mUAvAKjgPifQk3AsKZYtiPO0V7zZlElbCdqmG+P4fn1c+/Q316LZ/1XJdv Dq0Ulsk1P7WXKPPcxnr6B504I6vmTSpITUVFeacOT3gQMZjqqNO+R8BrTPKKHXbgzXmD 6DfA== X-Gm-Message-State: ALKqPwdi7Wl57XH4iyoYIKIAXxqEuW2H9H/8JLfkNFnVE2wRObdAkpmJ Atnu5ribRgC9Rh+Z1689B2c9V740/aQ= X-Received: by 2002:a17:902:694b:: with SMTP id k11-v6mr5292248plt.334.1527736229729; Wed, 30 May 2018 20:10:29 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:28 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:07 +0800 Message-Id: <1527736210-17133-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 3/6] Platform/HiKey960: enable virtual keyboard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable virtual keyboard on HiKey960 platform. It checks two conditions, such as pattern in memory and GPIO pin setting. Since code is ported from non-open The hardcoding code is taken from non-open reference code. Can't fix it for lack of documents. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 5 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 5 + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 1 + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h | 24 +++++ Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 97 ++++++++++++++++++++ 5 files changed, 132 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 6cc1c1edf453..79e68754976d 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -182,6 +182,11 @@ [Components.common] Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index b7d70b010598..d65f77878575 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -123,6 +123,11 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf index a1a7d005ce8b..46a9a5803e3d 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -39,6 +39,7 @@ [LibraryClasses] [Protocols] gEmbeddedGpioProtocolGuid + gPlatformVirtualKeyboardProtocolGuid [Guids] gEfiEndOfDxeEventGroupGuid diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h index ae8bdd5c8140..211eea55aa54 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h @@ -15,6 +15,30 @@ #ifndef __HIKEY960DXE_H__ #define __HIKEY960DXE_H__ +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define ADB_REBOOT_ADDRESS 0x32100000 +#define ADB_REBOOT_BOOTLOADER 0x77665500 +#define ADB_REBOOT_NONE 0x77665501 + +#define DETECT_SW_FASTBOOT 68 // GPIO8_4 + enum { BOOT_MODE_RECOVERY = 0, BOOT_MODE_MASK = 1, diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c index e88bad2167c6..13d6dda680c6 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -28,6 +28,8 @@ #include "HiKey960Dxe.h" +STATIC EMBEDDED_GPIO *mGpio; + STATIC VOID InitSdCard ( @@ -180,6 +182,94 @@ OnEndOfDxe ( EFI_STATUS EFIAPI +VirtualKeyboardRegister ( + IN VOID + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gEmbeddedGpioProtocolGuid, + NULL, + (VOID **) &mGpio + ); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardReset ( + IN VOID + ) +{ + EFI_STATUS Status; + + if (mGpio == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Configure GPIO68 as GPIO function + // + MmioWrite32 (0xe896c108, 0); + Status = mGpio->Set (mGpio, DETECT_SW_FASTBOOT, GPIO_MODE_INPUT); + return Status; +} + +BOOLEAN +EFIAPI +VirtualKeyboardQuery ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + EFI_STATUS Status; + UINTN Value = 0; + + if ((VirtualKey == NULL) || (mGpio == NULL)) { + return FALSE; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + goto Done; + } else { + Status = mGpio->Get (mGpio, DETECT_SW_FASTBOOT, &Value); + if (EFI_ERROR (Status) || (Value != 0)) { + return FALSE; + } + } +Done: + VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; + VirtualKey->Key.ScanCode = SCAN_NULL; + VirtualKey->Key.UnicodeChar = L'f'; + return TRUE; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardClear ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + if (VirtualKey == NULL) { + return EFI_INVALID_PARAMETER; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); + WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); + } + return EFI_SUCCESS; +} + +PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { + VirtualKeyboardRegister, + VirtualKeyboardReset, + VirtualKeyboardQuery, + VirtualKeyboardClear +}; + +EFI_STATUS +EFIAPI HiKey960EntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable @@ -208,5 +298,12 @@ HiKey960EntryPoint ( if (EFI_ERROR (Status)) { return Status; } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gPlatformVirtualKeyboardProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtualKeyboard + ); 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[198.145.21.10]) by mx.google.com with ESMTPS id 91-v6si16137799ple.308.2018.05.30.20.10.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ODdcAPu4; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 19DA0210CEA32; Wed, 30 May 2018 20:10:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4EBB1203B9933 for ; Wed, 30 May 2018 20:10:33 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id v24-v6so12312673plo.3 for ; Wed, 30 May 2018 20:10:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UfM9VVdW5mLrxHwxXP01+KxijK5rjdhIXeZHvjh6yJs=; b=ODdcAPu43miNcMUp82IXOvKYqzFsKy8gpYhQTTYmNZ4+gxQXMaeCAA9mnCv/Q/O9ua ThAqBLgqzkZuVLO8ZZduNgTR1gRLOAHzFSNHVdmjf1ESeqUtHPpRjSSC8+fSUfV946H2 1VwI4bcLV4hosyEQ9mn2EfaCRz0aRTPqhWO8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UfM9VVdW5mLrxHwxXP01+KxijK5rjdhIXeZHvjh6yJs=; b=d+tRCKH1qTn8xiuI5uUfLOhVuy9acY9v2tgJu51s0Dhjq/mxvhgXgI2PlVHsl812ol f5JQbzJSWNHnC6lhJ0ISmnxFtqwA/a1QqHvbgSHDKX2e1umaJX95KQJLbpMPfEuw42lh ThuOTezS5ozDQn8oc3NnzPtbKlxI4NCD6cXZzRlmcpSs3O9nybYM87Q27YkaGdeW1559 bpwcD+MfKJyGnIzT2ST7supv1tPZqXvfRYCOH5x1VzcrJvD4VYjUrhBJBt819oaL2egr USijIIMAlu4yXs6LR+N1t1R26nLAXHtsYJ3DPTnG7eGYXkhOUqcZXWggG3rGYKDiXucC 1ZKg== X-Gm-Message-State: ALKqPwc4RDduqCsBOHeHMnZX0celh+6gZFx2wMgjKXn4SAghs96K23WT MmFBde8a0lfxRVp0bCDAxn9/WBbDh3o= X-Received: by 2002:a17:902:c5:: with SMTP id a63-v6mr5285852pla.149.1527736232711; Wed, 30 May 2018 20:10:32 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:31 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:08 +0800 Message-Id: <1527736210-17133-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 4/6] Platform/Hisilicon/HiKey: add gpio platform driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add gpio platform driver to enable GPIO in HiKey platform. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf | 36 ++++++++++ Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c | 74 ++++++++++++++++++++ 2 files changed, 110 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf new file mode 100644 index 000000000000..2791b9f44cad --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf @@ -0,0 +1,36 @@ +# +# Copyright (c) 2018, Linaro. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKeyGpio + FILE_GUID = b51a851c-7bf7-463f-b261-cfb158b7f699 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKeyGpioEntryPoint + +[Sources.common] + HiKeyGpioDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + UefiDriverEntryPoint + +[Protocols] + gPlatformGpioProtocolGuid + +[Depex] + TRUE diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c new file mode 100644 index 000000000000..be535f8f1903 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2018, Linaro. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +GPIO_CONTROLLER gGpioDevice[] = { + // + // { base address, gpio index, gpio count } + // + { 0xf8011000, 0, 8 }, // GPIO0 + { 0xf8012000, 8, 8 }, // GPIO1 + { 0xf8013000, 16, 8 }, // GPIO2 + { 0xf8014000, 24, 8 }, // GPIO3 + { 0xf7020000, 32, 8 }, // GPIO4 + { 0xf7021000, 40, 8 }, // GPIO5 + { 0xf7022000, 48, 8 }, // GPIO6 + { 0xf7023000, 56, 8 }, // GPIO7 + { 0xf7024000, 64, 8 }, // GPIO8 + { 0xf7025000, 72, 8 }, // GPIO9 + { 0xf7026000, 80, 8 }, // GPIO10 + { 0xf7027000, 88, 8 }, // GPIO11 + { 0xf7028000, 96, 8 }, // GPIO12 + { 0xf7029000, 104, 8 }, // GPIO13 + { 0xf702a000, 112, 8 }, // GPIO14 + { 0xf702b000, 120, 8 }, // GPIO15 + { 0xf702c000, 128, 8 }, // GPIO16 + { 0xf702d000, 136, 8 }, // GPIO17 + { 0xf702e000, 144, 8 }, // GPIO18 + { 0xf702f000, 152, 8 } // GPIO19 +}; + +PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { + // + // { global gpio count, gpio controller counter, GPIO_CONTROLLER } + // + 160, 20, gGpioDevice +}; + +EFI_STATUS +EFIAPI +HiKeyGpioEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // Install the Embedded Platform GPIO Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, + NULL + ); + if (EFI_ERROR(Status)) { + Status = EFI_OUT_OF_RESOURCES; + } + + return Status; +} From patchwork Thu May 31 03:10:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 137315 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp6067733lji; Wed, 30 May 2018 20:10:40 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLPRMzAKV72VSHYfWwuW+gEWiSEyxjpddLQ2YbzKBfHurfIGVsyM0GL7bhJwyZaIBA+Dvn4 X-Received: by 2002:a17:902:8f84:: with SMTP id z4-v6mr5337317plo.194.1527736240196; Wed, 30 May 2018 20:10:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527736240; cv=none; d=google.com; s=arc-20160816; b=XUbUQMYLDdhYe9GlEEu5Xw+ca9oYsxPxhwyuqoDmRy5zcx0Unrfc2lp0LyXn3FYs0S CUOWuB/M3L9Rib18y0A0t3oRLdl9JJdHa9Tyq+sRxhRsTJrBDIzQV6K33x5PmP257j9g XX4whURTvcBy7ORt+JsABm8nb1h/jaIt5xPVdF+KlAh2fZ41gwhBZ33f82mQBO7eBJkO XL1k3oDCAgoFxKRUilASHcUZrTPWuIt7kloftPHnIWfjhxxMPtTor+dUAUSxZ1Sfx+jX FcCK6rEzKgqhkIn0MHgn4n6t14XCCEiU9CxSTvs+TTCQF0DJmhwIW07Rf9SZ7KRBw/q7 NvhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=mwFAbjaxmByrnbSMpfRcGJ7/RBc4awl7ngoYM+xBrNM=; b=rOLVMLwFmnXMxr/D6zuwIGOfkoMVB1/mOnaDNL7BbbenJHn+AHl6IKYhv2nzz/6QuD X40FwjZi6Cn85iCD5BRTaERSoaCti39FkpS0praon26tHokIajTBxyeFb5J1meIUntA2 eI19kGdpdjko2rVfLiMnJ3KTdfMRXKkqPkMjvhUD9/Sf+RUVtqTYXpMjq/6BsJGgETtq +2b5RsIcYsW2jEj4sbnCbURu1nzLO8+3Qoz/EIHMNf2Y4s3zL7RebwfTfZm07VrE2EHy 6gjluJTIixooceXPAn5jV04hinZADuvc8mg9GNhDBs+67g9dI+yPMyLJiufBtLfUQng0 Fc3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=g8ZxD2NU; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id l11-v6si27273262pgp.426.2018.05.30.20.10.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=g8ZxD2NU; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4D98820965DC7; Wed, 30 May 2018 20:10:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9E96B20965DC7 for ; Wed, 30 May 2018 20:10:36 -0700 (PDT) Received: by mail-pf0-x242.google.com with SMTP id p19-v6so5790792pff.13 for ; Wed, 30 May 2018 20:10:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OyuIYiCX6p6IGqzN2G70BKr180FlClD5A1zzibWt6XA=; b=g8ZxD2NUVkzZYQi4Zn+Vlv2/RllDgLhaIkpgYXzHPy5KGMqYDJl035Kxi26ZRwGv/d TDBfpcBYa2ArS3kTn8Eg/Yi73ok89yA7eiVsQwBGUJ8HAgJUsk4pCjeuP3KaqxDtp+sW AwV8KSnxMikUth28vUqoRr6hXgIb4teDHI5FQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OyuIYiCX6p6IGqzN2G70BKr180FlClD5A1zzibWt6XA=; b=TEFCmIh98746LVwQql0iAuqYVS5+6BKkE0879h0aybftlsChzCZK1UdLNBPpFs81OQ kcJRKJBdsyT8ywK0CEbhyYjbnZQav5SKRV1it2GD1DBF1OuOOxSVETlApFeOD2WrGaL5 ws6CE6UJWnhJgMNpKHTcZ/qz1PTmPjLEDSHruDfskwOSxvCVXwQm36ZXnOnq1GGQZWc3 QWbdPPXL8veEZB3JyKaTnKU3kjBnYIfC9OofAProETW0MNX+jpXvEQtT4KzJSQdq0Vg/ yTnrE4J7RFBzzOE91kr9hYtUSmyRcYWvEUGHNUEVxXM8idSl4tF0wDAVCJ2ClnZUKqO0 VgBg== X-Gm-Message-State: ALKqPwc75G9NVNptSpsO9KByT4BBlPY3Eptu4FkFkq7/9uOVhMhoq8Qw 4MyVIV+YkeqD1TglGErzpZs2Q4Qitls= X-Received: by 2002:a63:2547:: with SMTP id l68-v6mr4274230pgl.40.1527736235851; Wed, 30 May 2018 20:10:35 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:34 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:09 +0800 Message-Id: <1527736210-17133-6-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 5/6] Platform/HiKey: do basic initialization on hikey X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Do some basic initialization on HiKey platform, such as pin setting, regulators and making peripherals out of reset mode. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey/HiKey.dsc | 3 + Platform/Hisilicon/HiKey/HiKey.fdf | 3 + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf | 40 +++++++ Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h | 24 +++++ Silicon/Hisilicon/Hi6220/Include/Hi6220.h | 6 ++ Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h | 50 +++++++++ Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c | 109 ++++++++++++++++++++ 7 files changed, 235 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc index 5c1604d7f689..5cc4ff27f01b 100644 --- a/Platform/Hisilicon/HiKey/HiKey.dsc +++ b/Platform/Hisilicon/HiKey/HiKey.dsc @@ -189,8 +189,11 @@ [Components.common] # # GPIO # + Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf + # # MMC/SD # diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf index 2a5c5a4d6e79..39020d27dbcd 100644 --- a/Platform/Hisilicon/HiKey/HiKey.fdf +++ b/Platform/Hisilicon/HiKey/HiKey.fdf @@ -120,8 +120,11 @@ [FV.FvMain] # # GPIO # + INF Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + INF Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf + # # Multimedia Card Interface # diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf new file mode 100644 index 000000000000..34734391b45a --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf @@ -0,0 +1,40 @@ +# +# Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKeyDxe + FILE_GUID = f567684b-1089-4214-8881-d64b20cbda2f + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKeyEntryPoint + +[Sources.common] + HiKeyDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + IoLib + UefiLib + UefiDriverEntryPoint + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h new file mode 100644 index 000000000000..104048135f27 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.h @@ -0,0 +1,24 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HIKEYDXE_H__ +#define __HIKEYDXE_H__ + +#define DETECT_J15_FASTBOOT 24 // GPIO3_0 + +#define ADB_REBOOT_ADDRESS 0x05F01000 +#define ADB_REBOOT_BOOTLOADER 0x77665500 +#define ADB_REBOOT_NONE 0x77665501 + +#endif /* __HIKEYDXE_H__ */ diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h index 203424adfc8b..9b2508955772 100644 --- a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h +++ b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h @@ -23,6 +23,12 @@ #define HI6220_PERIPH_BASE 0xF4000000 #define HI6220_PERIPH_SZ 0x05800000 +#define IOMG_BASE 0xF7010000 +#define IOMG_080_REG (IOMG_BASE + 0x140) + +#define IOCG_BASE 0xF7010800 +#define IOCG_084_REG (IOCG_BASE + 0x150) + #define PERI_CTRL_BASE 0xF7030000 #define SC_PERIPH_CTRL4 0x00C #define CTRL4_FPGA_EXT_PHY_SEL BIT3 diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h new file mode 100644 index 000000000000..0db8af37d2d0 --- /dev/null +++ b/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h @@ -0,0 +1,50 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HI6220_REGS_PERI_H__ +#define __HI6220_REGS_PERI_H__ + +#define SC_PERIPH_CLKEN3 0x230 +#define SC_PERIPH_RSTEN3 0x330 +#define SC_PERIPH_RSTDIS0 0x304 +#define SC_PERIPH_RSTDIS3 0x334 +#define SC_PERIPH_RSTSTAT3 0x338 + +/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ +#define PERIPH_RST0_MMC2 (1 << 2) + +/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ +#define PERIPH_RST3_CSSYS (1 << 0) +#define PERIPH_RST3_I2C0 (1 << 1) +#define PERIPH_RST3_I2C1 (1 << 2) +#define PERIPH_RST3_I2C2 (1 << 3) +#define PERIPH_RST3_I2C3 (1 << 4) +#define PERIPH_RST3_UART1 (1 << 5) +#define PERIPH_RST3_UART2 (1 << 6) +#define PERIPH_RST3_UART3 (1 << 7) +#define PERIPH_RST3_UART4 (1 << 8) +#define PERIPH_RST3_SSP (1 << 9) +#define PERIPH_RST3_PWM (1 << 10) +#define PERIPH_RST3_BLPWM (1 << 11) +#define PERIPH_RST3_TSENSOR (1 << 12) +#define PERIPH_RST3_DAPB (1 << 18) +#define PERIPH_RST3_HKADC (1 << 19) +#define PERIPH_RST3_CODEC_SSI (1 << 20) +#define PERIPH_RST3_PMUSSI1 (1 << 22) + +#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) +#define PMUSSI_ONOFF8_REG (PMUSSI_BASE + (0x1c << 2)) +#define PMUSSI_ONOFF8_EN_32KB BIT6 + +#endif /* __HI6220_REGS_PERI_H__ */ diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c new file mode 100644 index 000000000000..8c752e06499c --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c @@ -0,0 +1,109 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +#include +#include + +#include "HiKeyDxe.h" + +STATIC +VOID +UartInit ( + IN VOID + ) +{ + UINT32 Val; + + /* make UART1 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1); + /* make UART2 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2); + /* make UART3 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3); + /* make UART4 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4); + + /* make DW_MMC2 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2); + + /* enable clock for BT/WIFI */ + Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB; + MmioWrite32 (PMUSSI_ONOFF8_REG, Val); +} + +STATIC +VOID +MtcmosInit ( + IN VOID + ) +{ + UINT32 Data; + + /* enable MTCMOS for GPU */ + MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D); + do { + Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0); + } while ((Data & PW_EN0_G3D) == 0); +} + +EFI_STATUS +HiKeyInitPeripherals ( + IN VOID + ) +{ + UINT32 Data, Bits; + + /* make I2C0/I2C1/I2C2/SPI0 out of reset */ + Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | \ + PERIPH_RST3_SSP; + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits); + + do { + Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3); + } while (Data & Bits); + + UartInit (); + /* MTCMOS -- Multi-threshold CMOS */ + MtcmosInit (); + + /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */ + MmioWrite32 (IOCG_084_REG, 0); /* configure GPIO24 as nopull */ + MmioWrite32 (IOMG_080_REG, 0); /* configure GPIO24 as GPIO */ + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +HiKeyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = HiKeyInitPeripherals (); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} From patchwork Thu May 31 03:10:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 137316 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp6067763lji; Wed, 30 May 2018 20:10:44 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKsKCVxR4rO/27XvT0phjnKmpUG5yYEf74YzHeBrRwnU9aqZ0P7ghpgEdRWp6aRw7wSeb7K X-Received: by 2002:a63:7a49:: with SMTP id j9-v6mr4110026pgn.353.1527736244596; Wed, 30 May 2018 20:10:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527736244; cv=none; d=google.com; s=arc-20160816; b=wQqh6+2z/vF08PWs3n+QcO44cfWI6RUO7QlmXxxdkCJZwpos50JAzpvdKQ49dLymO8 LWu+ZWaerTvqTy7ws9F4gJKoaeeCXfD15QMKblnqwl6dUG9gBigX+IZWsWmj4Ue9Sz1K P1TCizEFuPiEs2/yr/h337vV/Lh0KM13Pq5ShO6JMBQ+TByT9RWCLZvJosBNzST3V8Hq RgKjpPMBwvcXHXPKeV15D5eowgOzt2LBBldQ6y5c99JpZBECsgw+bKb/9OxIBPOo1MF7 S2qyp3LE5JeAIjh//2IKdMYv5nlgrRWHK0UAG1xuvzzxmMfyUoR2+hR9AaYCcc48tfvJ XP6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=nbAKPf5AG4SPvGjlcFFOepKpv0xjg+cOmok7AW6kOcI=; b=PB8QCwtAowzmZ2hCrR0o4GKCggLWLAnXvkY7U5NmJb7oAjK2Ojo8AEZgN4ewHUAT5g l9faCNoc6K7aRaWBBHdlHPUaxOIWqpxOwWEhrZaPTTQlC9lSvoxlrFIS5Kdrak/5rKVN XtVCmZ81yEiOsDRptaAAmJEfQlmvMSYpkydS2bbA5L1SLic998BiWyVKzWUetOwwDTqf Pge3xdkkG+a+L0dEv0VKZAc0VxLdfwZrHfUbqmOArassWfscFxlFDMHISr44+MpUy+cX gA8JosgjoDSZD9Z1bCcQx9/Zc5V6MAxf2jUDrNI81eXY/Lm9+nLx5aZlg14hNMvUBnBl mtvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GFLDTY/P; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id a6-v6si13543935pgd.579.2018.05.30.20.10.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 20:10:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GFLDTY/P; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 980D2209859B5; Wed, 30 May 2018 20:10:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 659D82098C20D for ; Wed, 30 May 2018 20:10:39 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id c41-v6so12294886plj.10 for ; Wed, 30 May 2018 20:10:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g0BLZj9RLJ2WCXwS+YhJcktPYZ40k7D5I0i5K8ImEdM=; b=GFLDTY/PTVuVd/Kuxz2eQ0zNm6iDpsxi4/bqMbC2BevdICX4t/R7ZCQRuT9p4juBA3 E1qsm7By65A1TBI3JaGAAztiA0WK0MM64L5MOpD0xLuP94Iwd0jfjW2lYdL1q8w2UdcU 8L7lqcWYR+SGBkjWwwGuhkNRd4Scsfsa80fwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g0BLZj9RLJ2WCXwS+YhJcktPYZ40k7D5I0i5K8ImEdM=; b=iqh2Rr21y0N2PvlFOFUbo2shukwqPd407jEeNDf4RQiFzQbtzA6yue/aqrFldUYnwk K6XHSgS7qrGlsTHV0+mkvbnpMUIjjsu6tSqNtky/fAKPpKB7kL33I3tEBBNGcfFjVe/w 9a74egTkXgPS5XOhwOlq8u7LAqfOu+Ea0ZTxJee33IhwwwzHcQspkZyFGXSeHu40l9tS L2TspiHrKX/Z/lmK4SjPgpBfZvT9oRpZCkWqvP8/GvVTfE2r35k7MxCSKnw4dKgusjBO NZb/oie6AZcAZQffIbVv6JUs9S0l0xf7foyG8kBEKFFR2VXHRDbh+E2BHmbimK3puMLg nLNw== X-Gm-Message-State: ALKqPwe+aT8fyzdXo8lgQMw1t8akeRjWRWNyZ7tBmWSGqVTAzVXmh46C EH2oPMq2yrOMOureXi/ZdyyOklnmdYw= X-Received: by 2002:a17:902:b417:: with SMTP id x23-v6mr5367815plr.388.1527736238846; Wed, 30 May 2018 20:10:38 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.182]) by smtp.gmail.com with ESMTPSA id q75-v6sm77114646pfj.94.2018.05.30.20.10.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 May 2018 20:10:37 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Thu, 31 May 2018 11:10:10 +0800 Message-Id: <1527736210-17133-7-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> References: <1527736210-17133-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH v7 edk-platforms 6/6] Platform/HiKey: enable virtual keyboard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable virtual keyboard on HiKey platform. It detects the pattern in memory and GPIO pin setting, and simulates them into virtual key. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/HiKey/HiKey.dsc | 5 + Platform/Hisilicon/HiKey/HiKey.fdf | 5 + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf | 5 + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c | 98 ++++++++++++++++++++ 4 files changed, 113 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc index 5cc4ff27f01b..83dd68a820b1 100644 --- a/Platform/Hisilicon/HiKey/HiKey.dsc +++ b/Platform/Hisilicon/HiKey/HiKey.dsc @@ -192,6 +192,11 @@ [Components.common] Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf # diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf index 39020d27dbcd..2bca7232b6e5 100644 --- a/Platform/Hisilicon/HiKey/HiKey.fdf +++ b/Platform/Hisilicon/HiKey/HiKey.fdf @@ -123,6 +123,11 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + INF Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf # diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf index 34734391b45a..41aa7f8081ed 100644 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf @@ -28,11 +28,16 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + CacheMaintenanceLib DebugLib IoLib UefiLib UefiDriverEntryPoint +[Protocols] + gEmbeddedGpioProtocolGuid + gPlatformVirtualKeyboardProtocolGuid + [Guids] gEfiEndOfDxeEventGroupGuid diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c index 8c752e06499c..832615f9cc80 100644 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c @@ -12,10 +12,15 @@ * **/ +#include #include #include +#include #include +#include +#include + #include #include @@ -50,6 +55,8 @@ UartInit ( MmioWrite32 (PMUSSI_ONOFF8_REG, Val); } +STATIC EMBEDDED_GPIO *mGpio; + STATIC VOID MtcmosInit ( @@ -94,6 +101,90 @@ HiKeyInitPeripherals ( EFI_STATUS EFIAPI +VirtualKeyboardRegister ( + IN VOID + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gEmbeddedGpioProtocolGuid, + NULL, + (VOID **) &mGpio + ); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardReset ( + IN VOID + ) +{ + EFI_STATUS Status; + + if (mGpio == NULL) { + return EFI_INVALID_PARAMETER; + } + Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT); + return Status; +} + +BOOLEAN +EFIAPI +VirtualKeyboardQuery ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + EFI_STATUS Status; + UINTN Value = 0; + + if ((VirtualKey == NULL) || (mGpio == NULL)) { + return FALSE; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + goto Done; + } else { + Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value); + if (EFI_ERROR (Status) || (Value != 0)) { + return FALSE; + } + } +Done: + VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; + VirtualKey->Key.ScanCode = SCAN_NULL; + VirtualKey->Key.UnicodeChar = L'f'; + return TRUE; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardClear ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + if (VirtualKey == NULL) { + return EFI_INVALID_PARAMETER; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); + WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); + } + return EFI_SUCCESS; +} + +PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { + VirtualKeyboardRegister, + VirtualKeyboardReset, + VirtualKeyboardQuery, + VirtualKeyboardClear +}; + +EFI_STATUS +EFIAPI HiKeyEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable @@ -105,5 +196,12 @@ HiKeyEntryPoint ( if (EFI_ERROR (Status)) { return Status; } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gPlatformVirtualKeyboardProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtualKeyboard + ); return Status; }