From patchwork Wed May 5 21:37:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AE13C43460 for ; Wed, 5 May 2021 21:38:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED10A613E3 for ; Wed, 5 May 2021 21:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbhEEVjC (ORCPT ); Wed, 5 May 2021 17:39:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231376AbhEEVjC (ORCPT ); Wed, 5 May 2021 17:39:02 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16E59C061763 for ; Wed, 5 May 2021 14:38:05 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so1734735pjv.1 for ; Wed, 05 May 2021 14:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vuvuy1+AT+Se+Ymw219J/gL7FUpA6VquAVOTuh+g8Jc=; b=uLOLtUcD3/U1CPx3mWyktMgcU6UbmGRwzeLDy4y7Ko+ItOTBeVT4QOjivBXuALBv1Z 54HWe0iEGbQEYyCBJ2mM+dIUqEYuwoHRv23IcpltCHEvUpbB5mV9o8YEfzyF4fgTmAgc VpMDp2zXpdU3XunQJKlaiAld9JzGfl4jL6hSmsebXSmPtAHp8oLn6lkNmJQOOH1UOYR1 X3Zfyb3GZ5j2F8pkHhMtaKjToe4oOhPvurX6uYcrBUvghfzKbouG4B/adKZ+hGJKWag+ RzJvBrTqmA0OQNcq7P/Pp3MOjBIrVbbawH1TIpNtswND6IsjO09IT2KuU4BdtxZOXbJu RumA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vuvuy1+AT+Se+Ymw219J/gL7FUpA6VquAVOTuh+g8Jc=; b=o+1/GGnTSi1Ij7FYmXijYpCaHI3wamGKk7IiS0ViSLR0Ng1/MHrSwV1/aHLgNJ6rMJ kLUPGPOQFO3IRAN9LAjxtQrHFI7TSsJlU7mNpfPDaSbrLIQOtc9yC7vj+nvVKa5gvQsR cpjrcwS3pDBZCbExxEO64jtthaEBMWe4T0sBAlVS4t1wc7+3HPFj75dZo3hCTpkX9R7V yqEhDnyVobbI3D/GYiFgqqQSbC3Mna+oKMqg3fMfcXel5u5Ywy+i/v+BfCHeUhgQT9gP MZGEEvvTdpMWm8nk4GrjRNPKK284zb1nKFHgD6LWVMoLzpIv0TpLrwb7639av5FEkdVt AD0w== X-Gm-Message-State: AOAM5328lanKvPqeljSuU5+S5i2A/kTHsmi5uyAwfni+82+oBAuZSsj2 96joALK/DcATOeW8nr85rDWDFw== X-Google-Smtp-Source: ABdhPJzgyvFxC589Qe4/bKRPP1/ndf0oUgZck9SproAnrE2LdXa+IqmozDQT9VjeQ6MEgdjPA6HmGA== X-Received: by 2002:a17:90a:e643:: with SMTP id ep3mr13636722pjb.194.1620250684644; Wed, 05 May 2021 14:38:04 -0700 (PDT) Received: from localhost.localdomain.name ([223.235.141.68]) by smtp.gmail.com with ESMTPSA id z26sm167031pfq.86.2021.05.05.14.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 14:38:04 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 01/17] dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties Date: Thu, 6 May 2021 03:07:15 +0530 Message-Id: <20210505213731.538612-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add new optional properties - 'interconnects' and 'interconnect-names' to the device-tree binding documentation for qcom-bam DMA IP. These properties describe the interconnect path between bam and main memory and the interconnect type respectively. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt index cf5b9e44432c..077242956ff2 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt @@ -13,12 +13,16 @@ Required properties: - clock-names: must contain "bam_clk" entry - qcom,ee : indicates the active Execution Environment identifier (0-7) used in the secure world. + +Optional properties: - qcom,controlled-remotely : optional, indicates that the bam is controlled by remote proccessor i.e. execution environment. - num-channels : optional, indicates supported number of DMA channels in a remotely controlled bam. - qcom,num-ees : optional, indicates supported number of Execution Environments in a remotely controlled bam. +- interconnects : Interconnect path between bam and main memory. +- interconnect-names: should be "memory". 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[23.128.96.18]) by mx.google.com with ESMTP id o20si612438pgv.200.2021.05.05.14.38.17; Wed, 05 May 2021 14:38:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iBQAa1NK; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232658AbhEEVjK (ORCPT + 3 others); Wed, 5 May 2021 17:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233841AbhEEVjH (ORCPT ); Wed, 5 May 2021 17:39:07 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AD0DC061761 for ; Wed, 5 May 2021 14:38:11 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id g24so1663915pji.4 for ; Wed, 05 May 2021 14:38:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G8+gYdiVbmjOwjaPy7U2TKEE4QviaMAH4q5NozXKn0Q=; b=iBQAa1NKgpUgni9h2YA6oy4Dn8VunyJlqmjKKrxMQ3nQ6IbaEFRXGLYlYp+pgZz5fT 4juD1l4LNyQyKEfwDt5lQ1qbmSyVPZRXOWH5t/g9PfGAmBDOVnQCoKTHQe4w6xJfgngd +UgsZOvjPV96U8y5firvnk35d14xflagdpdkrwzEX850NrG+kUIU4ydsTX7Cug/bQjfQ Q80OH4+HkkBX3vI35IfBIRTH9Xf5Y7n3baFScUzxxT6Xw05G4T7nRrus7lj/f7gHTxJd xXGnXALRWRZ5RXml1+sMSnlHE5BizZyLQ1tA3hlpDqlD8i8iwYh+cw1X//TT3ZL7F3Di HwUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G8+gYdiVbmjOwjaPy7U2TKEE4QviaMAH4q5NozXKn0Q=; b=a/8X1CtkIoYCGYJMYAyn6jcehJf8M3hYFy2CXfaDLn/VWG8w7rT3ZrROpGfd84X4wD 8dMd4aJdqnayZm2Txolx9+fBhQT3gVjkXG5dTFC8qNEA8sOHJEEOcSH89IzJb0sITx42 Vg9YRQOf9NyaRwJAw2zSLyagViDqFtPuRSxWFVDukLZJ/1TveqcQI39WtRHiBXkrYjRY oAlMIm6sCaw9AZOvPoRfAI5l26jdlsh0Dl4UL7F5DlJT0L++Koxo8iz8TcnPl9hL/h5Q MMKFFX7dmk5UJLdW097L3xuxOEGSf0xX9Mwm9cws1JYTWnz3UIMIJX2pL8INQKyA5E7K 5+1w== X-Gm-Message-State: AOAM533iszEPH2BS9xdzVnJXlOAxHIF3DkuFP+KjfAUTWOd3LkeeKVGW C5gmcRxHFDZjD2bKhUsek8GKeQ== X-Received: by 2002:a17:90a:246:: with SMTP id t6mr737090pje.228.1620250690710; Wed, 05 May 2021 14:38:10 -0700 (PDT) Received: from localhost.localdomain.name ([223.235.141.68]) by smtp.gmail.com with ESMTPSA id z26sm167031pfq.86.2021.05.05.14.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 14:38:10 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 02/17] dt-bindings: qcom-bam: Add 'iommus' to required properties Date: Thu, 6 May 2021 03:07:16 +0530 Message-Id: <20210505213731.538612-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add the missing required property - 'iommus' to the device-tree binding documentation for qcom-bam DMA IP. This property describes the phandle(s) to apps_smmu node with sid mask. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt index 077242956ff2..60a76c0fb118 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt @@ -13,6 +13,7 @@ Required properties: - clock-names: must contain "bam_clk" entry - qcom,ee : indicates the active Execution Environment identifier (0-7) used in the secure world. +- iommus : phandle to apps_smmu node with sid mask Optional properties: - qcom,controlled-remotely : optional, indicates that the bam is controlled by From patchwork Wed May 5 21:37:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431213 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867555jao; Wed, 5 May 2021 14:38:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzDBfB9l4BK8t8pxr6lAn6y9baubhKZxd+oPDJuno5PBnToU+tiC8ACmKiVeu8mg9CdDLT X-Received: by 2002:a63:1c54:: with SMTP id c20mr952284pgm.210.1620250705691; Wed, 05 May 2021 14:38:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250705; cv=none; d=google.com; s=arc-20160816; b=cRYAA5G4LFexc006nDpJFfCmkQTEyQgw0a30SIaRqS/4WyA1WjfK65vC34BcM00dqP 5ARewr8NTwTicUKarWVQ2eRq/JKuW294NRvk4jNo0l0LLae6lmS+A+t9wXdZVI/F7tX6 PWrizSdEsOI2j/6oFDAiyIYdxZEbjlFa3JglOMbHkxY3AroB9QtX6X1CMKEF7h0vFyJG 7P25EP7n7qzFEKh6Xei3q7ICMsHeXTEI/nIYAQEChIqDaTiFoQ8HERCzcxCMA2xGd1vB g1/IJwK17QMQ+lgSis7lp68UBLZglZUY1gO+eEVGtWgjwRBDAmXlxAFM6iN5OvShdxc4 aPZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mRrEkCTt84fVOsDtsgDP4oPLdjeOGHNGXk1uFFcE3+Y=; b=jyKHsgsZv0Jsx6sMG/XLdGvoC884SLgXfXQGWyzid+S/Nm42SlwXRVzyocX6VVvuRj fh9Nj1qfkslXTS1aMXVdrq182t32J4lcsIyinDLir2+Jf1bGIquhUVwSjsEVDEUyhp+r JESlTTKGCxhsrnIKlP86J+QkX+t1iYvJRI2nYNG/VoxbywBfBbDRjDVpZOq+1uYjlqcl Rg81lkaJ9SB7YG4lmRbaijRHwJIWNkelnYMHvY2qCYoYD+8Csli3E38J+emtMr/5SgUi KODu1iwG2gvy8Bg+peR+uR+IA/0n9fxiO8VgmAJEl9ETUkd1cNmS+cqkx+ZkU0758Hu/ PKgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nJWgip7B; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 03/17] dt-bindings: qcom-qce: Add 'iommus' to required properties Date: Thu, 6 May 2021 03:07:17 +0530 Message-Id: <20210505213731.538612-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add the missing required property - 'iommus' to the device-tree binding documentation for qcom-qce crypto IP. This property describes the phandle(s) to apps_smmu node with sid mask. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/crypto/qcom-qce.txt | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt index fdd53b184ba8..07ee1b12000b 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt @@ -11,6 +11,7 @@ Required properties: - dmas : DMA specifiers for tx and rx dma channels. For more see Documentation/devicetree/bindings/dma/dma.txt - dma-names : DMA request names should be "rx" and "tx" +- iommus : phandle to apps_smmu node with sid mask Example: crypto@fd45a000 { From patchwork Wed May 5 21:37:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431215 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867706jao; Wed, 5 May 2021 14:38:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxe9sQ7wtuyZTXwdWtk+JahUUVRrPV6X+IvUFpjvYn1u8ntPvZgcrL6bjS3H/OWVOg8+3sq X-Received: by 2002:a17:90b:1a8b:: with SMTP id ng11mr13719438pjb.93.1620250720015; Wed, 05 May 2021 14:38:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250720; cv=none; d=google.com; s=arc-20160816; b=TvgKMGlL1zqVGl24iOzZVgSUrmSrxCwkm+0DST1Njzjjk/8jjIDOZeFTTRoVnsgKCU x1zJQ5nTZEWDedPi2HSmXmR54fQDlaQpb5kYf4837vqBajOXfBfSDubPmMbQLnXXGNYk Z9SZCSS88aCuGOY7bpeOboniepY+ycoqU73gmI/DyEkJUp06iPnrCT7ff532mmADUb3L +1/9jAsv84UWb/HB3KL6EQ9xSDHhHoRS9QL8OeOUF9OpX+ZKk6l6udo71oFn4mzU3z93 ZUY+Citw2NBji59mEX0erJ8IdA6xvL9qK9HZXpcU7J02nyXJTUJdDzR/5x5cS3mEnQz0 rs0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qDeLoqy+m6bioGGQ0GfxGS6rwvI3pr4vU0sm5fTC/IA=; b=O+2BqWfkudT+kgjPSXyUVMLwfUKo/+DXLIb11r4LJLUK98BBGGivad0phtHsWU+X20 PCSVtScJm31ar8L3yIRWNSmmCC0mRg9Ocg/yNWUA1LRI16chjaqb56JIDo53SkPrF/7/ rajGhasjV9NnfQ8Yf8aclVBN0TqEYzUKEWoxBRg6Tu6pYb/LX06vCJBz8jo8/tZnrWVK GpdUypapHJDHbwrPoYRBp+vuTIcjt72/ZoqskjFA8u8dVxvdw9//5XEGF8MxS7yJdatb 8hPUKLWRWWPXIvOyxyF//n1KO7cf08jV4S8vQtJGXP924FD9ksoafsqmmHNeg9h8vc9C Dtpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qU2J7GvV; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 05/17] arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly Date: Thu, 6 May 2021 03:07:19 +0530 Message-Id: <20210505213731.538612-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine."), we decided to use the value indicated by constant RPMH_CE_CLK rather than using it directly. Now that the same RPMH clock value might be used for other SoCs (in addition to sdm845), let's use the constant RPMH_CE_CLK to make sure that this dtsi is compatible with the other qcom ones. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0a86fe71a66d..2ec4be930fd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2316,7 +2316,7 @@ cryptobam: dma@1dc4000 { compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; - clocks = <&rpmhcc 15>; + clocks = <&rpmhcc RPMH_CE_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; @@ -2332,7 +2332,7 @@ crypto: crypto@1dfa000 { reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>, - <&rpmhcc 15>; + <&rpmhcc RPMH_CE_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 6>, <&cryptobam 7>; dma-names = "rx", "tx"; From patchwork Wed May 5 21:37:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0920C43470 for ; Wed, 5 May 2021 21:38:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D883B613D6 for ; Wed, 5 May 2021 21:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234191AbhEEVjp (ORCPT ); Wed, 5 May 2021 17:39:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234194AbhEEVjm (ORCPT ); Wed, 5 May 2021 17:39:42 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26C5EC06138E for ; Wed, 5 May 2021 14:38:44 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id cl24-20020a17090af698b0290157efd14899so1738383pjb.2 for ; Wed, 05 May 2021 14:38:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E5tl04v9finFgI5dTLUvXSF6+C6BwGNEbEHhfHuvsdY=; b=ACKDEi3d8y/Es5bvtxn0l07L22kbFP+Tg3bHthNBDjeNhLT0RD0b30luapq6h1jr+k ihA0lPDekyGXGNtEsizSa93QkooYXi0yYZ/Hbhgssk+gGhl8Tnpf0bq+Vh+Mh5exkjBd L/xDggHHQz56PSkFhqnOEn+NeB+a0Hzp4BjOAVaPK3GhI7G1jIYpFOMnzJyNNJT8Hp8d 0WuYvDLSLn7AzU5isvMdBRcgavBQQCabPXAsJyTA6Pa3VhV1OvUBxmVdQbr7TOONLK7y W944jvb43h9iBU4Sq+rKDsnM81Kq6DcFxOfRsgXcwnqaNUY7LOXwewEsdrmgQZKmjP5T P0cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E5tl04v9finFgI5dTLUvXSF6+C6BwGNEbEHhfHuvsdY=; b=RUyLQGbqROpU9hgJsWiQElW0kbyjO0Exf7ZAv7eGZuiT2BWsTwiNzGRlCf4t6Z0mPK 5Z9XIVXEMc8O5LIHk5Xvea2phDpl0UqbVPbyd5OIu65s3I1qf8h0+P/5SJvTPWR5cYb3 +cp5QWUsuvvXROc6Nsu/eWfJbYXSC3qhW3vQyK4+telFgidOHZdLpn8f0TNbpcdvUOMR Fcw5Sqrs6N4u9MUDEZFYmsr1LKFOiVF+V9plJjr5vtzKC//2OOFkNt0N9pczlLCFXEii AODGtoaanyb/zl8bIUq8D7pTQX5Hneat4sm3spRQHbJMT3YmLZvcnEXxqi8PzxaJeRHJ Zh5A== X-Gm-Message-State: AOAM530ko2pjU1w6IUP/M217BifumIPG7yOfkbpOB7UCJR3cvY2tLypp 60ekSOcE2bKYle+DC/TsyE1WiA== X-Google-Smtp-Source: ABdhPJxokI0TPxCQxyWx3qoUxcst1Tw4Diqii8RFo16frzYUDUMAAjgoOQ4pxTkscIz5IfuV9xAs2A== X-Received: by 2002:a17:90b:8d5:: with SMTP id ds21mr13382570pjb.65.1620250723426; Wed, 05 May 2021 14:38:43 -0700 (PDT) Received: from localhost.localdomain.name ([223.235.141.68]) by smtp.gmail.com with ESMTPSA id z26sm167031pfq.86.2021.05.05.14.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 14:38:42 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 07/17] arm64/dts: qcom: Use new compatibles for crypto nodes Date: Thu, 6 May 2021 03:07:21 +0530 Message-Id: <20210505213731.538612-8-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since we are using soc specific qce crypto IP compatibles in the bindings now, use the same in the device tree files which include the crypto nodes. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9fa5b028e4f3..978c34f176de 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -205,7 +205,7 @@ cryptobam: dma-controller@704000 { }; crypto: crypto@73a000 { - compatible = "qcom,crypto-v5.1"; + compatible = "qcom,ipq6018-qce"; reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2ec4be930fd6..6423991fa303 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2328,7 +2328,7 @@ cryptobam: dma@1dc4000 { }; crypto: crypto@1dfa000 { - compatible = "qcom,crypto-v5.4"; + compatible = "qcom,sdm845-qce"; reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>, From patchwork Wed May 5 21:37:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431219 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867949jao; Wed, 5 May 2021 14:39:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJza/3nUIJrdFuwtMz5AOSNbZK6OkGiSWPmAVe9wMDV4tJx/DTEzTRoJy6sRIj1vnEGacw6B X-Received: by 2002:a17:90b:31cc:: with SMTP id jv12mr726051pjb.33.1620250744090; Wed, 05 May 2021 14:39:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250744; cv=none; d=google.com; s=arc-20160816; b=knz5KIHGwEr/VCar5roOqnP5dGOFIMM7Cbn3Kq+Hc666pbsHsHhxk5kbFpShg4sJtb xTRKle1VZjLn9S6RGS5TKZzNPGH0qKCrA3UIczFQU/cNR92+Fyv4UZh/Y4hzKinXAXTr 5avvp1B+bfzvvz/p6idC8MdAnY6iTiBJSXdbLhtRAYGNRMDGQyQEnLt6RhGRWu62CjFS CgOCFR4+V/HMWLqgkyyRN6WeZXh+GdIvLkSUxFP17Z5GnuU7M+/mbIcO66Tb0l2qwWG1 V12koRdmXvDDmFGZpd9O3K5Go4E1iMhmC/YKWcCv+KGK4Nmpdd5uphaRQbgjw/MKZYkA ytkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EiBQGXYFrfCnZUi3Qrj72wva/FJNobB/Gmt17VjquqY=; b=NCf6OfwdQ5LMirqgTM6xTFYDEK8GWQMFdzVz/n+tTvCKJ7eUa2hy8FzO0mfeYgzdYf +FxVPSFRoQokfK7lW6GydtLVWuGqVaC9CEsVxUmVDzVCpVC5zGERaNfdsSWnIjtj4pA/ HKFs8ggDRbxyOed8/5xYweGI61nz/5QzFKXKJnsFn2reG4W+q4cL4YY/5tQeI36opQWn bIXG59wbtTk4BQyKe950ItH1Ubh2ApbRAZ6iu/MAkNkr40XLij1DUrndoOnIw4zTquaX dEbebQ2kN8pHdsNPtk7wQwjE1ybgyKHBRn8Mfjci/hsx/Uh28Sd/9C9FINeViGECNyr4 gyzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MWoU747x; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 09/17] crypto: qce: core: Add support to initialize interconnect path Date: Thu, 6 May 2021 03:07:23 +0530 Message-Id: <20210505213731.538612-10-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Thara Gopinath Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 etc. requires interconnect path between the engine and memory to be explicitly enabled and bandwidth set prior to any operations. Add support in the qce core to enable the interconnect path appropriately. Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma [Make header file inclusion alphabetical] Signed-off-by: Thara Gopinath --- drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++------- drivers/crypto/qce/core.h | 1 + 2 files changed, 29 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 80b75085c265..92a0ff1d357e 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -21,6 +22,8 @@ #define QCE_MAJOR_VERSION5 0x05 #define QCE_QUEUE_LENGTH 1 +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 + static const struct qce_algo_ops *qce_ops[] = { #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER &skcipher_ops, @@ -202,21 +205,35 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret < 0) return ret; + qce->mem_path = of_icc_get(qce->dev, "memory"); + if (IS_ERR(qce->mem_path)) + return PTR_ERR(qce->mem_path); + qce->core = devm_clk_get(qce->dev, "core"); - if (IS_ERR(qce->core)) - return PTR_ERR(qce->core); + if (IS_ERR(qce->core)) { + ret = PTR_ERR(qce->core); + goto err_mem_path_put; + } qce->iface = devm_clk_get(qce->dev, "iface"); - if (IS_ERR(qce->iface)) - return PTR_ERR(qce->iface); + if (IS_ERR(qce->iface)) { + ret = PTR_ERR(qce->iface); + goto err_mem_path_put; + } qce->bus = devm_clk_get(qce->dev, "bus"); - if (IS_ERR(qce->bus)) - return PTR_ERR(qce->bus); + if (IS_ERR(qce->bus)) { + ret = PTR_ERR(qce->bus); + goto err_mem_path_put; + } + + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); + if (ret) + goto err_mem_path_put; ret = clk_prepare_enable(qce->core); if (ret) - return ret; + goto err_mem_path_disable; ret = clk_prepare_enable(qce->iface); if (ret) @@ -256,6 +273,10 @@ static int qce_crypto_probe(struct platform_device *pdev) clk_disable_unprepare(qce->iface); err_clks_core: clk_disable_unprepare(qce->core); +err_mem_path_disable: + icc_set_bw(qce->mem_path, 0, 0); +err_mem_path_put: + icc_put(qce->mem_path); return ret; } diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 085774cdf641..228fcd69ec51 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -35,6 +35,7 @@ struct qce_device { void __iomem *base; struct device *dev; struct clk *core, *iface, *bus; + struct icc_path *mem_path; struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; From patchwork Wed May 5 21:37:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431220 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868036jao; Wed, 5 May 2021 14:39:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3BOs7atoejrItoGuzqn7dny6uUStQY8+LS980zrXUwGPOB4y9ZABLgt/OIZWPBJdE2/Pa X-Received: by 2002:a17:902:7203:b029:e6:a8b1:8d37 with SMTP id ba3-20020a1709027203b02900e6a8b18d37mr1157815plb.44.1620250755193; Wed, 05 May 2021 14:39:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250755; cv=none; d=google.com; s=arc-20160816; b=WoVIYOQtkWqUZTbb4jUEVLwSWCRdqYOL0hxTzLrYalA4mR0D5N1DZs9XNHs0SRfC3b ECV2mFt0ZYhoROqyGpFk3BmGRbD3j4LWHrk22b42UkQh5AOm/1PMo7AypG5Y4dMCpi0I vK1KFY6lP0XO5XtHut7vUy5OCIL/ZA03WTFyNOmuD7LScc2MUZkRefrG9a/bVwYQR7tb qK5OMCOGa7bs53BI9dJchEHqTPl60NcYhT8Hl7j1wGkk0KpUbUza++HgiOy9N664HsfJ TTFSe+MSKD6nBWEGOeSiZaBTJqNRpx/xX8+SywygKP2f+OlQpP5hzfUijg8vOXT5PjFZ NJqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QTs/SEbir+LcEB2TCs+hMhq7sImYAohAveDk3rTOiyw=; b=EpT8oIp7ktXIUF0t0PbeHLoS/UtACr1ObzirpKdJaRB4dNvqXlha9+IXOjyovx3rG4 q86U4uHyYdEX8yVqj4Ker9hbBcHyqxHc+wGNxz0eW5m6uUbaDGIuVoVCGw2qpXDp0k/l LCA85QFKLuhes1e5vXJCsS2I3VSctTtIQUe9NnonfFDkqpVjiQAnyCgBWcHqlhVozLRa Js8MEpw7oUyLjkQMVMRPjC2IHohjmSNHXVaX1A9N5KFTpohun3PCebCG9B1/eHi/WVGM 0ElcP6CEBSCsZCJR+I/dK0XReSsdWobZHcbkWHfInixsHp68rnewN2RKhjMz1dvlMB6+ 6FcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dmGQrXTw; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 10/17] crypto: qce: Add new compatibles for qce crypto driver Date: Thu, 6 May 2021 03:07:24 +0530 Message-Id: <20210505213731.538612-11-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since we decided to use soc specific compatibles for describing the qce crypto IP nodes in the device-trees, adapt the driver now to handle the same. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.30.2 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 92a0ff1d357e..f6032c303c8c 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -294,8 +294,8 @@ static int qce_crypto_remove(struct platform_device *pdev) } static const struct of_device_id qce_crypto_of_match[] = { - { .compatible = "qcom,crypto-v5.1", }, - { .compatible = "qcom,crypto-v5.4", }, + { .compatible = "qcom,ipq6018-qce", }, + { .compatible = "qcom,sdm845-qce", }, {} }; MODULE_DEVICE_TABLE(of, qce_crypto_of_match); From patchwork Wed May 5 21:37:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8292C43460 for ; Wed, 5 May 2021 21:39:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADE0A613E3 for ; Wed, 5 May 2021 21:39:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234575AbhEEVkc (ORCPT ); Wed, 5 May 2021 17:40:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234621AbhEEVkJ (ORCPT ); Wed, 5 May 2021 17:40:09 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F16F5C06134A for ; Wed, 5 May 2021 14:39:09 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id y32so2791273pga.11 for ; Wed, 05 May 2021 14:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/siEfisWfBJM0n73hN/umrsNr10CV8eOAzqRCMOQV70=; b=tHz4qVImXJSw44ix7PkNJLpPXT9cB/ns98mZEirUEBuNj5aP/lzKoYOVppEePIm4Ey 0iVsIJN1x8zO20EEl+V9sG/hgend/EOUoINR+qq5TEotIL5clwrVaNOx20zmghwPxzFf CBrYFvwYgnSo/fzvdkLVpsxReBsqRjAER66cSYuM8mOxwvcaC94h09FaQ8RT1ZSdG0jD eXKHneXHWOjkFTPcB0YAtFxvRANzfxEqUyDa5AIqA/anv9SBwiGhpLgAPu6/qoal3jMt m5m/uUXPiATtLObVA3c0dyfrmT9z20nprwEN5Mn7Zb53oyZsWfO4OFDgwCK10hoXrD+1 O30Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/siEfisWfBJM0n73hN/umrsNr10CV8eOAzqRCMOQV70=; b=B1daYPHCmxBVFA8VIrltJAIC1xFshnOWUGiLZbbrAt3rjOl2Jg5hDDd6Qxzp9JeDAG vdYRPGZir5YtRdUbY10deZ4eE4HEDGjnRhaPUjZPLfyJTKQ9xNMPbLudg3be2EoxZlG2 ykCMQkvD1elPuJzjlIT7o012tXyOoPOOGzE/hW49GAB/V7TCju6WH1ZgY5QomcJ1mrNn NTO2sgZNOKfUBc+kJePT5shmBflIJaHo7yDdLsfP4RzSvCb/dcKYm0ExEubUQS6JY1d5 9y5zCZDmMyfnVBzOmg2oMaVxNLTmvp3qH+DuHZSeXpm+30Ze5WRQBMXwDsb8+1HDOWci hDgA== X-Gm-Message-State: AOAM533J0ydK2KFm2cU47FY2Dg+ZWhnmWE4Bq6zAKxqQUDb0HnmxXbPF m7RkFLDMSCx0oStHrcPCgbbBFA== X-Google-Smtp-Source: ABdhPJxx405bODF7L4idMIDItqAp6iCwVvXHGmuHWaLOHjAXU0qFlarx10b4GPxtSbwUE+1QqTFs+g== X-Received: by 2002:aa7:860e:0:b029:28e:b4a9:297f with SMTP id p14-20020aa7860e0000b029028eb4a9297fmr994740pfn.46.1620250749520; Wed, 05 May 2021 14:39:09 -0700 (PDT) Received: from localhost.localdomain.name ([223.235.141.68]) by smtp.gmail.com with ESMTPSA id z26sm167031pfq.86.2021.05.05.14.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 14:39:09 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 11/17] crypto: qce: core: Make clocks optional Date: Thu, 6 May 2021 03:07:25 +0530 Message-Id: <20210505213731.538612-12-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Thara Gopinath On certain Snapdragon processors, the crypto engine clocks are enabled by default by security firmware and the driver need not handle the clocks. Make acquiring of all the clocks optional in crypto enginer driver so that the driver intializes properly even if no clocks are specified in the dt. Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma [Make clock enablement optional only for qcom parts where firmware has already initialized them, using a bool variable] Signed-off-by: Thara Gopinath --- drivers/crypto/qce/core.c | 85 +++++++++++++++++++++++---------------- drivers/crypto/qce/core.h | 2 + 2 files changed, 53 insertions(+), 34 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index f6032c303c8c..293d0bfe3aab 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -184,12 +185,23 @@ static int qce_check_version(struct qce_device *qce) return 0; } +static const struct of_device_id qce_crypto_of_match[] = { + { .compatible = "qcom,ipq6018-qce", }, + { .compatible = "qcom,sdm845-qce", }, + { .compatible = "qcom,sm8250-qce", }, + {} +}; +MODULE_DEVICE_TABLE(of, qce_crypto_of_match); + static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + const struct of_device_id *of_id = + of_match_device(qce_crypto_of_match, &pdev->dev); int ret; + qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); if (!qce) return -ENOMEM; @@ -209,39 +221,51 @@ static int qce_crypto_probe(struct platform_device *pdev) if (IS_ERR(qce->mem_path)) return PTR_ERR(qce->mem_path); - qce->core = devm_clk_get(qce->dev, "core"); - if (IS_ERR(qce->core)) { - ret = PTR_ERR(qce->core); - goto err_mem_path_put; - } - - qce->iface = devm_clk_get(qce->dev, "iface"); - if (IS_ERR(qce->iface)) { - ret = PTR_ERR(qce->iface); - goto err_mem_path_put; - } - - qce->bus = devm_clk_get(qce->dev, "bus"); - if (IS_ERR(qce->bus)) { - ret = PTR_ERR(qce->bus); - goto err_mem_path_put; - } - ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); if (ret) goto err_mem_path_put; - ret = clk_prepare_enable(qce->core); - if (ret) - goto err_mem_path_disable; + /* On some qcom parts the crypto clocks are already configured by + * the firmware running before linux. In such cases we don't need to + * enable/configure them again. Check here for the same. + */ + if (!strcmp(of_id->compatible, "qcom,ipq6018-qce") || + !strcmp(of_id->compatible, "qcom,sdm845-qce")) + qce->clks_configured_by_fw = false; + else + qce->clks_configured_by_fw = true; + + if (!qce->clks_configured_by_fw) { + qce->core = devm_clk_get(qce->dev, "core"); + if (IS_ERR(qce->core)) { + ret = PTR_ERR(qce->core); + goto err_mem_path_put; + } + + qce->iface = devm_clk_get(qce->dev, "iface"); + if (IS_ERR(qce->iface)) { + ret = PTR_ERR(qce->iface); + goto err_mem_path_put; + } + + qce->bus = devm_clk_get(qce->dev, "bus"); + if (IS_ERR(qce->bus)) { + ret = PTR_ERR(qce->bus); + goto err_mem_path_put; + } + + ret = clk_prepare_enable(qce->core); + if (ret) + goto err_mem_path_disable; - ret = clk_prepare_enable(qce->iface); - if (ret) - goto err_clks_core; + ret = clk_prepare_enable(qce->iface); + if (ret) + goto err_clks_core; - ret = clk_prepare_enable(qce->bus); - if (ret) - goto err_clks_iface; + ret = clk_prepare_enable(qce->bus); + if (ret) + goto err_clks_iface; + } ret = qce_dma_request(qce->dev, &qce->dma); if (ret) @@ -293,13 +317,6 @@ static int qce_crypto_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id qce_crypto_of_match[] = { - { .compatible = "qcom,ipq6018-qce", }, - { .compatible = "qcom,sdm845-qce", }, - {} -}; -MODULE_DEVICE_TABLE(of, qce_crypto_of_match); - static struct platform_driver qce_crypto_driver = { .probe = qce_crypto_probe, .remove = qce_crypto_remove, diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 228fcd69ec51..d9bf05babecc 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -23,6 +23,7 @@ * @dma: pointer to dma data * @burst_size: the crypto burst size * @pipe_pair_id: which pipe pair id the device using + * @clks_configured_by_fw: clocks are already configured by fw * @async_req_enqueue: invoked by every algorithm to enqueue a request * @async_req_done: invoked by every algorithm to finish its request */ @@ -39,6 +40,7 @@ struct qce_device { struct qce_dma_data dma; int burst_size; unsigned int pipe_pair_id; + bool clks_configured_by_fw; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); From patchwork Wed May 5 21:37:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431223 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868378jao; Wed, 5 May 2021 14:39:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxdjpnA3/zQUXHC2PA/Tijdt1EtvQI7iOpNY3uZG6H364sZEUiJai5Mo0I3EkSaoVjqC7a0 X-Received: by 2002:a17:90a:5207:: with SMTP id v7mr13547812pjh.87.1620250791204; Wed, 05 May 2021 14:39:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250791; cv=none; d=google.com; s=arc-20160816; b=sim9u6Ogiqy4J93+cm2hICY+KNtIMVLdesslRkX2EtD13w1mHXR35cDH2QTJ6pAdDf /R/T2mCokB5VA1FoO+V4ywxAIj6uGidEH3ADlQzVygk72xaLfR5WaqO+RiGE+l3WZLHM ojzu9p6grjN7EItkPG1Prx4b/6495V/dp5hc73xn9ksv+kGg5bbftG9BfsmVvcVW8fkr b/WgxJWQx1d3vhiu2edeXuULvrTKhPHqtO1Qy/d43tN9gnbgmvKgBEDkuwzYrmOtEIMO XN0+0byYHIWCErIQmwDJvygZYOuAl+nt00L4E8k3zScXg2xfNX0fGBfWd81sv22O6QyZ RJHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ulnvpDvs2fMyqboyMzQm9/EA+gzjDEWFkHrEeAbq2gg=; b=tZfoDcAfWUFYLxj3fA2mybG0s4PlWtAUlwRueNgzTTt4YSvXN0WsrlTnHXrZ7r528y AXC6HIuQApQjriZILcxBdNAvjn19L3u1+5gZYU3lGBNDNyQ1JW16HV67KEAze5EcKPFJ pOOQf4fhEeGn0wClMyL8MhJa/lbMASc+zzIoA9WtUPsV29VDXkjEmBpbdyrOZ5M+jXP4 Ap2WwSy9YcjlTji4Pw70alc+j2oxT9A5V6b3sasq1bKO2bRp4zIifHVKFBPq41lKmDv6 WDhZbVx6Gfe0CzM9gKcOhzp7P4oBhvronE9Z3TaHXXVzMt60g4RG1uv8wS3j2grxBVAb 48fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xmcZO9Bq; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 13/17] crypto: qce: Convert the device found dev_dbg() to dev_info() Date: Thu, 6 May 2021 03:07:27 +0530 Message-Id: <20210505213731.538612-14-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org QCE crypto driver is right now too silent even if the probe() is ok and a valid crypto IP version is found. Convert the dev_dbg() message to a dev_info() instead. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.30.2 diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index bae08fdfc44f..9a7d7ef94687 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -179,7 +179,7 @@ static int qce_check_version(struct qce_device *qce) */ qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1; - dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n", + dev_info(qce->dev, "Crypto device found, version %d.%d.%d\n", major, minor, step); return 0; From patchwork Wed May 5 21:37:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431224 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868446jao; Wed, 5 May 2021 14:39:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxCmVf9tEq0WD1g18GAsepbAlAT6k1/h2l4XfBnkG7uPm/Bd26x50/F6FZ/MZ/S4/30t0zG X-Received: by 2002:a62:ce8c:0:b029:28e:cc4c:3b7e with SMTP id y134-20020a62ce8c0000b029028ecc4c3b7emr801726pfg.67.1620250797429; Wed, 05 May 2021 14:39:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250797; cv=none; d=google.com; s=arc-20160816; b=No50jd335hkSIjUEOcomm0sokjvFgMaVAoqhBokFkjZ0R1iK/nUYpY1moM0KAaiggy vU4WqL8jP5C5GRB6lv4Q3ONs6lN/kWhG0OBH8BE/TzX1Dvvyv4fBuxm5MquoI2uuDcag +0rOrfCHqLIrVw7bseWDkwU54n8vxoDcdebrtEv7aZEFNdn9lwuNNHWGncKYC5EzJqwx Yr63JlTCJewmPzo5c3p3wU3mg7igmReYvzEzsYXOUMOR3incNMB5JD8LmalPPB59Q5CR Ez+yk+pqrmSYUZL4j6hC9WXCdFxbyX+oZJFcmcRqbVumRnWi/DttwrpetPGMs5rlt7Qv GfmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y/Yp3jNXxf4UBodH2vshN4FPNgFABDbF9D9kjo2alJM=; b=s9tFTV4EcO2yjoyiB51SQfaRXjhyOKLvidERwbumfLgzpeerMINOSFiRkoQZVJd2bg MQiElfJ9SmvsCgIIScszuY+Cs4EEK/ZAKdtBYzCLaRxykheshmUwdNoA1suIWuDVLnK2 nbhBypXGSWbEV73Aar3eUljjiHiR6H+4NZlezJ2CwooPfTYViyvgVw9tUGj5sgWpAS/F oL1FyQtveAu1Fl8FleNz9pEXlunDvotPj8oJLiziwVRiCOx+yMzCs8nV9dqM34b1hVo2 BCOCiL+J1eD2VPD3qOINB4DDu+8fblpCLKXka0OgJfzeCw8P8RZ8qJw96SIpi6ir2lcJ PnVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NZc/1Qhq"; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 14/17] dma: qcom: bam_dma: Create a new header file for BAM DMA driver Date: Thu, 6 May 2021 03:07:28 +0530 Message-Id: <20210505213731.538612-15-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Create a new header file for BAM DMA driver to make sure that it can be included in the follow-up patch to defer probing drivers which require BAM DMA driver to be first probed successfully. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/dma/qcom/bam_dma.c | 283 +----------------------------------- include/soc/qcom/bam_dma.h | 290 +++++++++++++++++++++++++++++++++++++ 2 files changed, 293 insertions(+), 280 deletions(-) create mode 100644 include/soc/qcom/bam_dma.h -- 2.30.2 diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index fc84ef42507d..2bc3b7c7ee5a 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -42,23 +42,13 @@ #include #include #include +#include #include "../dmaengine.h" #include "../virt-dma.h" -struct bam_desc_hw { - __le32 addr; /* Buffer physical address */ - __le16 size; /* Buffer size in bytes */ - __le16 flags; -}; - -#define BAM_DMA_AUTOSUSPEND_DELAY 100 - -#define DESC_FLAG_INT BIT(15) -#define DESC_FLAG_EOT BIT(14) -#define DESC_FLAG_EOB BIT(13) -#define DESC_FLAG_NWD BIT(12) -#define DESC_FLAG_CMD BIT(11) +/* check if BAM is probed */ +static bool bam_probed; struct bam_async_desc { struct virt_dma_desc vd; @@ -78,273 +68,6 @@ struct bam_async_desc { struct bam_desc_hw desc[]; }; -enum bam_reg { - BAM_CTRL, - BAM_REVISION, - BAM_NUM_PIPES, - BAM_DESC_CNT_TRSHLD, - BAM_IRQ_SRCS, - BAM_IRQ_SRCS_MSK, - BAM_IRQ_SRCS_UNMASKED, - BAM_IRQ_STTS, - BAM_IRQ_CLR, - BAM_IRQ_EN, - BAM_CNFG_BITS, - BAM_IRQ_SRCS_EE, - BAM_IRQ_SRCS_MSK_EE, - BAM_P_CTRL, - BAM_P_RST, - BAM_P_HALT, - BAM_P_IRQ_STTS, - BAM_P_IRQ_CLR, - BAM_P_IRQ_EN, - BAM_P_EVNT_DEST_ADDR, - BAM_P_EVNT_REG, - BAM_P_SW_OFSTS, - BAM_P_DATA_FIFO_ADDR, - BAM_P_DESC_FIFO_ADDR, - BAM_P_EVNT_GEN_TRSHLD, - BAM_P_FIFO_SIZES, -}; - -struct reg_offset_data { - u32 base_offset; - unsigned int pipe_mult, evnt_mult, ee_mult; -}; - -static const struct reg_offset_data bam_v1_3_reg_info[] = { - [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, - [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, - [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, - [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 }, - [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 }, - [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 }, - [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 }, - [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 }, - [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 }, - [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 }, - [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 }, - [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 }, - [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 }, - [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 }, - [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 }, - [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 }, - [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 }, - [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 }, - [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 }, - [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 }, - [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 }, - [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, -}; - -static const struct reg_offset_data bam_v1_4_reg_info[] = { - [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, - [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, - [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, - [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 }, - [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, - [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, - [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, - [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 }, - [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 }, - [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 }, - [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 }, - [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 }, - [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 }, - [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 }, - [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 }, - [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 }, - [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 }, - [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 }, - [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, -}; - -static const struct reg_offset_data bam_v1_7_reg_info[] = { - [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, - [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, - [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, - [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 }, - [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 }, - [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 }, - [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 }, - [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 }, - [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 }, - [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 }, - [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 }, - [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 }, - [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 }, - [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 }, - [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 }, - [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 }, - [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 }, - [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 }, - [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 }, - [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 }, - [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, -}; - -/* BAM CTRL */ -#define BAM_SW_RST BIT(0) -#define BAM_EN BIT(1) -#define BAM_EN_ACCUM BIT(4) -#define BAM_TESTBUS_SEL_SHIFT 5 -#define BAM_TESTBUS_SEL_MASK 0x3F -#define BAM_DESC_CACHE_SEL_SHIFT 13 -#define BAM_DESC_CACHE_SEL_MASK 0x3 -#define BAM_CACHED_DESC_STORE BIT(15) -#define IBC_DISABLE BIT(16) - -/* BAM REVISION */ -#define REVISION_SHIFT 0 -#define REVISION_MASK 0xFF -#define NUM_EES_SHIFT 8 -#define NUM_EES_MASK 0xF -#define CE_BUFFER_SIZE BIT(13) -#define AXI_ACTIVE BIT(14) -#define USE_VMIDMT BIT(15) -#define SECURED BIT(16) -#define BAM_HAS_NO_BYPASS BIT(17) -#define HIGH_FREQUENCY_BAM BIT(18) -#define INACTIV_TMRS_EXST BIT(19) -#define NUM_INACTIV_TMRS BIT(20) -#define DESC_CACHE_DEPTH_SHIFT 21 -#define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT) -#define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT) -#define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT) -#define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT) -#define CMD_DESC_EN BIT(23) -#define INACTIV_TMR_BASE_SHIFT 24 -#define INACTIV_TMR_BASE_MASK 0xFF - -/* BAM NUM PIPES */ -#define BAM_NUM_PIPES_SHIFT 0 -#define BAM_NUM_PIPES_MASK 0xFF -#define PERIPH_NON_PIPE_GRP_SHIFT 16 -#define PERIPH_NON_PIP_GRP_MASK 0xFF -#define BAM_NON_PIPE_GRP_SHIFT 24 -#define BAM_NON_PIPE_GRP_MASK 0xFF - -/* BAM CNFG BITS */ -#define BAM_PIPE_CNFG BIT(2) -#define BAM_FULL_PIPE BIT(11) -#define BAM_NO_EXT_P_RST BIT(12) -#define BAM_IBC_DISABLE BIT(13) -#define BAM_SB_CLK_REQ BIT(14) -#define BAM_PSM_CSW_REQ BIT(15) -#define BAM_PSM_P_RES BIT(16) -#define BAM_AU_P_RES BIT(17) -#define BAM_SI_P_RES BIT(18) -#define BAM_WB_P_RES BIT(19) -#define BAM_WB_BLK_CSW BIT(20) -#define BAM_WB_CSW_ACK_IDL BIT(21) -#define BAM_WB_RETR_SVPNT BIT(22) -#define BAM_WB_DSC_AVL_P_RST BIT(23) -#define BAM_REG_P_EN BIT(24) -#define BAM_PSM_P_HD_DATA BIT(25) -#define BAM_AU_ACCUMED BIT(26) -#define BAM_CMD_ENABLE BIT(27) - -#define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \ - BAM_NO_EXT_P_RST | \ - BAM_IBC_DISABLE | \ - BAM_SB_CLK_REQ | \ - BAM_PSM_CSW_REQ | \ - BAM_PSM_P_RES | \ - BAM_AU_P_RES | \ - BAM_SI_P_RES | \ - BAM_WB_P_RES | \ - BAM_WB_BLK_CSW | \ - BAM_WB_CSW_ACK_IDL | \ - BAM_WB_RETR_SVPNT | \ - BAM_WB_DSC_AVL_P_RST | \ - BAM_REG_P_EN | \ - BAM_PSM_P_HD_DATA | \ - BAM_AU_ACCUMED | \ - BAM_CMD_ENABLE) - -/* PIPE CTRL */ -#define P_EN BIT(1) -#define P_DIRECTION BIT(3) -#define P_SYS_STRM BIT(4) -#define P_SYS_MODE BIT(5) -#define P_AUTO_EOB BIT(6) -#define P_AUTO_EOB_SEL_SHIFT 7 -#define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT) -#define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT) -#define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT) -#define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT) -#define P_PREFETCH_LIMIT_SHIFT 9 -#define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT) -#define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT) -#define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT) -#define P_WRITE_NWD BIT(11) -#define P_LOCK_GROUP_SHIFT 16 -#define P_LOCK_GROUP_MASK 0x1F - -/* BAM_DESC_CNT_TRSHLD */ -#define CNT_TRSHLD 0xffff -#define DEFAULT_CNT_THRSHLD 0x4 - -/* BAM_IRQ_SRCS */ -#define BAM_IRQ BIT(31) -#define P_IRQ 0x7fffffff - -/* BAM_IRQ_SRCS_MSK */ -#define BAM_IRQ_MSK BAM_IRQ -#define P_IRQ_MSK P_IRQ - -/* BAM_IRQ_STTS */ -#define BAM_TIMER_IRQ BIT(4) -#define BAM_EMPTY_IRQ BIT(3) -#define BAM_ERROR_IRQ BIT(2) -#define BAM_HRESP_ERR_IRQ BIT(1) - -/* BAM_IRQ_CLR */ -#define BAM_TIMER_CLR BIT(4) -#define BAM_EMPTY_CLR BIT(3) -#define BAM_ERROR_CLR BIT(2) -#define BAM_HRESP_ERR_CLR BIT(1) - -/* BAM_IRQ_EN */ -#define BAM_TIMER_EN BIT(4) -#define BAM_EMPTY_EN BIT(3) -#define BAM_ERROR_EN BIT(2) -#define BAM_HRESP_ERR_EN BIT(1) - -/* BAM_P_IRQ_EN */ -#define P_PRCSD_DESC_EN BIT(0) -#define P_TIMER_EN BIT(1) -#define P_WAKE_EN BIT(2) -#define P_OUT_OF_DESC_EN BIT(3) -#define P_ERR_EN BIT(4) -#define P_TRNSFR_END_EN BIT(5) -#define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN) - -/* BAM_P_SW_OFSTS */ -#define P_SW_OFSTS_MASK 0xffff - -#define BAM_DESC_FIFO_SIZE SZ_32K -#define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) -#define BAM_FIFO_SIZE (SZ_32K - 8) -#define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\ - MAX_DESCRIPTORS + 1) == 0) - struct bam_chan { struct virt_dma_chan vc; diff --git a/include/soc/qcom/bam_dma.h b/include/soc/qcom/bam_dma.h new file mode 100644 index 000000000000..d2cd63c13385 --- /dev/null +++ b/include/soc/qcom/bam_dma.h @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */ + +#ifndef QCOM_BAM_DMA_H +#define QCOM_BAM_DMA_H + +struct bam_desc_hw { + __le32 addr; /* Buffer physical address */ + __le16 size; /* Buffer size in bytes */ + __le16 flags; +}; + +#define BAM_DMA_AUTOSUSPEND_DELAY 100 + +#define DESC_FLAG_INT BIT(15) +#define DESC_FLAG_EOT BIT(14) +#define DESC_FLAG_EOB BIT(13) +#define DESC_FLAG_NWD BIT(12) +#define DESC_FLAG_CMD BIT(11) + +enum bam_reg { + BAM_CTRL, + BAM_REVISION, + BAM_NUM_PIPES, + BAM_DESC_CNT_TRSHLD, + BAM_IRQ_SRCS, + BAM_IRQ_SRCS_MSK, + BAM_IRQ_SRCS_UNMASKED, + BAM_IRQ_STTS, + BAM_IRQ_CLR, + BAM_IRQ_EN, + BAM_CNFG_BITS, + BAM_IRQ_SRCS_EE, + BAM_IRQ_SRCS_MSK_EE, + BAM_P_CTRL, + BAM_P_RST, + BAM_P_HALT, + BAM_P_IRQ_STTS, + BAM_P_IRQ_CLR, + BAM_P_IRQ_EN, + BAM_P_EVNT_DEST_ADDR, + BAM_P_EVNT_REG, + BAM_P_SW_OFSTS, + BAM_P_DATA_FIFO_ADDR, + BAM_P_DESC_FIFO_ADDR, + BAM_P_EVNT_GEN_TRSHLD, + BAM_P_FIFO_SIZES, +}; + +struct reg_offset_data { + u32 base_offset; + unsigned int pipe_mult, evnt_mult, ee_mult; +}; + +static const struct reg_offset_data bam_v1_3_reg_info[] = { + [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, + [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, + [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, + [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 }, + [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 }, + [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 }, + [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 }, + [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 }, + [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 }, + [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 }, + [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 }, + [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 }, + [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 }, + [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 }, + [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 }, + [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 }, + [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 }, + [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 }, + [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 }, + [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 }, + [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 }, + [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, +}; + +static const struct reg_offset_data bam_v1_4_reg_info[] = { + [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, + [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, + [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, + [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 }, + [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, + [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, + [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, + [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 }, + [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 }, + [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 }, + [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 }, + [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 }, + [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 }, + [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 }, + [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 }, + [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 }, + [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 }, + [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 }, + [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, +}; + +static const struct reg_offset_data bam_v1_7_reg_info[] = { + [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, + [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, + [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, + [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 }, + [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 }, + [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 }, + [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 }, + [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 }, + [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 }, + [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 }, + [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 }, + [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 }, + [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 }, + [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 }, + [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 }, + [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 }, + [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 }, + [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 }, + [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 }, + [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 }, + [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, +}; + +/* BAM CTRL */ +#define BAM_SW_RST BIT(0) +#define BAM_EN BIT(1) +#define BAM_EN_ACCUM BIT(4) +#define BAM_TESTBUS_SEL_SHIFT 5 +#define BAM_TESTBUS_SEL_MASK 0x3F +#define BAM_DESC_CACHE_SEL_SHIFT 13 +#define BAM_DESC_CACHE_SEL_MASK 0x3 +#define BAM_CACHED_DESC_STORE BIT(15) +#define IBC_DISABLE BIT(16) + +/* BAM REVISION */ +#define REVISION_SHIFT 0 +#define REVISION_MASK 0xFF +#define NUM_EES_SHIFT 8 +#define NUM_EES_MASK 0xF +#define CE_BUFFER_SIZE BIT(13) +#define AXI_ACTIVE BIT(14) +#define USE_VMIDMT BIT(15) +#define SECURED BIT(16) +#define BAM_HAS_NO_BYPASS BIT(17) +#define HIGH_FREQUENCY_BAM BIT(18) +#define INACTIV_TMRS_EXST BIT(19) +#define NUM_INACTIV_TMRS BIT(20) +#define DESC_CACHE_DEPTH_SHIFT 21 +#define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT) +#define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT) +#define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT) +#define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT) +#define CMD_DESC_EN BIT(23) +#define INACTIV_TMR_BASE_SHIFT 24 +#define INACTIV_TMR_BASE_MASK 0xFF + +/* BAM NUM PIPES */ +#define BAM_NUM_PIPES_SHIFT 0 +#define BAM_NUM_PIPES_MASK 0xFF +#define PERIPH_NON_PIPE_GRP_SHIFT 16 +#define PERIPH_NON_PIP_GRP_MASK 0xFF +#define BAM_NON_PIPE_GRP_SHIFT 24 +#define BAM_NON_PIPE_GRP_MASK 0xFF + +/* BAM CNFG BITS */ +#define BAM_PIPE_CNFG BIT(2) +#define BAM_FULL_PIPE BIT(11) +#define BAM_NO_EXT_P_RST BIT(12) +#define BAM_IBC_DISABLE BIT(13) +#define BAM_SB_CLK_REQ BIT(14) +#define BAM_PSM_CSW_REQ BIT(15) +#define BAM_PSM_P_RES BIT(16) +#define BAM_AU_P_RES BIT(17) +#define BAM_SI_P_RES BIT(18) +#define BAM_WB_P_RES BIT(19) +#define BAM_WB_BLK_CSW BIT(20) +#define BAM_WB_CSW_ACK_IDL BIT(21) +#define BAM_WB_RETR_SVPNT BIT(22) +#define BAM_WB_DSC_AVL_P_RST BIT(23) +#define BAM_REG_P_EN BIT(24) +#define BAM_PSM_P_HD_DATA BIT(25) +#define BAM_AU_ACCUMED BIT(26) +#define BAM_CMD_ENABLE BIT(27) + +#define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \ + BAM_NO_EXT_P_RST | \ + BAM_IBC_DISABLE | \ + BAM_SB_CLK_REQ | \ + BAM_PSM_CSW_REQ | \ + BAM_PSM_P_RES | \ + BAM_AU_P_RES | \ + BAM_SI_P_RES | \ + BAM_WB_P_RES | \ + BAM_WB_BLK_CSW | \ + BAM_WB_CSW_ACK_IDL | \ + BAM_WB_RETR_SVPNT | \ + BAM_WB_DSC_AVL_P_RST | \ + BAM_REG_P_EN | \ + BAM_PSM_P_HD_DATA | \ + BAM_AU_ACCUMED | \ + BAM_CMD_ENABLE) + +/* PIPE CTRL */ +#define P_EN BIT(1) +#define P_DIRECTION BIT(3) +#define P_SYS_STRM BIT(4) +#define P_SYS_MODE BIT(5) +#define P_AUTO_EOB BIT(6) +#define P_AUTO_EOB_SEL_SHIFT 7 +#define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT) +#define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT) +#define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT) +#define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT) +#define P_PREFETCH_LIMIT_SHIFT 9 +#define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT) +#define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT) +#define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT) +#define P_WRITE_NWD BIT(11) +#define P_LOCK_GROUP_SHIFT 16 +#define P_LOCK_GROUP_MASK 0x1F + +/* BAM_DESC_CNT_TRSHLD */ +#define CNT_TRSHLD 0xffff +#define DEFAULT_CNT_THRSHLD 0x4 + +/* BAM_IRQ_SRCS */ +#define BAM_IRQ BIT(31) +#define P_IRQ 0x7fffffff + +/* BAM_IRQ_SRCS_MSK */ +#define BAM_IRQ_MSK BAM_IRQ +#define P_IRQ_MSK P_IRQ + +/* BAM_IRQ_STTS */ +#define BAM_TIMER_IRQ BIT(4) +#define BAM_EMPTY_IRQ BIT(3) +#define BAM_ERROR_IRQ BIT(2) +#define BAM_HRESP_ERR_IRQ BIT(1) + +/* BAM_IRQ_CLR */ +#define BAM_TIMER_CLR BIT(4) +#define BAM_EMPTY_CLR BIT(3) +#define BAM_ERROR_CLR BIT(2) +#define BAM_HRESP_ERR_CLR BIT(1) + +/* BAM_IRQ_EN */ +#define BAM_TIMER_EN BIT(4) +#define BAM_EMPTY_EN BIT(3) +#define BAM_ERROR_EN BIT(2) +#define BAM_HRESP_ERR_EN BIT(1) + +/* BAM_P_IRQ_EN */ +#define P_PRCSD_DESC_EN BIT(0) +#define P_TIMER_EN BIT(1) +#define P_WAKE_EN BIT(2) +#define P_OUT_OF_DESC_EN BIT(3) +#define P_ERR_EN BIT(4) +#define P_TRNSFR_END_EN BIT(5) +#define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN) + +/* BAM_P_SW_OFSTS */ +#define P_SW_OFSTS_MASK 0xffff + +#define BAM_DESC_FIFO_SIZE SZ_32K +#define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) +#define BAM_FIFO_SIZE (SZ_32K - 8) +#define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\ + MAX_DESCRIPTORS + 1) == 0) + +bool bam_is_probed(void); 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Wed, 05 May 2021 14:39:36 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Thara Gopinath , Bjorn Andersson , Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 15/17] crypto: qce: Defer probing if BAM dma is not yet initialized Date: Thu, 6 May 2021 03:07:29 +0530 Message-Id: <20210505213731.538612-16-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Since the Qualcomm qce crypto driver needs the BAM dma driver to be setup first (to allow crypto operations), it makes sense to defer the qce crypto driver probing in case the BAM dma driver is not yet probed. This fixes the qce probe failure issues when both qce and BMA dma are compiled as static part of the kernel. Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/crypto/qce/core.c | 4 ++++ drivers/dma/qcom/bam_dma.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 9a7d7ef94687..3e742e9911fa 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "core.h" #include "cipher.h" @@ -201,6 +202,9 @@ static int qce_crypto_probe(struct platform_device *pdev) of_match_device(qce_crypto_of_match, &pdev->dev); int ret; + /* qce driver requires BAM dma driver to be setup first */ + if (!bam_is_probed()) + return -EPROBE_DEFER; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); if (!qce) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 2bc3b7c7ee5a..c854fcc82dbf 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -935,6 +935,12 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, INIT_LIST_HEAD(&bchan->desc_list); } +bool bam_is_probed(void) +{ + return bam_probed; +} +EXPORT_SYMBOL_GPL(bam_is_probed); + static const struct of_device_id bam_of_match[] = { { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, @@ -1084,6 +1090,7 @@ static int bam_dma_probe(struct platform_device *pdev) if (ret) goto err_unregister_dma; + bam_probed = true; if (!bdev->bamclk) { pm_runtime_disable(&pdev->dev); return 0; From patchwork Wed May 5 21:37:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 431227 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868688jao; Wed, 5 May 2021 14:40:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwXlrADcuTOl3UBMx12lmwUq8wt/SgSD6JZ3lNkPti+FElsdIzimfsS/YaocIuckjsLIajz X-Received: by 2002:a63:7c42:: with SMTP id l2mr921213pgn.98.1620250821914; Wed, 05 May 2021 14:40:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620250821; cv=none; d=google.com; s=arc-20160816; b=u5I/SpPYAA3Y1ytO0/3rvvNxJ1WTuUuthClLjJX9FD3GVUQmwDBeCv+Ikmb1o2HbSu cU6F5hghxVkd+mTsGpW+y9rEVNR9JnbWT6etJTO+/Tk/tJps22hXMq3lbdzLRRngosFs 0xvkQnvLAKSnVFccRHKpbK0JUA+N1lrqOqI9sLLExA8GHSAGJNQk15DDgQ6gPxvO8qhg 75VR55HPxS8X+8GZwBTnHiGjT1yqgct/r6BoClYhtz/MOlfLnREgjId+i370hSWd2DLm wn0ENkl168Y5Njg7GoMgvtq5g9KD+fs1bkO59+e1gv6bP5hq0ejP0oVrBWu6eKs3FGsN nJLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=e3tF0fKUCMUyKii5LLb+0W4Qsi0cFNspuvqMpLYFV6k=; b=Rz1U+Xp1sbAVmFxiW7Z7FAjosEPYWrS5u6YhGQXT4nlIbDNj32h+grtmaf8Cc6IicI PjMLj4i/qzAofKYt6uBuZ4sPLwzVeavZRg4Czdtema4LPeAJUGrWehYjwia7JPpvJzhQ 933ZtyahY1n48KM2IYsyenZOAix3XRI7i1wtrM4YFHaJQ+bm+7ZYGAZ9oZbVeiub2Tux XnoNM4gfxiHpyKEdP/oj8ibewV8Fym03BvJ/EbgVScJCFr9trvk6TqZ1hVzU7LYfvXKS pmb20JNoF9Nxg93WVqeSdngjadWWYA7E9NLRGTbMuPizMscggLPPyEFBwa16977LYmiK dOdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="u/Of22GL"; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH v2 17/17] arm64/dts: qcom: sm8250: Add dt entries to support crypto engine. Date: Thu, 6 May 2021 03:07:31 +0530 Message-Id: <20210505213731.538612-18-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210505213731.538612-1-bhupesh.sharma@linaro.org> References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add crypto engine (CE) and CE BAM related nodes and definitions to "sm8250.dtsi". Cc: Thara Gopinath Cc: Bjorn Andersson Cc: Rob Herring Cc: Andy Gross Cc: Herbert Xu Cc: David S. Miller Cc: Stephen Boyd Cc: Michael Turquette Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma Signed-off-by: Thara Gopinath --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..6700d609a7b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3796,6 +3796,34 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + + cryptobam: dma@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + iommus = <&apps_smmu 0x584 0x0011>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8250-qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x584 0x0011>, + <&apps_smmu 0x586 0x0011>, + <&apps_smmu 0x594 0x0011>, + <&apps_smmu 0x596 0x0011>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "memory"; + }; }; timer {