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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm19891650wru.72.2021.05.09.08.16.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 1/9] accel/tcg: Replace g_new() + memcpy() by g_memdup() Date: Sun, 9 May 2021 17:16:10 +0200 Message-Id: <20210509151618.2331764-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 84e7d91a5ca..f616b58a898 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -837,11 +837,8 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, } else if (encode_pbm_to_runon(&runon, d)) { async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); } else { - TLBFlushPageBitsByMMUIdxData *p - = g_new(TLBFlushPageBitsByMMUIdxData, 1); - /* Otherwise allocate a structure, freed by the worker. */ - *p = d; + TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d)); async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); } @@ -875,13 +872,11 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); } else { CPUState *dst_cpu; - TLBFlushPageBitsByMMUIdxData *p; /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { if (dst_cpu != src_cpu) { - p = g_new(TLBFlushPageBitsByMMUIdxData, 1); - *p = d; + TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d)); async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); @@ -927,15 +922,13 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { if (dst_cpu != src_cpu) { - p = g_new(TLBFlushPageBitsByMMUIdxData, 1); - *p = d; + p = g_memdup(&d, sizeof(d)); async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); } } - p = g_new(TLBFlushPageBitsByMMUIdxData, 1); - *p = d; + p = g_memdup(&d, sizeof(d)); async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); } From patchwork Sun May 9 15:16:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 432871 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2108878jao; Sun, 9 May 2021 08:20:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsSzFe9YUsJH0jhpd17a3z8HqLrZBe3IKORsaxA3J44QWRmk35ge6uQlW/224DrrRvA5Z5 X-Received: by 2002:a67:ef82:: with SMTP id r2mr16712064vsp.27.1620573645817; Sun, 09 May 2021 08:20:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620573645; cv=none; d=google.com; s=arc-20160816; b=pdUQ48C578SF7obz+RN10+r9uffBejNsCQQfnm95uKMYnY+CSY5Q93l2X7SeDuf8FI L5oK2PBEzn7OZyU6vRa507k/0W2YRHOBwkpF5c0M6RXE6/7TstQdKkg6wGokk+iIem/2 cqcC4EvaRetHmDQsUNvKjPnJpeAzciDVB63PezvztNDtWWz1AetHP4sbglAmLKUb7JFK /0tg4cozYs6Lfaj2Hq+YIZvOJfhC2LSp6cY4odhDhSjCpT40pfLpSyVyEysExjHejAZC xPLIyzv1q9dSdO2RhJum2tY6gdcp0RoZUq1ulyHQgPOEMAKO2JFU4yyTktWgZZhocwB6 bm7w== ARC-Message-Signature: i=1; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id k16sm15830386wmi.44.2021.05.09.08.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/9] accel/tcg: Pass length argument to tlb_flush_range_locked() Date: Sun, 9 May 2021 17:16:11 +0200 Message-Id: <20210509151618.2331764-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Rename tlb_flush_page_bits_locked() -> tlb_flush_range_locked(), and have callers pass a length argument (currently TARGET_PAGE_SIZE) via the TLBFlushPageBitsByMMUIdxData structure. Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 48 +++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 15 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f616b58a898..df5d5dbf879 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -707,8 +707,9 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } -static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, - target_ulong page, unsigned bits) +static void tlb_flush_range_locked(CPUArchState *env, int midx, + target_ulong addr, target_ulong len, + unsigned bits) { CPUTLBDesc *d = &env_tlb(env)->d[midx]; CPUTLBDescFast *f = &env_tlb(env)->f[midx]; @@ -718,20 +719,26 @@ static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, * If @bits is smaller than the tlb size, there may be multiple entries * within the TLB; otherwise all addresses that match under @mask hit * the same TLB entry. - * * TODO: Perhaps allow bits to be a few bits less than the size. * For now, just flush the entire TLB. + * + * If @len is larger than the tlb size, then it will take longer to + * test all of the entries in the TLB than it will to flush it all. */ - if (mask < f->mask) { + if (mask < f->mask || len > f->mask) { tlb_debug("forcing full flush midx %d (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - midx, page, mask); + TARGET_FMT_lx "/" TARGET_FMT_lx "+" TARGET_FMT_lx ")\n", + midx, addr, mask, len); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); return; } - /* Check if we need to flush due to large pages. */ - if ((page & d->large_page_mask) == d->large_page_addr) { + /* + * Check if we need to flush due to large pages. + * Because large_page_mask contains all 1's from the msb, + * we only need to test the end of the range. + */ + if (((addr + len - 1) & d->large_page_mask) == d->large_page_addr) { tlb_debug("forcing full flush midx %d (" TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, d->large_page_addr, d->large_page_mask); @@ -739,14 +746,20 @@ static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, return; } - if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask)) { - tlb_n_used_entries_dec(env, midx); + for (target_ulong i = 0; i < len; i += TARGET_PAGE_SIZE) { + target_ulong page = addr + i; + CPUTLBEntry *entry = tlb_entry(env, midx, page); + + if (tlb_flush_entry_mask_locked(entry, page, mask)) { + tlb_n_used_entries_dec(env, midx); + } + tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); } - tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); } typedef struct { target_ulong addr; + target_ulong len; uint16_t idxmap; uint16_t bits; } TLBFlushPageBitsByMMUIdxData; @@ -760,18 +773,20 @@ tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, assert_cpu_is_self(cpu); - tlb_debug("page addr:" TARGET_FMT_lx "/%u mmu_map:0x%x\n", - d.addr, d.bits, d.idxmap); + tlb_debug("range:" TARGET_FMT_lx "/%u+" TARGET_FMT_lx " mmu_map:0x%x\n", + d.addr, d.bits, d.len, d.idxmap); qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if ((d.idxmap >> mmu_idx) & 1) { - tlb_flush_page_bits_locked(env, mmu_idx, d.addr, d.bits); + tlb_flush_range_locked(env, mmu_idx, d.addr, d.len, d.bits); } } qemu_spin_unlock(&env_tlb(env)->c.lock); - tb_flush_jmp_cache(cpu, d.addr); + for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) { + tb_flush_jmp_cache(cpu, d.addr + i); + } } static bool encode_pbm_to_runon(run_on_cpu_data *out, @@ -829,6 +844,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; + d.len = TARGET_PAGE_SIZE; d.idxmap = idxmap; d.bits = bits; @@ -865,6 +881,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; + d.len = TARGET_PAGE_SIZE; d.idxmap = idxmap; d.bits = bits; @@ -908,6 +925,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id d3sm4507459wrs.41.2021.05.09.08.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData Date: Sun, 9 May 2021 17:16:12 +0200 Message-Id: <20210509151618.2331764-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index df5d5dbf879..36e7831ef70 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -762,11 +762,11 @@ typedef struct { target_ulong len; uint16_t idxmap; uint16_t bits; -} TLBFlushPageBitsByMMUIdxData; +} TLBFlushRangeData; static void tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, - TLBFlushPageBitsByMMUIdxData d) + TLBFlushRangeData d) { CPUArchState *env = cpu->env_ptr; int mmu_idx; @@ -790,7 +790,7 @@ tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, } static bool encode_pbm_to_runon(run_on_cpu_data *out, - TLBFlushPageBitsByMMUIdxData d) + TLBFlushRangeData d) { /* We need 6 bits to hold to hold @bits up to 63. */ if (d.idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) { @@ -800,11 +800,11 @@ static bool encode_pbm_to_runon(run_on_cpu_data *out, return false; } -static TLBFlushPageBitsByMMUIdxData +static TLBFlushRangeData decode_runon_to_pbm(run_on_cpu_data data) { target_ulong addr_map_bits = (target_ulong) data.target_ptr; - return (TLBFlushPageBitsByMMUIdxData){ + return (TLBFlushRangeData){ .addr = addr_map_bits & TARGET_PAGE_MASK, .idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6, .bits = addr_map_bits & 0x3f @@ -820,7 +820,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu, static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, run_on_cpu_data data) { - TLBFlushPageBitsByMMUIdxData *d = data.host_ptr; + TLBFlushRangeData *d = data.host_ptr; tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d); g_free(d); } @@ -828,7 +828,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -854,7 +854,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); } else { /* Otherwise allocate a structure, freed by the worker. */ - TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d)); + TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); } @@ -865,7 +865,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -893,7 +893,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { if (dst_cpu != src_cpu) { - TLBFlushPageBitsByMMUIdxData *p = g_memdup(&d, sizeof(d)); + TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); @@ -909,7 +909,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -935,7 +935,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, runon); } else { CPUState *dst_cpu; - TLBFlushPageBitsByMMUIdxData *p; + TLBFlushRangeData *p; /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { From patchwork Sun May 9 15:16:13 2021 Content-Type: text/plain; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id f6sm19892242wru.72.2021.05.09.08.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:39 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 4/9] accel/tcg: Add tlb_flush_range_by_mmuidx() Date: Sun, 9 May 2021 17:16:13 +0200 Message-Id: <20210509151618.2331764-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 19 +++++++++++++++++++ accel/tcg/cputlb.c | 20 +++++++++++++++----- 2 files changed, 34 insertions(+), 5 deletions(-) -- 2.26.3 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6b036cae8f6..5a5f6d4c1a8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -262,6 +262,20 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, void tlb_flush_page_bits_by_mmuidx_all_cpus_synced (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits); +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -365,6 +379,11 @@ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits) +{ +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 36e7831ef70..16924ceb777 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -825,14 +825,18 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, g_free(d); } -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, - uint16_t idxmap, unsigned bits) +void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits) { TLBFlushRangeData d; run_on_cpu_data runon; - /* If all bits are significant, this devolves to tlb_flush_page. */ - if (bits >= TARGET_LONG_BITS) { + /* + * If all bits are significant, and len is small, + * this devolves to tlb_flush_page. + */ + if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx(cpu, addr, idxmap); return; } @@ -844,7 +848,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; - d.len = TARGET_PAGE_SIZE; + d.len = len; d.idxmap = idxmap; d.bits = bits; @@ -860,6 +864,12 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, } } +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, + uint16_t idxmap, unsigned bits) +{ + tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); +} + void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr, uint16_t idxmap, From patchwork Sun May 9 15:16:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 432872 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2110169jao; Sun, 9 May 2021 08:22:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwqFU16sDXPJ5e5j0+ZHbyq99sQFtwQNAjy20bYDm+2MOjJ5iRVeFXYpnpRJ+xfKwuTIfAm X-Received: by 2002:a05:6e02:48b:: with SMTP id b11mr6745465ils.110.1620573765659; Sun, 09 May 2021 08:22:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620573765; cv=none; d=google.com; s=arc-20160816; b=cxQnwVqcXDpPAGxr86D+1j5DehtYJzVa043cKLram4OXAjt/orJKNhSU4pRgUoMWOk u/tTyWvccMGUwqbvXmEXSSZPYUpaWRDmwwykLuewqKl6VLU7dKJhPhNokeivbdJtVG6Y 3dOXBtuN/ClGJaIUQYCE0+iBCbr4TaB4g8ZImrwKIbmyt7c/cQaxAEPg9/vqneSdxtnp E3/XjfBQTaRO3vPkDY1qOgsyKH1Ls/k1kPqKuMJRFwb5CdxC2EM6fVwVrLSeFuhO6GDs 8YYRqi0zc2rKAT20XaQqxRpAzKCGvrIOsYOnRIc+TSRWssjV9N0DJf5UzET/BBnvpw06 kq1A== ARC-Message-Signature: i=1; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id p17sm18570283wru.1.2021.05.09.08.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 5/9] accel/tcg: Add tlb_flush_page_bits_by_mmuidx_all_cpus() Date: Sun, 9 May 2021 17:16:14 +0200 Message-Id: <20210509151618.2331764-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 13 +++++++++++++ accel/tcg/cputlb.c | 24 +++++++++++++++++------- 2 files changed, 30 insertions(+), 7 deletions(-) -- 2.26.3 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5a5f6d4c1a8..9a3dbb7ec08 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -276,6 +276,12 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, target_ulong len, uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -384,6 +390,13 @@ static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits) +{ +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 16924ceb777..5314349ef9d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -870,16 +870,18 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); } -void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap, - unsigned bits) +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, + target_ulong addr, target_ulong len, + uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; run_on_cpu_data runon; - /* If all bits are significant, this devolves to tlb_flush_page. */ - if (bits >= TARGET_LONG_BITS) { + /* + * If all bits are significant, and len is small, + * this devolves to tlb_flush_page. + */ + if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap); return; } @@ -891,7 +893,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; - d.len = TARGET_PAGE_SIZE; + d.len = len; d.idxmap = idxmap; d.bits = bits; @@ -914,6 +916,14 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d); } +void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, + target_ulong addr, + uint16_t idxmap, unsigned bits) +{ + tlb_flush_range_by_mmuidx_all_cpus(src_cpu, addr, TARGET_PAGE_SIZE, + idxmap, bits); +} + void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, target_ulong addr, uint16_t idxmap, From patchwork Sun May 9 15:16:15 2021 Content-Type: text/plain; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id 3sm15610156wms.30.2021.05.09.08.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced() Date: Sun, 9 May 2021 17:16:15 +0200 Message-Id: <20210509151618.2331764-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 12 ++++++++++++ accel/tcg/cputlb.c | 27 ++++++++++++++++++++------- 2 files changed, 32 insertions(+), 7 deletions(-) -- 2.26.3 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9a3dbb7ec08..8021adf38f4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -281,6 +281,11 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, target_ulong len, uint16_t idxmap, unsigned bits); +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits); /** * tlb_set_page_with_attrs: @@ -397,6 +402,13 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_long len, + uint16_t idxmap, + unsigned bits) +{ +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5314349ef9d..bc4370f4e21 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -924,16 +924,20 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, idxmap, bits); } -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap, - unsigned bits) +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits) { TLBFlushRangeData d; run_on_cpu_data runon; - /* If all bits are significant, this devolves to tlb_flush_page. */ - if (bits >= TARGET_LONG_BITS) { + /* + * If all bits are significant, and len is small, + * this devolves to tlb_flush_page. + */ + if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } @@ -945,7 +949,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, /* This should already be page aligned */ d.addr = addr & TARGET_PAGE_MASK; - d.len = TARGET_PAGE_SIZE; + d.len = len; d.idxmap = idxmap; d.bits = bits; @@ -972,6 +976,15 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, } } +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + uint16_t idxmap, + unsigned bits) +{ + tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu, addr, TARGET_PAGE_SIZE, + idxmap, bits); +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) From patchwork Sun May 9 15:16:16 2021 Content-Type: text/plain; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id m5sm4561059wrs.76.2021.05.09.08.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 Date: Sun, 9 May 2021 17:16:16 +0200 Message-Id: <20210509151618.2331764-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bc4370f4e21..47c83f0fc83 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -764,9 +764,8 @@ typedef struct { uint16_t bits; } TLBFlushRangeData; -static void -tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, - TLBFlushRangeData d) +static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, + TLBFlushRangeData d) { CPUArchState *env = cpu->env_ptr; int mmu_idx; @@ -814,14 +813,14 @@ decode_runon_to_pbm(run_on_cpu_data data) static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu, run_on_cpu_data runon) { - tlb_flush_page_bits_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon)); + tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon)); } static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, run_on_cpu_data data) { TLBFlushRangeData *d = data.host_ptr; - tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d); + tlb_flush_range_by_mmuidx_async_0(cpu, *d); g_free(d); } @@ -853,7 +852,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, d.bits = bits; if (qemu_cpu_is_self(cpu)) { - tlb_flush_page_bits_by_mmuidx_async_0(cpu, d); + tlb_flush_range_by_mmuidx_async_0(cpu, d); } else if (encode_pbm_to_runon(&runon, d)) { async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); } else { @@ -913,7 +912,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, } } - tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d); + tlb_flush_range_by_mmuidx_async_0(src_cpu, d); } void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, From patchwork Sun May 9 15:16:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 432875 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2110932jao; Sun, 9 May 2021 08:23:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwf/0TI2PoXqMTuf6+3PhW0wt5dRKCebcVz12OSFOXpad2XraOb1uD598o2I1Suh2/Zphkl X-Received: by 2002:a05:6e02:1069:: with SMTP id q9mr18172546ilj.217.1620573836494; Sun, 09 May 2021 08:23:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620573836; cv=none; d=google.com; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id h9sm15788362wmb.35.2021.05.09.08.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:16:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1] Date: Sun, 9 May 2021 17:16:17 +0200 Message-Id: <20210509151618.2331764-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 47c83f0fc83..ad0e44bce63 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -816,8 +816,8 @@ static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu, tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon)); } -static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, - run_on_cpu_data data) +static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu, + run_on_cpu_data data) { TLBFlushRangeData *d = data.host_ptr; tlb_flush_range_by_mmuidx_async_0(cpu, *d); @@ -858,7 +858,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, } else { /* Otherwise allocate a structure, freed by the worker. */ TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); - async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2, + async_run_on_cpu(cpu, tlb_flush_range_by_mmuidx_async_1, RUN_ON_CPU_HOST_PTR(p)); } } @@ -906,7 +906,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, if (dst_cpu != src_cpu) { TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); async_run_on_cpu(dst_cpu, - tlb_flush_page_bits_by_mmuidx_async_2, + tlb_flush_range_by_mmuidx_async_1, RUN_ON_CPU_HOST_PTR(p)); } } @@ -964,13 +964,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, CPU_FOREACH(dst_cpu) { if (dst_cpu != src_cpu) { p = g_memdup(&d, sizeof(d)); - async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2, + async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1, RUN_ON_CPU_HOST_PTR(p)); } } p = g_memdup(&d, sizeof(d)); - async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2, + async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, RUN_ON_CPU_HOST_PTR(p)); } } From patchwork Sun May 9 15:16:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 432876 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2111838jao; Sun, 9 May 2021 08:25:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHZPwpuUsdD1VK7oAX9sfyaT82A8zPKXDaFDVWu44Axa4UdpUUwFc09QMPnEl6fXN0O81y X-Received: by 2002:a67:8008:: with SMTP id b8mr16866740vsd.13.1620573926561; Sun, 09 May 2021 08:25:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620573926; cv=none; d=google.com; s=arc-20160816; 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[81.40.121.39]) by smtp.gmail.com with ESMTPSA id j13sm18099051wrw.93.2021.05.09.08.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 08:17:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ??? Date: Sun, 9 May 2021 17:16:18 +0200 Message-Id: <20210509151618.2331764-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210509151618.2331764-1-f4bug@amsat.org> References: <20210509151618.2331764-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Now than ... /* we use range? FILL ME... */ ... we can remove the encode_pbm_to_runon() and flush_all_helper() calls. Signed-off-by: Richard Henderson Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé --- XXX proper description, commit might be placed earlier in series. --- accel/tcg/cputlb.c | 86 +++++++++++----------------------------------- 1 file changed, 20 insertions(+), 66 deletions(-) -- 2.26.3 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ad0e44bce63..2f7088614a7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -788,34 +788,6 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, } } -static bool encode_pbm_to_runon(run_on_cpu_data *out, - TLBFlushRangeData d) -{ - /* We need 6 bits to hold to hold @bits up to 63. */ - if (d.idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) { - *out = RUN_ON_CPU_TARGET_PTR(d.addr | (d.idxmap << 6) | d.bits); - return true; - } - return false; -} - -static TLBFlushRangeData -decode_runon_to_pbm(run_on_cpu_data data) -{ - target_ulong addr_map_bits = (target_ulong) data.target_ptr; - return (TLBFlushRangeData){ - .addr = addr_map_bits & TARGET_PAGE_MASK, - .idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6, - .bits = addr_map_bits & 0x3f - }; -} - -static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu, - run_on_cpu_data runon) -{ - tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon)); -} - static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu, run_on_cpu_data data) { @@ -829,7 +801,6 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, unsigned bits) { TLBFlushRangeData d; - run_on_cpu_data runon; /* * If all bits are significant, and len is small, @@ -853,8 +824,6 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, if (qemu_cpu_is_self(cpu)) { tlb_flush_range_by_mmuidx_async_0(cpu, d); - } else if (encode_pbm_to_runon(&runon, d)) { - async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); } else { /* Otherwise allocate a structure, freed by the worker. */ TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); @@ -874,7 +843,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; - run_on_cpu_data runon; + CPUState *dst_cpu; /* * If all bits are significant, and len is small, @@ -896,19 +865,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, d.idxmap = idxmap; d.bits = bits; - if (encode_pbm_to_runon(&runon, d)) { - flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); - } else { - CPUState *dst_cpu; - - /* Allocate a separate data block for each destination cpu. */ - CPU_FOREACH(dst_cpu) { - if (dst_cpu != src_cpu) { - TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); - async_run_on_cpu(dst_cpu, - tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); - } + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu != src_cpu) { + TLBFlushRangeData *p = g_memdup(&d, sizeof(d)); + async_run_on_cpu(dst_cpu, + tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } } @@ -929,8 +892,8 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushRangeData d; - run_on_cpu_data runon; + TLBFlushRangeData d, *p; + CPUState *dst_cpu; /* * If all bits are significant, and len is small, @@ -952,27 +915,18 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, d.idxmap = idxmap; d.bits = bits; - if (encode_pbm_to_runon(&runon, d)) { - flush_all_helper(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon); - async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_1, - runon); - } else { - CPUState *dst_cpu; - TLBFlushRangeData *p; - - /* Allocate a separate data block for each destination cpu. */ - CPU_FOREACH(dst_cpu) { - if (dst_cpu != src_cpu) { - p = g_memdup(&d, sizeof(d)); - async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); - } + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu != src_cpu) { + p = g_memdup(&d, sizeof(d)); + async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } - - p = g_memdup(&d, sizeof(d)); - async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, - RUN_ON_CPU_HOST_PTR(p)); } + + p = g_memdup(&d, sizeof(d)); + async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); } void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,