From patchwork Tue Jul 3 05:57:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140898 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp767740ljj; Mon, 2 Jul 2018 23:08:10 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd9t9OkLI/M/OiY8OxcpnSt/0izr1Yz+/3gi2EPEmdLZgfGLLHQIBFNJ8TZ3UcvMYo1+DU/ X-Received: by 2002:a37:4f85:: with SMTP id d127-v6mr24603011qkb.183.1530598089928; Mon, 02 Jul 2018 23:08:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598089; cv=none; d=google.com; s=arc-20160816; b=gZeA9jZeFQqgml6sSIBYY9WZsE+cCrWKr2XRBODhOEbR3O/6ONmzSxYl6fxzVdn7Q6 KzyJ2vmzHMf15uJObHk6waec7oEFyn+8q1BtAkTc6urlaBsMX64sGM39ck8ZGBy8eHFn QAoafzlhBu6SKzvCTrgKX8096ZQ5Stg14iekT4wsT3lyXKpQGzYZUBtaCvYHcOp8gPqM FVMUCebAN1PO0UKce7qT6KdvnzrWD9Riitu/dtI4WBBQi+67ohkDFoh6Yy+DNN9Bkolj IYmUVeIUX85T3cdSwpE0SUlE6qisCJCQgyY5wBVB15JAs8QLhmjxXCqEAyGecn+fVqRl hd9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ExyJOnM0+3YIZKqgL5CAjzll9RYluH9gN1Lq+YPckeU=; b=m6FXnueKbUV6h9a+8iIv2/Hm2KKO/gajC7cbqZ0MSJuTtS3SiBk3/Eo272SvqBD949 R1JzzHHLy+yRbin80ZkivxTAG5CqRzBU1zNZKRXvDACzIGyw83wFPwnfyAyFZVBS72nW +gLFAkItUfxJLoJyBlSgqJn6bONsUjjWvzwJPprnA/hRHRMCslGunMQH0WggLWMeBWFS eiTfB+ICmqY72eyZwXR1aj3q7wcVPzbHuxZLDZKuYjhaQpof8tq1HN/+/VvObpaC5SvF PcyG+8baoBtA9wCd26AibtJgtQjBgEAKyrtR+vwBeBEcjJxx8wiDVxrC9dJgqXPgJVCg kDYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=f8Iran+G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id e1-v6si320876qvo.268.2018.07.02.23.08.09 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:08:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=f8Iran+G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faETx-0001xX-AP for patch@linaro.org; Tue, 03 Jul 2018 02:08:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKQ-0002mO-Fr for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKP-0006uJ-E2 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:18 -0400 Received: from ozlabs.org ([203.11.71.1]:33461) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKP-0006qT-1i; Tue, 03 Jul 2018 01:58:17 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM76lx8z9s8k; Tue, 3 Jul 2018 15:58:10 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597491; bh=uKJtkisTiKinECKXdYDXNin0kYLXxvzpO5mjwqT/BP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f8Iran+GJlRMkaXAmXEUvlBLe9S5dIbC6JD7wUoWqHy1zlw6G5Jy2ghFatq8yxSB9 PwrzKHNvS6RROIf59/Q5w6LR6RbHbAxbS+qxEFBLVpsxCLsam4RrEHjZ2xIow081VG Q6X6Z+7RQXh9jAnq9pxhlaMlANZmKPVscrCyTh1U= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:40 +1000 Message-Id: <20180703055804.13449-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 11/35] target/ppc: Add do_unaligned_access hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/excp_helper.c | 18 +++++++++++++++++- target/ppc/internal.h | 5 +++++ target/ppc/translate_init.inc.c | 1 + 3 files changed, 23 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index c092fbead0..d6e97a90e0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -22,7 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" - +#include "internal.h" #include "helper_regs.h" //#define DEBUG_OP @@ -1198,3 +1198,19 @@ void helper_book3s_msgsnd(target_ulong rb) qemu_mutex_unlock_iothread(); } #endif + +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + CPUPPCState *env = cs->env_ptr; + uint32_t insn; + + /* Restore state and reload the insn we executed, for filling in DSISR. */ + cpu_restore_state(cs, retaddr, true); + insn = cpu_ldl_code(env, env->nip); + + cs->exception_index = POWERPC_EXCP_ALIGN; + env->error_code = insn & 0x03FF0000; + cpu_loop_exit(cs); +} diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 1f441c6483..a9bcadff42 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -252,4 +252,9 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); + +/* Raise a data fault alignment exception for the specified virtual address */ +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #endif /* PPC_INTERNAL_H */ diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 76d6f3fd5e..7813b1b004 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10457,6 +10457,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = ppc_cpu_set_pc; cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_write_register = ppc_cpu_gdb_write_register; + cc->do_unaligned_access = ppc_cpu_do_unaligned_access; #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault; #else From patchwork Tue Jul 3 05:57:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140895 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp764019ljj; Mon, 2 Jul 2018 23:05:10 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcKqwnDIkSfF5O9WdywKZVNYegdFVJaw/4/6qntY6+N9bbvnUn1aU6vfpKq48oH7YRh17Jh X-Received: by 2002:a37:ae83:: with SMTP id x125-v6mr24882501qke.130.1530597910875; Mon, 02 Jul 2018 23:05:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530597910; cv=none; d=google.com; s=arc-20160816; b=sRZDYuTV6yroaCQ7GwI8PGMeDD8hn510QRFzkVI52V30lLJafMUz5mPAS1xQYi0uPI BK+DQkR6DnKmppO8gaBWs4DII1Q/EZNERARdRrXJp0p7TWE4dn9kph6xhrXpN753qHl6 fSUuusYG7GOEK8qcVw5SDaSK8Uf69uX/uVu7PeUmweCpwJcy68d5MHvGsGg8pLaUhx86 BmvgMT+r2RY4bfqBkbHwDHxpI1yWlHeINkimie2RGIa8DJkwla/BxH5hbz2aG1ApMRjq E097CXQGtRkCyaslPI8LXaHV4zVR+X0iqceYDjs4+qPgNYLXKg+2+IO5zff6vXriAHtP NCjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=fs+OFXgrj364vdFb+IvexEp5ify4p/ANr3E4/eog/4E=; b=k+ESbVwUmWZ+o9jOvmPySlhow4jR3JdpI/VZ771eyJ2zo7chcgittvDfgYQxt6jIhW NZfzlMy2gKapUDTepCPMGiZUHQ+CJkQNlARZ94nP9yKpjdaefXQU+R/xG78lpGhfwts6 AFZFZ3uM6FJRJ+NvyBaJJLTFOY3V08BYHDRMfEC2kwbkkdjHSIoCt5ZE63tqXPQLCnV3 +Keq4tUe0HmxX/FdOCHY4tEZGykjY15aEIs8fpHjlWA0VzdhdlrVZOy0xNoVIahsZdPS dv5phVk19b/PqrSBtwDUrj3pstaqksrvGhNExZHYSOIiiKiAPyyb6eWuf4jzKoF+kWUy 4L5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=eKC7DNEH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v185-v6si324286qkd.338.2018.07.02.23.05.10 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:05:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=eKC7DNEH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37957 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faER4-000799-AH for patch@linaro.org; Tue, 03 Jul 2018 02:05:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKU-0002r3-Ru for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKR-0006wh-Lt for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:22 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:38415) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKQ-0006td-T6; Tue, 03 Jul 2018 01:58:19 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM83gLbz9s8f; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597492; bh=pBgLmf8ySdtTV2Y4yNdwR4wXy7YFYYyGwDZs/oPOOdU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eKC7DNEHEBkO6EWIYyCgWCGNbAaJMytAZHSolGwdUQLPABba4D7UJRVQ4ABqwiQXU Yv+BtBRcDxFEtmHYq4SKub1cLV2p5alpxVGoSkurcVgl0MEQzvCbvg2IjeiHg7/MHW u8xJOQ1NjoQu/ecS0sfVdzTEtwu42qw+3j/cexWU= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:41 +1000 Message-Id: <20180703055804.13449-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 12/35] target/ppc: Use atomic load for LQ and LQARX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/cpu.h | 3 ++ target/ppc/helper.h | 5 +++ target/ppc/mem_helper.c | 20 ++++++++- target/ppc/translate.c | 91 ++++++++++++++++++++++++++++++----------- 4 files changed, 94 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c7f3fb6b73..973cf44cda 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1015,6 +1015,9 @@ struct CPUPPCState { /* Next instruction pointer */ target_ulong nip; + /* High part of 128-bit helper return. */ + uint64_t retxh; + int access_type; /* when a memory exception occurs, the access type is stored here */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d751f0e219..3f451a5d7e 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -799,3 +799,8 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) + +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +#endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index a34e604db3..44a8f3445a 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -21,9 +21,9 @@ #include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" - #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "tcg.h" #include "internal.h" //#define DEBUG_OP @@ -215,6 +215,24 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, return i; } +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, + uint32_t opidx) +{ + Int128 ret = helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); + env->retxh = int128_gethi(ret); + return int128_getlo(ret); +} + +uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, + uint32_t opidx) +{ + Int128 ret = helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); + env->retxh = int128_gethi(ret); + return int128_getlo(ret); +} +#endif + /*****************************************************************************/ /* Altivec extension helpers */ #if defined(HOST_WORDS_BIGENDIAN) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3a215a1dc6..0923cc24e3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2607,7 +2607,7 @@ static void gen_ld(DisasContext *ctx) static void gen_lq(DisasContext *ctx) { int ra, rd; - TCGv EA; + TCGv EA, hi, lo; /* lq is a legal user mode instruction starting in ISA 2.07 */ bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; @@ -2633,16 +2633,35 @@ static void gen_lq(DisasContext *ctx) EA = tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0x0F); - /* We only need to swap high and low halves. gen_qemu_ld64_i64 does - necessary 64-bit byteswap already. */ - if (unlikely(ctx->le_mode)) { - gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); + /* Note that the low part is always in RD+1, even in LE mode. */ + lo = cpu_gpr[rd + 1]; + hi = cpu_gpr[rd]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi = tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); } @@ -3236,9 +3255,8 @@ STCX(stdcx_, DEF_MEMOP(MO_Q)) /* lqarx */ static void gen_lqarx(DisasContext *ctx) { - TCGv EA; int rd = rD(ctx->opcode); - TCGv gpr1, gpr2; + TCGv EA, hi, lo; if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || (rd == rB(ctx->opcode)))) { @@ -3247,24 +3265,49 @@ static void gen_lqarx(DisasContext *ctx) } gen_set_access_type(ctx, ACCESS_RES); - EA = tcg_temp_local_new(); + EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - gen_check_align(ctx, EA, 15); - if (unlikely(ctx->le_mode)) { - gpr1 = cpu_gpr[rd+1]; - gpr2 = cpu_gpr[rd]; + + /* Note that the low part is always in RD+1, even in LE mode. */ + lo = cpu_gpr[rd + 1]; + hi = cpu_gpr[rd]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi = tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; + tcg_temp_free(EA); + return; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); + tcg_gen_mov_tl(cpu_reserve, EA); + gen_addr_add(ctx, EA, EA, 8); + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gpr1 = cpu_gpr[rd]; - gpr2 = cpu_gpr[rd+1]; + tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); + tcg_gen_mov_tl(cpu_reserve, EA); + gen_addr_add(ctx, EA, EA, 8); + tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); } - tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - tcg_gen_mov_tl(cpu_reserve, EA); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - - tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); tcg_temp_free(EA); + + tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); } /* stqcx. */ From patchwork Tue Jul 3 05:57:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140903 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp777116ljj; Mon, 2 Jul 2018 23:16:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdm2oiG8qICn02JaxvarJdgR5puq16KKepyQGf8tXKphvyfu4z8qA9zyhDuqu0PBgsD9lPs X-Received: by 2002:ac8:376a:: with SMTP id p39-v6mr15852423qtb.257.1530598583044; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id a25-v6si375038qtp.285.2018.07.02.23.16.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:16:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=miNqF7eR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38024 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEbu-0008PG-Dq for patch@linaro.org; Tue, 03 Jul 2018 02:16:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKT-0002pU-Mb for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKR-0006wZ-L4 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:21 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:46609) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKQ-0006tQ-Pz; Tue, 03 Jul 2018 01:58:19 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM820J3z9s5c; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597492; bh=+op4qHd5DWt9QN8eRmYhE6PDypEs4nGq0DdaqcdC1sE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=miNqF7eRHl5VoUaTsto9Sz4MTyboshlVvw1uO2yTyQZCCz9Y+s1ELJsotqCcwSJvy +kapJBwIcbeLZbEzPWVakQq3OQRrNcxajLB5WJ6VmFnaOEUvLEyYPV1+85WXxPAdIe LGF3c2YeGvDXpCN/jOd4FTHQBgOX/89jSCaI2oVI= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:42 +1000 Message-Id: <20180703055804.13449-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 13/35] target/ppc: Use atomic store for STQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/helper.h | 4 ++++ target/ppc/mem_helper.c | 14 ++++++++++++++ target/ppc/translate.c | 35 +++++++++++++++++++++++++++-------- 3 files changed, 45 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3f451a5d7e..cbc1228570 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -803,4 +803,8 @@ DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) #if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) +DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) +DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, + void, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 44a8f3445a..57e301edc3 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -231,6 +231,20 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, env->retxh = int128_gethi(ret); return int128_getlo(ret); } + +void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val = int128_make128(lo, hi); + helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); +} + +void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t lo, uint64_t hi, uint32_t opidx) +{ + Int128 val = int128_make128(lo, hi); + helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); +} #endif /*****************************************************************************/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0923cc24e3..3d63a62269 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2760,6 +2760,7 @@ static void gen_std(DisasContext *ctx) if ((ctx->opcode & 0x3) == 0x2) { /* stq */ bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; + TCGv hi, lo; if (!(ctx->insns_flags & PPC_64BX)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -2783,20 +2784,38 @@ static void gen_std(DisasContext *ctx) EA = tcg_temp_new(); gen_addr_imm_index(ctx, EA, 0x03); - /* We only need to swap high and low halves. gen_qemu_st64_i64 does - necessary 64-bit byteswap already. */ - if (unlikely(ctx->le_mode)) { - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + /* Note that the low part is always in RS+1, even in LE mode. */ + lo = cpu_gpr[rs + 1]; + hi = cpu_gpr[rs]; + + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { +#ifdef CONFIG_ATOMIC128 + TCGv_i32 oi = tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; +#endif + } else if (ctx->le_mode) { + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); } else { - gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); + tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); gen_addr_add(ctx, EA, EA, 8); - gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); + tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); } tcg_temp_free(EA); } else { - /* std / stdu*/ + /* std / stdu */ if (Rc(ctx->opcode)) { if (unlikely(rA(ctx->opcode) == 0)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); From patchwork Tue Jul 3 05:57:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140900 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp771590ljj; Mon, 2 Jul 2018 23:11:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdGPhv8DoceUEqNGelMPmjnrJlEBIr0BqUV2UV80zhU/meN18JGD/QXFS96Rn3oRQpHKn19 X-Received: by 2002:a0c:98d1:: with SMTP id g17-v6mr25113958qvd.27.1530598276920; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s53-v6si365345qta.352.2018.07.02.23.11.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:11:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="mc+eH5R/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEWy-0004Ze-AO for patch@linaro.org; Tue, 03 Jul 2018 02:11:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKR-0002nS-Mt for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKP-0006uq-VA for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:19 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:47075) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKP-0006qC-8K; Tue, 03 Jul 2018 01:58:17 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM73zhZz9s5b; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597491; bh=kZx9LNmQBYgUEikG2hSfR4qFM7Z4BSVR8Ym0xAxE+yI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mc+eH5R/rCB1wthQB11CymSH3PFa90brvozKXiVRVmewau/CYoCL7+OCyOmhdFOdg Xh/+X+mouZPLdXaZc2TfQBol33gtiD2HYlXgdzeOcyI8zJxDUnstwEIj6kSxyDyjH4 B5/55mrbwRUKxHDGI/F3c8ztVzIPh2wVyPtEE3qc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:43 +1000 Message-Id: <20180703055804.13449-15-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 14/35] target/ppc: Use atomic cmpxchg for STQCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/helper.h | 2 + target/ppc/mem_helper.c | 38 +++++++++++++++++ target/ppc/translate.c | 93 ++++++++++++++++++++++++++--------------- 3 files changed, 100 insertions(+), 33 deletions(-) -- 2.17.1 diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cbc1228570..5706c2497f 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -807,4 +807,6 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) +DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) +DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 57e301edc3..8f0d86d104 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -245,6 +245,44 @@ void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, Int128 val = int128_make128(lo, hi); helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } + +uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, + uint64_t new_lo, uint64_t new_hi, + uint32_t opidx) +{ + bool success = false; + + if (likely(addr == env->reserve_addr)) { + Int128 oldv, cmpv, newv; + + cmpv = int128_make128(env->reserve_val2, env->reserve_val); + newv = int128_make128(new_lo, new_hi); + oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, + opidx, GETPC()); + success = int128_eq(oldv, cmpv); + } + env->reserve_addr = -1; + return env->so + success * CRF_EQ_BIT; +} + +uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, + uint64_t new_lo, uint64_t new_hi, + uint32_t opidx) +{ + bool success = false; + + if (likely(addr == env->reserve_addr)) { + Int128 oldv, cmpv, newv; + + cmpv = int128_make128(env->reserve_val2, env->reserve_val); + newv = int128_make128(new_lo, new_hi); + oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, + opidx, GETPC()); + success = int128_eq(oldv, cmpv); + } + env->reserve_addr = -1; + return env->so + success * CRF_EQ_BIT; +} #endif /*****************************************************************************/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3d63a62269..c7b9d226eb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3332,50 +3332,77 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { - TCGv EA; - int reg = rS(ctx->opcode); - int len = 16; -#if !defined(CONFIG_USER_ONLY) - TCGLabel *l1; - TCGv gpr1, gpr2; -#endif + int rs = rS(ctx->opcode); + TCGv EA, hi, lo; - if (unlikely((rD(ctx->opcode) & 1))) { + if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } + gen_set_access_type(ctx, ACCESS_RES); - EA = tcg_temp_local_new(); + EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - if (len > 1) { - gen_check_align(ctx, EA, (len) - 1); - } -#if defined(CONFIG_USER_ONLY) - gen_conditional_store(ctx, EA, reg, 16); -#else - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); + /* Note that the low part is always in RS+1, even in LE mode. */ + lo = cpu_gpr[rs + 1]; + hi = cpu_gpr[rs]; - if (unlikely(ctx->le_mode)) { - gpr1 = cpu_gpr[reg + 1]; - gpr2 = cpu_gpr[reg]; + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); +#ifdef CONFIG_ATOMIC128 + if (ctx->le_mode) { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); + } else { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, oi); + } +#else + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; +#endif + tcg_temp_free(EA); + tcg_temp_free_i32(oi); } else { - gpr1 = cpu_gpr[reg]; - gpr2 = cpu_gpr[reg + 1]; - } - tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); + TCGLabel *lab_fail = gen_new_label(); + TCGLabel *lab_over = gen_new_label(); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); -#endif - tcg_temp_free(EA); -} + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + gen_qemu_ld64_i64(ctx, t0, cpu_reserve); + tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode + ? offsetof(CPUPPCState, reserve_val2) + : offsetof(CPUPPCState, reserve_val))); + tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + + tcg_gen_addi_i64(t0, cpu_reserve, 8); + gen_qemu_ld64_i64(ctx, t0, t0); + tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode + ? offsetof(CPUPPCState, reserve_val) + : offsetof(CPUPPCState, reserve_val2))); + tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + + /* Success */ + gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); + tcg_gen_addi_i64(t0, cpu_reserve, 8); + gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); + tcg_gen_br(lab_over); + gen_set_label(lab_fail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + } +} #endif /* defined(TARGET_PPC64) */ /* sync */ From patchwork Tue Jul 3 05:57:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140905 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp783713ljj; Mon, 2 Jul 2018 23:23:25 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdtCnXkGIrtR2ilRRp5K4krqYtD3xx2PuHxc6LzP1OHtNOjNNulVV+WwWX29EPWTrlLEAYs X-Received: by 2002:a37:9605:: with SMTP id y5-v6mr23796508qkd.236.1530599005801; Mon, 02 Jul 2018 23:23:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530599005; cv=none; d=google.com; s=arc-20160816; b=jgYQNzj2OkChpwqTxJ9xIY7bRABiMntHMQ6da2S3bYLUyXd+jhpW++bSAMzMo82AR4 wd4VbP3FKKAatYOdbaOzYzAbWEwyEo7Nd7En3sk79yM3Zl6cl3eLuojURwbV9BjzzuxH JdtJzJ1z1RV5OFqncqq5pEpTkjgxODEtFgS4NLbHydQY3+yZz2RGswvUvNQpQUYjwzr6 RJz4eBPJhP2Xw7OEjDUiLaG7NsPI+E7btRBESnOrS1pyKimiG5lypTk7mVpFKgN5htfZ Tr7+5Wwp9MWXCaW2hJVJklT2LYbTLeTdWeAQ3YsXvtQLula/hsq6bHb13Cnr/6OBoMaR Xpgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=TZgZAxqw/hZLiVnhjbkqkVWxlTEF/NewFWmVrfHa5go=; b=0WuvfaTua486/L8njwF8LUCZXmroXaAQnHBlBK8J6o8geFuvSLd7gO6shLlESTpdaP DRo0EwnbYNepb03MgzSt8uYSWOMHXFgMvc00pQl14sCViwOGNqRSzCG29XnVf3eDu1un zmYB8r7C/vcTmhjEVdi/8OHyXnSAESYg4urCFudqGKFrt0nRAfIOcMRz6+t8Ggt4DGuM y4/Krrsm6dPM8Zcah7H8B5Ky8yECf2ZqOGoEVoDGwQrU0H++f8OFv9eT4k2ypm5wtGv9 xisZD3U7zFMK3K02HCjA+umHcF6ibacOk/2YZHFgtEPIIcMByTZ1S6bhGIeLjHPrXAVO cMVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BiZ3C1T9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v184-v6si356610qkd.398.2018.07.02.23.23.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:23:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BiZ3C1T9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38072 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEij-0005XN-7O for patch@linaro.org; Tue, 03 Jul 2018 02:23:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKV-0002rC-P7 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006xs-IT for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:23 -0400 Received: from ozlabs.org ([203.11.71.1]:48151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006uF-P6; Tue, 03 Jul 2018 01:58:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM95kgWz9s9y; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=b9K6lgAlIlXGzW0zb2bBBQrlnAX0Fz3I1exeWmRL6qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BiZ3C1T91IVzidnguaTAMzKkEVb63YvVUJuEIFDVFTeAAJGT/O1EURTIl2tufHags wax2xynIWN/Oc4Ugbb+sR5Z6MP9Ae6mmGofKX5soAgikNGAym0WFtzcBnyF+09XhuK v8kTfrJektBuTaIcTnIgpZyCs4r5zlh65bAyeeLc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:44 +1000 Message-Id: <20180703055804.13449-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- linux-user/ppc/cpu_loop.c | 121 +++++++------------------------------- target/ppc/cpu.h | 5 -- target/ppc/translate.c | 14 ----- 3 files changed, 22 insertions(+), 118 deletions(-) -- 2.17.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 2fb516cb00..133a87f349 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -65,99 +65,23 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) return -1; } -static int do_store_exclusive(CPUPPCState *env) -{ - target_ulong addr; - target_ulong page_addr; - target_ulong val, val2 __attribute__((unused)) = 0; - int flags; - int segv = 0; - - addr = env->reserve_ea; - page_addr = addr & TARGET_PAGE_MASK; - start_exclusive(); - mmap_lock(); - flags = page_get_flags(page_addr); - if ((flags & PAGE_READ) == 0) { - segv = 1; - } else { - int reg = env->reserve_info & 0x1f; - int size = env->reserve_info >> 5; - int stored = 0; - - if (addr == env->reserve_addr) { - switch (size) { - case 1: segv = get_user_u8(val, addr); break; - case 2: segv = get_user_u16(val, addr); break; - case 4: segv = get_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv = get_user_u64(val, addr); break; - case 16: { - segv = get_user_u64(val, addr); - if (!segv) { - segv = get_user_u64(val2, addr + 8); - } - break; - } -#endif - default: abort(); - } - if (!segv && val == env->reserve_val) { - val = env->gpr[reg]; - switch (size) { - case 1: segv = put_user_u8(val, addr); break; - case 2: segv = put_user_u16(val, addr); break; - case 4: segv = put_user_u32(val, addr); break; -#if defined(TARGET_PPC64) - case 8: segv = put_user_u64(val, addr); break; - case 16: { - if (val2 == env->reserve_val2) { - if (msr_le) { - val2 = val; - val = env->gpr[reg+1]; - } else { - val2 = env->gpr[reg+1]; - } - segv = put_user_u64(val, addr); - if (!segv) { - segv = put_user_u64(val2, addr + 8); - } - } - break; - } -#endif - default: abort(); - } - if (!segv) { - stored = 1; - } - } - } - env->crf[0] = (stored << 1) | xer_so; - env->reserve_addr = (target_ulong)-1; - } - if (!segv) { - env->nip += 4; - } - mmap_unlock(); - end_exclusive(); - return segv; -} - void cpu_loop(CPUPPCState *env) { CPUState *cs = CPU(ppc_env_get_cpu(env)); target_siginfo_t info; - int trapnr; + int trapnr, sig; target_ulong ret; for(;;) { + bool arch_interrupt; + cpu_exec_start(cs); trapnr = cpu_exec(cs); cpu_exec_end(cs); process_queued_cpu_work(cs); - switch(trapnr) { + arch_interrupt = true; + switch (trapnr) { case POWERPC_EXCP_NONE: /* Just go on */ break; @@ -524,26 +448,15 @@ void cpu_loop(CPUPPCState *env) } env->gpr[3] = ret; break; - case POWERPC_EXCP_STCX: - if (do_store_exclusive(env)) { - info.si_signo = TARGET_SIGSEGV; + case EXCP_DEBUG: + sig = gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo = sig; info.si_errno = 0; - info.si_code = TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr = env->nip; + info.si_code = TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_DEBUG: - { - int sig; - - sig = gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo = sig; - info.si_errno = 0; - info.si_code = TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + } else { + arch_interrupt = false; } break; case EXCP_INTERRUPT: @@ -551,12 +464,22 @@ void cpu_loop(CPUPPCState *env) break; case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt = false; break; default: cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); break; } process_pending_signals(env); + + /* Most of the traps imply a transition through kernel mode, + * which implies an REI instruction has been executed. Which + * means that RX and LOCK_ADDR should be cleared. But there + * are a few exceptions for traps internal to QEMU. + */ + if (arch_interrupt) { + env->reserve_addr = -1; + } } } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 973cf44cda..4edcf62cf7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -196,7 +196,6 @@ enum { /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ - POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ }; /* Exceptions error codes */ @@ -994,10 +993,6 @@ struct CPUPPCState { /* Reservation value */ target_ulong reserve_val; target_ulong reserve_val2; - /* Reservation store address */ - target_ulong reserve_ea; - /* Reserved store source register and size */ - target_ulong reserve_info; /* Those ones are used in supervisor mode only */ /* machine state register */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c7b9d226eb..03e8c5df03 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,19 +3201,6 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif -#if defined(CONFIG_USER_ONLY) -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) -{ - TCGv t0 = tcg_temp_new(); - - tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); - tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); - tcg_temp_free(t0); - gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); -} -#else static void gen_conditional_store(DisasContext *ctx, TCGv EA, int reg, int memop) { @@ -3244,7 +3231,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, gen_set_label(l2); tcg_gen_movi_tl(cpu_reserve, -1); } -#endif #define STCX(name, memop) \ static void gen_##name(DisasContext *ctx) \ From patchwork Tue Jul 3 05:57:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140896 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp764076ljj; Mon, 2 Jul 2018 23:05:13 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfXcsAdsLH99tIQ+VDuLmbrNM9ljNS812R7NtpF93FlqZdRyJPCeqBOYAoaNOHFoWrPSgK7 X-Received: by 2002:a37:6301:: with SMTP id x1-v6mr24379647qkb.403.1530597913374; Mon, 02 Jul 2018 23:05:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530597913; cv=none; d=google.com; s=arc-20160816; b=YPJYoGj/8HzRoWptm+L1MjXOh8DPpzzAetHHlkopiXm93wjcgivLpC7SkDT5V7yahE ksSSGYLNlERTAv6jwGkD/kFGLeuJga8aBiEPv8r/q80Za7yWFltdLGIJrBlvg7lwpi0Q 1dBxKpHsMBldT3Otwbba/wbNZH0byxyFXtoWMfEvATjPmXSbDHIqrFdjNxsSz5+1i//j OE/SwJ44jW2hKSTAMziH1HYUTxsltUWmPJdSfFVUf0aEw91xNZVJZ3VHOPErw56bpzXk 67jeL0A4gUMbENHsS5kB1LziLsnUFX/Nm1matDAbw7ySt/LZJ8+dJ5/I2rY6bLN3tmqQ 9zyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ziMsUkJ+Txm8dbTb8YU94Glc+CC1pemqXBLKgkbGmN4=; b=xQoc43Q3u3xhBPE9dxoZdskOOfohVxL91tfSuXeqjF4Fi3y3FiNKytgxKJSvDIraPX sszOcG106wwZt8h2UmwTLbYdiuzbikgqDAxcegVIRMFWdwG6Okkz9qhv+PiSeLEQU1MB +lEro6G0Hb6U72NATnfeSZp8Ee6hZvicbhNoNfaGjfdDpbVloTUBpR4tCuAxK7+MPoda 0St6lBPATJLqHyYKWQa52AJXhzpUKy/+BRH1HguozR67FZfi32IbEl5ozrX5HzqN5UiX 3K8JLQ1lDjVA4hnEw2vpEAAsDRUtf/wGi1nu/FBSXL7bT1me13nP+lHcmJdlAU+PCft2 dyng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=FXkkjx29; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b4-v6si330922qto.332.2018.07.02.23.05.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:05:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=FXkkjx29; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faER6-0007y6-Lz for patch@linaro.org; Tue, 03 Jul 2018 02:05:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKU-0002pt-3c for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006xV-B2 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:22 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:56759) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006ty-PB; Tue, 03 Jul 2018 01:58:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM92HsWz9sBb; Tue, 3 Jul 2018 15:58:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=56GIdrD5g+BR6+2TQKBJx3WZ9W4j3UkpY4pjY0N6cZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FXkkjx29b7g1IxcwuGqYyW1kE9UhUFIbmRejtgsYyjTZ7+TOhGoUY/mow9LWq/EI+ l9SCRPzMYLNKK9wVTf85194doV8UHkW+7OQWOWpVU1jRvjeSi4OEGXF2V/74wVIdaY EHq1c3ww6p+JukIg/2lcOaIfPoDeiXMk7YtmKAoc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:45 +1000 Message-Id: <20180703055804.13449-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 16/35] target/ppc: Tidy gen_conditional_store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave only the minimal amount of code within the STCX macro, moving the rest of the code into gen_conditional_store. Remove the explicit call to gen_check_align; the matching LDAX will have already checked alignment, and we verify the same address. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 03e8c5df03..e751072404 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3201,14 +3201,17 @@ ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) #endif -static void gen_conditional_store(DisasContext *ctx, TCGv EA, - int reg, int memop) +static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) { TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); - TCGv t0; + TCGv t0 = tcg_temp_new(); + int reg = rS(ctx->opcode); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); + gen_set_access_type(ctx, ACCESS_RES); + gen_addr_reg_index(ctx, t0); + tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_temp_free(t0); t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, @@ -3232,19 +3235,10 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA, tcg_gen_movi_tl(cpu_reserve, -1); } -#define STCX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv t0; \ - int len = MEMOP_GET_SIZE(memop); \ - gen_set_access_type(ctx, ACCESS_RES); \ - t0 = tcg_temp_local_new(); \ - gen_addr_reg_index(ctx, t0); \ - if (len > 1) { \ - gen_check_align(ctx, t0, (len) - 1); \ - } \ - gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ - tcg_temp_free(t0); \ +#define STCX(name, memop) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + gen_conditional_store(ctx, memop); \ } STCX(stbcx_, DEF_MEMOP(MO_UB)) From patchwork Tue Jul 3 05:57:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140888 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp756709ljj; Mon, 2 Jul 2018 22:58:52 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeS333aBBaHwezOXIDh0CHkqTUsAEpLGnQ0fZ6opZaPGrc9I5jArMbJzVPj9bmeK0RdknKV X-Received: by 2002:a37:258b:: with SMTP id l11-v6mr23876493qkl.438.1530597532386; Mon, 02 Jul 2018 22:58:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530597532; cv=none; d=google.com; s=arc-20160816; b=nXtcfeLHcgFDONKSq4N50XS33Nb82bZuv+cbzWuymAxQMvNMYZCd9AkB/T00sLv1of vVV+V0XIzJXaM6raRBMicPfSQQ0tVRZi0+a8NNFNF2dWtXbqTFm8tRb3HXgZZKyRmoV9 KQ/Qkn46aOrXhHeKsZzkkzv5lzNCn3zPi9rhJs/pbCulZNJnJ6bdx8Xlf3Gg7rWJmFZN kyAY0btCGndOEmqePyq3Nt9ZP0YlWc7joqW1XGZU6rvZN3Ksw9PWUhx70+YbOTSFIYhq YZcqYvCKNg5JSfQs0mCkzcJvXrEIatcNNYHh1EV5ZHTGYM/NQqJb84jEzfzOuiaPUBp/ k/Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=tuBXnu7qY45o7+ayJX5gnvnCXU+3wpzMRmkL4imSlgY=; b=nmCXPtruylcgqNAjuOM0z12Ux2z3C8+LvEBzh94+AbTWF90IM82tm0iUSZfHEkgwzX qObbNxLmU8b4v1dbakKf86EQYhyjF1/hGWwkzsPB46tQu66ExBnEPgDe6TFPrWqoDG+g KRz9jFfacBEDz6gU6he52J4uUXfRF0GWKwgFE6PFb2XIYnxrVqgjwOI3UdFcRmgCHR5P xON7+vOOFRRnC6WD2TxDyMeKc5UpqBR7thgdMpTmUTrVazTOpX92OYYSvtKEOy6urKLv xdMHCU7Rbvb4gmPB2au1W0Oh7SMTTWgVT1TWOoS4w/CZO0IVOkYj4e5AfJRZxEUpPjQ/ PGyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=QcFArCdX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g4-v6si322763qth.293.2018.07.02.22.58.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 22:58:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=QcFArCdX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKx-0002t5-TL for patch@linaro.org; Tue, 03 Jul 2018 01:58:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKT-0002pS-Md for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006x1-0q for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:21 -0400 Received: from ozlabs.org ([203.11.71.1]:41219) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006tz-Jc; Tue, 03 Jul 2018 01:58:19 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM94Y0Bz9s9T; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=jQ+D44/6jbdI34RwZC4Q7pAZmq+H1BaA5lJmD7EFNgs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QcFArCdXduJQnmhMmaW8S3ClL1fpk6OwWHH7Ao3RRXk5oMEDjMIMdZRTUHPxgCWHD hcieqOttoGAyOk4eVtEcRW/0XmhKabvD27rz4vCoJrOMr0Sq3HhCx2FF65nZLezFRo sUK4/1Z6K3N9adCXBbSK6Ed8efR5Nrpxq+pmWHik= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:46 +1000 Message-Id: <20180703055804.13449-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 17/35] target/ppc: Split out gen_load_locked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Leave only the minimal amount of code within the LDAR macro, moving the rest of the code into gen_load_locked. Use MO_ALIGN and remove the explicit call to gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e751072404..f48fcbeefb 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3070,23 +3070,24 @@ static void gen_isync(DisasContext *ctx) #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - TCGv t0; \ - TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ - int len = MEMOP_GET_SIZE(memop); \ - gen_set_access_type(ctx, ACCESS_RES); \ - t0 = tcg_temp_local_new(); \ - gen_addr_reg_index(ctx, t0); \ - if ((len) > 1) { \ - gen_check_align(ctx, t0, (len)-1); \ - } \ - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ - tcg_gen_mov_tl(cpu_reserve, t0); \ - tcg_gen_mov_tl(cpu_reserve_val, gpr); \ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \ - tcg_temp_free(t0); \ +static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) +{ + TCGv gpr = cpu_gpr[rD(ctx->opcode)]; + TCGv t0 = tcg_temp_new(); + + gen_set_access_type(ctx, ACCESS_RES); + gen_addr_reg_index(ctx, t0); + tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); + tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_mov_tl(cpu_reserve_val, gpr); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + tcg_temp_free(t0); +} + +#define LARX(name, memop) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + gen_load_locked(ctx, memop); \ } /* lwarx */ From patchwork Tue Jul 3 05:57:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140899 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp768118ljj; Mon, 2 Jul 2018 23:08:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdvsjyPzKOl8Dm01WKQQRyMq2VedkSKzspZZ+9uI5vcBSqufsIRatqE0gVXOQzerxthovQc X-Received: by 2002:ac8:174a:: with SMTP id u10-v6mr19081542qtk.367.1530598108398; Mon, 02 Jul 2018 23:08:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598108; cv=none; d=google.com; s=arc-20160816; b=SN5SMPqunsNAnwP2+ha1Ec5zU2wToVmho4FkZrSpkjnj/+eGozkIPxleImseEXP3uQ TJo7cCPi1Pxqyi3HZKy+p0cF/niX6N/Iz1mvsvXgxv8o8/NvqUunmyErpM3k+Tq78tw+ /Zq2/6PscWycFOHQ2eH3Xa0DKs3cip3I1aE1kBEtGWunU2Zx47bmIORViYSBIy2Zs2re vQYx3ycvPfzrFGF1zpH/LuSXH8fUEnCavj/OF4ZhBBI6hegYYVLNWkVHzEf/IRf9wOER rez20/WOmP9I44kmx2YUMQ2uKVHkjgc1t2l13xO41R1PL4c7tWKuuAKSssK/zD6E2vzw iHfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=dwYs5YSf+jutZyAdGBbEg9XfxsF9RIINPa/eHcDKyvk=; b=xhqw/Sj8+W7KP8dmrnx8OsNI85hIfY9PVKxWG0pU8t7fk4iM1N0LcOQ7XnMRm3lILR XeJwKk4IUPa7Of6vHJT8OxQ5/5H69AW2pEr9XGR9nBiPT2Dwuzm/1YNsziotDWs/xAOr cpKy6xnr4BV/EOG1APXAsjzxlCWx05nAhFJ0S2h7uEWxh1vWRLzhVMYnC8nIPtENaN/G ScklNxCZBzMKdzKC+qJ7lFhfi34lKCQ5L51iPMI1stymzcvkabq4id103CHwLZUxJ2gz yszpUD9/KRlgF31vZEn+CsBCxjrebWTvRBISyVnHyLfKLCmLIY/TXIx6U6/VgIRMV+RF c3HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=N9pkRrvf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q53-v6si352455qte.315.2018.07.02.23.08.28 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:08:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=N9pkRrvf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37985 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEUF-0002Bp-QU for patch@linaro.org; Tue, 03 Jul 2018 02:08:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKW-0002rG-Mu for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKT-0006yn-PD for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:24 -0400 Received: from ozlabs.org ([203.11.71.1]:46381) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKS-0006um-Vy; Tue, 03 Jul 2018 01:58:21 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM96KkZz9s9G; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597493; bh=82ysa0rNFDy/kfS7HaxFjTLARUbZmvxjdH6OTbl17BM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N9pkRrvfVc5BBktEXEI6go+Y311we8KEUjf1qp1Ee01Yq1UtD/iAP6Ie0N04Uvjvb qgV4ACqutqeRcNDTa8ltHPYfH2R5xJGXHcCQ046rVzVFppgn+a6F/AhAqKALbL8IY7 FBOuC/xVQEnkUVP7o3PVpjWE7jehN6MgoxQ9lmwg= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:47 +1000 Message-Id: <20180703055804.13449-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 18/35] target/ppc: Split out gen_ld_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 105 ++++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f48fcbeefb..361b178db8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3095,61 +3095,60 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) -#define LD_ATOMIC(name, memop, tp, op, eop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len = MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC = FC(ctx->opcode); \ - TCGv EA = tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 = tcg_temp_new_##tp(); \ - t1 = tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* Fetch and add */ \ - tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* Fetch and xor */ \ - tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Fetch and or */ \ - tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* Fetch and 'and' */ \ - tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 8: /* Swap */ \ - tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Fetch and max unsigned */ \ - case 5: /* Fetch and max signed */ \ - case 6: /* Fetch and min unsigned */ \ - case 7: /* Fetch and min signed */ \ - case 16: /* compare and swap not equal */ \ - case 24: /* Fetch and increment bounded */ \ - case 25: /* Fetch and increment equal */ \ - case 28: /* Fetch and decrement bounded */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ +static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC = FC(ctx->opcode); + TCGv EA = tcg_temp_new(); + TCGv src, dst; + + gen_addr_register(ctx, EA); + dst = cpu_gpr[rD(ctx->opcode)]; + src = cpu_gpr[rD(ctx->opcode) + 1]; + + memop |= MO_ALIGN; + switch (gpr_FC) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + case 5: /* Fetch and max signed */ + case 6: /* Fetch and min unsigned */ + case 7: /* Fetch and min signed */ + case 16: /* compare and swap not equal */ + case 24: /* Fetch and increment bounded */ + case 25: /* Fetch and increment equal */ + case 28: /* Fetch and decrement bounded */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(EA); } -LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl) -#if defined(TARGET_PPC64) -LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64) +static void gen_lwat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_ldat(DisasContext *ctx) +{ + gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif #define ST_ATOMIC(name, memop, tp, op) \ From patchwork Tue Jul 3 05:57:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140904 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp781484ljj; Mon, 2 Jul 2018 23:20:57 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfqHHtLJrh87lMDjrhalS0nspVVBQ309axwa11Bc4bkkCHhYwZDxaCy03A0A/1CGLqhoInY X-Received: by 2002:a0c:e90c:: with SMTP id a12-v6mr10030927qvo.224.1530598857041; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id o2-v6si377859qto.294.2018.07.02.23.20.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:20:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=BUmh7uHz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEgK-0004Kt-9z for patch@linaro.org; Tue, 03 Jul 2018 02:20:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39827) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKW-0002rF-Gm for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKT-0006yv-T0 for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:24 -0400 Received: from ozlabs.org ([203.11.71.1]:52583) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKT-0006vi-3I; Tue, 03 Jul 2018 01:58:21 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMB0MTbz9sBJ; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597494; bh=aVS2gFIN8wMUj6HW1raMgi+7caIQqex88I1ycTzdwzY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BUmh7uHzDW3ExlUbWYNSoaHvFNw3CvRy+i1T0NTNPRSt9OJkOG6LVjEw0Y0EbXdXo x0u94iUbGUe3GY52iiykUaukh+Npsy/D3iez78nClX+RW82eFfOXkUFZ7ePqRGLCVD GuIPNh7+FPOshqUlNWmnB9zjo0jvbOjmYuONSMoo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:48 +1000 Message-Id: <20180703055804.13449-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 19/35] target/ppc: Split out gen_st_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the guts of ST_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 97 +++++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 48 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 361b178db8..53ca8f0114 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3151,54 +3151,55 @@ static void gen_ldat(DisasContext *ctx) } #endif -#define ST_ATOMIC(name, memop, tp, op) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - int len = MEMOP_GET_SIZE(memop); \ - uint32_t gpr_FC = FC(ctx->opcode); \ - TCGv EA = tcg_temp_local_new(); \ - TCGv_##tp t0, t1; \ - \ - gen_addr_register(ctx, EA); \ - if (len > 1) { \ - gen_check_align(ctx, EA, len - 1); \ - } \ - t0 = tcg_temp_new_##tp(); \ - t1 = tcg_temp_new_##tp(); \ - tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \ - \ - switch (gpr_FC) { \ - case 0: /* add and Store */ \ - tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 1: /* xor and Store */ \ - tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 2: /* Or and Store */ \ - tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 3: /* 'and' and Store */ \ - tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \ - break; \ - case 4: /* Store max unsigned */ \ - case 5: /* Store max signed */ \ - case 6: /* Store min unsigned */ \ - case 7: /* Store min signed */ \ - case 24: /* Store twin */ \ - gen_invalid(ctx); \ - break; \ - default: \ - /* invoke data storage error handler */ \ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \ - } \ - tcg_temp_free_##tp(t0); \ - tcg_temp_free_##tp(t1); \ - tcg_temp_free(EA); \ -} - -ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32) -#if defined(TARGET_PPC64) -ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64) +static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) +{ + uint32_t gpr_FC = FC(ctx->opcode); + TCGv EA = tcg_temp_new(); + TCGv src, discard; + + gen_addr_register(ctx, EA); + src = cpu_gpr[rD(ctx->opcode)]; + discard = tcg_temp_new(); + + memop |= MO_ALIGN; + switch (gpr_FC) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + case 5: /* Store max signed */ + case 6: /* Store min unsigned */ + case 7: /* Store min signed */ + case 24: /* Store twin */ + gen_invalid(ctx); + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + tcg_temp_free(discard); + tcg_temp_free(EA); +} + +static void gen_stwat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); +} + +#ifdef TARGET_PPC64 +static void gen_stdat(DisasContext *ctx) +{ + gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); +} #endif static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) From patchwork Tue Jul 3 05:57:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140894 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp763519ljj; Mon, 2 Jul 2018 23:04:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcl+dlGIn7kog59BtXef80BkHmzskmB79BD3ShtURNpUNfjNpJS/jKVHnpZD4iF+KT631uF X-Received: by 2002:a0c:89f8:: with SMTP id 53-v6mr21918521qvs.233.1530597884409; Mon, 02 Jul 2018 23:04:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530597884; cv=none; d=google.com; s=arc-20160816; b=DcFUuzD/jLyaECET2Batj+jllYqz7jTwvH6sFE/tVIX7O8ivzgFiYvSK0NToAzrjqW xaQma1bsybeNK+ICVBTB0hSWC3ZtpQTFsHzb0mlK+iFaM9pTXYGXZk5AyDeIVxQCHxHD JMoYl98SF8oTiqc5GtClutbeMvn46NItdiiK86Pb0ZKJKhLepZxxDtGzWC6DK+AYNmAX CpA121D9cP4Ve+L2U7AVvFpb26NnbFf12pYOJrsrcSQ5niF95tjwQEDafrxz1syAZ759 wEoizNwvcsYvyxVxsJa+RIUPY1bGDz5RZSHu0Ehg9IeQ7ABRtk4dV5OqZuhlxGfmf2hf FL/g== ARC-Message-Signature: i=1; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id c59-v6si371885qva.149.2018.07.02.23.04.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:04:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=dsl25rdQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37956 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEQd-0006oO-Ps for patch@linaro.org; Tue, 03 Jul 2018 02:04:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKU-0002qE-8l for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKS-0006xc-CS for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:22 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:44505) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKR-0006tp-NB; Tue, 03 Jul 2018 01:58:20 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYM85BWyz9s78; Tue, 3 Jul 2018 15:58:12 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597492; bh=/tGRmhjXbAUf/n5ke5eecw2i4jfxDvsr5FNtGq//Rqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dsl25rdQOG4G8tXG1eJzqvKhlG/NQpstUuxqtR3qeBXsxDJrh5CLa/AZc9iadhkk1 Hux5BW6J04Sp9EWF9zX6TCx761QxOXz239OsprLiLHJSfRMFUfiGGY4H9mmvrsnqrM vjlMdb+KioqjVy/jgunaumCasajL7cZwKgL4gFqw= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:49 +1000 Message-Id: <20180703055804.13449-21-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 20/35] target/ppc: Use MO_ALIGN for EXIWX and ECOWX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This avoids the need for gen_check_align entirely. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 53ca8f0114..c2a28be6d7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2388,23 +2388,6 @@ static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, } } -static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) -{ - TCGLabel *l1 = gen_new_label(); - TCGv t0 = tcg_temp_new(); - TCGv_i32 t1, t2; - tcg_gen_andi_tl(t0, EA, mask); - tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); - t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); - t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); - gen_update_nip(ctx, ctx->base.pc_next - 4); - gen_helper_raise_exception_err(cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - gen_set_label(l1); - tcg_temp_free(t0); -} - static inline void gen_align_no_le(DisasContext *ctx) { gen_exception_err(ctx, POWERPC_EXCP_ALIGN, @@ -4706,8 +4689,8 @@ static void gen_eciwx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_EXT); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x03); - gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); + tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, + DEF_MEMOP(MO_UL | MO_ALIGN)); tcg_temp_free(t0); } @@ -4719,8 +4702,8 @@ static void gen_ecowx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_EXT); t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x03); - gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); + tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, + DEF_MEMOP(MO_UL | MO_ALIGN)); tcg_temp_free(t0); } From patchwork Tue Jul 3 05:57:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140902 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp775082ljj; Mon, 2 Jul 2018 23:14:32 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe0wtwk02fJKHYkHENxIOgMQ/NmGGvnjQM8wIDt2ApZIbCFEuO3jjJHK3GmYPelpJIBNagT X-Received: by 2002:ac8:5393:: with SMTP id x19-v6mr25315164qtp.402.1530598472632; Mon, 02 Jul 2018 23:14:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598472; cv=none; d=google.com; s=arc-20160816; b=MawlpOLtgNkEnH7j1LZRPn93YmFZ1hLGvnQ2kfCcjqHoswcavf07cu2oOwk8XR3tWo kFCzaxuE9r7lrCN+lUhzH8IF9YxXT1LJckMOJJ5MGpxPJ7xInDSSml1t3Mufq30i6KRu i0BQmFaC5JtNqd7yGLp6QjelDJSA9W7Al62TDu8QrDf21+Ub1tLuiPAOdEGDwUozcS9a 1vZ6AVQfUMP+uyUY7dHQFp5ohvUvUgTFcFl6NBnGr1qLuDYNyXRXZSO5y4oqQ6ATSDls y6r+vJ5mHBkwckz8Yw+4xsn3u2ql8Xnam1yEVetptXwXdrd7JyyVGlHmnn4bK1j0wuPA uAUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=BrMzsLYVwDH9ITY8PASiQlCZHKk4XnJt079Q788CcCo=; b=fyshBuLI2FIVr94Oq/ZqijkPeEVzvKOFWIXdpZifdT2Mumg1LT7l+TyXs1uR6HVp44 lMQvTAwyUtLjyRyCHZYU8K9nfvbt4IcF4soJFWFmhXQZPj35pBLDlyB0P/oFvQIV57ye hvZ3kGKxtGuskKWn1/nemiciw6UNGLBUj0QeXSbuiN1vvfMSCI/ZR4e0vVOWdxH5iccE CNInWtwc31xz772Scq8a5AK0dc38hcru93eX/whNaQKCWqihEEmKMZIPgO0UpEVof8Dn FPvVvF3Ms4lKxHGNIwDCx03unCIgLwLMezktuePRKc7AqlLpPDzsOL0ostA9kyF17+iC qlbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=RBsaun2t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id z124-v6si387733qke.27.2018.07.02.23.14.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:14:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=RBsaun2t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEa7-0006ol-Ut for patch@linaro.org; Tue, 03 Jul 2018 02:14:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39956) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKZ-0002uj-Ro for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKV-00070i-5P for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from ozlabs.org ([203.11.71.1]:54425) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKU-0006y7-Mf; Tue, 03 Jul 2018 01:58:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMC0K50z9sBk; Tue, 3 Jul 2018 15:58:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597495; bh=K5siGL/TPnZ2c+RHbEMCenbhb5lOhB7Qo5pf7b3L9wc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RBsaun2ttV6N3/Wk63rulA7YCyb1Za+/H7KwAyQX7I7npmBuLPbq26ejLsR1+mzBG Ca8Azu3LfePn/qwWwNhw9e7witpdVJBe7ZB2h7oYddf5hgPi1y2VTFOKg6nTaopZgz 85lXz6/TJsaHeAfgLtz2DB9tXEaSmjZd9N8OTjyA= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:50 +1000 Message-Id: <20180703055804.13449-22-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 21/35] target/ppc: Use atomic min/max helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These operations were previously unimplemented for ppc. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2a28be6d7..79285b6698 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3102,13 +3102,21 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) case 3: /* Fetch and 'and' */ tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); break; - case 8: /* Swap */ - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); - break; case 4: /* Fetch and max unsigned */ + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); + break; case 5: /* Fetch and max signed */ + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); + break; case 6: /* Fetch and min unsigned */ + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); + break; case 7: /* Fetch and min signed */ + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; case 16: /* compare and swap not equal */ case 24: /* Fetch and increment bounded */ case 25: /* Fetch and increment equal */ @@ -3159,9 +3167,17 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); break; case 4: /* Store max unsigned */ + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; case 5: /* Store max signed */ + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; case 6: /* Store min unsigned */ + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; case 7: /* Store min signed */ + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; case 24: /* Store twin */ gen_invalid(ctx); break; From patchwork Tue Jul 3 05:57:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140897 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp765487ljj; Mon, 2 Jul 2018 23:06:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfU3H+K4g8zMhPM/MZnhEOIKJCi91+hDLu1L1qV8tDQKsPIP2cH9GN/x6ar9WgxBeyQJI6A X-Received: by 2002:a37:7c6:: with SMTP id 189-v6mr16197776qkh.15.1530597982892; Mon, 02 Jul 2018 23:06:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530597982; cv=none; d=google.com; s=arc-20160816; b=xf76wXxwRc3OfgCG93pOklWTsbBMWvE50ZvP7eMp9PYtc5RrSzdsbK/SMJXg2PAIso sI3YetKP5qJguEJesPTfjzz840HAZI50MtFD9OebbbXsuKhDlv8XQpq7kwWHbKf1r5Hy 5iR1+mf2pe5xW2Ziv8J3GVLWaHzKL9nFNKWo/UyCiprojqeE0YjPtAOX/h7eEj5LBDs8 C1oYFNSHUPBe3gg8hcrz+w9bALS+0ELf7owg6jkXzmRXqyr4zdvf3GXNyyNGj2pKhUWv tBZ59vK6rSahzMHWrqOCLwWxU9A9wWdFARPXQUHuN+bSO1HVKaxND8/eSIIk3gwGiVUO I12w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=89BjUrFOXUP96RNHzUQS4+21FyUqbcHnhG5H7AonNik=; b=DZS7MqTVBxT6x0nMKB6ALBlUs1/pG+rc0Qo64cJh5jVlUT8LRdhCgPoqj5lQE44Zdv CMmNlI8h+1J4bNemQkmtN55CN23jdP9FLcKbLWWbd4Brw9Bd4MX9PBBJWv6dUz4chHf+ LFlf3KmT2sDaSJq333ZsxKHApKaXAHxf2HLDPm9Uc41qFa8ooeU1GXGxFMvwo7BdZ+jT 5ssZavAY347J8LZrCzoqfHRePBfuZrBBWdS/KTvEq2jOvZblOmH3mJ6yp9J1eP497tfA /g9tpvaukLGRd23EAdnJzZEMpp62aiEIFn3MXef9kbKKLgfw+1A/kNwqbtcMJd65gzgB 0Ccw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=bKJl9wGC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 61-v6si325003qtf.322.2018.07.02.23.06.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:06:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=bKJl9wGC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37974 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faESE-0000ZR-8M for patch@linaro.org; Tue, 03 Jul 2018 02:06:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKY-0002sV-2w for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKV-00071s-OZ for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:26 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:32831) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKU-0006xx-RN; Tue, 03 Jul 2018 01:58:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMB634yz9sBs; Tue, 3 Jul 2018 15:58:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597494; bh=kcbHI7VcKyE/gHvFWADW0Ha5EEQDj1GjzAloZ1A66+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bKJl9wGCrpK10Bu4U+74/gkjflrifElgT2bGO6L8OGX57rRfp3eT6uDZTSvcNP8pf gGs3zGsqO3pK1duLOr3aJRdxd/26xszLHluqby9JvWQGejcfk74xE+TgkXsz8nnuHM 6eHD35q/+ISLTmqXNt6zCFzfs1DFdH0GtOfeh84I= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:51 +1000 Message-Id: <20180703055804.13449-23-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 22/35] target/ppc: Implement the rest of gen_ld_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These cases were stubbed out. For now, implement them only within a serial context, forcing parallel execution to synchronize. It would be possible to implement these with cmpxchg loops, if we care. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 83 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 79 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 79285b6698..597a37d3ec 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3078,16 +3078,45 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) +static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, + TCGv EA, TCGCond cond, int addend) +{ + TCGv t = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGv u = tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); + tcg_gen_addi_tl(u, t, addend); + + /* E.g. for fetch and increment bounded... */ + /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ + tcg_gen_movcond_tl(cond, u, t, t2, u, t); + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); + + /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ + tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); + tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); + + tcg_temp_free(t); + tcg_temp_free(t2); + tcg_temp_free(u); +} + static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) { uint32_t gpr_FC = FC(ctx->opcode); TCGv EA = tcg_temp_new(); + int rt = rD(ctx->opcode); + bool need_serial; TCGv src, dst; gen_addr_register(ctx, EA); - dst = cpu_gpr[rD(ctx->opcode)]; - src = cpu_gpr[rD(ctx->opcode) + 1]; + dst = cpu_gpr[rt]; + src = cpu_gpr[(rt + 1) & 31]; + need_serial = false; memop |= MO_ALIGN; switch (gpr_FC) { case 0: /* Fetch and add */ @@ -3117,17 +3146,63 @@ static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) case 8: /* Swap */ tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); break; - case 16: /* compare and swap not equal */ + + case 16: /* Compare and swap not equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial = true; + } else { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); + if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { + tcg_gen_mov_tl(t1, src); + } else { + tcg_gen_ext32u_tl(t1, src); + } + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, + cpu_gpr[(rt + 2) & 31], t0); + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); + tcg_gen_mov_tl(dst, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case 24: /* Fetch and increment bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial = true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); + } + break; case 25: /* Fetch and increment equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial = true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); + } + break; case 28: /* Fetch and decrement bounded */ - gen_invalid(ctx); + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial = true; + } else { + gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); + } break; + default: /* invoke data storage error handler */ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); } tcg_temp_free(EA); + + if (need_serial) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; + } } static void gen_lwat(DisasContext *ctx) From patchwork Tue Jul 3 05:57:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 140901 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp771598ljj; Mon, 2 Jul 2018 23:11:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfzPiONm/clUKHtZAC5ZSASyunxUmL+Hv3Fn+mloyBWnZFb0ZhjrPky4fD/uPDe0yDerr8u X-Received: by 2002:a0c:aac7:: with SMTP id g7-v6mr2858361qvb.76.1530598277178; Mon, 02 Jul 2018 23:11:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530598277; cv=none; d=google.com; s=arc-20160816; b=i1PInXf47UqSCZyJixTRMNzjeeEtoZRmI9dovJajPNIyNz40KEm5qml7fTpC13IEIp 61of/kXiS58RKlxd0dhkK44LNZ90sg8bcA9x61U97T3RgnSplMu5F5aKPo9925PG2sXT pTX7/655Y1ktfLsRbqpOhb4SvaB8SnQZT0dHhbYCS+hPPMc+3aiZBeMRp/M1eCJVXxkT zW7OgBUJx1xqjNG/DHAcvILgy4nuTO4vRUab2jOJmeQHMIhdpkTlAfhDOiSNvxTx60Qg CJ6O6otRigSc0CV6LJI/9n/79Qq7IwR0xTI18jBcncAdLG3NKv0GpmHGGa8yk3wD576i cY6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=tN2eafpMQyW3569TOeRUi7AJHWiAeydG/drZH/F7xBg=; b=0osLGsO6klnQKqOoqD93w+5sOTCrSP00zG5c6LEeDPg+LC0dZkoIU6ZbUaOlMOPUZk q0ztdAuot9rlX9dl35PTreRRi8edrZfsnzzshvoRslNths9lcHAmxtgxinoMjmL5HEGs TpAVc5Qbdnx7pvNzEt2rcHDE/PzkH9YMMdgKLoS3Wq6i4v4UvCwqCjX1ZGVwfIQL3khu Vs7BnsBymbLaZMScK8Atb7+sZlRdL59fjRAYcDiQCx/qEv2n4l8mMM9KfpEaLSWVmWzc ws4H2KxuoKrgVmfv4Z8j93NYHjk4Y5LL8IOdf32wx/Z9zBs+C3UJ6kLJF2wvFVkjeYPs GYhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=D1BA6V6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c32-v6si362782qvc.108.2018.07.02.23.11.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 02 Jul 2018 23:11:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=D1BA6V6q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:38003 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEWy-0004aI-I2 for patch@linaro.org; Tue, 03 Jul 2018 02:11:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1faEKZ-0002u7-Eu for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1faEKU-000706-Ov for qemu-devel@nongnu.org; Tue, 03 Jul 2018 01:58:27 -0400 Received: from ozlabs.org ([203.11.71.1]:34269) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1faEKU-0006x0-84; Tue, 03 Jul 2018 01:58:22 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41KYMB31vvz9sBZ; Tue, 3 Jul 2018 15:58:13 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1530597494; bh=9JmbGYpkXqRuPWSZNnzwgmJeArXiZC0b10euIj5kODY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D1BA6V6qXHH6pVerB8bNyZqAdVVdyF6WtVLwQArnJXip77sf6GuN7PqXX0CnX1ZEm 4OY8+apjQzCkcawfcny1DvzpdU2gFdT0eaCOutIuzt9Ng8gMKSiFcpPDNlfEAWWSm6 uf8TuvfeFZ08beVITjsK0zW1JYsB+88aihC2evzo= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 3 Jul 2018 15:57:52 +1000 Message-Id: <20180703055804.13449-24-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703055804.13449-1-david@gibson.dropbear.id.au> References: <20180703055804.13449-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 23/35] target/ppc: Implement the rest of gen_st_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, Richard Henderson , mdroth@linux.vnet.ibm.com, agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The store twin case was stubbed out. For now, implement it only within a serial context, forcing parallel execution to synchronize. It would be possible to implement with a cmpxchg loop, if we care, but the loose alignment requirements (simply no crossing 32-byte boundary) might send us back to the serial context anyway. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 597a37d3ec..e120f2ed0b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3254,7 +3254,31 @@ static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); break; case 24: /* Store twin */ - gen_invalid(ctx); + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp = DISAS_NORETURN; + } else { + TCGv t = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGv s = tcg_temp_new(); + TCGv s2 = tcg_temp_new(); + TCGv ea_plus_s = tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); + + tcg_temp_free(ea_plus_s); + tcg_temp_free(s2); + tcg_temp_free(s); + tcg_temp_free(t2); + tcg_temp_free(t); + } break; default: /* invoke data storage error handler */