From patchwork Thu May 20 23:07:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E73CAC43611 for ; Thu, 20 May 2021 23:08:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7310613B6 for ; Thu, 20 May 2021 23:08:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233148AbhETXKE (ORCPT ); Thu, 20 May 2021 19:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233113AbhETXKD (ORCPT ); Thu, 20 May 2021 19:10:03 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8156EC061761; Thu, 20 May 2021 16:08:40 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id a2so26881190lfc.9; Thu, 20 May 2021 16:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4wjkerGjnODWZW9w3YSKmK8x5ot3hbK6hwMuTDmldcE=; b=eY+JcN50EErXfJJBHxuOt6AxKLX5cM00mV5NGLoPgAIKNZxqPRMaG0FnienMoaG5SV /+kB14sss/j2hn7khi3mnGNY+hu8x0EtJv3xy56MOyqGQBVl2tLnuGTrwjIAX/O01ecn q0ytzsaDaJ73gmOfBgsWjCdaF/jzKEioVYEpaYVDdNyorgAjLfGcBBC/nx+d6kD8FseV mmfdHzk2NwbKtQXNEzJ3kSg97304srhrirFdZyi23nkpgHPtfaL4xf/TdlIKx2hGM3SK jPjG8EwnRTuzzNMW0Tu6Rfk+XIku5nIqPNTUdVLlPHtJ8twLHFphwhR4AcZpQXbGWfYW PlFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4wjkerGjnODWZW9w3YSKmK8x5ot3hbK6hwMuTDmldcE=; b=D5W54YktIo5eeZ3J+PzEF3NZr9ynK52JxEUfNkJCnhfVw5flmhN8s0BoLsrIk5zEuF /utlOP97IoHFoF5JCOR33lC2VXU8hoZ54qR2Su22+8hBpB7cK465nSFFCvOjPQ7k7zzF LhAJa53V2o+JVGC+qJMC4rA6oz+Trf15Wes2cQKclfd+Bo+T5PqoKq9+f+FHQxEnhoRY YUff0LOqQxUGqbvUTxlw1bBzvX0Qra7SoFvaxtEzySVlinEQyDcCWs19F2gc5LK5Ur2J bbbma8MKEHj90WwnJvtgfvGEp7GWYCvGlnh6TiFVwyyINXm2wAwFwUhfTE1fH1B/ccyz 9dUw== X-Gm-Message-State: AOAM5304SDb4lXgblePiTc0M3BcyQx8P/3dLlnFz4Ga0gXfcL+0UAszL xvJthSrXaVzeoUcWPKnVyxk= X-Google-Smtp-Source: ABdhPJyIlz9t4Ds3YgggFlv9Ncz2YTCg7pWLILTlZ7oCF4wxyxUhe0yQiOCr2vbdtbuhCU1robe2hw== X-Received: by 2002:ac2:5289:: with SMTP id q9mr4613760lfm.141.1621552118935; Thu, 20 May 2021 16:08:38 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:38 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 01/13] regulator: core: Add regulator_sync_voltage_rdev() Date: Fri, 21 May 2021 02:07:39 +0300 Message-Id: <20210520230751.26848-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some NVIDIA Tegra devices use a CPU soft-reset method for the reboot and in this case we need to restore the coupled voltages to the state that is suitable for hardware during boot. Add new regulator_sync_voltage_rdev() helper which is needed by regulator drivers in order to sync voltage of a coupled regulators. Acked-by: Mark Brown Signed-off-by: Dmitry Osipenko --- drivers/regulator/core.c | 23 +++++++++++++++++++++++ include/linux/regulator/driver.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index f192bf19492e..ead0b6d2af45 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -4105,6 +4105,29 @@ int regulator_set_voltage_time_sel(struct regulator_dev *rdev, } EXPORT_SYMBOL_GPL(regulator_set_voltage_time_sel); +int regulator_sync_voltage_rdev(struct regulator_dev *rdev) +{ + int ret; + + regulator_lock(rdev); + + if (!rdev->desc->ops->set_voltage && + !rdev->desc->ops->set_voltage_sel) { + ret = -EINVAL; + goto out; + } + + /* balance only, if regulator is coupled */ + if (rdev->coupling_desc.n_coupled > 1) + ret = regulator_balance_voltage(rdev, PM_SUSPEND_ON); + else + ret = -EOPNOTSUPP; + +out: + regulator_unlock(rdev); + return ret; +} + /** * regulator_sync_voltage - re-apply last regulator output voltage * @regulator: regulator source diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index 4ea520c248e9..35e5a611db81 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -540,6 +540,7 @@ int regulator_set_current_limit_regmap(struct regulator_dev *rdev, int regulator_get_current_limit_regmap(struct regulator_dev *rdev); void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data); int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay); +int regulator_sync_voltage_rdev(struct regulator_dev *rdev); /* * Helper functions intended to be used by regulator drivers prior registering From patchwork Thu May 20 23:07:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B13C43462 for ; Thu, 20 May 2021 23:08:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53CD8613C4 for ; Thu, 20 May 2021 23:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233223AbhETXKH (ORCPT ); Thu, 20 May 2021 19:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233158AbhETXKF (ORCPT ); Thu, 20 May 2021 19:10:05 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9A5AC061574; Thu, 20 May 2021 16:08:41 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id i22so26749790lfl.10; Thu, 20 May 2021 16:08:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zLZwOwVhuIbHTTUdoWppFfwsPZfVF88GWvkyOwsujd4=; b=D9x5/bPIxbimpi1DB6Y6D/karAe1eJ4yvIUhWWoQK+s3SsjgKeu51JlyJecOaTpIkM wQcPM2ug3H2yTZlc90zeLCBdyD1/EHtoXk3lk/TLQXs8lBEFEkvOc+7XtvcqWcqa9Q30 lLzT57bfkYTToPDq9xwOVoMzBYO29Sq67L4kTxcYRxmphS+mhy0PEiFXMksd9bEK/nH5 6XZhM7VQXdS5P5LIsllGp5SuRN8Nm8EUXRy+Zjknk6DgFXS7vNC7DTlgKoj5qngoUddf WtUMdz8u8GarGcJimow1fDaJcuB5SvtxswRj5r66cRuPfSkAZ7YrYSsAbTMzvCrZGEI7 /nEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zLZwOwVhuIbHTTUdoWppFfwsPZfVF88GWvkyOwsujd4=; b=L7QCSgRe9xXbj/I/smBeBYJCIONKpbiWhNqOpEwkrZ3hY2qnYgdjC47gMKIeO0a3Q+ GkG4mgmvgvjSve2bkgVoCb+utY5FIXr/7z6ICCbt95Tju0+RqFAjPYf1a+NHAnjW8IB6 CKN43TqT9+2YDoPoESusXb+hpDgAbDoxMjKgookB8ydLpWU/+wXHZdlUWQCwbdGtc6ci meBpWJaHJR9bMHeL05gXdgZPkhx8eCJz/W5tfJgB5rVX72G5EwI4qfGZFMCOqgXh1BiW tUl2Uj0Pxajq78W97L7fBIIybP0ENnBT3SajOnAlJ6wFgQuMs2xDVj8aG4F8NMEsBSsZ +PXQ== X-Gm-Message-State: AOAM533sAqXy4Hln3xQezc98A8c8UN31yrtchCBziaJFFtehKiH96qL5 AvM6ttJ0w51AhCROfq9JDrE= X-Google-Smtp-Source: ABdhPJzxNlf6eWuMOIYag1iH++U9JnyryFe1oHI2uBYCvsQEtLf8yFBfjj95PYHEgxv2WbSEJ6HQyw== X-Received: by 2002:a05:6512:3f93:: with SMTP id x19mr4745893lfa.182.1621552120151; Thu, 20 May 2021 16:08:40 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:39 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 02/13] soc/tegra: regulators: Bump voltages on system reboot Date: Fri, 21 May 2021 02:07:40 +0300 Message-Id: <20210520230751.26848-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Ensure that SoC voltages are at a level suitable for a system reboot. This is important for some devices that use CPU reset method for the rebooting. SoC CPU and core voltages now are be restored to a level that is suitable for rebooting. This patch fixes hang on reboot on Asus Transformer TF101, it was also reported as fixing some of reboot issues on Toshiba AC100. Reported-by: Nikola Milosavljević Tested-by: Nikola Milosavljević # TF101 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra20.c | 75 ++++++++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 78 +++++++++++++++++++++++++- 2 files changed, 151 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 367a71a3cd10..3479be5ee494 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -21,7 +22,10 @@ struct tegra_regulator_coupler { struct regulator_dev *core_rdev; struct regulator_dev *cpu_rdev; struct regulator_dev *rtc_rdev; - int core_min_uV; + struct notifier_block reboot_notifier; + int core_min_uV, cpu_min_uV; + bool sys_reboot_mode_req; + bool sys_reboot_mode; }; static inline struct tegra_regulator_coupler * @@ -242,6 +246,10 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, if (cpu_uV < 0) return cpu_uV; + /* store boot voltage level */ + if (!tegra->cpu_min_uV) + tegra->cpu_min_uV = cpu_uV; + /* * CPU's regulator may not have any consumers, hence the voltage * must not be changed in that case because CPU simply won't @@ -250,6 +258,10 @@ static int tegra20_cpu_voltage_update(struct tegra_regulator_coupler *tegra, if (!cpu_min_uV_consumers) cpu_min_uV = cpu_uV; + /* restore boot voltage level */ + if (tegra->sys_reboot_mode) + cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + if (cpu_min_uV > cpu_uV) { err = tegra20_core_rtc_update(tegra, core_rdev, rtc_rdev, cpu_uV, cpu_min_uV); @@ -290,6 +302,8 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, return -EINVAL; } + tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + if (rdev == cpu_rdev) return tegra20_cpu_voltage_update(tegra, cpu_rdev, core_rdev, rtc_rdev); @@ -303,6 +317,51 @@ static int tegra20_regulator_balance_voltage(struct regulator_coupler *coupler, return -EPERM; } +static int tegra20_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, + bool sys_reboot_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->rtc_rdev || !tegra->cpu_rdev) + return 0; + + WRITE_ONCE(tegra->sys_reboot_mode_req, true); + + /* + * Some devices use CPU soft-reboot method and in this case we + * should ensure that voltages are sane for the reboot by restoring + * the minimum boot levels. + */ + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode); + + return 0; +} + +static int tegra20_regulator_reboot(struct notifier_block *notifier, + unsigned long event, void *cmd) +{ + struct tegra_regulator_coupler *tegra; + int ret; + + if (event != SYS_RESTART) + return NOTIFY_DONE; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + reboot_notifier); + + ret = tegra20_regulator_prepare_reboot(tegra, true); + + return notifier_from_errno(ret); +} + static int tegra20_regulator_attach(struct regulator_coupler *coupler, struct regulator_dev *rdev) { @@ -335,6 +394,14 @@ static int tegra20_regulator_detach(struct regulator_coupler *coupler, { struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler); + /* + * We don't expect regulators to be decoupled during reboot, + * this may race with the reboot handler and shouldn't ever + * happen in practice. + */ + if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING)) + return -EPERM; + if (tegra->core_rdev == rdev) { tegra->core_rdev = NULL; return 0; @@ -359,13 +426,19 @@ static struct tegra_regulator_coupler tegra20_coupler = { .detach_regulator = tegra20_regulator_detach, .balance_voltage = tegra20_regulator_balance_voltage, }, + .reboot_notifier.notifier_call = tegra20_regulator_reboot, }; static int __init tegra_regulator_coupler_init(void) { + int err; + if (!of_machine_is_compatible("nvidia,tegra20")) return 0; + err = register_reboot_notifier(&tegra20_coupler.reboot_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra20_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 0e776b20f625..6e4f3d9e7be1 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,7 +23,10 @@ struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; struct regulator_dev *cpu_rdev; - int core_min_uV; + struct notifier_block reboot_notifier; + int core_min_uV, cpu_min_uV; + bool sys_reboot_mode_req; + bool sys_reboot_mode; }; static inline struct tegra_regulator_coupler * @@ -172,6 +176,10 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (cpu_uV < 0) return cpu_uV; + /* store boot voltage level */ + if (!tegra->cpu_min_uV) + tegra->cpu_min_uV = cpu_uV; + /* * CPU's regulator may not have any consumers, hence the voltage * must not be changed in that case because CPU simply won't @@ -195,6 +203,10 @@ static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, if (err) return err; + /* restore boot voltage level */ + if (tegra->sys_reboot_mode) + cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV); + if (core_min_limited_uV > core_uV) { pr_err("core voltage constraint violated: %d %d %d\n", core_uV, core_min_limited_uV, cpu_uV); @@ -263,9 +275,56 @@ static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler, return -EINVAL; } + tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req); + return tegra30_voltage_update(tegra, cpu_rdev, core_rdev); } +static int tegra30_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra, + bool sys_reboot_mode) +{ + int err; + + if (!tegra->core_rdev || !tegra->cpu_rdev) + return 0; + + WRITE_ONCE(tegra->sys_reboot_mode_req, true); + + /* + * Some devices use CPU soft-reboot method and in this case we + * should ensure that voltages are sane for the reboot by restoring + * the minimum boot levels. + */ + err = regulator_sync_voltage_rdev(tegra->cpu_rdev); + if (err) + return err; + + err = regulator_sync_voltage_rdev(tegra->core_rdev); + if (err) + return err; + + WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode); + + return 0; +} + +static int tegra30_regulator_reboot(struct notifier_block *notifier, + unsigned long event, void *cmd) +{ + struct tegra_regulator_coupler *tegra; + int ret; + + if (event != SYS_RESTART) + return NOTIFY_DONE; + + tegra = container_of(notifier, struct tegra_regulator_coupler, + reboot_notifier); + + ret = tegra30_regulator_prepare_reboot(tegra, true); + + return notifier_from_errno(ret); +} + static int tegra30_regulator_attach(struct regulator_coupler *coupler, struct regulator_dev *rdev) { @@ -292,6 +351,17 @@ static int tegra30_regulator_detach(struct regulator_coupler *coupler, { struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler); + /* + * We don't expect regulators to be decoupled during reboot, + * this may race with the reboot handler and shouldn't ever + * happen in practice. + */ + if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING)) + return -EPERM; + + /* bring regulators to the state that is safe for reboot */ + tegra30_regulator_prepare_reboot(tegra, false); + if (tegra->core_rdev == rdev) { tegra->core_rdev = NULL; return 0; @@ -311,13 +381,19 @@ static struct tegra_regulator_coupler tegra30_coupler = { .detach_regulator = tegra30_regulator_detach, .balance_voltage = tegra30_regulator_balance_voltage, }, + .reboot_notifier.notifier_call = tegra30_regulator_reboot, }; static int __init tegra_regulator_coupler_init(void) { + int err; + if (!of_machine_is_compatible("nvidia,tegra30")) return 0; + err = register_reboot_notifier(&tegra30_coupler.reboot_notifier); + WARN_ON(err); + return regulator_coupler_register(&tegra30_coupler.coupler); } arch_initcall(tegra_regulator_coupler_init); From patchwork Thu May 20 23:07:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00EEAC43461 for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:40 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 03/13] soc/tegra: Add stub for soc_is_tegra() Date: Fri, 21 May 2021 02:07:41 +0300 Message-Id: <20210520230751.26848-4-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add stub required for compile-testing of drivers. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/common.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 98027a76ce3d..744280ecab5f 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,6 +6,15 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include + +#ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +#else +static inline bool soc_is_tegra(void) +{ + return false; +} +#endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu May 20 23:07:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42873C4360C for ; Thu, 20 May 2021 23:08:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27A10611AE for ; Thu, 20 May 2021 23:08:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233384AbhETXKM (ORCPT ); Thu, 20 May 2021 19:10:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233232AbhETXKH (ORCPT ); Thu, 20 May 2021 19:10:07 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA09C061761; Thu, 20 May 2021 16:08:44 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id w15so21770435ljo.10; Thu, 20 May 2021 16:08:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+ru1Y5AhCOlhA7q2BKIbg+3l43tX1d5MlWRnc4jqFnM=; b=t4DPbheCJLYB6Y2YvuMw8oTIGEInCL4pXOndvs24PIpcVEDFDWYQsS782+HuvSZBot FiqPAPURVwCbVbIV1QAcMvf/q9gHOglllhrj6EzPjOSdJImXSrOuCC16Qo/tjJUsK4Yt 4hXAf7LApyp6ilHDhM4u0dYt4iaElkjpxnwvuv1p7HVvNf5Faz1GR0HTaK1WSKoDBuo7 JO6UDJZhVnE8+k7TnHw2wiuwlaWg3oNbe0U0vinIC5A0K+X4IQwDl9wVPY5HFnmIRv7n 4Om3sHsdVfMy+nsM9l48a/oK1ghM3GFkF3xaB6VtwNuAh9NmDOna+ubS4ZHN9nTHTlti 4KuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+ru1Y5AhCOlhA7q2BKIbg+3l43tX1d5MlWRnc4jqFnM=; b=NNabUAHUbyf9nW4oNr3HsfIgjyVBWmpQC+bPU1ZINIjsua0KgA9EJFfJsFEIqJ5pmU bLzbKO0vigOWDMPhen6v8BXwIw/+xcla+kIsDaR/db2eZRFO2bOE2p2FvmZQi2ycZvFc vS/huZHAXrHB+WMUW1elRmWPP+HF/jgZzXKl12Enog+5IhQOmkU377brzKhR0PCPOA1y 3wIc47g5DDERUMFr657qRce22fHe49BsSuNF80g5rgukl1y6Oxww1shZZr7e1X/nSoin r8k6SnpjZs3shInKVrdOkkvtD9+cSL821CWYWbKOWIg50ppuKf8Zlj9JFRZaAk0Y4JML TKzg== X-Gm-Message-State: AOAM533x0cClX/6Ar9hAS4Q24TEV6vkp77x5PahetznueIrit7XCAaK5 x4vUqnNiz5FeGLV1TGOvEeU= X-Google-Smtp-Source: ABdhPJw/ysGQ7427eYQET0NAy6+evYOUqKtx2xtDlmMkJLzkbdWOfRMxbxW9hh0/e2L5YHJAOiwryA== X-Received: by 2002:a2e:a0cb:: with SMTP id f11mr4675154ljm.72.1621552122338; Thu, 20 May 2021 16:08:42 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:42 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 04/13] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Date: Fri, 21 May 2021 02:07:42 +0300 Message-Id: <20210520230751.26848-5-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add common helper which initializes OPP table for Tegra SoC core devices. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/common.c | 97 ++++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 22 +++++++++ 2 files changed, 119 insertions(+) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 3dc54f59cafe..cd33e99249c3 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -3,9 +3,16 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ +#define dev_fmt(fmt) "tegra-soc: " fmt + +#include +#include +#include #include +#include #include +#include static const struct of_device_id tegra_machine_match[] = { { .compatible = "nvidia,tegra20", }, @@ -31,3 +38,93 @@ bool soc_is_tegra(void) return match != NULL; } + +static int tegra_core_dev_init_opp_state(struct device *dev) +{ + unsigned long rate; + struct clk *clk; + int err; + + clk = devm_clk_get(dev, NULL); + if (IS_ERR(clk)) { + dev_err(dev, "failed to get clk: %pe\n", clk); + return PTR_ERR(clk); + } + + rate = clk_get_rate(clk); + if (!rate) { + dev_err(dev, "failed to get clk rate\n"); + return -EINVAL; + } + + /* first dummy rate-setting initializes voltage vote */ + err = dev_pm_opp_set_rate(dev, rate); + if (err) { + dev_err(dev, "failed to initialize OPP clock: %d\n", err); + return err; + } + + return 0; +} + +/** + * devm_tegra_core_dev_init_opp_table() - initialize OPP table + * @dev: device for which OPP table is initialized + * @params: pointer to the OPP table configuration + * + * This function will initialize OPP table and sync OPP state of a Tegra SoC + * core device. + * + * Return: 0 on success or errorno. + */ +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + u32 hw_version; + int err; + + err = devm_pm_opp_set_clkname(dev, NULL); + if (err) { + dev_err(dev, "failed to set OPP clk: %d\n", err); + return err; + } + + /* Tegra114+ doesn't support OPP yet */ + if (!of_machine_is_compatible("nvidia,tegra20") && + !of_machine_is_compatible("nvidia,tegra30")) + return -ENODEV; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + err = devm_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (err) { + dev_err(dev, "failed to set OPP supported HW: %d\n", err); + return err; + } + + /* + * Older device-trees have an empty OPP table, we will get + * -ENODEV from devm_pm_opp_of_add_table() in this case. + */ + err = devm_pm_opp_of_add_table(dev); + if (err) { + if (err == -ENODEV) + dev_err_once(dev, "OPP table not found, please update device-tree\n"); + else + dev_err(dev, "failed to add OPP table: %d\n", err); + + return err; + } + + if (params->init_state) { + err = tegra_core_dev_init_opp_state(dev); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table); diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index 744280ecab5f..af41ad80ec21 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -6,15 +6,37 @@ #ifndef __SOC_TEGRA_COMMON_H__ #define __SOC_TEGRA_COMMON_H__ +#include #include +struct device; + +/** + * Tegra SoC core device OPP table configuration + * + * @init_state: pre-initialize OPP state of a device + */ +struct tegra_core_opp_params { + bool init_state; +}; + #ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); + +int devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params); #else static inline bool soc_is_tegra(void) { return false; } + +static inline int +devm_tegra_core_dev_init_opp_table(struct device *dev, + struct tegra_core_opp_params *params) +{ + return -ENODEV; +} #endif #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Thu May 20 23:07:43 2021 Content-Type: text/plain; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:43 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 05/13] soc/tegra: fuse: Add stubs needed for compile-testing Date: Fri, 21 May 2021 02:07:43 +0300 Message-Id: <20210520230751.26848-6-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add missing stubs that will allow Tegra memory driver to be compile-tested by kernel build bots. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/fuse.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 78cbc787a4dc..990701f788bc 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -52,14 +52,28 @@ struct tegra_sku_info { enum tegra_revision revision; }; +#ifdef CONFIG_ARCH_TEGRA +extern struct tegra_sku_info tegra_sku_info; u32 tegra_read_straps(void); u32 tegra_read_ram_code(void); int tegra_fuse_readl(unsigned long offset, u32 *value); - -#ifdef CONFIG_ARCH_TEGRA -extern struct tegra_sku_info tegra_sku_info; #else static struct tegra_sku_info tegra_sku_info __maybe_unused; + +static inline u32 tegra_read_straps(void) +{ + return 0; +} + +static inline u32 tegra_read_ram_code(void) +{ + return 0; +} + +static inline int tegra_fuse_readl(unsigned long offset, u32 *value) +{ + return -ENODEV; +} #endif struct device *tegra_soc_device_register(void); From patchwork Thu May 20 23:07:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A1A2C43600 for ; Thu, 20 May 2021 23:08:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA8D3613C5 for ; Thu, 20 May 2021 23:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233477AbhETXKQ (ORCPT ); Thu, 20 May 2021 19:10:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233310AbhETXKK (ORCPT ); Thu, 20 May 2021 19:10:10 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EFAEC06138A; Thu, 20 May 2021 16:08:46 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id z13so26915272lft.1; Thu, 20 May 2021 16:08:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GyIAF+FPDoF3L0c8SxBikD76UBKYvvu1WBUmyZdYlws=; b=dT782xigAvMZGuiMZUJtdzP8P1Ndn8d18C4nErOh7hlRxvjaJf68jCerk2cwRY2KNm BJuWyxoBHfEPECmT1fp90ZoPlyBpdihDwYGV1b7vUKiVFIK+clvD4thmaxLJaefzHsNi /ZgAJbhmRndPpbwUj9DDBaTLWdwdMCq0er8pw/pi7oMUQlm22ss/NG4PS2ZOCr2hfkTI VVAu1f267teP2Zr7GpmwEFEOmvBg3rQFhoeF9EMth0SppVP0BEinuXi240lJUVeo78GR seOSzsW9gC5YfcOFKaFLRC6oeTXTU1AkUwhWUBRM8BE1R2T4Sq+mpc9p9Zb+bNP4hdG0 aBYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GyIAF+FPDoF3L0c8SxBikD76UBKYvvu1WBUmyZdYlws=; b=REFb5PuB9sJJgSNopNYXE9BgBKabUbsg9x1/E74H0e8XaSVBrVAYCnDwr0Ifh0/m3z ewurCA+hO8MbUdUsvpSAS+abdhvFAXxh902hqcwjPU6OwUIa03CGRRubt9LscNS4FIAP CYXuasJJ33tDTXcbgSsnBHYVwNmJuZ0xYZRvyWGwzjfp4VkHmz1Ko8pyGb2FR/eMCcfE FSTy/ZoRMEX7Wkh2lAVGpRe0Imcuz1awazHfeQrpzIuVFPRlyU3sEJ/6B4CPWc6UpPU3 4kK6jL6F897fydSGTn89L72UhGqWwhdGQpJPGHvWTHRC89GXrJ5yjNsHYpB5B9k7uvsJ KP/A== X-Gm-Message-State: AOAM53185EQliGKtpLUoVhksx/OeDZVpzqsw0vLMctGGiVVZ4kB7Y04R pQ1cV4BSMqLfY4GiJM6Ag2k= X-Google-Smtp-Source: ABdhPJy6gBEFQ+VAaEcZ0Wm4eVWqnt5KdO8Hlz/U9iAczXGHQicCANZaveV3uNCn8FnHiIvcLcfP0g== X-Received: by 2002:a05:6512:40a:: with SMTP id u10mr4623215lfk.341.1621552124459; Thu, 20 May 2021 16:08:44 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:44 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 06/13] clk: tegra: Add stubs needed for compile-testing Date: Fri, 21 May 2021 02:07:44 +0300 Message-Id: <20210520230751.26848-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add stubs needed for compile-testing of Tegra memory drivers. Signed-off-by: Dmitry Osipenko --- include/linux/clk/tegra.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index f7ff722a03dd..d540b2879c26 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -144,17 +144,37 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, unsigned long min_rate, unsigned long max_rate, void *arg); +typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, + unsigned long rate); +#ifdef CONFIG_ARCH_TEGRA void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, void *cb_arg); int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); -typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, - unsigned long rate); -typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, - unsigned long rate); void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, tegra124_emc_complete_timing_change_cb *complete_cb); +#else +static inline void +tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, + void *cb_arg) +{ +} + +static inline int +tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) +{ + return 0; +} + +static inline void +tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, + tegra124_emc_complete_timing_change_cb *complete_cb) +{ +} +#endif struct tegra210_clk_emc_config { unsigned long rate; From patchwork Thu May 20 23:07:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F333C43619 for ; Thu, 20 May 2021 23:08:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A5E1611AE for ; Thu, 20 May 2021 23:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233521AbhETXKR (ORCPT ); Thu, 20 May 2021 19:10:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233304AbhETXKJ (ORCPT ); Thu, 20 May 2021 19:10:09 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C21EC06138B; Thu, 20 May 2021 16:08:47 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 131so21797567ljj.3; Thu, 20 May 2021 16:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vyfuUJygPypv3PLq8+UwCGzuqV5dXIOCDthlvjoInWA=; b=lrCzowrEA2YL5iBi5edNzQ+WSfZSB+9c0qNQDEe3fkMhAStJG0QnIVnJe4Q/aV6RcG 55LDUra4Qrct/27K3vrAmF7egfwsr3FmU6PDzPDkgZh/4dRBjI0gWvkBJ4llg+PF/9zi mmyr1WgOlnpTLWApwP4H2XzUONL5NFszPF9ZwgBVt+f2lAVMOw+E5utIa7vTDBH5lVSH uBzzSlXy48vpO/TKgXQ+V2uYkzIbahqKnWyIyMGHUnPY1jsaLhNoQSiBMD6eeUrC2cIt rOmW5YYH8tEHJry44EMhZ44jOxVKKpUkpsqByx1397N1NQAxFq8obRqpsrc/CqtMNyag 9rZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vyfuUJygPypv3PLq8+UwCGzuqV5dXIOCDthlvjoInWA=; b=nmCDJUy/R1tK/9RokBncUZSOSmrEpWctmb2RQdYxIDKbgsA0a2+Z24WNqsNFcBVjMw jYy66LFSxj5VR8gyXlT9+MIHU2PjLvu/lAMBIDQqt4t16Ci8CWpz7gAFVeRoRkj3LzXp 6KUd6ZkiZtNHH/mj4Uyj8zRKcVWFIHFZTuSayShrqjHj4HLXyOIN3908gnxYYx7Pppz7 V4L7d+MT1iLsdvZWs1V/P3l/c5Amd6DjFW3TPRbPhKTgAr/xla3ZnyH7XpzSC82BwEJh U1UcIH8YasvR8zL0wY+5y2RH3N39TzOEqVX/KKy3DA8WmNFOmeqIPk2Yw0DGewWGPgHG Qw+Q== X-Gm-Message-State: AOAM533fng/RE8tAd/Fb32XUuFW9voRmGU6ZkjhcFHxkUX8gEPxVGO1U Lu9rJf35xTCjCvJ+jIRK+RA= X-Google-Smtp-Source: ABdhPJy4cHP6cqgA7BLVTv7uNonvfnAu9aOfdSUF9/JoTjuLftMsSikVyUxDnan3jb7UqTzaDAWQ0w== X-Received: by 2002:a05:651c:1404:: with SMTP id u4mr4456555lje.451.1621552125727; Thu, 20 May 2021 16:08:45 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 07/13] memory: tegra: Fix compilation warnings on 64bit platforms Date: Fri, 21 May 2021 02:07:45 +0300 Message-Id: <20210520230751.26848-8-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix compilation warning on 64bit platforms caused by implicit promotion of 32bit signed integer to a 64bit unsigned value which happens after enabling compile-testing of the EMC drivers. Reported-by: kernel test robot Reviewed-by: Nathan Chancellor Signed-off-by: Dmitry Osipenko Reviewed-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra124-emc.c | 4 ++-- drivers/memory/tegra/tegra30-emc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 5699d909abc2..a21ca8e0841a 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -272,8 +272,8 @@ #define EMC_PUTERM_ADJ 0x574 #define DRAM_DEV_SEL_ALL 0 -#define DRAM_DEV_SEL_0 (2 << 30) -#define DRAM_DEV_SEL_1 (1 << 30) +#define DRAM_DEV_SEL_0 BIT(31) +#define DRAM_DEV_SEL_1 BIT(30) #define EMC_CFG_POWER_FEATURES_MASK \ (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 829f6d673c96..a2f2738ccb94 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -150,8 +150,8 @@ #define EMC_SELF_REF_CMD_ENABLED BIT(0) #define DRAM_DEV_SEL_ALL (0 << 30) -#define DRAM_DEV_SEL_0 (2 << 30) -#define DRAM_DEV_SEL_1 (1 << 30) +#define DRAM_DEV_SEL_0 BIT(31) +#define DRAM_DEV_SEL_1 BIT(30) #define DRAM_BROADCAST(num) \ ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) From patchwork Thu May 20 23:07:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E753BC43611 for ; Thu, 20 May 2021 23:08:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8F73613B6 for ; Thu, 20 May 2021 23:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233544AbhETXKS (ORCPT ); Thu, 20 May 2021 19:10:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233197AbhETXKK (ORCPT ); Thu, 20 May 2021 19:10:10 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A25CC061763; Thu, 20 May 2021 16:08:48 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id q7so25562068lfr.6; Thu, 20 May 2021 16:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CLef4wehN1atwulqXH4JMD3Wb9mRwmm7RCBYkfihR6M=; b=XuxxZV+UsNtRpkov9Sh86zbp1PDi+43UKiTfPCa8AAo9V/O2rI0vopCFIxNhG27v8R G7J/7I20w7avnQ50Hd7bproQUrwCf3fOA7Cm7RyjV4z+GkcjaO33TAJbu08MLDtxlqI5 XTO97Mg7X2xu5uzNyZU6Jj8FT7EVJGXr/kDLK2A3DZRAcV+ROTTFdN/xqplrITPhpTmH rdZRXuptqNgjWYRODDEm1fJpI6GLvErzBLcY0H6UHjqJMMISDAvYTvFeRrMUprPcTCtk JaF9YwfFPT+rubfhOW4NyufAwl1agaTRRYH6Jc4QiOqHF4ke/E7FH8FJHf0N3Jf8mc1Q DV+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CLef4wehN1atwulqXH4JMD3Wb9mRwmm7RCBYkfihR6M=; b=ZbvnxKi4PEDPJgve/W1PqE0zOqHX4XFNOjdQ16pr18LznWTAhTyE3gkpc5lgHmWbCa xOfpowRncL/Cjyo3sYj7C6A7opFcZBoTUIH3hX5ztTC2Z8m+LJOY0wEdKByXdj/TGOlI pD5UX6EkY26qyU3tKzo61em9WbQW1rhHplPf4ckFOmtQagmmoPiCnMPgPbeXwerPadyo wp6HjP3pZk095Fl+Eq0X/0WmQhLlaNmUHjayje5dAMrAj5IToF3ZwS1SYgV6GZl3G8EV BoGUuzJdmFtu0tTBtnW7ZkDzsB661OzLY33YeI2q3YBP7ptYo5PH1D60Tv40HryUpvC4 RpXw== X-Gm-Message-State: AOAM532C00SulXDxbEcGiTFgSungLRf6uowF+PTInHIPFDZHepODVCtM knDGi9FNLDXT5NPo3HTjm6g= X-Google-Smtp-Source: ABdhPJw6yrdHBR/OfktJ4jUtzPkIGTTiGC1DIM0+sGbXA5lnzbIBHKd9s4LrtFgo6JvJ4rP/jxovtg== X-Received: by 2002:a19:c3d1:: with SMTP id t200mr4483967lff.421.1621552126852; Thu, 20 May 2021 16:08:46 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 08/13] memory: tegra: Enable compile testing for all drivers Date: Fri, 21 May 2021 02:07:46 +0300 Message-Id: <20210520230751.26848-9-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable compile testing for all Tegra memory drivers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index a70967a56e52..c63ffa74ab94 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -2,16 +2,18 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y - depends on ARCH_TEGRA + depends on ARCH_TEGRA || COMPILE_TEST select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. +if TEGRA_MC + config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST select DEVFREQ_GOV_SIMPLE_ONDEMAND select PM_DEVFREQ help @@ -23,7 +25,7 @@ config TEGRA20_EMC config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -34,8 +36,8 @@ config TEGRA30_EMC config TEGRA124_EMC tristate "NVIDIA Tegra124 External Memory Controller driver" default y - depends on TEGRA_MC && ARCH_TEGRA_124_SOC - select TEGRA124_CLK_EMC + depends on ARCH_TEGRA_124_SOC || COMPILE_TEST + select TEGRA124_CLK_EMC if ARCH_TEGRA select PM_OPP help This driver is for the External Memory Controller (EMC) found on @@ -49,10 +51,12 @@ config TEGRA210_EMC_TABLE config TEGRA210_EMC tristate "NVIDIA Tegra210 External Memory Controller driver" - depends on TEGRA_MC && ARCH_TEGRA_210_SOC + depends on ARCH_TEGRA_210_SOC || COMPILE_TEST select TEGRA210_EMC_TABLE help This driver is for the External Memory Controller (EMC) found on Tegra210 chips. The EMC controls the external DRAM on the board. This driver is required to change memory timings / clock rate for external memory. + +endif From patchwork Thu May 20 23:07:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5976C43140 for ; Thu, 20 May 2021 23:09:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C0358613C4 for ; Thu, 20 May 2021 23:09:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233612AbhETXKT (ORCPT ); Thu, 20 May 2021 19:10:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233113AbhETXKM (ORCPT ); Thu, 20 May 2021 19:10:12 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85433C061761; Thu, 20 May 2021 16:08:49 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id w7so8410033lji.6; Thu, 20 May 2021 16:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ueM1JtdL2WEXVwCBbL9rRWyabHSIsAzV58fGIccOqXs=; b=ScRQ6CA087L27fm3HJWgN4uDimqch4eVaPGIfcXsl0wqhX9m6Suje7Hhzhvu+YEXat lFsr6sqxZ5flPlmywvWEaMAHhBofQj1VwM0TxP7wfoJyew80ewG/5kNu9wxXvH4go8AI Bcf2qdUAiPl8e4/nrRIrH80gsxTvpYe1/29jlMLg18+UZfdS7kfjIhZxAjMLmEgqvmgI yICCE8aFjTqkLjrDZ8bFUaJveh1HEpDuLr4NoUh3vy1J09xomamzQHxLP7mpScDlp8+O DRXhj5VnaRzJTLuHZBG+ume8Hfx6VLYqy6CD0K41Og1QyKVRKpSk5lF1wRONiHcj/Vzq h28g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ueM1JtdL2WEXVwCBbL9rRWyabHSIsAzV58fGIccOqXs=; b=ejaT54Klv7TmO2CEKfWPYvac9MFANTHZKGmnMZ7NOnWnYBUOM55hd9xcbfdHdcRHtq bhHPr2JEGvylEoVjfi1KLmluHI+f6vtZIIFSZHm1f5jspLeTDnc+XsduySE1HmQgvQH8 JHK2cXrRQfm5G5MHaLfsJVuwB+UW3BbDlBY63mBs3knsT4TP4QJAfLBR2Rx0d4ObJO6/ gIbKOMLhBcwgegwB9p4FjabZd0k7QcCjxZyzWkjFQEAPkuEbDn5vKDbIFZg1a9sExrRZ AOReVeg5jVJvWPBI6hWZY8QSOkJ9TLAGADi2hcmiN5HcYIcIsd2xC5Rmght/fYvRbLuF I08w== X-Gm-Message-State: AOAM5338shWrmBY8QA/nhg3K4J4HNzsKTCBGHne19wqYCWBIyYJ7g8vt 3pamSV9mZYvW+YMUBb+jYDU= X-Google-Smtp-Source: ABdhPJxtYewR6f5gVCXQzz+EP35CO4z7YrCr0YJ+FuWki0bPT+0Cvvgcszs2YMxR3hhTUAopfCyE+w== X-Received: by 2002:a2e:9d59:: with SMTP id y25mr4461068ljj.399.1621552127936; Thu, 20 May 2021 16:08:47 -0700 (PDT) Received: from localhost.localdomain (109-252-193-76.dynamic.spd-mgts.ru. [109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:47 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 09/13] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() Date: Fri, 21 May 2021 02:07:47 +0300 Message-Id: <20210520230751.26848-10-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization. Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20-emc.c | 48 +++--------------------------- 1 file changed, 4 insertions(+), 44 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index da8a0da8da79..a534197a5fb2 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -908,49 +908,6 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc) return err; } -static int tegra_emc_opp_table_init(struct tegra_emc *emc) -{ - u32 hw_version = BIT(tegra_sku_info.soc_process_id); - struct opp_table *hw_opp_table; - int err; - - hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); - err = PTR_ERR_OR_ZERO(hw_opp_table); - if (err) { - dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); - return err; - } - - err = dev_pm_opp_of_add_table(emc->dev); - if (err) { - if (err == -ENODEV) - dev_err(emc->dev, "OPP table not found, please update your device tree\n"); - else - dev_err(emc->dev, "failed to add OPP table: %d\n", err); - - goto put_hw_table; - } - - dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); - - /* first dummy rate-set initializes voltage state */ - err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); - if (err) { - dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); - goto remove_table; - } - - return 0; - -remove_table: - dev_pm_opp_of_remove_table(emc->dev); -put_hw_table: - dev_pm_opp_put_supported_hw(hw_opp_table); - - return err; -} - static void devm_tegra_emc_unset_callback(void *data) { tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1077,6 +1034,7 @@ static int tegra_emc_devfreq_init(struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { + struct tegra_core_opp_params opp_params = {}; struct device_node *np; struct tegra_emc *emc; int irq, err; @@ -1122,7 +1080,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - err = tegra_emc_opp_table_init(emc); + opp_params.init_state = true; + + err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); if (err) return err; From patchwork Thu May 20 23:07:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ADF2C43460 for ; Thu, 20 May 2021 23:09:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 46082613C4 for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:48 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 10/13] memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() Date: Fri, 21 May 2021 02:07:48 +0300 Message-Id: <20210520230751.26848-11-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table initialization. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Reviewed-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30-emc.c | 48 +++--------------------------- 1 file changed, 4 insertions(+), 44 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index a2f2738ccb94..63e1983f8a0d 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1480,49 +1480,6 @@ static int tegra_emc_interconnect_init(struct tegra_emc *emc) return err; } -static int tegra_emc_opp_table_init(struct tegra_emc *emc) -{ - u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); - struct opp_table *hw_opp_table; - int err; - - hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); - err = PTR_ERR_OR_ZERO(hw_opp_table); - if (err) { - dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); - return err; - } - - err = dev_pm_opp_of_add_table(emc->dev); - if (err) { - if (err == -ENODEV) - dev_err(emc->dev, "OPP table not found, please update your device tree\n"); - else - dev_err(emc->dev, "failed to add OPP table: %d\n", err); - - goto put_hw_table; - } - - dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", - hw_version, clk_get_rate(emc->clk) / 1000000); - - /* first dummy rate-set initializes voltage state */ - err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); - if (err) { - dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); - goto remove_table; - } - - return 0; - -remove_table: - dev_pm_opp_of_remove_table(emc->dev); -put_hw_table: - dev_pm_opp_put_supported_hw(hw_opp_table); - - return err; -} - static void devm_tegra_emc_unset_callback(void *data) { tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1568,6 +1525,7 @@ static int tegra_emc_init_clk(struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { + struct tegra_core_opp_params opp_params = {}; struct device_node *np; struct tegra_emc *emc; int err; @@ -1617,7 +1575,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - err = tegra_emc_opp_table_init(emc); + opp_params.init_state = true; + + err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); if (err) return err; From patchwork Thu May 20 23:07:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7177BC43461 for ; Thu, 20 May 2021 23:09:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4C63E613B6 for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:49 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 11/13] dt-bindings: soc: tegra-pmc: Document core power domain Date: Fri, 21 May 2021 02:07:49 +0300 Message-Id: <20210520230751.26848-12-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All NVIDIA Tegra SoCs have a core power domain where majority of hardware blocks reside. Document the new core power domain properties. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 43fd2f8927d0..0afec83cc723 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -301,6 +301,33 @@ patternProperties: additionalProperties: false + core-domain: + type: object + description: | + The vast majority of hardware blocks of Tegra SoC belong to a + Core power domain, which has a dedicated voltage rail that powers + the blocks. + + properties: + operating-points-v2: + description: + Should contain level, voltages and opp-supported-hw property. + The supported-hw is a bitfield indicating SoC speedo or process + ID mask. + + "#power-domain-cells": + const: 0 + + required: + - operating-points-v2 + - "#power-domain-cells" + + additionalProperties: false + + core-supply: + description: + Phandle to voltage regulator connected to the SoC Core power rail. + required: - compatible - reg @@ -325,6 +352,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x7000e400 0x400>; + core-supply = <®ulator>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; @@ -338,17 +366,24 @@ examples: nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; resets = <&tegra_car 198>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; pd_xusbss: xusba { clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; #power-domain-cells = <0>; }; }; From patchwork Thu May 20 23:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 443442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0EC3C2B9FE for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 12/13] soc/tegra: pmc: Add core power domain Date: Fri, 21 May 2021 02:07:50 +0300 Message-Id: <20210520230751.26848-13-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org NVIDIA Tegra SoCs have multiple power domains, each domain corresponds to an external SoC power rail. Core power domain covers vast majority of hardware blocks within a Tegra SoC. The voltage of a power domain should be set to a level which satisfies all devices within the power domain. Add support for the core power domain which controls voltage state of the domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs. The PMC powergate domains now are sub-domains of the core domain, this requires device-tree updating, older DTBs are unaffected. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/Kconfig | 14 ++++ drivers/soc/tegra/pmc.c | 143 +++++++++++++++++++++++++++++++++++++ include/soc/tegra/common.h | 7 ++ 3 files changed, 164 insertions(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 976dee036470..7057254604ee 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC select PINCTRL_TEGRA20 select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA20_VOLTAGE_COUPLER @@ -27,6 +28,7 @@ config ARCH_TEGRA_3x_SOC select ARM_ERRATA_764369 if SMP select PINCTRL_TEGRA30 select PL310_ERRATA_769419 if CACHE_L2X0 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select SOC_TEGRA30_VOLTAGE_COUPLER @@ -40,6 +42,7 @@ config ARCH_TEGRA_114_SOC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -51,6 +54,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -66,6 +70,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help @@ -77,6 +82,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_COMMON select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC select TEGRA_TIMER @@ -99,6 +105,7 @@ config ARCH_TEGRA_186_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a @@ -115,6 +122,7 @@ config ARCH_TEGRA_194_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra194 SoC. @@ -125,6 +133,7 @@ config ARCH_TEGRA_234_SOC select TEGRA_BPMP select TEGRA_HSP_MBOX select TEGRA_IVC + select SOC_TEGRA_COMMON select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra234 SoC. @@ -132,6 +141,11 @@ config ARCH_TEGRA_234_SOC endif endif +config SOC_TEGRA_COMMON + bool + select PM_OPP + select PM_GENERIC_DOMAINS + config SOC_TEGRA_FUSE def_bool y depends on ARCH_TEGRA diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 8e3b78bb2ac2..33b6e0885020 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -428,6 +429,8 @@ struct tegra_pmc { struct irq_chip irq; struct notifier_block clk_nb; + + bool core_domain_state_synced; }; static struct tegra_pmc *pmc = &(struct tegra_pmc) { @@ -1302,12 +1305,115 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) return err; } +bool tegra_soc_core_domain_state_synced(void) +{ + return pmc->core_domain_state_synced; +} + +static int +tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, + unsigned int level) +{ + struct dev_pm_opp *opp; + int err; + + opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); + if (IS_ERR(opp)) { + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", + level, opp); + return PTR_ERR(opp); + } + + mutex_lock(&pmc->powergates_lock); + err = dev_pm_opp_set_opp(pmc->dev, opp); + mutex_unlock(&pmc->powergates_lock); + + dev_pm_opp_put(opp); + + if (err) { + dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", + level, err); + return err; + } + + return 0; +} + +static unsigned int +tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd, + struct dev_pm_opp *opp) +{ + return dev_pm_opp_get_level(opp); +} + +static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) +{ + static struct lock_class_key tegra_core_domain_lock_class; + struct generic_pm_domain *genpd; + const char *rname = "core"; + int err; + + genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = np->name; + genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; + genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; + + err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1); + if (err) + return dev_err_probe(pmc->dev, err, + "failed to set core OPP regulator\n"); + + err = pm_genpd_init(genpd, NULL, false); + if (err) { + dev_err(pmc->dev, "failed to init core genpd: %d\n", err); + return err; + } + + /* + * We have a "PMC pwrgate -> Core" hierarchy of the power domains + * where PMC needs to resume and change performance (voltage) of the + * Core domain from the PMC GENPD on/off callbacks, hence we need + * to annotate the lock in order to remove confusion from the + * lockdep checker when a nested access happens. + */ + lockdep_set_class(&genpd->mlock, &tegra_core_domain_lock_class); + + err = of_genpd_add_provider_simple(np, genpd); + if (err) { + dev_err(pmc->dev, "failed to add core genpd: %d\n", err); + goto remove_genpd; + } + + return 0; + +remove_genpd: + pm_genpd_remove(genpd); + + return err; +} + static int tegra_powergate_init(struct tegra_pmc *pmc, struct device_node *parent) { + struct of_phandle_args child_args, parent_args; struct device_node *np, *child; int err = 0; + /* + * Core power domain is the parent of powergate domains, hence it + * should be registered first. + */ + np = of_get_child_by_name(parent, "core-domain"); + if (np) { + err = tegra_pmc_core_pd_add(pmc, np); + of_node_put(np); + if (err) + return err; + } + np = of_get_child_by_name(parent, "powergates"); if (!np) return 0; @@ -1318,6 +1424,21 @@ static int tegra_powergate_init(struct tegra_pmc *pmc, of_node_put(child); break; } + + if (of_parse_phandle_with_args(child, "power-domains", + "#power-domain-cells", + 0, &parent_args)) + continue; + + child_args.np = child; + child_args.args_count = 0; + + err = of_genpd_add_subdomain(&parent_args, &child_args); + of_node_put(parent_args.np); + if (err) { + of_node_put(child); + break; + } } of_node_put(np); @@ -1361,6 +1482,12 @@ static void tegra_powergate_remove_all(struct device_node *parent) } of_node_put(np); + + np = of_get_child_by_name(parent, "core-domain"); + if (np) { + of_genpd_del_provider(np); + of_genpd_remove_last(np); + } } static const struct tegra_io_pad_soc * @@ -3672,6 +3799,21 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static void tegra_pmc_sync_state(struct device *dev) +{ + int err; + + pmc->core_domain_state_synced = true; + + /* this is a no-op if core regulator isn't used */ + mutex_lock(&pmc->powergates_lock); + err = dev_pm_opp_sync_regulators(dev); + mutex_unlock(&pmc->powergates_lock); + + if (err) + dev_err(dev, "failed to sync regulators: %d\n", err); +} + static struct platform_driver tegra_pmc_driver = { .driver = { .name = "tegra-pmc", @@ -3680,6 +3822,7 @@ static struct platform_driver tegra_pmc_driver = { #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif + .sync_state = tegra_pmc_sync_state, }, .probe = tegra_pmc_probe, }; diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index af41ad80ec21..135a6956a18c 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -23,6 +23,8 @@ struct tegra_core_opp_params { #ifdef CONFIG_ARCH_TEGRA bool soc_is_tegra(void); +bool tegra_soc_core_domain_state_synced(void); + int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params); #else @@ -31,6 +33,11 @@ static inline bool soc_is_tegra(void) return false; } +static inline bool tegra_soc_core_domain_state_synced(void) +{ + return false; +} + static inline int devm_tegra_core_dev_init_opp_table(struct device *dev, struct tegra_core_opp_params *params) From patchwork Thu May 20 23:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 444848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 518DFC43619 for ; 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[109.252.193.76]) by smtp.gmail.com with ESMTPSA id 4sm427821lfr.175.2021.05.20.16.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 16:08:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= , =?utf-8?q?Nikola_Milosavljevi=C4=87?= , Ulf Hansson , Peter Geis , Nicolas Chauvet , Viresh Kumar , Stephen Boyd , Matt Merhar , Paul Fertser , Krzysztof Kozlowski , Mikko Perttunen Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Mark Brown , Liam Girdwood , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Nathan Chancellor , linux-clk@vger.kernel.org Subject: [PATCH v1 13/13] soc/tegra: regulators: Support core domain state syncing Date: Fri, 21 May 2021 02:07:51 +0300 Message-Id: <20210520230751.26848-14-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520230751.26848-1-digetx@gmail.com> References: <20210520230751.26848-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The core voltage shall not drop until state of core domain is synced, i.e. all device drivers that use core domain are loaded and ready. Support core domain state syncing. The core domain driver invokes the core-regulator voltage syncing once the state of domain is synced, at this point the core voltage is allowed to go lower than the level left after bootloader. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Reviewed-by: Ulf Hansson Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++- drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c index 3479be5ee494..81787ae3d03e 100644 --- a/drivers/soc/tegra/regulators-tegra20.c +++ b/drivers/soc/tegra/regulators-tegra20.c @@ -17,6 +17,8 @@ #include #include +#include + struct tegra_regulator_coupler { struct regulator_coupler coupler; struct regulator_dev *core_rdev; @@ -42,6 +44,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra20 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced() && !tegra->sys_reboot_mode) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -62,7 +79,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; } diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c index 6e4f3d9e7be1..e0203f78b396 100644 --- a/drivers/soc/tegra/regulators-tegra30.c +++ b/drivers/soc/tegra/regulators-tegra30.c @@ -17,6 +17,7 @@ #include #include +#include #include struct tegra_regulator_coupler { @@ -43,6 +44,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, int core_cur_uV; int err; + /* + * Tegra30 SoC has critical DVFS-capable devices that are + * permanently-active or active at a boot time, like EMC + * (DRAM controller) or Display controller for example. + * + * The voltage of a CORE SoC power domain shall not be dropped below + * a minimum level, which is determined by device's clock rate. + * This means that we can't fully allow CORE voltage scaling until + * the state of all DVFS-critical CORE devices is synced. + */ + if (tegra_soc_core_domain_state_synced() && !tegra->sys_reboot_mode) { + pr_info_once("voltage state synced\n"); + return 0; + } + if (tegra->core_min_uV > 0) return tegra->core_min_uV; @@ -63,7 +79,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, */ tegra->core_min_uV = core_max_uV; - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); return tegra->core_min_uV; }