From patchwork Wed Jun 2 12:34:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 452896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9EEBC47093 for ; Wed, 2 Jun 2021 12:34:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2541613D2 for ; Wed, 2 Jun 2021 12:34:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229886AbhFBMga (ORCPT ); Wed, 2 Jun 2021 08:36:30 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38722 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbhFBMga (ORCPT ); Wed, 2 Jun 2021 08:36:30 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 152CYem2025846; Wed, 2 Jun 2021 07:34:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622637280; bh=WGSya+3XDa+aXOHljEVNaXhvhidxFT4fdTvbYH+aX3w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gxdt15psyrawt4xXojRSLOloXEjl/ypoxO8O1T7e0jlsWTYe/1hPNuTpLL7BBzlTy EzDvlg6E9/xQin+SDv+C2uu/35xEm26nGcfPYmTLePahpVJ3Y2oonOoSFPbDmjGMht UU2tpycLoxhxYtVT5QR6x77D75VN4Ky56hjZKvIk= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 152CYePH096654 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Jun 2021 07:34:40 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 2 Jun 2021 07:34:39 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 2 Jun 2021 07:34:39 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 152CYKN4023646; Wed, 2 Jun 2021 07:34:32 -0500 From: Aswath Govindraju CC: Lokesh Vutla , Vignesh Raghavendra , Kishon Vijay Abraham I , Grygorii Strashko , Aswath Govindraju , Mark Brown , Rob Herring , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Tero Kristo , , , , , Subject: [PATCH 1/5] ARM: dts: am335x: align ti, pindir-d0-out-d1-in property with dt-shema Date: Wed, 2 Jun 2021 18:04:11 +0530 Message-ID: <20210602123416.20378-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602123416.20378-1-a-govindraju@ti.com> References: <20210602123416.20378-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Signed-off-by: Aswath Govindraju --- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 36d963db4026..ec4730c82d39 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -496,7 +496,7 @@ status = "okay"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; /* WLS1271 WiFi */ wlcore: wlcore@1 { compatible = "ti,wl1271"; From patchwork Wed Jun 2 12:34:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 452895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F77AC47083 for ; Wed, 2 Jun 2021 12:35:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39AD4613DC for ; Wed, 2 Jun 2021 12:35:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230056AbhFBMgw (ORCPT ); Wed, 2 Jun 2021 08:36:52 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35266 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbhFBMgw (ORCPT ); Wed, 2 Jun 2021 08:36:52 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 152CZ57o073672; Wed, 2 Jun 2021 07:35:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622637305; bh=SqQKNsh6bz7/NUTj9eXT54AA/AulM1klcuIl12Cj+Cg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D7aob2CwOCZ3txJrCeNdFwhFxxDvIG9Va7J4ZKgBN7oR94NWSb3ZxOFDIeTEt03Lf DQfsoyEk/QIwTREf1ARgYywRLc7DJTUBdzew/rk8aPvuDTGwCXX04gQJKooJ1FtRBW 2Qa/sI7GFxBRtFVvLiK4elrn+DMN1U0SPLmpBPrM= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 152CZ4IC014954 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Jun 2021 07:35:05 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 2 Jun 2021 07:35:04 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 2 Jun 2021 07:35:05 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 152CYKN6023646; Wed, 2 Jun 2021 07:34:55 -0500 From: Aswath Govindraju CC: Lokesh Vutla , Vignesh Raghavendra , Kishon Vijay Abraham I , Grygorii Strashko , Aswath Govindraju , Mark Brown , Rob Herring , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Tero Kristo , , , , , Subject: [PATCH 3/5] arm64: dts: ti: am65: align ti, pindir-d0-out-d1-in property with dt-shema Date: Wed, 2 Jun 2021 18:04:13 +0530 Message-ID: <20210602123416.20378-4-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602123416.20378-1-a-govindraju@ti.com> References: <20210602123416.20378-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org ti,pindir-d0-out-d1-in property is expected to be of type boolean. Therefore, fix the property accordingly. Signed-off-by: Aswath Govindraju --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index f4ec9ed52939..23d51b6a9cf2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -575,7 +575,7 @@ #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index eddb2ffb93ca..1b947e2c2e74 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -299,7 +299,7 @@ pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; + ti,pindir-d0-out-d1-in; flash@0{ compatible = "jedec,spi-nor"; From patchwork Wed Jun 2 12:34:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 452894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E484C47092 for ; Wed, 2 Jun 2021 12:35:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5B4D861396 for ; Wed, 2 Jun 2021 12:35:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230104AbhFBMhU (ORCPT ); Wed, 2 Jun 2021 08:37:20 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40460 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbhFBMhT (ORCPT ); Wed, 2 Jun 2021 08:37:19 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 152CZU3f027790; Wed, 2 Jun 2021 07:35:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1622637330; bh=i3QEOXysvQImmF/O6Ym6rYgSqMjCwg+DVqqgsbiucz0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=igsTvpECG/fACRSRdt4rZ4stR2ODEgnUMzo1QVLhun8vKf7wQDYy0ggpuzyTiMq/6 LVT02p/4Xy6h/cIJKqckDifoO0UZlG9Ot4hTKKSFM7LMc9y2A5Eri/n/TdBegWDU07 oksylvqnezk32+ApQZqWF/84Mm0ZwSkF+n3ExXds= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 152CZUo2015822 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Jun 2021 07:35:30 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 2 Jun 2021 07:35:29 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 2 Jun 2021 07:35:29 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 152CYKN8023646; Wed, 2 Jun 2021 07:35:20 -0500 From: Aswath Govindraju CC: Lokesh Vutla , Vignesh Raghavendra , Kishon Vijay Abraham I , Grygorii Strashko , Aswath Govindraju , Mark Brown , Rob Herring , =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Nishanth Menon , Tero Kristo , , , , , Subject: [PATCH 5/5] dt-bindings: spi: omap-spi: Convert to json-schema Date: Wed, 2 Jun 2021 18:04:15 +0530 Message-ID: <20210602123416.20378-6-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602123416.20378-1-a-govindraju@ti.com> References: <20210602123416.20378-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Convert omap-spi dt-binding documentation from txt to yaml format. Signed-off-by: Aswath Govindraju --- .../devicetree/bindings/spi/omap-spi.txt | 48 ------- .../devicetree/bindings/spi/omap-spi.yaml | 126 ++++++++++++++++++ 2 files changed, 126 insertions(+), 48 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/omap-spi.txt create mode 100644 Documentation/devicetree/bindings/spi/omap-spi.yaml diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt deleted file mode 100644 index 487208c256c0..000000000000 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ /dev/null @@ -1,48 +0,0 @@ -OMAP2+ McSPI device - -Required properties: -- compatible : - - "ti,am654-mcspi" for AM654. - - "ti,omap2-mcspi" for OMAP2 & OMAP3. - - "ti,omap4-mcspi" for OMAP4+. -- ti,spi-num-cs : Number of chipselect supported by the instance. -- ti,hwmods: Name of the hwmod associated to the McSPI -- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as - input. The default is D0 as input and - D1 as output. - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required for each chip select. -- dma-names: List of DMA request names. These strings correspond - 1:1 with the DMA specifiers listed in dmas. The string naming - is to be "rxN" and "txN" for RX and TX requests, - respectively, where N equals the chip select number. - -Examples: - -[hwmod populated DMA resources] - -mcspi1: mcspi@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,omap4-mcspi"; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <4>; -}; - -[generic DMA request binding] - -mcspi1: mcspi@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,omap4-mcspi"; - ti,hwmods = "mcspi1"; - ti,spi-num-cs = <2>; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; - dma-names = "tx0", "rx0", "tx1", "rx1"; -}; diff --git a/Documentation/devicetree/bindings/spi/omap-spi.yaml b/Documentation/devicetree/bindings/spi/omap-spi.yaml new file mode 100644 index 000000000000..cd20704f2edc --- /dev/null +++ b/Documentation/devicetree/bindings/spi/omap-spi.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/omap-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI controller bindings for OMAP and K3 SoCs + +maintainers: + - Mark Brown + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,am654-mcspi + - ti,am4372-mcspi + - const: ti,omap4-mcspi + - items: + - enum: + - ti,omap2-mcspi + - ti,omap4-mcspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + power-domains: + maxItems: 1 + + ti,spi-num-cs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of chipselect supported by the instance. + minimum: 1 + maximum: 4 + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + description: + Must be "mcspi", n being the instance number (1-based). + This property is applicable only on legacy platforms mainly omap2/3 + and ti81xx and should not be used on other platforms. + deprecated: true + + ti,pindir-d0-out-d1-in: + description: + Select the D0 pin as output and D1 as input. The default is D0 + as input and D1 as output. + type: boolean + + dmas: + description: + List of DMA specifiers with the controller specific format as + described in the generic DMA client binding. A tx and rx + specifier is required for each chip select. + minItems: 1 + maxItems: 8 + + dma-names: + description: + List of DMA request names. These strings correspond 1:1 with + the DMA sepecifiers listed in dmas. The string names is to be + "rxN" and "txN" for RX and TX requests, respectively. Where N + is the chip select number. + minItems: 1 + maxItems: 8 + +patternProperties: + "@[0-9a-f]+$": + type: object + description: + Flash devices are defined as a sub-node of the spi controller + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +if: + properties: + compatible: + oneOf: + - const: ti,omap2-mcspi + - const: ti,omap4-mcspi + +then: + properties: + ti,hwmods: + items: + - pattern: "^mcspi([1-9])$" + +else: + properties: + ti,hwmods: false + +examples: + - | + #include + #include + #include + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x2100000 0x400>; + interrupts = ; + clocks = <&k3_clks 137 1>; + power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; + dma-names = "tx0", "rx0"; + };