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[209.85.220.41]) by mx.google.com with SMTPS id z125-v6sor2140160pgb.426.2018.07.23.06.19.55 for (Google Transport Security); Mon, 23 Jul 2018 06:19:55 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MzRHVdZC; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.41 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=yEvwFpYKkSJUXgAeUyA6XSCvnatKoUYUdA7qefnMiH4=; b=MzRHVdZCq/u2Ltt97wnJNcexzXXebaPaMdTO7RB3SfbZTqzIIc9ablRfOQiK5rLgMV GZE3uQLCobl+qPXLRtf9tJiO7L/xMHe+n1BEeQj5XC665OfLzOguPsOjVfEXR1jKuG0e EEm3A/V1ULJru2dL4l4Vr669lLyreQCaJ3+zc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yEvwFpYKkSJUXgAeUyA6XSCvnatKoUYUdA7qefnMiH4=; b=mgeY03rLq9b99NCw08oOPdbkOhHMsWhKFHB7PTPofe6OcFb4Tdu50GSyiTaJ4T0BM3 /4nX2Aoj8OD2q1tPGL1lMOHg8nppMKyg86UsM2bA4SAwCqmNOLqRdsuAenmS0vKIUThu WAz/XyWyKd8lhDTPI697rxuKgBpDcCsi9sH0lYH4K+CXJDRNas9hUEbPMXxRoc4M/lxD JhuW21g1631ng05jEkpLq0PA4O2snn8t2qEX1gAMHtc7CyXoEfdeOc5huqW2Vfm7dOys 9iuEkFJ7V5BKvoHw4X5HmNALmzIM4NepjTnITt1LjNzuNS3fLvSyO6AqJtRjL3lf2Omk QeOw== X-Gm-Message-State: AOUpUlED+H4z1XLy2LoAn9OvOuTUj4lJ75xafjNaMClvY30GiNFfXRYf XOMfzU4xuwmhFsylQ7NShEDDL95c X-Google-Smtp-Source: AAOMgpepZnFVxE/6cptO+KLdSdFb2oeCH/e3RAvN73WmWA9uX5MdpiQV40YU3aVKvFfmKOGjM8fHlQ== X-Received: by 2002:a63:f756:: with SMTP id f22-v6mr12044693pgk.289.1532351995364; Mon, 23 Jul 2018 06:19:55 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.241.97.199]) by smtp.gmail.com with ESMTPSA id z20-v6sm19287326pfd.99.2018.07.23.06.19.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 06:19:54 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Cc: patches@linaro.org, Sumit Garg , Ard Biesheuvel , Leif Lindholm Subject: [edk2][PATCH edk2-platforms v2 1/1] Silicon/SynQuacer: add optional OP-TEE DT node Date: Mon, 23 Jul 2018 18:49:21 +0530 Message-Id: <1532351961-17377-1-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 OP-TEE is optional on Developerbox controlled via SCP firmware. To check if we need to delete OP-TEE DT node, we use DRAM1 region info as SCP firmware conditionally carves out Secure memory from DRAM1 region. Cc: Ard Biesheuvel Cc: Leif Lindholm Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg --- Changes since v1: - Add support for optional OP-TEE DT node addition Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 3 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 33 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 7 +++++ 3 files changed, 43 insertions(+) -- 2.7.4 diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf index 548d62fd5c0a..46cd3f85e509 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf @@ -35,6 +35,9 @@ [LibraryClasses] FdtLib MemoryAllocationLib +[FixedPcd] + gSynQuacerTokenSpaceGuid.PcdDramInfoBase + [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask gSynQuacerTokenSpaceGuid.PcdPlatformSettings diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 897d06743708..da1209b4a613 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -19,10 +19,13 @@ #include #include #include +#include #include // add enough space for three instances of 'status = "disabled"' #define DTB_PADDING 64 +// base address for OP-TEE used to determine its presence +#define OPTEE_BASE_ADDR 0xFC000000 STATIC VOID @@ -47,6 +50,29 @@ DisableDtNode ( } } +STATIC +VOID +DeleteDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node = fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc = fdt_del_node (Dtb, Node); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to delete node on '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + /** Return a pool allocated copy of the DTB image that is appropriate for booting the current platform via DT. @@ -73,6 +99,7 @@ DtPlatformLoadDtb ( UINTN CopyDtbSize; INT32 Rc; UINT64 SettingsVal; + DRAM_INFO *DramInfo; SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, @@ -107,6 +134,12 @@ DtPlatformLoadDtb ( DisableDtNode (CopyDtb, "/sdhci@52300000"); } + DramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); + + if ((DramInfo->Entry[0].Base + DramInfo->Entry[0].Size) > OPTEE_BASE_ADDR) { + DeleteDtNode (CopyDtb, "/firmware/optee"); + } + *Dtb = CopyDtb; *DtbSize = CopyDtbSize; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37d642e4b237..d109a5742793 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -574,6 +574,13 @@ #address-cells = <1>; #size-cells = <0>; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; #include "SynQuacerCaches.dtsi"