From patchwork Thu Jul 26 15:45:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 142983 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp616176ljj; Thu, 26 Jul 2018 08:46:56 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfBuC0H5kxYWIViqHcuzlxM9mim78Zi+7TNGan0VTniQaU5Rz4DlbG5OYJEvPT08eTzR07Q X-Received: by 2002:a17:902:822:: with SMTP id 31-v6mr2442267plk.172.1532620016177; Thu, 26 Jul 2018 08:46:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532620016; cv=none; d=google.com; s=arc-20160816; b=KsJ7kZqDU7gAvKbGvNdiNivI0E0laI3YUbWYSKHgTLYOV5+B78+CIZqNyUO174ni8V qBI9xMlbCWnqHjrcpqiw15010cKf3V9xlKJtYiX6Vm4WM52aoubO5ZBBPdSf0ohghTow LA6XaJWG1u7DeluhuRqFS2Sf+saAAsSbDM6P//9M6a2Ayx9Akl7Q/JCKPiZrC28k/xRO sLbGY5Xhc0f8xiTDmmWPA688vgvGq4AFBwgPNDqeXfeb7Iyp2lkKI1Ifw+52JyEin4wN 6izlsAtr0gueYf2ImLuY1MbNZMWyMd0V4UTImD3v9rePOiw9LAfvuHu57QbMXszCEKqG LJMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=B5VHjDoArZfwJoeuBac8pCYMc/MhBY/ent7SYqhw7jI=; b=0/CzhDa5Eht2E5BNui0K/DNka61l0r06jI74MRohy4nUZcCukQWIY9M0Wl6FaoP3Em zlPwU0m5ubixp8ju+Fefx9qYfysNQR2y0yrue+ZXWqxXTMgVcVToaGeUKfBLrFpjcPFS dgT2X7uM4X8iAd6J68X5UsQ4cnjxcMagPIsHDwl3yPwi4w+3Z7Co6BKK59q5JpdKBWf2 vv6H7koo7/16LInDihZmqkAsieT47DkFLppzCo/+6UoRmCjBqqDJ3hPQPCNx/UKrTiQ7 7LdzIDEqUKwK13cDBLDhkJ8EG+uXk0IBE7QOqXs1Dsx5EHWoi4XAAVLcPyxAoS4vCVZd TNzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DC6gZu3j; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u7-v6si1723945pfb.227.2018.07.26.08.46.55; Thu, 26 Jul 2018 08:46:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DC6gZu3j; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731962AbeGZREU (ORCPT + 5 others); Thu, 26 Jul 2018 13:04:20 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:45367 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731948AbeGZRET (ORCPT ); Thu, 26 Jul 2018 13:04:19 -0400 Received: by mail-pl0-f65.google.com with SMTP id j8-v6so998708pll.12 for ; Thu, 26 Jul 2018 08:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G9Pra/HIrTIdZzogTmPr0pWDqZgp6mkljxVwg8UNDhk=; b=DC6gZu3jfWRhlaATLhMnFFP04tmIDsx0VsdYvuwkDrWcBQrmghBqV61XGG5wxF39F8 lkAOUeAvBaWtjXzkN8fniu2YiKWimvhHZZFmj7vofEN5iTC047bZ+oXbJeZ7DQJcKao8 yK3rA5M8hHxXm/YeV+ZYIInDRsSWMA6qs7emo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G9Pra/HIrTIdZzogTmPr0pWDqZgp6mkljxVwg8UNDhk=; b=uBrDpF67vL2s0Xf+RVdzqjUZZiQEzrQ67CSHFsLlDM6ByyS+/2ZnN7c7XKPtNGLrZK 6NYTPEF/3dtj8F9ZqJ0BVtcNROb4lXPo0kDfSrShlE3VC5QFB4Rjw4xFruB1dE4zt/jD Tz17IWx229XQHLSEod9kfRpZnFX1bgn8c6+GnqLo2hdZaUWqQJT03C5o048w+PNBmtkU W75luBUxTgOHgbzATRTm+CCiig+kOHfKSeeh8JMXD4NjuPcRhlVhIQXPDuQGPxmSDyi7 jmWyEBzKefThG2jbIbV7De9nW8wWYblEY0Xts6lMxhPLjhGKibqZhwNPGdtFt0XAzVdD QTAQ== X-Gm-Message-State: AOUpUlGgk8AY07w5UNLnBhQrXOBTvTxyTwVY/ijXJc1NHHn7oWJ0enmZ A0zp5GTubv5QbpnhPC/vpouI X-Received: by 2002:a17:902:20e9:: with SMTP id v38-v6mr2463010plg.107.1532620014463; Thu, 26 Jul 2018 08:46:54 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:628e:aef6:6d51:3501:dada:e06d]) by smtp.gmail.com with ESMTPSA id z11-v6sm3755322pff.162.2018.07.26.08.46.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jul 2018 08:46:53 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v7 2/6] arm64: dts: actions: Add pinctrl definition for S900 I2C controller Date: Thu, 26 Jul 2018 21:15:59 +0530 Message-Id: <20180726154603.5089-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> References: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl definition for Actions Semiconductor S900 I2C controller. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Signed-off-by: Manivannan Sadhasivam --- .../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi new file mode 100644 index 000000000000..95e8b31071f9 --- /dev/null +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pinctrl { + + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; +}; From patchwork Thu Jul 26 15:46:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 142984 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp616363ljj; Thu, 26 Jul 2018 08:47:07 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc3couhDL+RY1Og4u9Wq5WSoXLzEVLAjWU36i7CSxs43UlBDG1ifnP/ao+O71FkZTXnRjt0 X-Received: by 2002:a17:902:8d91:: with SMTP id v17-v6mr2496348plo.9.1532620027058; Thu, 26 Jul 2018 08:47:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532620027; cv=none; d=google.com; s=arc-20160816; b=bwJ+5WnHjgYMnMAv5VRowOIw+sJmPYo8DdaePrm6JDjJqlRddTnvs+GglCIb075yP5 HUDBwjTDvw+kZWvegr9jcbPhIgzS1MKA1kQhfDuwNcRBA0+3rWiKdZa6hauuladQlH3P D2RITxwjRwpOeq7lOF4nrY/MTup7d0dVB56ENAegSKDhIYR5izZKzDYVTNQTT9E9WJle BEzZPEh2LqYs9g6O9zvvvpGw0BSHbOIkFuvaDle2GZu6OXZvKfmCgdxm6+Ae8q61OhnW +OqoHBrFlqBAwvAnrKX8/q3NNFR385Y5K8Zw1eYkwwcZKdx9qVTzZDZRCTCMaVx5u6O+ CyfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1EAAyyNR0bj+HJHQT2gpnaJAnzgb1+Fm8kt38UzI5rw=; b=zYpRTe4JDP/NixlO/n3Gin2jMXiOErNBjZ/5DqRHYJWqM3HwF7Stb2sKMvODLNXwz5 AI+2OK/A0kAfi+zU0B8qPcmrha/h23xHjMslLtyjZZH7LL/LMJjuCT/tJpTr7wR8xKgI xde0RPh4hx3M3Z9TRZqhHFmLW3ynYkIzi9qaQLk5rJd51aGoM9C5OOk/YLoMRVdZ1ckX G0KOwtoQJWJfBdT+iB8dKCbtq2nWpxO06v1Fq1sJ0ujk4ZLcUe9kiclhOoI6IauDXtm6 kgIAc3NRU/DkQAFA+R8687/7EG2vVgxeqGnS7iQ5BXIJQCTMtxexJJsYrB2Ng2j/14CL EUyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Z77Pxt0H; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n6-v6si1610283pgt.268.2018.07.26.08.47.06; Thu, 26 Jul 2018 08:47:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Z77Pxt0H; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731974AbeGZREb (ORCPT + 5 others); Thu, 26 Jul 2018 13:04:31 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:40691 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731949AbeGZREa (ORCPT ); Thu, 26 Jul 2018 13:04:30 -0400 Received: by mail-pl0-f65.google.com with SMTP id s17-v6so1004053plp.7 for ; Thu, 26 Jul 2018 08:47:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2pWiTqMDsoMOxuo1kybX0qJyORiAw5vulAq9JPZVfNM=; b=Z77Pxt0H3glitbvPEMsOOOn8IpWEja4kbrhcyZqQ5ISstEhAX421O8kVAJ5BtrTOmM 6ml/WG9cyIu6ilgMUzLJhPPdpKBd5U/v05UCHcgPsLfc4mo1xOt2MPYJ4btHB9lNorYs sYGSQxxRFpLgGUeXYiyCnPAqqJGySKZP2LG2c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2pWiTqMDsoMOxuo1kybX0qJyORiAw5vulAq9JPZVfNM=; b=cablyWpor5gURT0qFY1hFWXx8RZIoQNeBN1bGI/z4sOAEuRGaBLBPFnAhSFg0vDCRC f7xGuqS5R3FZkFE0dBFwmBuazfeHLqWQ6GG1fIb0+7fgaA8bzZXjQRiB6QbxEsYBvDDp fA2ffOzua3t8Oa59CZFSsxw0SWcOe7hBUUwwwk09yABjb/YfL0fUf1KzZ2ms+9pE4Eo1 ucfCu+wi+U9uTtGK6DkG8bSFRkOBu+5a7tJb4VCpmn7dUA7p+V+nodI8AMO6+BdBnIu1 wgKB231j9w6AOgWcUEIpSh2yqfIpCQgFERVIm9J8qkHNdz+30V/jLRy2FLnOdAlbBY8A fdjg== X-Gm-Message-State: AOUpUlFOuzWz+AmHSEOhDIOy7PoQ5RKvvpxHw8Oi1wL16OKESeKRoqxT j78l8YGvDOUd1ZEVFXbR865I X-Received: by 2002:a17:902:8604:: with SMTP id f4-v6mr2484651plo.225.1532620025508; Thu, 26 Jul 2018 08:47:05 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:628e:aef6:6d51:3501:dada:e06d]) by smtp.gmail.com with ESMTPSA id z11-v6sm3755322pff.162.2018.07.26.08.46.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jul 2018 08:47:05 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v7 3/6] arm64: dts: actions: Add Actions Semiconductor S900 I2C controller nodes Date: Thu, 26 Jul 2018 21:16:00 +0530 Message-Id: <20180726154603.5089-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> References: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add I2C controller nodes for Actions Semiconductor S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900.dtsi | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi index 7ae8b931f000..6f7b89edbe4d 100644 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ b/arch/arm64/boot/dts/actions/s900.dtsi @@ -174,6 +174,66 @@ #clock-cells = <1>; }; + i2c0: i2c@e0170000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0170000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + }; + + i2c1: i2c@e0172000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0172000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + }; + + i2c2: i2c@e0174000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0174000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; + }; + + i2c3: i2c@e0176000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0176000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e0178000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe0178000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e017a000 { + compatible = "actions,s900-i2c"; + reg = <0 0xe017a000 0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl@e01b0000 { compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; From patchwork Thu Jul 26 15:46:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 142986 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp616704ljj; Thu, 26 Jul 2018 08:47:27 -0700 (PDT) X-Google-Smtp-Source: AAOMgpedjgZZIQJ/KqrTfL00Bs59k20xfmkjREJB80SUmHFDWvm3L7xtVzEuz/Ae8Ks8CejYARX5 X-Received: by 2002:a63:f449:: with SMTP id p9-v6mr2497591pgk.213.1532620047836; Thu, 26 Jul 2018 08:47:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532620047; cv=none; d=google.com; s=arc-20160816; b=wdbdDDKs4JHH9fRk6dR9loCKT4ZQF36xe42oLW644yN2EEMAnLZrD+rvd8XCQxEJRp i33Xslai4OcWCxHSO3m1waeuuKHjy6wLGN/vrDtgk83B//hzj16FhghQFhQaXD5utc4k vJu3dnoGzY+zpB1f7PprFLjqQ1YlNwfJMcOYXmA0LLOyFHJe0CKyr2CTzKzAV2Bglpu+ bQNmqmMTijwKAktkcCk0e0MIacobMDvj9tT1RmgBCYSYt+V7Hs96GbdQuMMEhNLnfdR6 +eWPyL1o5sTa/uw39eoDveAYYb6TYMnrplqVpFRNA/KFuXp2tSM/72m7qG/+Dv9UM0G2 eW9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=laawrEYGY7frvC5zhzQwigRNnLEUThvwD8eWQ95AWQs=; b=WLfmDF0sImwpcfzDs/qVVpyL4icpVvnIh2AsgfynPj7YFDYW3IHngstpJ5yBc6fUIa Cbgw148DJIrubGu/lRppG9smnJtw7ewK9K3jJT5OI2JJVJycgAvg4czXqRqGQRKJpm0B wzO+gSbomZdS8Nl2lkca0Rjg7d8K55Olsk33Ktj24Hr2gi+UaiOeGSrID8RcreGL0ouU ysBsxQnkXjcBrVUKd0tJJsF4pfDBIk+lRVaK4gtz1rycMZf8vglYnqlY4ihxqnNzYMf8 YiiFdtk2fWfuIoqfGoM/HrAmkkFCx2dGIVdw/3aMc8bAmeWYdYHb+PTfOZ+MoGl6aEzt WRBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JxFOH2q8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f200-v6si1698383pfa.164.2018.07.26.08.47.27; Thu, 26 Jul 2018 08:47:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JxFOH2q8; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732019AbeGZREv (ORCPT + 5 others); Thu, 26 Jul 2018 13:04:51 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:44292 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732017AbeGZREv (ORCPT ); Thu, 26 Jul 2018 13:04:51 -0400 Received: by mail-pg1-f193.google.com with SMTP id r1-v6so1411484pgp.11 for ; Thu, 26 Jul 2018 08:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=arLzsRMWw+gX3H9eRFhB6LwOUelzOo0/Gwxew7QhRd8=; b=JxFOH2q8JU3nkY/dToTU/Nm6sVp2fH/OMfk73yE+ShhZMnmztYY3EcsF83iWHfV4Mc jqYUjnVrA9bjdIizfUZSBTBmxh3pPZz9vNKzcvZ9VgPt5vjh8tQFTQE1VoyxU3Tso3Dc UIAfSJBSnyM7w5ZLry418l5VeKEvrDDY7/3DM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=arLzsRMWw+gX3H9eRFhB6LwOUelzOo0/Gwxew7QhRd8=; b=JruBPIut6ATf9vSCFmSiPzTIBnlXyRf/6jbuD2WxD+wsNf4tPNFZI6ifTwcTvZvLt1 G6HeRBkgKCEz6l75LzX9cctoOzsbuJqOo1IW+2THgZ/+bL8sLkyGo2jqbivv3x0Z1t5t dkEErdAw0SkkCqVEiuvSe40pa5IQV6TSBs5fRFWlJnB6JL4fcWFU/5nPyJxOBUoi76/D SbLuyQXmyPgmixWVO92r8jyU0+k3pbHcbcTDgqwxnwyTMZC6JAq1MwjlGaLvqXQoVB49 4fLy7PlI5PMaZKhmBw1+sM6GRQ0dzNXAZGPdnFuhtJe6vXP/yr7Kzm2fOE/uO+u0Nf1F Bx9w== X-Gm-Message-State: AOUpUlFiFvNg90SsQRpwjV2ffeMUkZBNNHEtLi2v/t2Xl9S5twujgMeV 4T8hGZwYlHPWEKPtmy6JCQXv X-Received: by 2002:a62:5486:: with SMTP id i128-v6mr2635493pfb.166.1532620045687; Thu, 26 Jul 2018 08:47:25 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:628e:aef6:6d51:3501:dada:e06d]) by smtp.gmail.com with ESMTPSA id z11-v6sm3755322pff.162.2018.07.26.08.47.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jul 2018 08:47:25 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v7 5/6] i2c: Add Actions Semiconductor Owl family S900 I2C driver Date: Thu, 26 Jul 2018 21:16:02 +0530 Message-Id: <20180726154603.5089-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> References: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add Actions Semiconductor Owl family S900 I2C driver. Signed-off-by: Manivannan Sadhasivam Acked-by: Peter Rosin --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-owl.c | 495 +++++++++++++++++++++++++++++++++++ 3 files changed, 503 insertions(+) create mode 100644 drivers/i2c/busses/i2c-owl.c -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4f8df2ec87b1..8c8025f87ce4 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -762,6 +762,13 @@ config I2C_OMAP Like OMAP1510/1610/1710/5912 and OMAP242x. For details see http://www.ti.com/omap. +config I2C_OWL + tristate "Actions Semiconductor Owl I2C Controller" + depends on ARCH_ACTIONS || COMPILE_TEST + help + Say Y here if you want to use the I2C bus controller on + the Actions Semiconductor Owl SoC's. + config I2C_PASEMI tristate "PA Semi SMBus interface" depends on PPC_PASEMI && PCI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 5a869144a0c5..b71618f77880 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o +obj-$(CONFIG_I2C_OWL) += i2c-owl.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c new file mode 100644 index 000000000000..a92a6c610478 --- /dev/null +++ b/drivers/i2c/busses/i2c-owl.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Actions Semiconductor Owl SoC's I2C driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +/* I2C registers */ +#define OWL_I2C_REG_CTL 0x0000 +#define OWL_I2C_REG_CLKDIV 0x0004 +#define OWL_I2C_REG_STAT 0x0008 +#define OWL_I2C_REG_ADDR 0x000C +#define OWL_I2C_REG_TXDAT 0x0010 +#define OWL_I2C_REG_RXDAT 0x0014 +#define OWL_I2C_REG_CMD 0x0018 +#define OWL_I2C_REG_FIFOCTL 0x001C +#define OWL_I2C_REG_FIFOSTAT 0x0020 +#define OWL_I2C_REG_DATCNT 0x0024 +#define OWL_I2C_REG_RCNT 0x0028 + +/* I2Cx_CTL Bit Mask */ +#define OWL_I2C_CTL_RB BIT(1) +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) +#define OWL_I2C_CTL_IRQE BIT(5) +#define OWL_I2C_CTL_EN BIT(7) +#define OWL_I2C_CTL_AE BIT(8) +#define OWL_I2C_CTL_SHSM BIT(10) + +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) + +/* I2Cx_STAT Bit Mask */ +#define OWL_I2C_STAT_RACK BIT(0) +#define OWL_I2C_STAT_BEB BIT(1) +#define OWL_I2C_STAT_IRQP BIT(2) +#define OWL_I2C_STAT_LAB BIT(3) +#define OWL_I2C_STAT_STPD BIT(4) +#define OWL_I2C_STAT_STAD BIT(5) +#define OWL_I2C_STAT_BBB BIT(6) +#define OWL_I2C_STAT_TCB BIT(7) +#define OWL_I2C_STAT_LBST BIT(8) +#define OWL_I2C_STAT_SAMB BIT(9) +#define OWL_I2C_STAT_SRGC BIT(10) + +/* I2Cx_CMD Bit Mask */ +#define OWL_I2C_CMD_SBE BIT(0) +#define OWL_I2C_CMD_RBE BIT(4) +#define OWL_I2C_CMD_DE BIT(8) +#define OWL_I2C_CMD_NS BIT(9) +#define OWL_I2C_CMD_SE BIT(10) +#define OWL_I2C_CMD_MSS BIT(11) +#define OWL_I2C_CMD_WRS BIT(12) +#define OWL_I2C_CMD_SECL BIT(15) + +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) + +/* I2Cx_FIFOCTL Bit Mask */ +#define OWL_I2C_FIFOCTL_NIB BIT(0) +#define OWL_I2C_FIFOCTL_RFR BIT(1) +#define OWL_I2C_FIFOCTL_TFR BIT(2) + +/* I2Cc_FIFOSTAT Bit Mask */ +#define OWL_I2C_FIFOSTAT_RNB BIT(1) +#define OWL_I2C_FIFOSTAT_RFE BIT(2) +#define OWL_I2C_FIFOSTAT_TFF BIT(5) +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) + +/* I2C bus timeout */ +#define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) + +#define OWL_I2C_MAX_RETRIES 50 + +#define OWL_I2C_DEF_SPEED_HZ 100000 +#define OWL_I2C_MAX_SPEED_HZ 400000 + +struct owl_i2c_dev { + struct i2c_adapter adap; + struct i2c_msg *msg; + struct completion msg_complete; + struct clk *clk; + spinlock_t lock; + void __iomem *base; + unsigned long clk_rate; + u32 bus_freq; + u32 msg_ptr; +}; + +static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) +{ + unsigned int regval; + + regval = readl(reg); + + if (state) + regval |= val; + else + regval &= ~val; + + writel(regval, reg); +} + +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) +{ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + mdelay(1); + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, true); + + /* Clear status registers */ + writel(0, i2c_dev->base + OWL_I2C_REG_STAT); +} + +static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val, timeout = 0; + + /* Reset FIFO */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, + true); + + /* Wait 50ms for FIFO reset complete */ + do { + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) + break; + usleep_range(500, 1000); + } while (timeout++ < OWL_I2C_MAX_RETRIES); + + if (timeout > OWL_I2C_MAX_RETRIES) { + dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val; + + val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); + + /* Set clock divider factor */ + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); +} + +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) +{ + struct owl_i2c_dev *i2c_dev = _dev; + struct i2c_msg *msg = i2c_dev->msg; + unsigned long flags; + unsigned int stat, fifostat; + + spin_lock_irqsave(&i2c_dev->lock, flags); + + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); + if (fifostat & OWL_I2C_FIFOSTAT_RNB) { + dev_dbg(&i2c_dev->adap.dev, "received NACK from device\n"); + goto stop; + } + + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (stat & OWL_I2C_STAT_BEB) { + dev_dbg(&i2c_dev->adap.dev, "bus error\n"); + goto stop; + } + + /* Handle FIFO read */ + if (msg->flags & I2C_M_RD) { + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + + OWL_I2C_REG_RXDAT); + } + } else { + /* Handle the remaining bytes which were not sent */ + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { + writel(msg->buf[i2c_dev->msg_ptr++], + i2c_dev->base + OWL_I2C_REG_TXDAT); + } + } + +stop: + /* Clear pending interrupts */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, + OWL_I2C_STAT_IRQP, true); + + complete_all(&i2c_dev->msg_complete); + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + return IRQ_HANDLED; +} + +static u32 owl_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + unsigned long timeout; + + /* Check for Bus busy */ + timeout = jiffies + OWL_I2C_TIMEOUT; + while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { + if (time_after(jiffies, timeout)) { + dev_err(&adap->dev, "Bus busy timeout\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + struct i2c_msg *msg; + unsigned long time_left, flags; + unsigned int i2c_cmd, val; + unsigned int addr; + int ret, idx; + + spin_lock_irqsave(&i2c_dev->lock, flags); + + /* Reset I2C controller */ + owl_i2c_reset(i2c_dev); + + /* Set bus frequency */ + owl_i2c_set_freq(i2c_dev); + + /* + * Spinlock should be released before calling reset FIFO and + * bus busy check since those functions may sleep + */ + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + /* Reset FIFO */ + ret = owl_i2c_reset_fifo(i2c_dev); + if (ret) + goto unlocked_err_exit; + + /* Check for bus busy */ + ret = owl_i2c_check_bus_busy(adap); + if (ret) + goto unlocked_err_exit; + + spin_lock_irqsave(&i2c_dev->lock, flags); + + /* Check for Arbitration lost */ + val = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (val & OWL_I2C_STAT_LAB) { + val &= ~OWL_I2C_STAT_LAB; + writel(val, i2c_dev->base + OWL_I2C_REG_STAT); + ret = -EAGAIN; + goto err_exit; + } + + reinit_completion(&i2c_dev->msg_complete); + + /* Enable I2C controller interrupt */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_IRQE, true); + + /* + * Select: FIFO enable, Master mode, Stop enable, Data count enable, + * Send start bit + */ + i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | + OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; + + /* Handle repeated start condition */ + if (num > 1) { + /* Set internal address length and enable repeated start */ + i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | + OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; + + /* Write slave address */ + addr = i2c_8bit_addr_from_msg(&msgs[0]); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + /* Write internal register address */ + for (idx = 0; idx < msgs[0].len; idx++) + writel(msgs[0].buf[idx], + i2c_dev->base + OWL_I2C_REG_TXDAT); + + msg = &msgs[1]; + } else { + /* Set address length */ + i2c_cmd |= OWL_I2C_CMD_AS(1); + msg = &msgs[0]; + } + + i2c_dev->msg = msg; + i2c_dev->msg_ptr = 0; + + /* Set data count for the message */ + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); + + addr = i2c_8bit_addr_from_msg(msg); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + if (!(msg->flags & I2C_M_RD)) { + /* Write data to FIFO */ + for (idx = 0; idx < msg->len; idx++) { + /* Check for FIFO full */ + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_TFF) + break; + + writel(msg->buf[idx], + i2c_dev->base + OWL_I2C_REG_TXDAT); + } + + i2c_dev->msg_ptr = idx; + } + + /* Ignore the NACK if needed */ + if (msg->flags & I2C_M_IGNORE_NAK) + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, true); + else + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, false); + + /* Start the transfer */ + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); + + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, + adap->timeout); + + spin_lock_irqsave(&i2c_dev->lock, flags); + if (time_left == 0) { + dev_err(&adap->dev, "Transaction timed out\n"); + /* Send stop condition and release the bus */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, + true); + ret = -ETIMEDOUT; + goto err_exit; + } + + /* + * Here, -ENXIO will be returned if interrupt occurred but no + * read or write happened. Else if msg_ptr equals to message length, + * message count will be returned. + */ + ret = i2c_dev->msg_ptr == msg->len ? num : -ENXIO; + +err_exit: + spin_unlock_irqrestore(&i2c_dev->lock, flags); + +unlocked_err_exit: + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + + return ret; +} + +static const struct i2c_algorithm owl_i2c_algorithm = { + .master_xfer = owl_i2c_master_xfer, + .functionality = owl_i2c_func, +}; + +static const struct i2c_adapter_quirks owl_i2c_quirks = { + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, + .max_read_len = 240, + .max_write_len = 240, + .max_comb_1st_msg_len = 6, + .max_comb_2nd_msg_len = 240, +}; + +static int owl_i2c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct owl_i2c_dev *i2c_dev; + struct resource *res; + int ret, irq; + + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get IRQ number\n"); + return irq; + } + + if (of_property_read_u32(dev->of_node, "clock-frequency", + &i2c_dev->bus_freq)) + i2c_dev->bus_freq = OWL_I2C_DEF_SPEED_HZ; + + /* We support only frequencies of 100k and 400k for now */ + if (i2c_dev->bus_freq != OWL_I2C_DEF_SPEED_HZ && + i2c_dev->bus_freq != OWL_I2C_MAX_SPEED_HZ) { + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) + return ret; + + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); + if (!i2c_dev->clk_rate) { + dev_err(dev, "input clock rate should not be zero\n"); + ret = -EINVAL; + goto disable_clk; + } + + init_completion(&i2c_dev->msg_complete); + spin_lock_init(&i2c_dev->lock); + i2c_dev->adap.owner = THIS_MODULE; + i2c_dev->adap.algo = &owl_i2c_algorithm; + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; + i2c_dev->adap.quirks = &owl_i2c_quirks; + i2c_dev->adap.dev.parent = dev; + i2c_dev->adap.dev.of_node = dev->of_node; + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), + "%s", "OWL I2C adapter"); + i2c_set_adapdata(&i2c_dev->adap, i2c_dev); + + platform_set_drvdata(pdev, i2c_dev); + + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, + i2c_dev); + if (ret) { + dev_err(dev, "failed to request irq %d\n", irq); + goto disable_clk; + } + + return i2c_add_adapter(&i2c_dev->adap); + +disable_clk: + clk_disable_unprepare(i2c_dev->clk); + + return ret; +} + +static const struct of_device_id owl_i2c_of_match[] = { + { .compatible = "actions,s900-i2c" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_i2c_of_match); + +static struct platform_driver owl_i2c_driver = { + .probe = owl_i2c_probe, + .driver = { + .name = "owl-i2c", + .of_match_table = of_match_ptr(owl_i2c_of_match), + }, +}; +module_platform_driver(owl_i2c_driver); + +MODULE_AUTHOR("David Liu "); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jul 26 15:46:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 142987 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp616849ljj; Thu, 26 Jul 2018 08:47:36 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfestf5GA06OkIf97eT3iyBgIDwKa+CTneDThOW95Aqq/SDnoEZLnKcRPIsOh+5tYXsSn+O X-Received: by 2002:a62:3b03:: with SMTP id i3-v6mr2632147pfa.197.1532620056615; Thu, 26 Jul 2018 08:47:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532620056; cv=none; d=google.com; s=arc-20160816; b=dF2lr84aoA7vrrpIQCq8Bc1HMqAqjZ2TlxtJ+EFXf/yK6UlqRBTyDlBPAkYT2FKm3J atMH2wPvI6cUg5NCrM9n6OZz8XVwsgTHCh4rCEp7ej6xipRqJYc3TjBKSOSA/zaqSkAh 7Hl4ZCNPOCxN7PQ7fUosWrUJlid09fG/i68cZZJns6iuIkRsv2k/imNalz/FKQCz/fnR Cwf3WAv6zJQUB4q9eRRv44JUvGQd+d+iQaABY0uyH6WeyEv93hLidtDUMpmLon0KVaFV u+/sA6+TYTRbOkIavB9BqYojWOSOHhuqHc1wfJLg8lkT7rSAzWSVQaoKTM34/TEfYlTG s9vg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id k22-v6si1398290pll.118.2018.07.26.08.47.36; Thu, 26 Jul 2018 08:47:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JnK364Fg; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732037AbeGZRFA (ORCPT + 5 others); Thu, 26 Jul 2018 13:05:00 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:40735 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732035AbeGZRFA (ORCPT ); Thu, 26 Jul 2018 13:05:00 -0400 Received: by mail-pl0-f67.google.com with SMTP id s17-v6so1004655plp.7 for ; Thu, 26 Jul 2018 08:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/b+N2DvOUUyA2A2wTJ+2C32b3lKHmvgv0TH8hNrLKeQ=; b=JnK364FgCcvwl1hRoUw22bKaVzouoAVfQkln9dZo+3L7/CGrynFIZ9t06FSi6p2MBG 7Z0ZjxSKmaweMpB87jx2J6qDT4XDWSumFzpzciNKMsFuLU+p/JtQz+I5O6EvJ9SAipT8 gPnt2b2/B9vcW8/G/PPc1VK3brEDimfXG0xhQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/b+N2DvOUUyA2A2wTJ+2C32b3lKHmvgv0TH8hNrLKeQ=; b=uZbIyh2tVeQAq2nMLlZA4bhVfR9UXjKwMo13zzdvZSpKZKOLK8aPi+c0RIPB3Z/haE vh6SHsGpn3SFeGVHnb/e9EPQtlMa2NsPAvEHJRn3WxoBvTeAARjtlR+8ytYp0O6qz/tS HM/CjjaiFGhfLLJIzI/v5+lO9R5C2pXlWh1f70sOnyH/dgf6gRE1xRFux71aFOxT3NLa myYP6PMT+COXcJKWwrEqqFsoBRWnnKMHGNCxKZ/VDUO2lkXMdgn9QUMybjkDpFs1Idk6 rYdEfX/azt71+uxM3JUXdVYoVx6id751wd74YDTBIR+UL1GlFvrXe9uIM1n1Su/fhjox H0Ow== X-Gm-Message-State: AOUpUlEDt6WhYfAYALZfcAMeqiW6zzfXQbU/9St9/9oeYdTPGGi8fDRm eSP9VAUz9ikM8WtQDeTukANv X-Received: by 2002:a17:902:1566:: with SMTP id b35-v6mr2437438plh.135.1532620055163; Thu, 26 Jul 2018 08:47:35 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:628e:aef6:6d51:3501:dada:e06d]) by smtp.gmail.com with ESMTPSA id z11-v6sm3755322pff.162.2018.07.26.08.47.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jul 2018 08:47:34 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v7 6/6] MAINTAINERS: Add entry for Actions Semiconductor Owl I2C driver Date: Thu, 26 Jul 2018 21:16:03 +0530 Message-Id: <20180726154603.5089-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> References: <20180726154603.5089-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add entry for Actions Semiconductor Owl I2C driver under ARM/ACTIONS Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/MAINTAINERS b/MAINTAINERS index 09b54e9ebc6f..5084c62712fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1145,12 +1145,14 @@ F: arch/arm/boot/dts/owl-* F: arch/arm64/boot/dts/actions/ F: drivers/clk/actions/ F: drivers/clocksource/owl-* +F: drivers/i2c/busses/i2c-owl.c F: drivers/pinctrl/actions/* F: drivers/soc/actions/ F: include/dt-bindings/power/owl-* F: include/linux/soc/actions/ F: Documentation/devicetree/bindings/arm/actions.txt F: Documentation/devicetree/bindings/clock/actions,s900-cmu.txt +F: Documentation/devicetree/bindings/i2c/i2c-owl.txt F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt