From patchwork Tue May 9 19:47:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 98953 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1991544qge; Tue, 9 May 2017 12:47:52 -0700 (PDT) X-Received: by 10.98.35.142 with SMTP id q14mr1821277pfj.220.1494359272689; Tue, 09 May 2017 12:47:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494359272; cv=none; d=google.com; s=arc-20160816; b=sYNRFQr42l3R4BFuS0TMPb5X/jqZ33UhAcKyPWCPJLfGG8lmzEQhxXp1AWbA0SaFtj E7jAVNw4oQskD5SPdGyJ7c2VrhrooBQZ9iwpytykGTKrt3eppbrugD0Bl3Z5UpCTqFxh 0gSlZqF3gipscAtno2Fp9V/z2fbgHIEiTWfXf6AaScC0kvldDxWyMnEXW1z5zEHh8BUl 2bkccH+UScpFBJmrMt0DyFfHnmLyWyGJiaCzJXTi3+kmRjLq/qYHN5c48hNEL8A6VtWw CMC+m8oTdIZoZam5gS85SYc0+dvO1M+dZSkQsVvwmzH/sFtz1ULFg/TiJRzDzP3ohwFq o/ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=VdVgYiMDlaG19GWomrYqtTrsNb9OKiW7YlA1zi0/BP4=; b=P+QF+Ivcgkb5d/9YjMVtlmdn85UtBauNBw9H8XWfJnpyNBDBpLnFi+wVl1KGZUaF0/ CIVEw6+HxhhMUsraI8iTCcSaPychtpVTjiFQnJaNHOYAN7sjx/RfOeaD39RgVRWfee7p n8n0IXvwLccr0bMF9fFqDWNsunS0DQR2TS4osbiJzhi8Vgvr46F//NBRrkDm/IVFxl9P yQ4ap6G2eDpRFUQMApf6ajTZprshAxLcBJcvqKqH4j95tz/12ckltV7F1r1pvh0RpJ1c x/BZB3O3edC3YrQiqZ/Kvt6g2Q54J4jGJffbSaXfgND+9PIVZex9IS6U5M5udRU708jA Ui2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id x2sm1279236pfi.80.2017.05.09.12.47.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 12:47:07 -0700 (PDT) From: Bjorn Andersson To: Jassi Brar Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: [PATCH v6 2/4] mailbox: Support stateless mailboxes without txdone Date: Tue, 9 May 2017 12:47:01 -0700 Message-Id: <20170509194703.28871-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170509194703.28871-1-bjorn.andersson@linaro.org> References: <20170509194703.28871-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For some types of doorbell-like mailbox hardware there is no mechanism for delivery notification and the only possible message is an identity element; i.e. the mailbox is stateless and writing any number of messages to the mailbox is equivalent to writing a single message. Support this type of mailbox hardware by introducing the "none" tx done method, which means that neither the hardware nor the client is expected to tick the mailbox state machine. Signed-off-by: Bjorn Andersson --- Changes since v5: - New patch drivers/mailbox/mailbox.c | 2 ++ drivers/mailbox/mailbox.h | 1 + include/linux/mailbox_controller.h | 2 ++ 3 files changed, 5 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c index 505651ce9dcc..bf224c7c8f58 100644 --- a/drivers/mailbox/mailbox.c +++ b/drivers/mailbox/mailbox.c @@ -453,6 +453,8 @@ int mbox_controller_register(struct mbox_controller *mbox) txdone = TXDONE_BY_IRQ; else if (mbox->txdone_poll) txdone = TXDONE_BY_POLL; + else if (mbox->txdone_none) + txdone = TXDONE_NONE; else /* It has to be ACK then */ txdone = TXDONE_BY_ACK; diff --git a/drivers/mailbox/mailbox.h b/drivers/mailbox/mailbox.h index 456ba68513bb..708c8bb822fe 100644 --- a/drivers/mailbox/mailbox.h +++ b/drivers/mailbox/mailbox.h @@ -7,6 +7,7 @@ #ifndef __MAILBOX_H #define __MAILBOX_H +#define TXDONE_NONE 0 /* mailbox provides no means of flow control */ #define TXDONE_BY_IRQ BIT(0) /* controller has remote RTR irq */ #define TXDONE_BY_POLL BIT(1) /* controller can read status of last TX */ #define TXDONE_BY_ACK BIT(2) /* S/W ACK recevied by Client ticks the TX */ diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h index 74deadb42d76..43fa4ab9b3e1 100644 --- a/include/linux/mailbox_controller.h +++ b/include/linux/mailbox_controller.h @@ -58,6 +58,7 @@ struct mbox_chan_ops { * @ops: Operators that work on each communication chan * @chans: Array of channels * @num_chans: Number of channels in the 'chans' array. + * @txdone_none: The controller has no sense of TX done * @txdone_irq: Indicates if the controller can report to API when * the last transmitted data was read by the remote. * Eg, if it has some TX ACK irq. @@ -78,6 +79,7 @@ struct mbox_controller { int num_chans; bool txdone_irq; bool txdone_poll; + bool txdone_none; unsigned txpoll_period; struct mbox_chan *(*of_xlate)(struct mbox_controller *mbox, const struct of_phandle_args *sp); From patchwork Tue May 9 19:47:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 98952 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1991506qge; Tue, 9 May 2017 12:47:46 -0700 (PDT) X-Received: by 10.98.49.195 with SMTP id x186mr1836622pfx.148.1494359266257; Tue, 09 May 2017 12:47:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494359266; cv=none; d=google.com; s=arc-20160816; b=ZjfY89yFS5UBXCxpYJlN1o7A/U2kaIMDbH7vwi7iHPBpv+Zj7yvKBtSSB80/gNGA3J v01/xANNIDBWDHImxshFiBv3HMM3YaF4+iEQuR/K3ali1Moi2nCv/QuOjU9gNaSMhRj/ De+zBBPBCw2lc3gXn2fTPZyzKf0zWoTfwO9XX4i/B26FTyM49E5XSGDsMzwEClSap9PZ Ype+lis+0geu3uANCuSQsQeB+zhD7RWhOsNs06zzJw6XLkpQzqDLqR6vugV8rceUQXCf LAWyIIohx0zm+u5Z9LOT+Ld86t+8WquYFIryu2Rla6XQTRQNNpFZePvUaeQfIsBsO7h+ coRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=L6XDwpfEU17jGXkJJA1Z7R1QMwV9GP4Nr7CKy4oTO38=; b=TJoXCVQcHs2Li3MEogJMQsxDdeLh93l/Kf3cMuPy9lV4bKRWojQTRheHizwN2dEHaO WRpEyOCizPwhcH+IyklgoQsVvhdHeDB3k0agxJp1Oe5bvNGHag9lPZ8KKXUCZhQmOoTJ RBzNwCuSdTMmmEg8+RSEwySeksOHZl0VWDxBmX/MOsQAPwcZ4Bhq6oEsYV4LijpX8WWC 1hR582wm2tkHuMQFJMlpvKsLEFdz1PJKcRyZTnO087ZDYMSHOZGdAENhHS8+ara8OmnS 9+fGHa44jv81pDOSDI05j5cTtUsN+Mw6N+Qdb5wakxaEmbhEbpAqZ18dM353WzLUio2C iQog== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id x2sm1279236pfi.80.2017.05.09.12.47.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 12:47:08 -0700 (PDT) From: Bjorn Andersson To: Rob Herring , Mark Rutland , Jassi Brar Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: [PATCH v6 3/4] dt-bindings: mailbox: Introduce Qualcomm APCS global binding Date: Tue, 9 May 2017 12:47:02 -0700 Message-Id: <20170509194703.28871-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170509194703.28871-1-bjorn.andersson@linaro.org> References: <20170509194703.28871-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce a binding for the Qualcomm APCS global block, exposing a mailbox for invoking interrupts on remote processors in the system. Signed-off-by: Bjorn Andersson --- Changes since v5: - None .../bindings/mailbox/qcom,apcs-kpss-global.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt new file mode 100644 index 000000000000..eaa9e780f412 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -0,0 +1,46 @@ +Binding for the Qualcomm APCS global block +========================================== + +This binding describes the APCS "global" block found in various Qualcomm +platforms. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,msm8916-apcs-kpss-global", + "qcom,msm8996-apcs-hmss-global" + +- reg: + Usage: required + Value type: + Definition: must specify the base address and size of the global block + +- #mbox-cells: + Usage: required + Value type: + Definition: as described in mailbox.txt, must be 1 + + += EXAMPLE +The following example describes the APCS HMSS found in MSM8996 and part of the +GLINK RPM referencing the "rpm_hlos" doorbell therein. + + apcs_glb: mailbox@9820000 { + compatible = "qcom,msm8996-apcs-hmss-global"; + reg = <0x9820000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + mboxes = <&apcs_glb 0>; + mbox-names = "rpm_hlos"; + }; + From patchwork Tue May 9 19:47:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 98951 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1991414qge; Tue, 9 May 2017 12:47:31 -0700 (PDT) X-Received: by 10.99.224.69 with SMTP id n5mr1983017pgj.113.1494359251451; Tue, 09 May 2017 12:47:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494359251; cv=none; d=google.com; s=arc-20160816; b=qT8hUBq1VGxNg1fWtZgP7dtG9EENPSqOAjw6g4LUZT02Vodej99FTcfBce4u90Ylen FgVT7V6BA6VrVZET8sDh9Nf5cuUgdAMhhTAMB48qBLA82ThLZeFqfslpHYOKPELwIrsb dLTydYZTEyxu42BE5K0UoiE9Bfn8WDqeZH4V29s7ksBJiMCi7FqgHsEZtXNK6fX2nIZv D0zRbzku7V6YAPmYbLORd4awrRb2Dv12db0VSYC07B54tu6NpK6JMWMz2sNE+fMZr71l mpuDDPtSF3jcbNdUlgxP9/xVJWlffjoX5kWYnZQ2s6My0fpIxuzSB9Kfx1nIbQtH6rIy dsYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mSJZ97mfV9woetYnIHeSzXymlPyscWDOlJvCqNLdn3w=; b=wVbh9w8pTyxwA/FVmcyzpQ6I/QM47H9VIv/PD8UHNAKpPSAuQ/PGeHmSt3rnJ5VCrZ yTZYTFkbTvkjcvnIftnfuiMTk5EwTL5raifpfTM8gjLzlEpXua6rfbGEJEtrfx4uwr0a Kf9JGhH69enjdgDr7yQxXDd8KYycMY4pNaBcFYD4D9PJjvnUyI3zRujp2W/zCLyulsVD 3brLpyjqDkBc2jrQjKrKeQ8NefH2O2RwwlES0lBvxvVFmCYXOYg8lULUR4BtI/ZeZsfX zkSnokdHIJdvC3x9hZ216OPlpDfO7tUT5yroTu5BmS+bNAbPzP1Bmg6qlM/OJRA8cPGO 7BCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[68.111.223.48]) by smtp.gmail.com with ESMTPSA id x2sm1279236pfi.80.2017.05.09.12.47.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 May 2017 12:47:10 -0700 (PDT) From: Bjorn Andersson To: Jassi Brar Cc: Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: [PATCH v6 4/4] mailbox: Introduce Qualcomm APCS IPC driver Date: Tue, 9 May 2017 12:47:03 -0700 Message-Id: <20170509194703.28871-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170509194703.28871-1-bjorn.andersson@linaro.org> References: <20170509194703.28871-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This implements a driver that exposes the IPC bits found in the APCS Global block in various Qualcomm platforms. The bits are used to signal inter-processor communication signals from the application CPU to other masters. Signed-off-by: Bjorn Andersson --- Changes since v5: - Set txdone_none drivers/mailbox/Kconfig | 8 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 129 ++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/mailbox/qcom-apcs-ipc-mailbox.c -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index ceff415f201c..fffc64da61f9 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -124,6 +124,14 @@ config MAILBOX_TEST Test client to help with testing new Controller driver implementations. +config QCOM_APCS_IPC + tristate "Qualcomm APCS IPC driver" + depends on ARCH_QCOM + help + Say y here to enable support for the APCS IPC mailbox driver, + providing an interface for invoking the inter-process communication + signals from the application processor to other masters. + config TEGRA_HSP_MBOX bool "Tegra HSP (Hardware Synchronization Primitives) Driver" depends on ARCH_TEGRA_186_SOC diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 7dde4f609ae8..cc718c79669a 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -30,4 +30,6 @@ obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o +obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o + obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c new file mode 100644 index 000000000000..4dddf8627acc --- /dev/null +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2017, Linaro Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_APCS_IPC_BITS 32 + +struct qcom_apcs_ipc { + struct device *dev; + + struct mbox_controller mbox; + struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS]; + + void __iomem *base; + unsigned long offset; +}; + +static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data) +{ + struct qcom_apcs_ipc *apcs = container_of(chan->mbox, + struct qcom_apcs_ipc, mbox); + unsigned long idx = (unsigned long)chan->con_priv; + + writel(BIT(idx), apcs->base + apcs->offset); + + return 0; +} + +static const struct mbox_chan_ops qcom_apcs_ipc_ops = { + .send_data = qcom_apcs_ipc_send_data, +}; + +static int qcom_apcs_ipc_probe(struct platform_device *pdev) +{ + struct qcom_apcs_ipc *apcs; + struct resource *res; + unsigned long i; + int ret; + + apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL); + if (!apcs) + return -ENOMEM; + + apcs->dev = &pdev->dev; + apcs->offset = (unsigned long)of_device_get_match_data(&pdev->dev); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + apcs->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(apcs->base)) + return PTR_ERR(apcs->base); + + /* Initialize channel identifiers */ + for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++) + apcs->mbox_chans[i].con_priv = (void *)i; + + apcs->mbox.dev = &pdev->dev; + apcs->mbox.ops = &qcom_apcs_ipc_ops; + apcs->mbox.txdone_none = true; + apcs->mbox.chans = apcs->mbox_chans; + apcs->mbox.num_chans = ARRAY_SIZE(apcs->mbox_chans); + + ret = mbox_controller_register(&apcs->mbox); + if (ret) { + dev_err(&pdev->dev, "failed to register APCS IPC controller\n"); + return ret; + } + + platform_set_drvdata(pdev, apcs); + + return 0; +} + +static int qcom_apcs_ipc_remove(struct platform_device *pdev) +{ + struct qcom_apcs_ipc *apcs = platform_get_drvdata(pdev); + + mbox_controller_unregister(&apcs->mbox); + + return 0; +} + +/* .data is the offset of the ipc register within the global block */ +static const struct of_device_id qcom_apcs_ipc_of_match[] = { + { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 }, + { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match); + +static struct platform_driver qcom_apcs_ipc_driver = { + .probe = qcom_apcs_ipc_probe, + .remove = qcom_apcs_ipc_remove, + .driver = { + .name = "qcom_apcs_ipc", + .of_match_table = qcom_apcs_ipc_of_match, + }, +}; + +static int __init qcom_apcs_ipc_init(void) +{ + return platform_driver_register(&qcom_apcs_ipc_driver); +} +postcore_initcall(qcom_apcs_ipc_init); + +static void __exit qcom_apcs_ipc_exit(void) +{ + platform_driver_unregister(&qcom_apcs_ipc_driver); +} +module_exit(qcom_apcs_ipc_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm APCS IPC driver");