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[23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.42; Thu, 24 Jun 2021 07:57:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cykGp7ub; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbhFXPAA (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231194AbhFXPAA (ORCPT ); Thu, 24 Jun 2021 11:00:00 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BEE0C061756 for ; Thu, 24 Jun 2021 07:57:40 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id j4so10766201lfc.8 for ; Thu, 24 Jun 2021 07:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zdxuO3FXcMYXnxkLpZHy8crKZag9SkX+E8b620Ln9pw=; b=cykGp7ubjyVx8XXCI0fgrRViUFGxjm6cjAzX0svOBQMbugUbJivFvBvyN57aLUv1+S 4iUG6X23ACy2rtX2bKN3M7iFaopOh7h2MJhDkeYhseKGTBH6A4Fe1rUCqmFXKwqvA7H4 4PWbLJF2nECpLfDa94DcQCqbxZo2Q1t9UP1sur5sgYhPN5PI5tnU3DL/P7jmTuxDcQ1i XdztqWdsz2UyPgniZT0IRdNwEAb5Lt6ti2BvAhZc7QaHqetdRysMXMreyRJGAG+W1LY2 +G7kwRlcrSiQnsl9PE47939+Neyn8DLrf9/Flboc42u0VqIXE5oKSSIeQb66px1mCM3V UoFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zdxuO3FXcMYXnxkLpZHy8crKZag9SkX+E8b620Ln9pw=; b=STfDaWXJEzTFEB7F8m/HoAl0rSZq0hHG5wvNE5Z9WIhto8pWo9EyBbRKL8u7eNsxrO 4nDX3EddRz9cIE7cBxenwg7hTKn31x/IVnQ2QvD3olOJrCcyPWZUAAtslnBBAI0w0Gem ES0l25eHcHb17+lSwqcyDAQC9Altqy3SmgZCkgVrHfpkdrJpAzFp9ie3vqqrcqy/JGa5 knF7Jqd3Z1XaCcOPX62heGzupvjCLpipMtFgW94+OTA1NFRjL/aB+kMAZ8yLi5JrJKEl pF0b3N9Wq8pMRhtZWIiX03hIDDh1ok8bFGOwsv5U+whkVaA890qxVsvs/J/HGmiy4uUs W2qQ== X-Gm-Message-State: AOAM531GYty3kv/Uy9ZlVXB3+PJIwWdYoHfJsQWT6U4eIgXiz7QBs6xg YdrK1wEgKaT953EyW/dAEmWI9Q== X-Received: by 2002:ac2:597a:: with SMTP id h26mr4194874lfp.406.1624546658871; Thu, 24 Jun 2021 07:57:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:38 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 01/17] drm/msm/dpu: move LUT levels out of QOS config Date: Thu, 24 Jun 2021 17:57:17 +0300 Message-Id: <20210624145733.2561992-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org LUT levels are setup outside of setup_qos_ctrl, so remove them from the struct dpu_hw_pipe_qos_cfg. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 15 ++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++++----------- 3 files changed, 20 insertions(+), 28 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 69eed7932486..cbafb61404d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -569,19 +569,20 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum } static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg) + u32 danger_lut, + u32 safe_lut) { u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, danger_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); } static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg) + u64 creq_lut) { u32 idx; @@ -589,11 +590,11 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, return; if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, creq_lut); DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx, - cfg->creq_lut >> 32); + creq_lut >> 32); } else { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); + DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, creq_lut); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index fdfd4b46e2c6..27263bc1a1ef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -166,18 +166,12 @@ struct dpu_hw_pipe_cfg { /** * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration - * @danger_lut: LUT for generate danger level based on fill level - * @safe_lut: LUT for generate safe level based on fill level - * @creq_lut: LUT for generate creq level based on fill level * @creq_vblank: creq value generated to vbif during vertical blanking * @danger_vblank: danger value generated during vertical blanking * @vblank_en: enable creq_vblank and danger_vblank during vblank * @danger_safe_en: enable danger safe generation */ struct dpu_hw_pipe_qos_cfg { - u32 danger_lut; - u32 safe_lut; - u64 creq_lut; u32 creq_vblank; u32 danger_vblank; bool vblank_en; @@ -302,20 +296,22 @@ struct dpu_hw_sspp_ops { /** * setup_danger_safe_lut - setup danger safe LUTs * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe QoS configuration + * @danger_lut: LUT for generate danger level based on fill level + * @safe_lut: LUT for generate safe level based on fill level * */ void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg); + u32 danger_lut, + u32 safe_lut); /** * setup_creq_lut - setup CREQ LUT * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe QoS configuration + * @creq_lut: LUT for generate creq level based on fill level * */ void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_qos_cfg *cfg); + u64 creq_lut); /** * setup_qos_ctrl - setup QoS control diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ec4a6f04394a..1e2c53a3f47b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -348,8 +348,6 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, qos_lut = _dpu_plane_get_qos_lut( &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); - pdpu->pipe_qos_cfg.creq_lut = qos_lut; - trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); @@ -359,7 +357,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, &pdpu->pipe_qos_cfg); + pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); } /** @@ -397,24 +395,21 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, } } - pdpu->pipe_qos_cfg.danger_lut = danger_lut; - pdpu->pipe_qos_cfg.safe_lut = safe_lut; - trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, (fmt) ? fmt->fetch_mode : 0, - pdpu->pipe_qos_cfg.danger_lut, - pdpu->pipe_qos_cfg.safe_lut); + danger_lut, + safe_lut); DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, fmt ? fmt->fetch_mode : -1, - pdpu->pipe_qos_cfg.danger_lut, - pdpu->pipe_qos_cfg.safe_lut); + danger_lut, + safe_lut); pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, - &pdpu->pipe_qos_cfg); + danger_lut, safe_lut); } /** From patchwork Thu Jun 24 14:57:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466350 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536753jao; Thu, 24 Jun 2021 07:57:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzcH5+2J3GHHhGxUdLSMy8GFktCn6CSZB59qbN0TuRQvs2Btrg52eU/blXyVzGXaW9NPn1b X-Received: by 2002:a92:c0cc:: with SMTP id t12mr3965707ilf.177.1624546663799; Thu, 24 Jun 2021 07:57:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546663; cv=none; d=google.com; s=arc-20160816; b=KOq/ZUcaGJuofxPkmRZadAHSL3Py43lBxLGlyICdd7wpLEb/DyEw0LOsp9kPMhOhEw M1goxI9HlAOE27dTf4fm4wfCRB7RUl7YiLmRLYj63c3+6e7bTgusUUIIe9RRlg2g+85K Gu4w6xAOTAfk3Ldd9sNWpH1NMY+pyqZU2jIhadS6MSqPpKF27xjI0sxX9TW4YFy3KyF6 rBeTFChBDYfdY/rax3Gw6Ip8iiF4B6xPeO2Y8y2r91fYcGMpXB+aVKyrtiRVXGxHNh2r JX9XNioOUcqnmauUfssCe6MQ022v6wsCIQtY7h5u7SGtMY5SlYLFyOKe+R4nMUbuTpD1 DlRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TUMTyMrUgUh3fG+Mf/N14gZsUnvHUSJ7GKGw9bXuGME=; b=0u0zgfFoMh1LU6M/VSzM6dYADik78SzwMSqQnntg5rED7I1n8v4prZ63U1vh0KB6Rx T+3GkQ0V4VV0TW0qwVwwHghMlGE5uTpree91Qdy4JNmfYxQ6Vu5HijyOK1IZH86OM+08 zqXvWn4ENLIFLiO0iVv07StXYeMUCEuplWcMt32mDXx5+XQc7WsQccehqkG4+dS0utDQ iFW4ToQ+f/CljvAJEaxWjRFEsckeYhzWt5GI7I+415KOmce+L6/EBrdw5bHR4lHRlqvV +4ihpY5EYuwna5y2zBdhdSTfgYNdl0Rwgoorjhe3Pw71amm4infkGQ9j9LW1FDsJ6hna xUWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H+vdYyPB; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++++++----------- 1 file changed, 16 insertions(+), 14 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 1e2c53a3f47b..20ff1832c958 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -105,7 +105,6 @@ struct dpu_plane { struct dpu_hw_pipe *pipe_hw; struct dpu_hw_pipe_cfg pipe_cfg; - struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -422,38 +421,41 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; + + memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; - pdpu->pipe_qos_cfg.danger_vblank = + pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; + pipe_qos_cfg.danger_vblank = pdpu->pipe_sblk->danger_vblank; - pdpu->pipe_qos_cfg.vblank_en = enable; + pipe_qos_cfg.vblank_en = enable; } if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { /* this feature overrules previous VBLANK_CTRL */ - pdpu->pipe_qos_cfg.vblank_en = false; - pdpu->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ + pipe_qos_cfg.vblank_en = false; + pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ } if (flags & DPU_PLANE_QOS_PANIC_CTRL) - pdpu->pipe_qos_cfg.danger_safe_en = enable; + pipe_qos_cfg.danger_safe_en = enable; if (!pdpu->is_rt_pipe) { - pdpu->pipe_qos_cfg.vblank_en = false; - pdpu->pipe_qos_cfg.danger_safe_en = false; + pipe_qos_cfg.vblank_en = false; + pipe_qos_cfg.danger_safe_en = false; } DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", pdpu->pipe - SSPP_VIG0, - pdpu->pipe_qos_cfg.danger_safe_en, - pdpu->pipe_qos_cfg.vblank_en, - pdpu->pipe_qos_cfg.creq_vblank, - pdpu->pipe_qos_cfg.danger_vblank, + pipe_qos_cfg.danger_safe_en, + pipe_qos_cfg.vblank_en, + pipe_qos_cfg.creq_vblank, + pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, - &pdpu->pipe_qos_cfg); + &pipe_qos_cfg); } /** From patchwork Thu Jun 24 14:57:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466352 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536780jao; Thu, 24 Jun 2021 07:57:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzLTI1O9B2H0FMbNtDbiircA/ohKoVoED+TRICB5AiCeAcLF8/3K3qkN2tGG0nu1kEgusCP X-Received: by 2002:a92:d942:: with SMTP id l2mr3923071ilq.107.1624546665497; Thu, 24 Jun 2021 07:57:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546665; cv=none; d=google.com; s=arc-20160816; b=gl/BOSy6lDEB76eNfLEiHh4IDQPlvPd+1SS0pkj5ZX9XDsyPEec46XfG5lkAO0UYbN /NGj+KSFfQ5V3KZa4Aw9OLGhUhCkvdkIykA9VBKaRX3MqXYNHoC7YzK0+3vYrlLMRoEh eDfxadsBd5fc8GGCZwc80RTnMg8IB1mtbFa3uaMMwB1NI/qppKTL1W0HwZr1mW6vT7sv HKbsyrJoCAtUrRY9oQNNxWFHssWVBY6ZvQAKdYmaZMUCZdhbsg7z3Dr/IUHPUGyVBb/r iQRL/2qyRzsCodwDhWBi6HnMG37yR9O5Lr1P3nB5eGKHQ2rAz5XyTcRgwYS3+DLAvG7O ncmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GdDMjhCpUMomtdmjludjL5DxnUY1JT83cC3CTovzo2Y=; b=N34X82GLZ/5XL7NvkpJfeAME0ShWGHCpFcetal24I8Ku+cyXAFI4g2UVG/UOluinkc lYLGl+1QJ9LOtP4oEi+SgU02RUUBYR4eAvzYeAIefT0PqVpe6xszPx7eCyhN5G9aFK6X dEQDyTGGb22o0u3HCeDbGPlvVru65B8lJcY7Ch6rU6nwIIVbimyT5otnzDbPH9p3pglC U/JuyuaAwdBoxULIsjEa0hOjUwegZVuN+o8Q6Gu7Vs8Hynu9MVkdOZPDdYhfy7ADTtaW AmpDDS2//ERJaLmbdfvSLUh2ejnaQAaKMjLK4chWkOzRzsNQZIvkVI7lG3cx3J5EsDcL wCTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zRkE9OGf; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 20ff1832c958..97507e25f4f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -115,7 +115,6 @@ struct dpu_plane { struct dpu_csc_cfg *csc_ptr; const struct dpu_sspp_sub_blks *pipe_sblk; - char pipe_name[DPU_NAME_SIZE]; /* debugfs related stuff */ struct dentry *debugfs_root; @@ -1431,7 +1430,7 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane) /* create overall sub-directory for the pipe */ pdpu->debugfs_root = - debugfs_create_dir(pdpu->pipe_name, + debugfs_create_dir(plane->name, plane->dev->primary->debugfs_root); /* don't error check these */ @@ -1656,12 +1655,9 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, /* success! finalize initialization */ drm_plane_helper_add(plane, &dpu_plane_helper_funcs); - /* save user friendly pipe name for later */ - snprintf(pdpu->pipe_name, DPU_NAME_SIZE, "plane%u", plane->base.id); - mutex_init(&pdpu->lock); - DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, + DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name, pipe, plane->base.id, master_plane_id); return plane; From patchwork Thu Jun 24 14:57:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466351 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536768jao; Thu, 24 Jun 2021 07:57:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1qyRP9BmT0WDZuMzZPLzk9/rGWZAnlXiCDd/kjm3TSh5fXQDSLXEUj1Sis7jvUEbFXgsc X-Received: by 2002:a92:1942:: with SMTP id e2mr4099335ilm.4.1624546664762; Thu, 24 Jun 2021 07:57:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546664; cv=none; d=google.com; s=arc-20160816; b=VGVgJkTxmPQEjVfRMGkt36tqH21/6EEXSe6zdNdMFNRQyLEKmKF/zloQNfW0T/kI5G wDfWs7jwQ0jPF70YrdTdt1v70XRVSBVSQ+3rRR0601Q1adHMCvMVMP5/ry24qICWtuDO c8SuvypxnVn/zEsd6TyHU+yApor/F3Hr4AEb0UAgVRpdOipoYdfTXZUi80t7V9CelNmZ 0kCdJq++MA0gpE2t5AOcSC5SjeqJu7AQlEoN1Rit03envYDeYTdMqkJlYjPyq94j1TOQ 7Pjj0kl50H6BS1MZQJMM45SbLEBdItTCllTaDvIasDFAKyhX6Bqz0e9LPyjB6ugWrGsA ArdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uKeS2D6NI+nwzdlSN/CbA1/E6G9yn+fxXMAvAL8n5i8=; b=Kp8ZOtDdqg90e0s1BFKqrVRGhDWLjmNxOnrzizyMVQD88s8S49WLeoR8Lz6mzd4y8o 3yVnrgbBv3x22Zt6iYrndMzNzFvRIwfhxGcRtt/JbeEy2SKLDWzQ+5idZ3Erid5Wa4CR ObxfPFMBLabNc1L2jeuGhwsP/DwMOS9tgg3WpvWc0Fhd5NxJ+LPtvkdcMWvvW2/iEdsV Z47foSoLJ9EroyIfUp46Gdpv/axLDSBnADE78K9Djr3bG/DCTan+z2BrtkK5Yy0pZmfY ds4+xIk4meftHY+/5XnaaaXGGBpnNywhkU7dEbW6e9tNkfnt4/Z0tErxnVJw4fH1949T vAng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o9bVyES5; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 -- 2 files changed, 6 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9a5c70c87cc8..ea678ddd4589 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -190,7 +190,8 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) } static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, - struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer) + struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, + struct dpu_hw_stage_cfg *stage_cfg) { struct drm_plane *plane; struct drm_framebuffer *fb; @@ -199,7 +200,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_plane_state *pstate = NULL; struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg; u32 flush_mask; uint32_t stage_idx, lm_idx; @@ -275,6 +275,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer = cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; + struct dpu_hw_stage_cfg stage_cfg; int i; DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -288,9 +289,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } /* initialize stage cfg */ - memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); for (i = 0; i < cstate->num_mixers; i++) { ctl = mixer[i].lm_ctl; @@ -311,7 +312,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].flush_mask); ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &dpu_crtc->stage_cfg); + &stage_cfg); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index cec3474340e8..30535acec670 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -116,7 +116,6 @@ struct dpu_crtc_frame_event { * @drm_requested_vblank : Whether vblanks have been enabled in the encoder * @property_info : Opaque structure for generic property support * @property_defaults : Array of default values for generic property support - * @stage_cfg : H/w mixer stage configuration * @debugfs_root : Parent of debugfs node * @vblank_cb_count : count of vblank callback since last reset * @play_count : frame count between crtc enable and disable @@ -147,7 +146,6 @@ struct dpu_crtc { struct drm_pending_vblank_event *event; u32 vsync_count; - struct dpu_hw_stage_cfg stage_cfg; struct dentry *debugfs_root; u32 vblank_cb_count; From patchwork Thu Jun 24 14:57:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466353 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536792jao; Thu, 24 Jun 2021 07:57:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxcnvGdncPVYVe8xL180a6z7v8H4xtsBegncv6Uik4W+t/FRmrjbr2Pccn9L6oFHThKJBZ6 X-Received: by 2002:a05:6e02:1a62:: with SMTP id w2mr3942053ilv.217.1624546666201; Thu, 24 Jun 2021 07:57:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546666; cv=none; d=google.com; s=arc-20160816; b=ya9VeLM5YAV2VzSjzH+elFBjRg2XJfkxwFlzFyThaEBpwn1GVZ9de0vHrjHVQGQgm5 kkckRoVFZ5oHQ1nU4pOYsbvck502ZBjtc/wIFmCn7BOMWBWrDJO/K9Gkqs+UmNYcuO8M l74VpAbBByScc6CHcY6MfxP53G2KUMvTpdFXChHeCcg7NYc0QzT18bqg/mxjWmY+Q+9l AtyXY+nFVGwAqUVzLQLoeAO+FolDSge2Cj6jGjvbes2i5ud+dNEIiJ0l0Gzy2kinP2e1 Velmd6jN9wffQcxq3e5PM8ZNhUI3AwdNarTNfgxkqMZ6LU50zUTmVlz4L0xNepcCYmM+ Jehw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KwCX2sP+0U2a5GatYHIEUMkfFfS/xQl+/uAE4M8pDy8=; b=Bk4GXCVr7qtiBriw+rQR5ZbKdwMPuc5ErG5bqiSi0EfWnUHGk3p3EJRjlVAkPvKn1h 3oOLOzFiMAm2LfJlta5mvj9QM2Eol/50Wa/eMkDPAEefNfs1zkc1OEU8P9DYws6Qx7mX xFAEqrN9clvW/9ts54PZUACeiYHbZzOPbdij79qd1mKtER8mZwiseRnkdttZehdmAxxv kkQxLFuxun8BoH9RNtCRWHoWqq7Qc6gYeTTKxhqa5atlcCm7bp7f04jAGb8OFnPev3Fl mapDzWelEQnnzd7cZo3Fgc0QIimYZw9y4qEcMpTChGmqYFbbH9ljanrfoDGr3ZpRF416 jGjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tmZ1vTA6; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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In preparation to reworking DPU planes, drop support for master planes (which was not used anyway). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 67 ++++------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 13 +---- 4 files changed, 15 insertions(+), 78 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index ea678ddd4589..6fe0af9ffc23 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -974,17 +974,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } for (i = 1; i < SSPP_MAX; i++) { - if (pipe_staged[i]) { + if (pipe_staged[i]) dpu_plane_clear_multirect(pipe_staged[i]); - - if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { - DPU_ERROR( - "r1 only virt plane:%d not supported\n", - pipe_staged[i]->plane->base.id); - rc = -EINVAL; - goto end; - } - } } z_pos = -1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1d3a4f395e74..b7b73d0de6f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -623,7 +623,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); plane = dpu_plane_init(dev, catalog->sspp[i].id, type, - (1UL << max_crtc_count) - 1, 0); + (1UL << max_crtc_count) - 1); if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret = PTR_ERR(plane); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 97507e25f4f3..dbc9c2c28ae0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -91,7 +91,6 @@ enum dpu_plane_qos { * struct dpu_plane - local dpu plane structure * @aspace: address space pointer * @csc_ptr: Points to dpu_csc_cfg structure to use for current - * @mplane_list: List of multirect planes of the same pipe * @catalog: Points to dpu catalog structure * @revalidate: force revalidation of all the plane properties */ @@ -108,8 +107,6 @@ struct dpu_plane { uint32_t color_fill; bool is_error; bool is_rt_pipe; - bool is_virtual; - struct list_head mplane_list; struct dpu_mdss_cfg *catalog; struct dpu_csc_cfg *csc_ptr; @@ -237,7 +234,7 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane) static int _dpu_plane_calc_fill_level(struct drm_plane *plane, const struct dpu_format *fmt, u32 src_width) { - struct dpu_plane *pdpu, *tmp; + struct dpu_plane *pdpu; struct dpu_plane_state *pstate; u32 fixed_buff_size; u32 total_fl; @@ -251,16 +248,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, pstate = to_dpu_plane_state(plane->state); fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; - list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { - if (!tmp->base.state->visible) - continue; - DPU_DEBUG("plane%d/%d src_width:%d/%d\n", - pdpu->base.base.id, tmp->base.base.id, - src_width, - drm_rect_width(&tmp->pipe_cfg.src_rect)); - src_width = max_t(u32, src_width, - drm_rect_width(&tmp->pipe_cfg.src_rect)); - } + /* FIXME: in multirect case account for the src_width of all the planes */ if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { if (fmt->chroma_sample == DPU_CHROMA_420) { @@ -836,13 +824,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) } done: - if (dpu_plane[R0]->is_virtual) { - pstate[R0]->multirect_index = DPU_SSPP_RECT_1; - pstate[R1]->multirect_index = DPU_SSPP_RECT_0; - } else { - pstate[R0]->multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->multirect_index = DPU_SSPP_RECT_1; - } + pstate[R0]->multirect_index = DPU_SSPP_RECT_0; + pstate[R1]->multirect_index = DPU_SSPP_RECT_1; DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", pstate[R0]->multirect_mode, pstate[R0]->multirect_index); @@ -1218,19 +1201,13 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) static void _dpu_plane_atomic_disable(struct drm_plane *plane) { - struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - trace_dpu_plane_disable(DRMID(plane), is_dpu_plane_virtual(plane), + trace_dpu_plane_disable(DRMID(plane), false, pstate->multirect_mode); pstate->pending = true; - - if (is_dpu_plane_virtual(plane) && - pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, - DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); } static void dpu_plane_atomic_update(struct drm_plane *plane, @@ -1556,17 +1533,12 @@ enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; } -bool is_dpu_plane_virtual(struct drm_plane *plane) -{ - return plane ? to_dpu_plane(plane)->is_virtual : false; -} - /* initialize plane */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, - unsigned long possible_crtcs, u32 master_plane_id) + unsigned long possible_crtcs) { - struct drm_plane *plane = NULL, *master_plane = NULL; + struct drm_plane *plane = NULL; const uint32_t *format_list; struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; @@ -1586,18 +1558,9 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, /* cache local stuff for later */ plane = &pdpu->base; pdpu->pipe = pipe; - pdpu->is_virtual = (master_plane_id != 0); - INIT_LIST_HEAD(&pdpu->mplane_list); - master_plane = drm_plane_find(dev, NULL, master_plane_id); - if (master_plane) { - struct dpu_plane *mpdpu = to_dpu_plane(master_plane); - - list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); - } /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, - master_plane_id != 0); + pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, false); if (IS_ERR(pdpu->pipe_hw)) { DPU_ERROR("[%u]SSPP init failed\n", pipe); ret = PTR_ERR(pdpu->pipe_hw); @@ -1615,14 +1578,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, goto clean_sspp; } - if (pdpu->is_virtual) { - format_list = pdpu->pipe_sblk->virt_format_list; - num_formats = pdpu->pipe_sblk->virt_num_formats; - } - else { - format_list = pdpu->pipe_sblk->format_list; - num_formats = pdpu->pipe_sblk->num_formats; - } + format_list = pdpu->pipe_sblk->format_list; + num_formats = pdpu->pipe_sblk->num_formats; ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1657,8 +1614,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, mutex_init(&pdpu->lock); - DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", plane->name, - pipe, plane->base.id, master_plane_id); + DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, + pipe, plane->base.id); return plane; clean_sspp: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 34e03ac05f4a..d5b7f5876e64 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -67,14 +67,6 @@ struct dpu_multirect_plane_states { */ enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); -/** - * is_dpu_plane_virtual - check for virtual plane - * @plane: Pointer to DRM plane object - * returns: true - if the plane is virtual - * false - if the plane is primary - */ -bool is_dpu_plane_virtual(struct drm_plane *plane); - /** * dpu_plane_get_ctl_flush - get control flush mask * @plane: Pointer to DRM plane object @@ -102,14 +94,11 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error); * @pipe: dpu hardware pipe identifier * @type: Plane type - PRIMARY/OVERLAY/CURSOR * @possible_crtcs: bitmask of crtc that can be attached to the given pipe - * @master_plane_id: primary plane id of a multirect pipe. 0 value passed for - * a regular plane initialization. A non-zero primary plane - * id will be passed for a virtual pipe initialization. * */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, - unsigned long possible_crtcs, u32 master_plane_id); + unsigned long possible_crtcs); /** * dpu_plane_validate_multirecti_v2 - validate the multirect planes From patchwork Thu Jun 24 14:57:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466355 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536820jao; Thu, 24 Jun 2021 07:57:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkcn32V3twcTPxhqhGA8Tlp75Z1OGaKrWe94Y8OtjQdGdrv12tbSz98b+WRZWnzobBUMIk X-Received: by 2002:a02:a501:: with SMTP id e1mr4987708jam.83.1624546667411; Thu, 24 Jun 2021 07:57:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546667; cv=none; d=google.com; s=arc-20160816; b=okfAkGVgpNRFx8vC8PCCYwZAf+kulxbISxan06PeHcC9j0s8bWYlsvGWLn9dcukV4n Ive+VJ5vxHh1CkY3fNsGQz/YaOb0XjAC993OL1+jN216oiE09kiHiXJ8/EjwaStTMevb uqtIRhFJ03ZTzgQAbDMw3keoSKhjvEYlwjhQ649+Z35H6bjLsrzbCSJSbeN3e7zaPfUv T/tco50hoJY9HGMn2jV00tl6ntcthh18UoQimmQ6IoK5ErjWvQnAVhHC8u4HZgOWe+wE 4RTmBKSoMyqnVYU3Y/xMenYCLKi83por0N5LOniVmhFimR/WJ2O1vtlLAX4DGXAQGhNZ 2vBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vHOr5O91BQvkeV001owIbHLjqhC1uAPXk4QfUUezW3I=; b=CJS1WKzQTlCt8zoJh4f70x7v3ww0xUqKeKTeifowgKWwOxehLtkZZ63053d99a7Gml tyq2GHqUJdKp7tjkIA5+JQccqNDdC5PM5fBUIWJexqtxRzVOemIX92oUauehWbk4za77 UYZV99BIKrAFplPx9qcRiZ4Z4Par2mtZxxiK1vQb4IQW7e/RbyAvaVZOtffrqZ5KlX00 kbpM8EGNrWmspEsoHrKtybfapIsVQM62FNgE0Z0HLTNHFXdkLaF0TH8szI4yaOYGBjLN M/JCxk6R8zt3xOq/3GBvs6RZC2YnrkGjumk369qVqaQsL8alAf5IHY4UGAo/zpeALoSo gTZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6ZIyn0G; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 91 ++++++++++++----------- 1 file changed, 46 insertions(+), 45 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index dbc9c2c28ae0..521ae699dc5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -103,7 +103,6 @@ struct dpu_plane { uint32_t features; /* capabilities from catalog */ struct dpu_hw_pipe *pipe_hw; - struct dpu_hw_pipe_cfg pipe_cfg; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -145,9 +144,9 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) * Prefill BW Equation: line src bytes * line_time */ static void _dpu_plane_calc_bw(struct drm_plane *plane, - struct drm_framebuffer *fb) + struct drm_framebuffer *fb, + struct dpu_hw_pipe_cfg *pipe_cfg) { - struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate; struct drm_display_mode *mode; const struct dpu_format *fmt = NULL; @@ -164,9 +163,9 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); - src_width = drm_rect_width(&pdpu->pipe_cfg.src_rect); - src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); - dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); + src_width = drm_rect_width(&pipe_cfg->src_rect); + src_height = drm_rect_height(&pipe_cfg->src_rect); + dst_height = drm_rect_height(&pipe_cfg->dst_rect); fps = drm_mode_vrefresh(mode); vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; @@ -200,9 +199,8 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane) +static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg) { - struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate; struct drm_display_mode *mode; int dst_width, src_height, dst_height, fps; @@ -210,9 +208,9 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane) pstate = to_dpu_plane_state(plane->state); mode = &plane->state->crtc->mode; - src_height = drm_rect_height(&pdpu->pipe_cfg.src_rect); - dst_width = drm_rect_width(&pdpu->pipe_cfg.dst_rect); - dst_height = drm_rect_height(&pdpu->pipe_cfg.dst_rect); + src_height = drm_rect_height(&pipe_cfg->src_rect); + dst_width = drm_rect_width(&pipe_cfg->dst_rect); + dst_height = drm_rect_height(&pipe_cfg->dst_rect); fps = drm_mode_vrefresh(mode); pstate->plane_clk = @@ -309,7 +307,7 @@ static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, * @fb: Pointer to framebuffer associated with the given plane */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb) + struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); const struct dpu_format *fmt = NULL; @@ -323,7 +321,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fb->format->format, fb->modifier); total_fl = _dpu_plane_calc_fill_level(plane, fmt, - drm_rect_width(&pdpu->pipe_cfg.src_rect)); + drm_rect_width(&pipe_cfg->src_rect)); if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) lut_usage = DPU_QOS_LUT_USAGE_LINEAR; @@ -451,7 +449,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * @crtc: Pointer to drm crtc */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, - struct drm_crtc *crtc) + struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; @@ -460,8 +458,8 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, memset(&ot_params, 0, sizeof(ot_params)); ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; - ot_params.width = drm_rect_width(&pdpu->pipe_cfg.src_rect); - ot_params.height = drm_rect_height(&pdpu->pipe_cfg.src_rect); + ot_params.width = drm_rect_width(&pipe_cfg->src_rect); + ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; @@ -639,17 +637,18 @@ static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, struct dpu_plane_state *pstate, - const struct dpu_format *fmt, bool color_fill) + const struct dpu_format *fmt, bool color_fill, + struct dpu_hw_pipe_cfg *pipe_cfg) { const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); /* don't chroma subsample if decimating */ /* update scaler. calculate default config for QSEED3 */ _dpu_plane_setup_scaler3(pdpu, pstate, - drm_rect_width(&pdpu->pipe_cfg.src_rect), - drm_rect_height(&pdpu->pipe_cfg.src_rect), - drm_rect_width(&pdpu->pipe_cfg.dst_rect), - drm_rect_height(&pdpu->pipe_cfg.dst_rect), + drm_rect_width(&pipe_cfg->src_rect), + drm_rect_height(&pipe_cfg->src_rect), + drm_rect_width(&pipe_cfg->dst_rect), + drm_rect_height(&pipe_cfg->dst_rect), &pstate->scaler3_cfg, fmt, info->hsub, info->vsub); } @@ -667,6 +666,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); + struct dpu_hw_pipe_cfg pipe_cfg; DPU_DEBUG_PLANE(pdpu, "\n"); @@ -683,13 +683,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, pstate->multirect_index); /* override scaler/decimation if solid fill */ - pdpu->pipe_cfg.src_rect.x1 = 0; - pdpu->pipe_cfg.src_rect.y1 = 0; - pdpu->pipe_cfg.src_rect.x2 = - drm_rect_width(&pdpu->pipe_cfg.dst_rect); - pdpu->pipe_cfg.src_rect.y2 = - drm_rect_height(&pdpu->pipe_cfg.dst_rect); - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true); + pipe_cfg.src_rect.x1 = 0; + pipe_cfg.src_rect.y1 = 0; + pipe_cfg.src_rect.x2 = + drm_rect_width(&pipe_cfg.dst_rect); + pipe_cfg.src_rect.y2 = + drm_rect_height(&pipe_cfg.dst_rect); + _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); if (pdpu->pipe_hw->ops.setup_format) pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, @@ -698,7 +698,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, if (pdpu->pipe_hw->ops.setup_rects) pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pdpu->pipe_cfg, + &pipe_cfg, pstate->multirect_index); if (pdpu->pipe_hw->ops.setup_pe) @@ -708,7 +708,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, if (pdpu->pipe_hw->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, - &pdpu->pipe_cfg, &pstate->pixel_ext, + &pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); } @@ -1070,10 +1070,11 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) bool is_rt_pipe, update_qos_remap; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); + struct dpu_hw_pipe_cfg pipe_cfg; - memset(&(pdpu->pipe_cfg), 0, sizeof(struct dpu_hw_pipe_cfg)); + memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg)); - _dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb); + _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); pstate->pending = true; @@ -1085,17 +1086,17 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) crtc->base.id, DRM_RECT_ARG(&state->dst), (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - pdpu->pipe_cfg.src_rect = state->src; + pipe_cfg.src_rect = state->src; /* state->src is 16.16, src_rect is not */ - pdpu->pipe_cfg.src_rect.x1 >>= 16; - pdpu->pipe_cfg.src_rect.x2 >>= 16; - pdpu->pipe_cfg.src_rect.y1 >>= 16; - pdpu->pipe_cfg.src_rect.y2 >>= 16; + pipe_cfg.src_rect.x1 >>= 16; + pipe_cfg.src_rect.x2 >>= 16; + pipe_cfg.src_rect.y1 >>= 16; + pipe_cfg.src_rect.y2 >>= 16; - pdpu->pipe_cfg.dst_rect = state->dst; + pipe_cfg.dst_rect = state->dst; - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false); + _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { @@ -1105,7 +1106,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) if (pdpu->pipe_hw->ops.setup_rects) { pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pdpu->pipe_cfg, + &pipe_cfg, pstate->multirect_index); } @@ -1122,7 +1123,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) if (pdpu->pipe_hw->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, - &pdpu->pipe_cfg, &pstate->pixel_ext, + &pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); if (pdpu->pipe_hw->ops.setup_multirect) @@ -1175,12 +1176,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pdpu->csc_ptr = 0; } - _dpu_plane_set_qos_lut(plane, fb); + _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); _dpu_plane_set_danger_lut(plane, fb); if (plane->type != DRM_PLANE_TYPE_CURSOR) { _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, crtc); + _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg); } update_qos_remap = (is_rt_pipe != pdpu->is_rt_pipe) || @@ -1194,9 +1195,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) _dpu_plane_set_qos_remap(plane); } - _dpu_plane_calc_bw(plane, fb); + _dpu_plane_calc_bw(plane, fb, &pipe_cfg); - _dpu_plane_calc_clk(plane); + _dpu_plane_calc_clk(plane, &pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) From patchwork Thu Jun 24 14:57:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466354 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536808jao; 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Use pdpu->pipe_hw->cap->features directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 521ae699dc5a..cf45a86877e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -100,7 +100,6 @@ struct dpu_plane { struct mutex lock; enum dpu_sspp pipe; - uint32_t features; /* capabilities from catalog */ struct dpu_hw_pipe *pipe_hw; uint32_t color_fill; @@ -624,7 +623,7 @@ static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) return; } - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; else pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; @@ -972,8 +971,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; if (DPU_FORMAT_IS_YUV(fmt) && - (!(pdpu->features & DPU_SSPP_SCALER) || - !(pdpu->features & (BIT(DPU_SSPP_CSC) + (!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) || + !(pdpu->pipe_hw->cap->features & (BIT(DPU_SSPP_CSC) | BIT(DPU_SSPP_CSC_10BIT))))) { DPU_DEBUG_PLANE(pdpu, "plane doesn't have scaler/csc for yuv\n"); @@ -1412,8 +1411,8 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane) plane->dev->primary->debugfs_root); /* don't error check these */ - debugfs_create_x32("features", 0600, - pdpu->debugfs_root, &pdpu->features); + debugfs_create_xul("features", 0600, + pdpu->debugfs_root, (unsigned long *)&pdpu->pipe_hw->cap->features); /* add register dump support */ dpu_debugfs_setup_regset32(&pdpu->debugfs_src, @@ -1572,7 +1571,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, } /* cache features mask for later */ - pdpu->features = pdpu->pipe_hw->cap->features; pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; if (!pdpu->pipe_sblk) { DPU_ERROR("[%u]invalid sblk\n", pipe); From patchwork Thu Jun 24 14:57:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466356 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536836jao; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJytZE9OrD99Z7VYkImN0JTcRz4ouRpjIGTyU+P7JS1zuA/KP/Le7iYQZH6GrPGKpV7sTN3g X-Received: by 2002:a5d:9a97:: with SMTP id c23mr4573257iom.38.1624546668537; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546668; cv=none; d=google.com; s=arc-20160816; b=lQib7A7Yfu1PqcPKLLX5Xq9AtTJZGJQNR0i9DfU5HG3JWOxBwj1y4chws/ZSHRMRRA inLqQRbQpBsEgui4QV35jcP8TR0ATS6feTfe4hTkj2vTqC1WCKg1Ary7XpoKTQDQfsIt yEuZtaPo2Lp8100671HrEQJ5YC0PtpcHtZgmThJLnMKc+J5dWw8/x/rb6tq6GjH4qsE4 6XQkPKcK4gYJfXX0SayL9svFj9LAe1MndUXlq87MjFZolZrwOs/9idegQpNOGMdeCIIe rFNq/k7dKMOt4BY1rfRwfhUnGr76PNN4GZxb8HBlVmJs468NUPwnq09ekJfKGzqiLqII 2j6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9riuerPahbGrv0+etuSxf5QM+cT8r/JYRQInCd02eGY=; b=C+da9TdKaAWWJYQk6wW1jNEaQd6Hfy6RcGDNpCUaPLlPu4mnIa/kmXBo8JlWBHii5h LWprTgjvh1eDRdjAVASts8kOm38vBoTRcACMZ+BZiQ3J4Q9LbActsBDEL036MPsTfPbq f8SIrSNbQFtLqYKiUcrGpb4FrbCvgstBJclIJT8vkJuD/iMUPidiMSjruxz+b2JAMq0N 0g1GL+GPQMl312t0swJrXLUQRQg8AOVxtCDGTkHwQ43TdhdXaVEEPqmrCQO2o+V9Uk3l 84cvK8AwIrYulNPs4MJec1FwofFuU9mlZgol5q7Xkb7tFWOo0Ay/tgJ0zPdt6vY3A6Vr epew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YIeXhsB1; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Use pdpu->pipe_hw->cap->sblk directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index cf45a86877e2..c5b221ecfa05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -109,8 +109,6 @@ struct dpu_plane { struct dpu_csc_cfg *csc_ptr; - const struct dpu_sspp_sub_blks *pipe_sblk; - /* debugfs related stuff */ struct dentry *debugfs_root; struct dpu_debugfs_regset32 debugfs_src; @@ -410,9 +408,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pdpu->pipe_sblk->danger_vblank; + pdpu->pipe_hw->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -942,10 +940,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale); + min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale); ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, - pdpu->pipe_sblk->maxdwnscale << 16, + pdpu->pipe_hw->cap->sblk->maxdwnscale << 16, true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); @@ -1570,15 +1568,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, goto clean_sspp; } - /* cache features mask for later */ - pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; - if (!pdpu->pipe_sblk) { - DPU_ERROR("[%u]invalid sblk\n", pipe); - goto clean_sspp; - } - - format_list = pdpu->pipe_sblk->format_list; - num_formats = pdpu->pipe_sblk->num_formats; + format_list = pdpu->pipe_hw->cap->sblk->format_list; + num_formats = pdpu->pipe_hw->cap->sblk->num_formats; ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, From patchwork Thu Jun 24 14:57:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466357 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536843jao; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzurqD6df6M5Rfy2kPTnIOfKjjjxPsE2i473oGH2+gdA1cr9BNcKo3mUUrBega9WFa3VhuN X-Received: by 2002:a02:90cb:: with SMTP id c11mr5118304jag.53.1624546668844; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546668; cv=none; d=google.com; s=arc-20160816; b=r4R1Tcmfq86TePcSxNyVWT8GoKjAQaPgoS57n5+obi3YioP9aVnbXBymoPfOyF7RwK dKZCaxJI2fBGrH9zq1z6aG/0l7k0jG6bE1EP8SxomFOsELWOFdVsCt3z7coHNzKTOLd9 iNZ+hoYVO3ca/VnCNrWUQVjTkJccv29CWMueQVrP3IKEZl1B94tFC9h2Sf+js0+BIjr2 zALLLpocbUBghzsk9q4+eojsQCQPezB5QDMU2JMtCvQbZRC2mUzeJWX2535mDl3ECPqm Y6ZR1fy1uYFC27MVP85ljJkC2Kk03naPg6xRErYQsUxVkjxQSLUOIX6lW04WU+RUuPqP 0WYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tnbmWvMR7qV/tUMEFyHhHaWBzojVpDF5JIeoneSoL/E=; b=UpE7RvUM/ILIu4tJXzjGkGJboWZLTd5yE/63B997AUFXvfrjnjcb9HClnOz3iVuVgw NR59VqiC9b5lpFKZnwSe7EJ//W8D2atNCH4bKVtLm6ZMBuU30EoL2BIWJJMAFTlmglmV 0pJXEzdQPF42ql2y3JVwOsuAGCjYNovf2q9yffbi7GrFPezE9S/rPtuqLAYbPzPh9wsr Cm+4sMd36dUo4Ywy1z2UsHb5iRCot1f+PZdX97C4EQBYxGlCpJ4INT3uvspMUI0qg9gG jZzkOmyPYs8C2AxC9WQUr9UfY3rFwYAZOg5hlKX1/tbXh0iUlW/IiS6DC3vS66RLgY3c AOjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lMOzwkbe; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also move disable_danger file to danger/ debugfs subdir where it belongs. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 123 ++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 69 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 171 +--------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 + 4 files changed, 69 insertions(+), 300 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index b7b73d0de6f8..66a1c8889cf3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -101,84 +101,85 @@ static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v) } DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats); -static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, - struct dentry *parent) +static ssize_t _dpu_plane_danger_read(struct file *file, + char __user *buff, size_t count, loff_t *ppos) { - struct dentry *entry = debugfs_create_dir("danger", parent); + struct dpu_kms *kms = file->private_data; + int len; + char buf[40]; - debugfs_create_file("danger_status", 0600, entry, - dpu_kms, &dpu_debugfs_danger_stats_fops); - debugfs_create_file("safe_status", 0600, entry, - dpu_kms, &dpu_debugfs_safe_stats_fops); + len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); + + return simple_read_from_buffer(buff, count, ppos, buf, len); } -static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) +static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) { - struct dpu_debugfs_regset32 *regset = s->private; - struct dpu_kms *dpu_kms = regset->dpu_kms; - void __iomem *base; - uint32_t i, addr; - - if (!dpu_kms->mmio) - return 0; - - base = dpu_kms->mmio + regset->offset; - - /* insert padding spaces, if needed */ - if (regset->offset & 0xF) { - seq_printf(s, "[%x]", regset->offset & ~0xF); - for (i = 0; i < (regset->offset & 0xF); i += 4) - seq_puts(s, " "); - } - - pm_runtime_get_sync(&dpu_kms->pdev->dev); - - /* main register output */ - for (i = 0; i < regset->blk_len; i += 4) { - addr = regset->offset + i; - if ((addr & 0xF) == 0x0) - seq_printf(s, i ? "\n[%x]" : "[%x]", addr); - seq_printf(s, " %08x", readl_relaxed(base + i)); + struct drm_plane *plane; + + drm_for_each_plane(plane, kms->dev) { + if (plane->fb && plane->state) { + dpu_plane_danger_signal_ctrl(plane, enable); + DPU_DEBUG("plane:%d img:%dx%d ", + plane->base.id, plane->fb->width, + plane->fb->height); + DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", + plane->state->src_x >> 16, + plane->state->src_y >> 16, + plane->state->src_w >> 16, + plane->state->src_h >> 16, + plane->state->crtc_x, plane->state->crtc_y, + plane->state->crtc_w, plane->state->crtc_h); + } else { + DPU_DEBUG("Inactive plane:%d\n", plane->base.id); + } } - seq_puts(s, "\n"); - pm_runtime_put_sync(&dpu_kms->pdev->dev); - - return 0; } -static int dpu_debugfs_open_regset32(struct inode *inode, - struct file *file) +static ssize_t _dpu_plane_danger_write(struct file *file, + const char __user *user_buf, size_t count, loff_t *ppos) { - return single_open(file, _dpu_debugfs_show_regset32, inode->i_private); -} + struct dpu_kms *kms = file->private_data; + int disable_panic; + int ret; -static const struct file_operations dpu_fops_regset32 = { - .open = dpu_debugfs_open_regset32, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; + ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); + if (ret) + return ret; -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset, - uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) -{ - if (regset) { - regset->offset = offset; - regset->blk_len = length; - regset->dpu_kms = dpu_kms; + if (disable_panic) { + /* Disable panic signal for all active pipes */ + DPU_DEBUG("Disabling danger:\n"); + _dpu_plane_set_danger_state(kms, false); + kms->has_danger_ctrl = false; + } else { + /* Enable panic signal for all active pipes */ + DPU_DEBUG("Enabling danger:\n"); + kms->has_danger_ctrl = true; + _dpu_plane_set_danger_state(kms, true); } + + return count; } -void dpu_debugfs_create_regset32(const char *name, umode_t mode, - void *parent, struct dpu_debugfs_regset32 *regset) +static const struct file_operations dpu_plane_danger_enable = { + .open = simple_open, + .read = _dpu_plane_danger_read, + .write = _dpu_plane_danger_write, +}; + +static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms, + struct dentry *parent) { - if (!name || !regset || !regset->dpu_kms || !regset->blk_len) - return; + struct dentry *entry = debugfs_create_dir("danger", parent); - /* make sure offset is a multiple of 4 */ - regset->offset = round_down(regset->offset, 4); + debugfs_create_file("danger_status", 0600, entry, + dpu_kms, &dpu_debugfs_danger_stats_fops); + debugfs_create_file("safe_status", 0600, entry, + dpu_kms, &dpu_debugfs_safe_stats_fops); + debugfs_create_file("disable_danger", 0600, entry, + dpu_kms, &dpu_plane_danger_enable); - debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); } static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 323a6bce9e64..ab65c817eb42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -166,75 +166,6 @@ struct dpu_global_state struct dpu_global_state *__must_check dpu_kms_get_global_state(struct drm_atomic_state *s); -/** - * Debugfs functions - extra helper functions for debugfs support - * - * Main debugfs documentation is located at, - * - * Documentation/filesystems/debugfs.rst - * - * @dpu_debugfs_setup_regset32: Initialize data for dpu_debugfs_create_regset32 - * @dpu_debugfs_create_regset32: Create 32-bit register dump file - * @dpu_debugfs_get_root: Get root dentry for DPU_KMS's debugfs node - */ - -/** - * Companion structure for dpu_debugfs_create_regset32. Do not initialize the - * members of this structure explicitly; use dpu_debugfs_setup_regset32 instead. - */ -struct dpu_debugfs_regset32 { - uint32_t offset; - uint32_t blk_len; - struct dpu_kms *dpu_kms; -}; - -/** - * dpu_debugfs_setup_regset32 - Initialize register block definition for debugfs - * This function is meant to initialize dpu_debugfs_regset32 structures for use - * with dpu_debugfs_create_regset32. - * @regset: opaque register definition structure - * @offset: sub-block offset - * @length: sub-block length, in bytes - * @dpu_kms: pointer to dpu kms structure - */ -void dpu_debugfs_setup_regset32(struct dpu_debugfs_regset32 *regset, - uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms); - -/** - * dpu_debugfs_create_regset32 - Create register read back file for debugfs - * - * This function is almost identical to the standard debugfs_create_regset32() - * function, with the main difference being that a list of register - * names/offsets do not need to be provided. The 'read' function simply outputs - * sequential register values over a specified range. - * - * Similar to the related debugfs_create_regset32 API, the structure pointed to - * by regset needs to persist for the lifetime of the created file. The calling - * code is responsible for initialization/management of this structure. - * - * The structure pointed to by regset is meant to be opaque. Please use - * dpu_debugfs_setup_regset32 to initialize it. - * - * @name: File name within debugfs - * @mode: File mode within debugfs - * @parent: Parent directory entry within debugfs, can be NULL - * @regset: Pointer to persistent register block definition - */ -void dpu_debugfs_create_regset32(const char *name, umode_t mode, - void *parent, struct dpu_debugfs_regset32 *regset); - -/** - * dpu_debugfs_get_root - Return root directory entry for KMS's debugfs - * - * The return value should be passed as the 'parent' argument to subsequent - * debugfs create calls. - * - * @dpu_kms: Pointer to DPU's KMS structure - * - * Return: dentry pointer for DPU's debugfs location - */ -void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms); - /** * DPU info management functions * These functions/definitions allow for building up a 'dpu_info' structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index c5b221ecfa05..991697150f0d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -108,13 +108,6 @@ struct dpu_plane { struct dpu_mdss_cfg *catalog; struct dpu_csc_cfg *csc_ptr; - - /* debugfs related stuff */ - struct dentry *debugfs_root; - struct dpu_debugfs_regset32 debugfs_src; - struct dpu_debugfs_regset32 debugfs_scaler; - struct dpu_debugfs_regset32 debugfs_csc; - bool debugfs_default_scale; }; static const uint64_t supported_format_modifiers[] = { @@ -1316,7 +1309,7 @@ static void dpu_plane_reset(struct drm_plane *plane) } #ifdef CONFIG_DEBUG_FS -static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); @@ -1328,168 +1321,8 @@ static void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } - -static ssize_t _dpu_plane_danger_read(struct file *file, - char __user *buff, size_t count, loff_t *ppos) -{ - struct dpu_kms *kms = file->private_data; - int len; - char buf[40]; - - len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); - - return simple_read_from_buffer(buff, count, ppos, buf, len); -} - -static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable) -{ - struct drm_plane *plane; - - drm_for_each_plane(plane, kms->dev) { - if (plane->fb && plane->state) { - dpu_plane_danger_signal_ctrl(plane, enable); - DPU_DEBUG("plane:%d img:%dx%d ", - plane->base.id, plane->fb->width, - plane->fb->height); - DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n", - plane->state->src_x >> 16, - plane->state->src_y >> 16, - plane->state->src_w >> 16, - plane->state->src_h >> 16, - plane->state->crtc_x, plane->state->crtc_y, - plane->state->crtc_w, plane->state->crtc_h); - } else { - DPU_DEBUG("Inactive plane:%d\n", plane->base.id); - } - } -} - -static ssize_t _dpu_plane_danger_write(struct file *file, - const char __user *user_buf, size_t count, loff_t *ppos) -{ - struct dpu_kms *kms = file->private_data; - int disable_panic; - int ret; - - ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic); - if (ret) - return ret; - - if (disable_panic) { - /* Disable panic signal for all active pipes */ - DPU_DEBUG("Disabling danger:\n"); - _dpu_plane_set_danger_state(kms, false); - kms->has_danger_ctrl = false; - } else { - /* Enable panic signal for all active pipes */ - DPU_DEBUG("Enabling danger:\n"); - kms->has_danger_ctrl = true; - _dpu_plane_set_danger_state(kms, true); - } - - return count; -} - -static const struct file_operations dpu_plane_danger_enable = { - .open = simple_open, - .read = _dpu_plane_danger_read, - .write = _dpu_plane_danger_write, -}; - -static int _dpu_plane_init_debugfs(struct drm_plane *plane) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_kms *kms = _dpu_plane_get_kms(plane); - const struct dpu_sspp_cfg *cfg = pdpu->pipe_hw->cap; - const struct dpu_sspp_sub_blks *sblk = cfg->sblk; - - /* create overall sub-directory for the pipe */ - pdpu->debugfs_root = - debugfs_create_dir(plane->name, - plane->dev->primary->debugfs_root); - - /* don't error check these */ - debugfs_create_xul("features", 0600, - pdpu->debugfs_root, (unsigned long *)&pdpu->pipe_hw->cap->features); - - /* add register dump support */ - dpu_debugfs_setup_regset32(&pdpu->debugfs_src, - sblk->src_blk.base + cfg->base, - sblk->src_blk.len, - kms); - dpu_debugfs_create_regset32("src_blk", 0400, - pdpu->debugfs_root, &pdpu->debugfs_src); - - if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || - cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || - cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || - cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) { - dpu_debugfs_setup_regset32(&pdpu->debugfs_scaler, - sblk->scaler_blk.base + cfg->base, - sblk->scaler_blk.len, - kms); - dpu_debugfs_create_regset32("scaler_blk", 0400, - pdpu->debugfs_root, - &pdpu->debugfs_scaler); - debugfs_create_bool("default_scaling", - 0600, - pdpu->debugfs_root, - &pdpu->debugfs_default_scale); - } - - if (cfg->features & BIT(DPU_SSPP_CSC) || - cfg->features & BIT(DPU_SSPP_CSC_10BIT)) { - dpu_debugfs_setup_regset32(&pdpu->debugfs_csc, - sblk->csc_blk.base + cfg->base, - sblk->csc_blk.len, - kms); - dpu_debugfs_create_regset32("csc_blk", 0400, - pdpu->debugfs_root, &pdpu->debugfs_csc); - } - - debugfs_create_u32("xin_id", - 0400, - pdpu->debugfs_root, - (u32 *) &cfg->xin_id); - debugfs_create_u32("clk_ctrl", - 0400, - pdpu->debugfs_root, - (u32 *) &cfg->clk_ctrl); - debugfs_create_x32("creq_vblank", - 0600, - pdpu->debugfs_root, - (u32 *) &sblk->creq_vblank); - debugfs_create_x32("danger_vblank", - 0600, - pdpu->debugfs_root, - (u32 *) &sblk->danger_vblank); - - debugfs_create_file("disable_danger", - 0600, - pdpu->debugfs_root, - kms, &dpu_plane_danger_enable); - - return 0; -} -#else -static int _dpu_plane_init_debugfs(struct drm_plane *plane) -{ - return 0; -} #endif -static int dpu_plane_late_register(struct drm_plane *plane) -{ - return _dpu_plane_init_debugfs(plane); -} - -static void dpu_plane_early_unregister(struct drm_plane *plane) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - - debugfs_remove_recursive(pdpu->debugfs_root); -} - static bool dpu_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) { @@ -1514,8 +1347,6 @@ static const struct drm_plane_funcs dpu_plane_funcs = { .reset = dpu_plane_reset, .atomic_duplicate_state = dpu_plane_duplicate_state, .atomic_destroy_state = dpu_plane_destroy_state, - .late_register = dpu_plane_late_register, - .early_unregister = dpu_plane_early_unregister, .format_mod_supported = dpu_plane_format_mod_supported, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index d5b7f5876e64..b0c08bd54170 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -123,4 +123,10 @@ void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); int dpu_plane_color_fill(struct drm_plane *plane, uint32_t color, uint32_t alpha); +#ifdef CONFIG_DEBUG_FS +void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable); +#else +static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {} +#endif + #endif /* _DPU_PLANE_H_ */ From patchwork Thu Jun 24 14:57:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466358 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536900jao; Thu, 24 Jun 2021 07:57:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6HKbpOb56dgdm7/Dxcce4Oy4lFCIgwiirpkw/6VS2WAuWRXq74Z/53q9H6YMZqpEbiTMS X-Received: by 2002:a02:cc52:: with SMTP id i18mr5017324jaq.47.1624546672817; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 84 +++++++++++---------- 5 files changed, 48 insertions(+), 44 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index cbafb61404d0..103d4bd7585b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -537,7 +537,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, } static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, - struct dpu_csc_cfg *data) + const struct dpu_csc_cfg *data) { u32 idx; bool csc10 = false; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 27263bc1a1ef..e8939d7387cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -262,7 +262,7 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @data: Pointer to config structure */ - void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data); + void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data); /** * setup_solidfill - enable/disable colorfill diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index f94584c982cd..aad85116b0a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -374,7 +374,7 @@ u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u32 csc_reg_off, - struct dpu_csc_cfg *data, bool csc10) + const struct dpu_csc_cfg *data, bool csc10) { static const u32 matrix_shift = 7; u32 clamp_shift = csc10 ? 16 : 8; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index ff3cffde84cd..bc2fdb2b8f5f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -321,6 +321,6 @@ u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c, void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u32 csc_reg_off, - struct dpu_csc_cfg *data, bool csc10); + const struct dpu_csc_cfg *data, bool csc10); #endif /* _DPU_HW_UTIL_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 991697150f0d..c4a76dd6dbd5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -107,7 +107,7 @@ struct dpu_plane { bool is_rt_pipe; struct dpu_mdss_cfg *catalog; - struct dpu_csc_cfg *csc_ptr; + const struct dpu_csc_cfg *csc_ptr; }; static const uint64_t supported_format_modifiers[] = { @@ -578,51 +578,58 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->enable = 1; } -static void _dpu_plane_setup_csc(struct dpu_plane *pdpu) -{ - static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { - { - /* S15.16 format */ - 0x00012A00, 0x00000000, 0x00019880, - 0x00012A00, 0xFFFF9B80, 0xFFFF3000, - 0x00012A00, 0x00020480, 0x00000000, +static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { + { + /* S15.16 format */ + 0x00012A00, 0x00000000, 0x00019880, + 0x00012A00, 0xFFFF9B80, 0xFFFF3000, + 0x00012A00, 0x00020480, 0x00000000, + }, + /* signed bias */ + { 0xfff0, 0xff80, 0xff80,}, + { 0x0, 0x0, 0x0,}, + /* unsigned clamp */ + { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, + { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, +}; +static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { + { + /* S15.16 format */ + 0x00012A00, 0x00000000, 0x00019880, + 0x00012A00, 0xFFFF9B80, 0xFFFF3000, + 0x00012A00, 0x00020480, 0x00000000, }, - /* signed bias */ - { 0xfff0, 0xff80, 0xff80,}, - { 0x0, 0x0, 0x0,}, - /* unsigned clamp */ - { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,}, - { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,}, - }; - static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { - { - /* S15.16 format */ - 0x00012A00, 0x00000000, 0x00019880, - 0x00012A00, 0xFFFF9B80, 0xFFFF3000, - 0x00012A00, 0x00020480, 0x00000000, - }, - /* signed bias */ - { 0xffc0, 0xfe00, 0xfe00,}, - { 0x0, 0x0, 0x0,}, - /* unsigned clamp */ - { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, - { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, - }; + /* signed bias */ + { 0xffc0, 0xfe00, 0xfe00,}, + { 0x0, 0x0, 0x0,}, + /* unsigned clamp */ + { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,}, + { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, +}; + +static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) +{ + const struct dpu_csc_cfg *csc_ptr; if (!pdpu) { DPU_ERROR("invalid plane\n"); - return; + return NULL; } + if (!DPU_FORMAT_IS_YUV(fmt)) + return NULL; + if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) - pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc10_YUV2RGB_601L; + csc_ptr = &dpu_csc10_YUV2RGB_601L; else - pdpu->csc_ptr = (struct dpu_csc_cfg *)&dpu_csc_YUV2RGB_601L; + csc_ptr = &dpu_csc_YUV2RGB_601L; DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", - pdpu->csc_ptr->csc_mv[0], - pdpu->csc_ptr->csc_mv[1], - pdpu->csc_ptr->csc_mv[2]); + csc_ptr->csc_mv[0], + csc_ptr->csc_mv[1], + csc_ptr->csc_mv[2]); + + return csc_ptr; } static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, @@ -1160,10 +1167,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } /* update csc */ - if (DPU_FORMAT_IS_YUV(fmt)) - _dpu_plane_setup_csc(pdpu); - else - pdpu->csc_ptr = 0; + pdpu->csc_ptr = _dpu_plane_get_csc(pdpu, fmt); } _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); From patchwork Thu Jun 24 14:57:27 2021 Content-Type: text/plain; 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[23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.52; Thu, 24 Jun 2021 07:57:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jBBk1j3o; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232257AbhFXPAK (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232280AbhFXPAI (ORCPT ); Thu, 24 Jun 2021 11:00:08 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F936C061756 for ; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id d25so8139429lji.7 for ; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KCaAu4jnvmCU/Mq+LvdhaCaR+6bzwbaah2dceb8YTQg=; b=jBBk1j3oGnIGLCHfTVQaUkMQtQUYnnT81R3vgIRx7iKhJbZUEOPYWjFwPegOach714 6ejdrzs2m5XwCDJc26GJz30+1MLcIEsIRX+4rj4yW1Q6GHUTZcvJjeoZScYkkWijKchu dfdm5HCIF8+r2JxOfp7gDvghhlNTaTiGqzxuR+5Dhw3RaZSbQVa0Tp91cZMr+Or1Cf2X Eiey30sC1V+xipRaM6rL/qUUdBwFxxe+/UaNahh8wHSMkUgorEjC77NvHjSg+SliMboa JfS7RIaZSAIHcSGSAWUjTHE4mPesOINdWubPm6ZKrGE4OoNC1Y9+dJyFKbIGEFILyOKG XFwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KCaAu4jnvmCU/Mq+LvdhaCaR+6bzwbaah2dceb8YTQg=; b=N8U35022M56psKlxvx/FSKuciiuI7Z0iA52rR8yda8HdY3yBqnjItg1N9EMdqmdv4Y x2ctMoOgiGn9w6ouzUuxuXwNpVgUg1oelnxCD5D1JYUjt+yME4IbGrrBzjchTwTxuiyb nZ2m3Yf4XTf2sCyB7/qCYyfN2AJFGMQCBYycRXqYu94nMC0Gazb45Wm507z0KcCJOBmX Vz6dP5CZkFyepgFGWBDwaGRrACN59wLKnkEWNMizjTvN7q81/efpXYZtNU0QVISOpiIL MH0e4vd+QAW01SMtMC+Xin4tyHBz5u5OZDTuNbUvWNLME7tcEgIY4DfR3WIC0+4Bz4Mg ZKIQ== X-Gm-Message-State: AOAM533JuXvmw+VF0lhRaOcrfy9fl3c9DVlkCuJvi0H1+TCdaNkytfPt U6PpOA0p7s/pV8ZQoT7wAamZNpvE8eLynw== X-Received: by 2002:a2e:bc13:: with SMTP id b19mr4328707ljf.480.1624546666648; Thu, 24 Jun 2021 07:57:46 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:46 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 11/17] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check Date: Thu, 24 Jun 2021 17:57:27 +0300 Message-Id: <20210624145733.2561992-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Neither source split nor multirect are properly supported at this moment. Both of these checks depend on zpos being equal for several planes (which is a clear userspace bug). Drop these checks to simplify dpu_crtc_atomic_check(). The actual support for either of these features is not removed from the backend code (sspp, ctl, etc). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 123 +---------------------- 1 file changed, 3 insertions(+), 120 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 6fe0af9ffc23..b62e8e4e8d0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -895,12 +895,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_plane *plane; struct drm_display_mode *mode; - int cnt = 0, rc = 0, mixer_width = 0, i, z_pos; + int cnt = 0, rc = 0, mixer_width = 0, i; - struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; - int multirect_count = 0; - const struct drm_plane_state *pipe_staged[SSPP_MAX]; - int left_zpos_cnt = 0, right_zpos_cnt = 0; struct drm_rect crtc_rect = { 0 }; pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); @@ -920,8 +916,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (crtc_state->active_changed) crtc_state->mode_changed = true; - memset(pipe_staged, 0, sizeof(pipe_staged)); - if (cstate->num_mixers) { mixer_width = mode->hdisplay / cstate->num_mixers; @@ -947,18 +941,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); pstates[cnt].drm_pstate = pstate; pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = dpu_plane_pipe(plane); - - if (pipe_staged[pstates[cnt].pipe_id]) { - multirect_plane[multirect_count].r0 = - pipe_staged[pstates[cnt].pipe_id]; - multirect_plane[multirect_count].r1 = pstate; - multirect_count++; - pipe_staged[pstates[cnt].pipe_id] = NULL; - } else { - pipe_staged[pstates[cnt].pipe_id] = pstate; - } + dpu_plane_clear_multirect(pstate); cnt++; @@ -973,19 +957,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } - for (i = 1; i < SSPP_MAX; i++) { - if (pipe_staged[i]) - dpu_plane_clear_multirect(pipe_staged[i]); - } - - z_pos = -1; for (i = 0; i < cnt; i++) { - /* reset counts at every new blend stage */ - if (pstates[i].stage != z_pos) { - left_zpos_cnt = 0; - right_zpos_cnt = 0; - z_pos = pstates[i].stage; - } + int z_pos = pstates[i].stage; /* verify z_pos setting before using it */ if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { @@ -993,40 +966,12 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DPU_STAGE_MAX - DPU_STAGE_0); rc = -EINVAL; goto end; - } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { - if (left_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on left\n", - z_pos); - rc = -EINVAL; - goto end; - } - left_zpos_cnt++; - - } else { - if (right_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on right\n", - z_pos); - rc = -EINVAL; - goto end; - } - right_zpos_cnt++; } pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); } - for (i = 0; i < multirect_count; i++) { - if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { - DPU_ERROR( - "multirect validation failed for planes (%d - %d)\n", - multirect_plane[i].r0->plane->base.id, - multirect_plane[i].r1->plane->base.id); - rc = -EINVAL; - goto end; - } - } - atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); rc = dpu_core_perf_crtc_check(crtc, crtc_state); @@ -1036,68 +981,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, goto end; } - /* validate source split: - * use pstates sorted by stage to check planes on same stage - * we assume that all pipes are in source split so its valid to compare - * without taking into account left/right mixer placement - */ - for (i = 1; i < cnt; i++) { - struct plane_state *prv_pstate, *cur_pstate; - struct drm_rect left_rect, right_rect; - int32_t left_pid, right_pid; - int32_t stage; - - prv_pstate = &pstates[i - 1]; - cur_pstate = &pstates[i]; - if (prv_pstate->stage != cur_pstate->stage) - continue; - - stage = cur_pstate->stage; - - left_pid = prv_pstate->dpu_pstate->base.plane->base.id; - left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); - - right_pid = cur_pstate->dpu_pstate->base.plane->base.id; - right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); - - if (right_rect.x1 < left_rect.x1) { - swap(left_pid, right_pid); - swap(left_rect, right_rect); - } - - /** - * - planes are enumerated in pipe-priority order such that - * planes with lower drm_id must be left-most in a shared - * blend-stage when using source split. - * - planes in source split must be contiguous in width - * - planes in source split must have same dest yoff and height - */ - if (right_pid < left_pid) { - DPU_ERROR( - "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", - stage, left_pid, right_pid); - rc = -EINVAL; - goto end; - } else if (right_rect.x1 != drm_rect_width(&left_rect)) { - DPU_ERROR("non-contiguous coordinates for src split. " - "stage: %d left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } else if (left_rect.y1 != right_rect.y1 || - drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { - DPU_ERROR("source split at stage: %d. invalid " - "yoff/height: left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } - } - end: kfree(pstates); return rc; From patchwork Thu Jun 24 14:57:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466360 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536916jao; Thu, 24 Jun 2021 07:57:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYLn2+INA8Ll520Cxk8mvExqnUI34RIPhrpTOpdW8aGRgEfPvsMDAMAL0X0qGIW6VgfhuD X-Received: by 2002:a6b:d108:: with SMTP id l8mr4354256iob.65.1624546673693; Thu, 24 Jun 2021 07:57:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546673; cv=none; d=google.com; s=arc-20160816; b=G1OQWTSpRF7oOxjv5ETL3YT1vEmxQfHJFfM/wuakzlqAeDsScYDuQAQBCz7Xqy0TtN S1CHinc9oVXei6/T2c2cF4rfwDa8grV3BTGaOVzMb6ScmI9TKIvepIXiciSLe9IgntB4 m0N2Pgmp1YrJdkpCjVBovbDpMStH7lZnLvs32j8WZvMZmvrKx3HjZlwiZ3vLVcZmOreb jdmjowl0wbvdgW0rCl3L0yJC3ibcyBzurHiMo/Gplg4M7M7WCqHSjFtZa66o6XT347eL fd4s/tR1Enh8qdDSQKIIA5Di4PPuD46OPgGjOmliyqD+NObMdmc0wiW4mPYrE6/mMSVB oWfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tDsHX0hxp/QVNOmO09ufPm+XNBvCicnDs8mQ30Y15QQ=; b=Gd8hEAu+MTOUrY1untb98ByF58nQ//jNwn+1iCovy2FEJQ5s9EvquOGmFEpxaEX/4x EXwgXV9PLSj1RTXRi9QDxKdIt7z2wrZdZnDX7Ns580UTQzzj8pUnXlUm2QjGrP6LKBG7 pSM5dnvTODdnCwSV6jDBOvRil6JAKfn6X9x7tO7x0BG1w/IrewoKZ+g7gUmg2nOFxAA3 BYlMZst736hn23YAxcAVcyggzPWLMQwUJZ/QJAUSpE19yPXYhOv5qzqw81hxKVujTj/4 1I79c7paMR3q59/o2VA7wfnqJ8CvQGH3RxnQ7CzY+/sZ4i5MF9OUqi6AeVkAS0N11MR5 zBgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qhpAF/vp"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.53; Thu, 24 Jun 2021 07:57:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qhpAF/vp"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232053AbhFXPAL (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232235AbhFXPAJ (ORCPT ); Thu, 24 Jun 2021 11:00:09 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76259C061574 for ; Thu, 24 Jun 2021 07:57:49 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id k10so10706791lfv.13 for ; Thu, 24 Jun 2021 07:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tDsHX0hxp/QVNOmO09ufPm+XNBvCicnDs8mQ30Y15QQ=; b=qhpAF/vpepGprjlgjI8xJn8+G7gGXphsnZQOd99413gIcRZFHqhuUtOd1L9w0SPbDz TI1gpe00wVuFH4q09c/LlAouOZa1EzndjHKo7he+G28wmrtOlj+Q3AKMztdiLKDHDl8N yu35lG3D0W8jRAMrbByn7j7S+uDWBPbotQZPx3LQGOn3cjclIQYcb5NpOf0RJ2hoogAN AT+nMVWIzs9IocRdfT6dM4ZZi+xUGS0DTQM88lVUob5pXhHw9YD8OpG/ipEE0+7317ZM Yodyu6RnpTqudNpQgPr5aFeCJv4VP9+48chN3XDc+BlGHHDSirK5t6/asBNywNatKWeA ouJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tDsHX0hxp/QVNOmO09ufPm+XNBvCicnDs8mQ30Y15QQ=; b=GFf6/EmWsgpXJyvzlboLPrKkaifLGCXMO8xnI+o2ZEZbRfn0UtpGSeBXzzGh1kS7+X lSsLQclQcAUVdBjw35suxui/FJtgVpspp4iML7v9NFo9JXfabNvLbphHh1JKgN7Bl6Hy y9QXx4KWvuRoUQHzZ173pKniAOXUn6aoXyYSftIAP6eFeDvx+yUgXpOBQbZ5EZwzMjdM vwcJtBTwT0NF9wyryHJyrj1hnzdE2PE5/K+Gd5GpH6K/zsoRf+zfRUI7pi7bcZp+br9F aCJJ4RxVkZvE4dznHP9EqMR3Yt+Zp/qmu8vx8HQMelwAfprFZOZwcW1f657cpTqjEPs1 41UQ== X-Gm-Message-State: AOAM531B/9++kFEU7WmG/8fNR4TdazZo5hGSOJEb46mi0zBevHYuOGt0 9hd3miH3c+BEcILOdQ6XQuuXTw== X-Received: by 2002:ac2:42cd:: with SMTP id n13mr4118450lfl.330.1624546667500; Thu, 24 Jun 2021 07:57:47 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:46 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 12/17] drm/msm/dpu: add list of supported formats to the DPU caps Date: Thu, 24 Jun 2021 17:57:28 +0300 Message-Id: <20210624145733.2561992-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As we are going to add virtual planes, add the list of supported formats to the hw catalog entry. It will be used to setup universal planes, with later selecting a pipe depending on whether the YUV format is used for the framebuffer. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ++++ 2 files changed, 14 insertions(+) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index d01c4c919504..b8e0fece1f0b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -195,6 +195,8 @@ static const struct dpu_caps sdm845_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .format_list = plane_formats_yuv, + .num_formats = ARRAY_SIZE(plane_formats_yuv), }; static const struct dpu_caps sc7180_dpu_caps = { @@ -207,6 +209,8 @@ static const struct dpu_caps sc7180_dpu_caps = { .has_idle_pc = true, .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .format_list = plane_formats_yuv, + .num_formats = ARRAY_SIZE(plane_formats_yuv), }; static const struct dpu_caps sm8150_dpu_caps = { @@ -223,6 +227,8 @@ static const struct dpu_caps sm8150_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .max_hdeci_exp = MAX_HORZ_DECIMATION, .max_vdeci_exp = MAX_VERT_DECIMATION, + .format_list = plane_formats_yuv, + .num_formats = ARRAY_SIZE(plane_formats_yuv), }; static const struct dpu_caps sm8250_dpu_caps = { @@ -237,6 +243,8 @@ static const struct dpu_caps sm8250_dpu_caps = { .has_3d_merge = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .format_list = plane_formats_yuv, + .num_formats = ARRAY_SIZE(plane_formats_yuv), }; static const struct dpu_caps sc7280_dpu_caps = { @@ -249,6 +257,8 @@ static const struct dpu_caps sc7280_dpu_caps = { .has_idle_pc = true, .max_linewidth = 2400, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .format_list = plane_formats_yuv, + .num_formats = ARRAY_SIZE(plane_formats_yuv), }; static const struct dpu_mdp_cfg sdm845_mdp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index d2a945a27cfa..f3c5aa3f4b3f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -324,6 +324,8 @@ struct dpu_qos_lut_tbl { * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes * @max_hdeci_exp max horizontal decimation supported (max is 2^value) * @max_vdeci_exp max vertical decimation supported (max is 2^value) + * @format_list: Pointer to list of supported formats + * @num_formats: Number of supported formats */ struct dpu_caps { u32 max_mixer_width; @@ -340,6 +342,8 @@ struct dpu_caps { u32 pixel_ram_size; u32 max_hdeci_exp; u32 max_vdeci_exp; + const u32 *format_list; + u32 num_formats; }; /** From patchwork Thu Jun 24 14:57:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466361 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536926jao; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9l8citgPEXsOearI2voovoLPOxZqvYzK8hxvvkqP7MQS/juDI5RUj5JQFxrCXCrYBMwdz X-Received: by 2002:a92:7312:: with SMTP id o18mr3737018ilc.289.1624546674092; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546674; cv=none; d=google.com; s=arc-20160816; b=onkkeQproA/DYMU+SnMbSYFIaItkLNYKSYfEGyF6JPllhhCn0U7SXWl3BYDfOGziQn GZD0M7BYH9/+3zebc2NekdhjdAa1E/PgM55sWoDfq6rHbwq5+8Q6tGg6cxDpalBL2hBs PmeEULu2fNWPhllMxMjHgSGLAsi/dXq5gNnf5+hI/93UPmNJQ36f5mI7OqwGZQ5yVIC8 /LZqEyTNOSRALpQTz7+5ZsaWveOnK08AsOdZ2iHfum+VmdfPjVbN+IaL30B2NptCfvpA tfbjmTwRMhcIzI9Vx/to3fOzOkvKIMnZRaq5AChwaWonBCuTyrtjHIUzLF8yckJ+Zjlv 915Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=96wZKbVAZc0QZ8GAGuoZzdhN1om+iu8T/MIvGHo2HXM=; b=r6kZqXZ4C9pVo/DvHj9O0bYfwQHAFcK4PY0AAO0v2y3uZlK+W+qk5W1obceQvb8BDQ JnBeZvIzRomFekbv5URIVtkMF3E4Mbih84niYf/tQdnJdIK8+DLGysIy4BSvnhKq2/oa Z6DV9Ms/WdmsVGjxn9DAjKzdZmFTprXLbZhDY6RrJ+KKuLjUh5vjUU4OqZEmCCdOQC7a TjrRLB4Ht+NvsA5RpjwzO2QeI8wkJwwljajmhDh5Ms254/WkDGacMMyxWyfD/ed3y4nx 7Jfse6pb9Hlc/Qomnphn1lbwurMl06NuyvLCq4KVdZjo6cK1CL5mQ3ZrB9sIlsOoW0gH SWqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HMBIcdCw; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.53; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HMBIcdCw; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232280AbhFXPAL (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232289AbhFXPAJ (ORCPT ); Thu, 24 Jun 2021 11:00:09 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C13A9C06175F for ; Thu, 24 Jun 2021 07:57:49 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id f30so10854535lfj.1 for ; Thu, 24 Jun 2021 07:57:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=96wZKbVAZc0QZ8GAGuoZzdhN1om+iu8T/MIvGHo2HXM=; b=HMBIcdCwiXMI824k6NBLU5oyVzXqtHS6oMwtm74emcbOkZsjNFVX+oNkpcemXQsYTy mHTBn+9XVDwJFHySUAJLjgwaOQrn+53h0O+BqC5sudvn/thi/k6OVx3Tpzzy3n/1szZv bTjmWSTS7D46QhPPAHqiZZj+zpUC18KAgiTcTjDwH950nA8OojAgC7/kVz6FHSA2VErg lkn6YvaNvQrfNIPnHfUx0S0fWx1irgb3ytHsVlmnFIY+J/f6Oh01njccuDK08K6YvbL1 BmjirTc+oLIGHAjIHS7Zp6i/+BhWldFe3E4L7VcpAZAlhZi5b8CWRWJkZy54C/3cPpGv 8ihQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=96wZKbVAZc0QZ8GAGuoZzdhN1om+iu8T/MIvGHo2HXM=; b=l8r+Jl7D2KFGqGi4SK31m48CVgOWL8vbf25fQEgUklK0a8iQQn+X0ksshjJzxBquNe b+i+QADeOqSZi+mLKKFppMK8r84TlwVypskZ1zPkshd90WDlfn7pmkzP6VXkxlfkjtMm 3Dh5E6mckt2DVf+TG+kMzcdzVKxrb+ZxtUDGMeSQSDUyJ+tmp7GJnmK66KF1BZ1O4ilL 4gDz332aowZjeCUV6C0HR4DtLWgF0X7PfrGHuAI64EP9i5/Dn3g/rCeTU9rrjlOlzOta oMxWWkvEK31zhczLs+PAOkdymAmdiWkV3qxbFJG+8xHlGSn6VAaZ+eymoiZ7d6amZi1h GxRQ== X-Gm-Message-State: AOAM533qvXJcgrtciue030yEtlSmwqNSU7GmUvaviwsFDnd4JJfUc0CW zHicybDc3JqssHxt/oH8HeCnHQ== X-Received: by 2002:a05:6512:3ca2:: with SMTP id h34mr1974898lfv.26.1624546668126; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:47 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 13/17] drm/msm/dpu: simplify DPU_SSPP features checks Date: Thu, 24 Jun 2021 17:57:29 +0300 Message-Id: <20210624145733.2561992-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DPU_SSPP_CSC_ANY denoting any CSC block. As we are at it, rewrite DPU_SSPP_SCALER (any scaler) to use BIT(x) instead of hand-coded bitshifts. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 +++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-- 2 files changed, 12 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index e8939d7387cb..fcf131f77df2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -25,11 +25,17 @@ struct dpu_hw_pipe; /** * Define all scaler feature bits in catalog */ -#define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \ - (1UL << DPU_SSPP_SCALER_QSEED2) | \ - (1UL << DPU_SSPP_SCALER_QSEED3) | \ - (1UL << DPU_SSPP_SCALER_QSEED3LITE) | \ - (1UL << DPU_SSPP_SCALER_QSEED4)) +#define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \ + BIT(DPU_SSPP_SCALER_QSEED2) | \ + BIT(DPU_SSPP_SCALER_QSEED3) | \ + BIT(DPU_SSPP_SCALER_QSEED3LITE) | \ + BIT(DPU_SSPP_SCALER_QSEED4)) + +/* + * Define all CSC feature bits in catalog + */ +#define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \ + BIT(DPU_SSPP_CSC_10BIT)) /** * Component indices diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index c4a76dd6dbd5..4658410eedfb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -970,8 +970,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (DPU_FORMAT_IS_YUV(fmt) && (!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) || - !(pdpu->pipe_hw->cap->features & (BIT(DPU_SSPP_CSC) - | BIT(DPU_SSPP_CSC_10BIT))))) { + !(pdpu->pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) { DPU_DEBUG_PLANE(pdpu, "plane doesn't have scaler/csc for yuv\n"); return -EINVAL; From patchwork Thu Jun 24 14:57:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466362 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536930jao; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxEh1lfjr6APT0j7IQGstXTsIWijfMHbe1WObD6uViUhUyBJwbp+dlkNrXKhmu9G+STIXYC X-Received: by 2002:a02:7348:: with SMTP id a8mr4982698jae.116.1624546674537; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546674; cv=none; d=google.com; s=arc-20160816; b=xUPaOO4xHy9JHxQg84GrAgvwx5GXZL/xFeHZEHuyZz4UzAiKghipI3OxIFC7BCpn1g Kwdp94Asjru5E6nd+JZCH/j6hc/ghshBNudiNf63ArzhPflLANgE6LEzdswtQYjKkBDr /ObdRdh0KLkrz64R8rvOLYwsEWFxPqBtLNCM9Eb+3xee1AeLJv/3zcTXP8h535UBN4TK ZO+i0X9hTXYqTa8Pfq1ON6f+x0e+3uoeqr/dgirxAUeh27H3csVeqW1kjoyxdIs3N8wi CKowKbAlUjheVSBY+tHMVkKh0dKqMhoWVVI1e9xIwt/Z1wzh/G4Wrcbhn1AJ4cER02tv qj8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4naGYo6Q7vXKVyJFMwcq6Oq3/UZm+MxRt8NyXrzXPuc=; b=zXv600CAOAqH+G9rsPi16vwj9auRo07Qq0lDRD7R//tSCfMZXFuc05OdaJ/NdxOHIW oIQ+ie4tBFlAdkCpTwoM8dW1/oXzu8d4d//qrKiI42lEWYaincDYAw1cp2iWeZRYMjVx 9YjyBHtKtQXBqf61gDJ/0npqzbhrpXOFlpPKdiGU/N5v+vH+iTgp241do8DpwWM8/VrA ydsx7dBj14RbFrKRaBoAlYOO0T+fheHXvORtYziAhPWikFGSSF3Fa3/edJ3L//uqF2n2 v/Vh6pvnkOzPpqwCDw0eX7GqYecT1FMGDooT9PXCQggCdc15SEA6jBBoHEfJ+3hGuBZO xKQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b5Hb6gwl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.54; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b5Hb6gwl; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232285AbhFXPAM (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232300AbhFXPAK (ORCPT ); Thu, 24 Jun 2021 11:00:10 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FD44C061760 for ; Thu, 24 Jun 2021 07:57:50 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id u2so2881879ljo.1 for ; Thu, 24 Jun 2021 07:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4naGYo6Q7vXKVyJFMwcq6Oq3/UZm+MxRt8NyXrzXPuc=; b=b5Hb6gwlVgE7E9fxC+jhksQM3CacT3Ee6wIxCO13yES6cmq1+Bbv8XdeJS2xvX0KPy PTYO7f78kcfA0heSnreu8XuKWPgKbl7iEKlkD5RvKvvJRv0lamgXKusE7aVtr1qjnKhJ ze//Csgb+Kr0zTp5r+ucjAUc1M0ds+SPafSqVCK2jy2aRJcO1vnPxOseAQYVI9yFAeM1 ton8nZ1ywugAr93GNZ7VE0XdWX4nK/n8lAKqZ1henNgcloTJapbya73DBZpJa8/HuKEa OP79Ki8flUDDReVM+sAbi3vKmG1O+PxbSslsfbUTAtZMGffedlNEDWK7BR133009ENE2 eUgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4naGYo6Q7vXKVyJFMwcq6Oq3/UZm+MxRt8NyXrzXPuc=; b=cvJ5l7gTICXOEtiVgcbfDrOTImdeFpy8YJfYgSmbOcmKysVqR0fDkxXGYYoqacYU1h 3Z5FtU1wuEXBwWz9yj8S09gFtWp4JIQRRyKb7nzaBgnk5WEr81Mt/UKjGclfPkx59GZX eHKdqkkdRcB7ivLTafx0J3tvSzZDV5Fu84u/ou7VbYvMwdgzOxvjN4h7/fXEdg++wZ9N Gvnui/duPxkckwvdot4fiTIFbuQYwwnGYzmv3yK3/avj48ai29daFnCJF7MawHqUheBH q35wtwYQYyKSAQShh9danA9XW8AeLGCg0LCF5uOtfJAwRGrSDvRKhWxSaw3f7uuBlsfX 180Q== X-Gm-Message-State: AOAM5331aFg11Ma0qOKY2Ff32tVASiAxO7mA+bbfYHXLGzV4H5GJPjE/ slyaWWTTsiwp+MgVfM2qKSyuZQ== X-Received: by 2002:a2e:8748:: with SMTP id q8mr891051ljj.508.1624546668845; Thu, 24 Jun 2021 07:57:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:48 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 14/17] drm/msm/dpu: do not limit the zpos property Date: Thu, 24 Jun 2021 17:57:30 +0300 Message-Id: <20210624145733.2561992-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Stop limiting zpos property values, we use normalized_zpos anyway. And nothing stops userspace from assigning several planes to a single zpos (it is a userspace bug, but the kernel is forgiving about it). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4658410eedfb..8a8727ff7645 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -44,7 +44,6 @@ #define DPU_NAME_SIZE 12 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) -#define DPU_ZPOS_MAX 255 /* multirect rect index */ enum { @@ -1375,7 +1374,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); - int zpos_max = DPU_ZPOS_MAX; uint32_t num_formats; int ret = -EINVAL; @@ -1413,14 +1411,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->catalog = kms->catalog; - if (kms->catalog->mixer_count && - kms->catalog->mixer[0].sblk->maxblendstages) { - zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1; - if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1) - zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1; - } - - ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max); + ret = drm_plane_create_zpos_property(plane, 0, 0, 255); if (ret) DPU_ERROR("failed to install zpos property, rc = %d\n", ret); From patchwork Thu Jun 24 14:57:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466363 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536944jao; Thu, 24 Jun 2021 07:57:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyL74Ya8huZg38tyvaM7GOeBIpL32xNaelytBKTIQUwb4XTTjatWVjUH/ymLfnSiVw42JFF X-Received: by 2002:a5d:85c1:: with SMTP id e1mr4409104ios.18.1624546674973; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546674; cv=none; d=google.com; s=arc-20160816; b=CmYo7V8A0bkFDBUKCHOK7dp+ZsmUUWb8e6z1Tza0rG2nNFScpxERpCNo0UrPi8zT4R xt2QMx/S2WsNNVHVm+7A56R0AS8XCv8L73/bZyU/XymP1rL6nBhTCDFkafM2Vdvd3dBs CjVNDoa+zfGxi6TpynAZsGjAOOSeuTo/OXOHRY8qlprGQymuDW5+bU/AXe27BDXcuayF zjXq5d6O3Q+vVOLg0naEIsCAdPO6eBn9H+YDPvWFCMYatE6agVU7BsOTnNwA8eVX4bCr SKd0H0e/U3rJXIdsL/UD1r2H3iALRo9nyRKHmTZTlqC9DzELdy/SvvGcCHgPuX4z6pPe skjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RvPUwkcU8YKdVpw0wmyULc3mE/3A3bYC7lrOVQW/d7g=; b=AppLy3/d+bUWynJk6D3w7MksdbcCgYf1l0v7hAbeuRBDJeKYxD+tbnNfx/ThycSwiZ QcJOA5ml1YgfpLmz+pVtddO72BC2oGcj6nUoTwjjNdyrlX9DL1Xwd0DCzuuKJ5iYI612 wNDR4eq//nar1+paCJ//YKuTXIyDTw79AFXGh9jBjb13VpGxjqYPEzX5SBtrycDLhh5Q wrPRFMglgcz05ll3pbKErqBGJhTv/K+At0FozV37gBgwdO+LCuYANgI33RCAxGrSlMS2 4PyYJEJkD6MMOw9fVsqHHMG09BAJt+WMaY4jO3vwQS27vWzys79r3Vz0QEwGCo6Bu53o qjnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i+PSGyzr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j25si3607720jaj.93.2021.06.24.07.57.54; Thu, 24 Jun 2021 07:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i+PSGyzr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232296AbhFXPAM (ORCPT + 17 others); Thu, 24 Jun 2021 11:00:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232235AbhFXPAL (ORCPT ); Thu, 24 Jun 2021 11:00:11 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DE11C061756 for ; Thu, 24 Jun 2021 07:57:51 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id i13so10789795lfc.7 for ; Thu, 24 Jun 2021 07:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RvPUwkcU8YKdVpw0wmyULc3mE/3A3bYC7lrOVQW/d7g=; b=i+PSGyzrpBs3DlVNlxKzljj/zSHJcFHpZsYbN5lbz4IL6zU67zg8J5Fb0t1ZH/R4tC CvWGbZ0mBowetCnqUvVAhIfO5Asx/O2P2hmm41UoXjEw6LrMA/VM59bidgrQDfRVV74f P8VyoJu5pcZdlHRIvoOvxOkM/tFoNy2Y1EjqVKkV+kEOPMFSupzMYH5/pylovJtHXNsc /U/TiNpzzXGnrAW2TcbQ4h1azhugDRNnZAolQcZXcEYhrrFyoTqZS9lvx0yPqE1OGvyR ZtErtpwBmPpG5R7hIivwVp6LeU3rUwK0JMJi7l3SVy+XPvjLbVe4jJXJ1Ibmlrwj9+2o OqwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RvPUwkcU8YKdVpw0wmyULc3mE/3A3bYC7lrOVQW/d7g=; b=hbwB+t5aUcclebyeUkipl+zjdCHF67pAM9yxyg1/k9F7undGP3jdm6o/u/wKQiGAf9 E8PF0T7CuUS8bjB+3xpay0ddkEzsEFHvPqCIOai9LD6jpQ2NGIQTOcMruYr3ag4Pxn0q HMZHvtz4sEZKRxDL8oVaz45EZZpEXe3NSC2/d+hDsmnoYNYsKVU8OhWv4atHJpmMmze2 8IvRfpty0MgZf/ACqNLLjsBQcqbflFVSLEg38rQRquBl+UB48GnS6vnj0Mc2TZmMqH0v 1g+HxKruDeXbBuQzHGMFSX4WvbTgLv10xqQdddgpG5L+hsZv6wJrccsc0QprSDMce1Ti iU3Q== X-Gm-Message-State: AOAM530R13lOV9TZUWBnnqABgeB7GkEgByyjsblbBWp/9nCKdbKXDwxf 7M0xJNBujzZvvv0adf1M0AA0zQ== X-Received: by 2002:ac2:5982:: with SMTP id w2mr4223270lfn.80.1624546669599; Thu, 24 Jun 2021 07:57:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e17sm306329ljn.125.2021.06.24.07.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 07:57:49 -0700 (PDT) From: Dmitry Baryshkov To: Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar Cc: Jonathan Marek , Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 15/17] drm/msm/dpu: add support for SSPP allocation to RM Date: Thu, 24 Jun 2021 17:57:31 +0300 Message-Id: <20210624145733.2561992-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> References: <20210624145733.2561992-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for handling and allocting SSPP blocks through the resource manager. Handling code is not converted to use it though. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 10 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 81 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 6 ++ 5 files changed, 104 insertions(+), 12 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index fcf131f77df2..1bbe178f6db5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -387,6 +387,16 @@ struct dpu_hw_pipe { struct dpu_hw_sspp_ops ops; }; +/** + * to_dpu_hw_pipe - convert base object dpu_hw_base to container + * @hw: Pointer to base hardware block + * return: Pointer to hardware block container + */ +static inline struct dpu_hw_pipe *to_dpu_hw_pipe(struct dpu_hw_blk *hw) +{ + return container_of(hw, struct dpu_hw_pipe, base); +} + /** * dpu_hw_sspp_init - initializes the sspp hw driver object. * Should be called once before accessing every pipe. diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index ab65c817eb42..04a2ab548f54 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -159,6 +159,7 @@ struct dpu_global_state { uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; + uint32_t pipe_to_plane_id[SSPP_MAX - SSPP_NONE]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8a8727ff7645..70e3eb165363 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1235,8 +1235,6 @@ static void dpu_plane_destroy(struct drm_plane *plane) /* this will destroy the states as well */ drm_plane_cleanup(plane); - dpu_hw_sspp_destroy(pdpu->pipe_hw); - kfree(pdpu); } } @@ -1390,14 +1388,13 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->pipe = pipe; /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, false); - if (IS_ERR(pdpu->pipe_hw)) { - DPU_ERROR("[%u]SSPP init failed\n", pipe); - ret = PTR_ERR(pdpu->pipe_hw); + if (!kms->rm.sspp_blks[pipe - SSPP_NONE]) goto clean_plane; - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { + pdpu->pipe_hw = to_dpu_hw_pipe(kms->rm.sspp_blks[pipe - SSPP_NONE]); + + if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); - goto clean_sspp; + goto clean_plane; } format_list = pdpu->pipe_hw->cap->sblk->format_list; @@ -1407,7 +1404,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, format_list, num_formats, supported_format_modifiers, type, NULL); if (ret) - goto clean_sspp; + goto clean_plane; pdpu->catalog = kms->catalog; @@ -1433,9 +1430,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pipe, plane->base.id); return plane; -clean_sspp: - if (pdpu && pdpu->pipe_hw) - dpu_hw_sspp_destroy(pdpu->pipe_hw); clean_plane: kfree(pdpu); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index f9c83d6e427a..9772427eae6b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -8,6 +8,7 @@ #include "dpu_hw_lm.h" #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" +#include "dpu_hw_sspp.h" #include "dpu_hw_intf.h" #include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" @@ -35,6 +36,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) { int i; + for (i = 0; i < ARRAY_SIZE(rm->sspp_blks); i++) { + struct dpu_hw_pipe *hw; + + if (rm->sspp_blks[i]) { + hw = to_dpu_hw_pipe(rm->sspp_blks[i]); + dpu_hw_sspp_destroy(hw); + } + } for (i = 0; i < ARRAY_SIZE(rm->pingpong_blks); i++) { struct dpu_hw_pingpong *hw; @@ -166,6 +175,24 @@ int dpu_rm_init(struct dpu_rm *rm, rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; } + for (i = 0; i < cat->sspp_count; i++) { + struct dpu_hw_pipe *hw; + const struct dpu_sspp_cfg *sspp = &cat->sspp[i]; + + if (sspp->id <= SSPP_NONE || sspp->id >= SSPP_MAX) { + DPU_ERROR("skip sspp %d with invalid id\n", sspp->id); + continue; + } + hw = dpu_hw_sspp_init(sspp->id, mmio, cat, false); + if (IS_ERR_OR_NULL(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed sspp object creation: err %d\n", + rc); + goto fail; + } + rm->sspp_blks[sspp->id - SSPP_NONE] = &hw->base; + } + for (i = 0; i < cat->intf_count; i++) { struct dpu_hw_intf *hw; const struct dpu_intf_cfg *intf = &cat->intf[i]; @@ -660,3 +687,57 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, return num_blks; } + +enum dpu_sspp dpu_rm_get_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t plane_id, bool yuv, bool scale) +{ + int i; + enum dpu_sspp pipe = SSPP_NONE; + struct dpu_hw_pipe *pipe_hw; + bool retry = false; + +retry_loop: + for (i = 0; i < ARRAY_SIZE(rm->sspp_blks) && pipe == SSPP_NONE; i++) { + if (!rm->sspp_blks[i]) + continue; + if (reserved_by_other(global_state->pipe_to_plane_id, i, plane_id)) + continue; + + pipe_hw = to_dpu_hw_pipe(rm->sspp_blks[i]); + + /* skip incompatible planes */ + if (scale && !(pipe_hw->cap->features & DPU_SSPP_SCALER)) + continue; + + if (yuv && (!(pipe_hw->cap->features & DPU_SSPP_SCALER) || + !(pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) + continue; + + /* For non-yuv, non-scaled planes try to find simple (DMA) + * plane, fallback to VIG on a second try. + * + * This way we'd leave VIG pipes to be later used for YUV formats. + */ + + if (!scale && !yuv && !retry && + (pipe_hw->cap->features & (DPU_SSPP_SCALER | DPU_SSPP_CSC_ANY))) + continue; + + pipe = i + SSPP_NONE; + }; + + if (!scale && !yuv && !retry && pipe == SSPP_NONE) { + retry = true; + goto retry_loop; + } + + if (pipe != SSPP_NONE) + global_state->pipe_to_plane_id[pipe - SSPP_NONE] = plane_id; + + return pipe; +} + +void dpu_rm_release_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, struct drm_plane *plane) +{ + _dpu_rm_clear_mapping(global_state->pipe_to_plane_id, + ARRAY_SIZE(global_state->pipe_to_plane_id), plane->base.id); +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..abd20509f963 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -16,6 +16,7 @@ struct dpu_global_state; /** * struct dpu_rm - DPU dynamic hardware resource manager * @pingpong_blks: array of pingpong hardware resources + * @sspp_blks: array of sspp hardware resources * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources @@ -25,6 +26,7 @@ struct dpu_global_state; */ struct dpu_rm { struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; + struct dpu_hw_blk *sspp_blks[SSPP_MAX - SSPP_NONE]; struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; @@ -88,5 +90,9 @@ void dpu_rm_release(struct dpu_global_state *global_state, int dpu_rm_get_assigned_resources(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); + +enum dpu_sspp dpu_rm_get_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t plane_id, bool yuv, bool scale); +void dpu_rm_release_sspp(struct dpu_rm *rm, struct dpu_global_state *global_state, struct drm_plane *plane); + #endif /* __DPU_RM_H__ */ From patchwork Thu Jun 24 14:57:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466365 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536958jao; 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This allows one userspace to use any plane without caring if it supports scaler or YUV formats. The kernel space will select the appropriate SSPP pipe or return an error if we run out of resources. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 84 +++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 226 +++++++++++++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 23 +-- 3 files changed, 211 insertions(+), 122 deletions(-) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b62e8e4e8d0a..002bdf0ecd00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -206,6 +206,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); + enum dpu_sspp pipe; memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { @@ -216,14 +217,19 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); - set_bit(dpu_plane_pipe(plane), fetch_active); + if (WARN_ON(!pstate->pipe_hw)) + continue; + + pipe = pstate->pipe_hw->idx; + + flush_mask = ctl->ops.get_bitmask_sspp(ctl, pipe); + set_bit(pipe, fetch_active); DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", crtc->base.id, pstate->stage, plane->base.id, - dpu_plane_pipe(plane) - SSPP_VIG0, + pipe - SSPP_VIG0, state->fb ? state->fb->base.id : -1); format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); @@ -233,13 +239,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, stage_idx = zpos_cnt[pstate->stage]++; stage_cfg->stage[pstate->stage][stage_idx] = - dpu_plane_pipe(plane); + pipe; stage_cfg->multirect_index[pstate->stage][stage_idx] = pstate->multirect_index; trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, pstate, stage_idx, - dpu_plane_pipe(plane) - SSPP_VIG0, + pipe - SSPP_VIG0, format->base.pixel_format, fb ? fb->modifier : 0); @@ -875,13 +881,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, drm_crtc_vblank_on(crtc); } -struct plane_state { - struct dpu_plane_state *dpu_pstate; - const struct drm_plane_state *drm_pstate; - int stage; - u32 pipe_id; -}; - static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -889,17 +888,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct plane_state *pstates; - const struct drm_plane_state *pstate; + struct dpu_plane_state **pstates; + + struct drm_plane_state *plane_state; struct drm_plane *plane; struct drm_display_mode *mode; - int cnt = 0, rc = 0, mixer_width = 0, i; + int rc = 0, mixer_width = 0, i; + unsigned int num_planes, max_zpos = 0; + struct drm_rect dst; struct drm_rect crtc_rect = { 0 }; - pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); + num_planes = DPU_STAGE_MAX * 4; + pstates = kcalloc(num_planes, sizeof(*pstates), GFP_KERNEL); if (!crtc_state->enable || !crtc_state->active) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", @@ -926,28 +929,26 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc_rect.y2 = mode->vdisplay; /* get plane state for all drm planes associated with crtc state */ - drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { - struct drm_rect dst, clip = crtc_rect; - - if (IS_ERR_OR_NULL(pstate)) { - rc = PTR_ERR(pstate); + drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) { + rc = PTR_ERR(plane_state); DPU_ERROR("%s: failed to get plane%d state, %d\n", dpu_crtc->name, plane->base.id, rc); goto end; } - if (cnt >= DPU_STAGE_MAX * 4) + + if (plane_state->normalized_zpos >= num_planes) continue; - pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); - pstates[cnt].drm_pstate = pstate; - pstates[cnt].stage = pstate->normalized_zpos; + pstates[plane_state->normalized_zpos] = to_dpu_plane_state(plane_state); - dpu_plane_clear_multirect(pstate); + dpu_plane_clear_multirect(plane_state); - cnt++; + max_zpos = max(max_zpos, plane_state->normalized_zpos); - dst = drm_plane_state_dest(pstate); - if (!drm_rect_intersect(&clip, &dst)) { + dst = drm_plane_state_dest(plane_state); + if (!drm_rect_intersect(&dst, &crtc_rect)) { DPU_ERROR("invalid vertical/horizontal destination\n"); DPU_ERROR("display: " DRM_RECT_FMT " plane: " DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), @@ -957,8 +958,14 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } - for (i = 0; i < cnt; i++) { - int z_pos = pstates[i].stage; + for (i = 0; i <= max_zpos; i++) { + struct dpu_plane_state *pstate = pstates[i]; + int z_pos; + + if (!pstate) + continue; + + z_pos = pstate->base.normalized_zpos; /* verify z_pos setting before using it */ if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { @@ -968,7 +975,20 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, goto end; } - pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; + plane = pstate->base.plane; + rc = dpu_plane_set_pipe(plane, pstate); + if (rc) { + DPU_ERROR("%s: error setting pipe for %s\n", dpu_crtc->name, plane->name); + goto end; + } + + rc = dpu_plane_real_atomic_check(plane, state); + if (rc) { + DPU_ERROR("%s: error checking pipe for %s\n", dpu_crtc->name, plane->name); + goto end; + } + + pstates[i]->stage = z_pos + DPU_STAGE_0; DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 70e3eb165363..7b881dba8ad1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -100,7 +100,6 @@ struct dpu_plane { enum dpu_sspp pipe; - struct dpu_hw_pipe *pipe_hw; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -299,6 +298,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u64 qos_lut; u32 total_fl = 0, lut_usage; @@ -330,7 +330,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); + pstate->pipe_hw->ops.setup_creq_lut(pstate->pipe_hw, qos_lut); } /** @@ -342,6 +342,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u32 danger_lut, safe_lut; @@ -381,7 +382,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, + pstate->pipe_hw->ops.setup_danger_safe_lut(pstate->pipe_hw, danger_lut, safe_lut); } @@ -395,14 +396,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pstate->pipe_hw->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pdpu->pipe_hw->cap->sblk->danger_vblank; + pstate->pipe_hw->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -428,7 +430,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, + pstate->pipe_hw->ops.setup_qos_ctrl(pstate->pipe_hw, &pipe_qos_cfg); } @@ -441,18 +443,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; + ot_params.xin_id = pstate->pipe_hw->cap->xin_id; + ot_params.num = pstate->pipe_hw->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; + ot_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -465,14 +468,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, static void _dpu_plane_set_qos_remap(struct drm_plane *plane) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_qos_params qos_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; + qos_params.clk_ctrl = pstate->pipe_hw->cap->clk_ctrl; + qos_params.xin_id = pstate->pipe_hw->cap->xin_id; + qos_params.num = pstate->pipe_hw->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -499,11 +503,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); else if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pdpu->pipe_hw->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, + else if (pstate->pipe_hw->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pstate->pipe_hw->idx, &pipe_cfg->layout, pstate->multirect_index); - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, + pstate->pipe_hw->ops.setup_sourceaddress(pstate->pipe_hw, pipe_cfg, pstate->multirect_index); } } @@ -549,7 +553,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pdpu->pipe_hw->cap->features & + if (pstate->pipe_hw->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -608,6 +612,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) { + struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state); const struct dpu_csc_cfg *csc_ptr; if (!pdpu) { @@ -618,7 +623,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe_hw->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; @@ -673,8 +678,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); /* update sspp */ - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, + if (fmt && pstate->pipe_hw->ops.setup_solidfill) { + pstate->pipe_hw->ops.setup_solidfill(pstate->pipe_hw, (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), pstate->multirect_index); @@ -687,23 +692,23 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, drm_rect_height(&pipe_cfg.dst_rect); _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); - if (pdpu->pipe_hw->ops.setup_format) - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, + if (pstate->pipe_hw->ops.setup_format) + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, DPU_SSPP_SOLID_FILL, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_rects) - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->pipe_hw->ops.setup_rects) + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw, &pipe_cfg, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_pe) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + if (pstate->pipe_hw->ops.setup_pe) + pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw, &pstate->pixel_ext); - if (pdpu->pipe_hw->ops.setup_scaler && + if (pstate->pipe_hw->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, + pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw, &pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); } @@ -830,18 +835,6 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) return 0; } -/** - * dpu_plane_get_ctl_flush - get control flush for the given plane - * @plane: Pointer to drm plane structure - * @ctl: Pointer to hardware control driver - * @flush_sspp: Pointer to sspp flush control word - */ -void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, - u32 *flush_sspp) -{ - *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane)); -} - static int dpu_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { @@ -922,8 +915,86 @@ static bool dpu_plane_validate_src(struct drm_rect *src, drm_rect_equals(fb_rect, src); } +int dpu_plane_set_pipe(struct drm_plane *plane, struct dpu_plane_state *pstate) +{ + struct dpu_kms *kms = _dpu_plane_get_kms(plane); + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_global_state *global_state = dpu_kms_get_global_state(pstate->base.state); + enum dpu_sspp pipe; + + if (pdpu->pipe != SSPP_NONE) { + pipe = pdpu->pipe; + } else { + bool yuv, scale; + struct drm_rect src, dst; + + yuv = pstate->base.fb ? DPU_FORMAT_IS_YUV (to_dpu_format(msm_framebuffer_format(pstate->base.fb))) : false; + src = drm_plane_state_src(&pstate->base); + dst = drm_plane_state_dest(&pstate->base); + scale = (drm_rect_width(&src) >> 16 != drm_rect_width(&dst)) || + (drm_rect_height(&src) >> 16 != drm_rect_height(&dst)); + + pipe = dpu_rm_get_sspp(&kms->rm, global_state, plane->base.id, yuv, scale); + DRM_DEBUG_ATOMIC("PLANE %d got SSPP %d\n", plane->base.id, pipe); + } + + if (pipe == SSPP_NONE || pipe >= SSPP_MAX || !kms->rm.sspp_blks[pipe - SSPP_NONE]) + return -EINVAL; + + pstate->pipe_hw = to_dpu_hw_pipe(kms->rm.sspp_blks[pipe - SSPP_NONE]); + + return 0; +} + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) +{ + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_global_state *global_state = dpu_kms_get_global_state(state); + + if (!new_plane_state->fb) + new_plane_state->visible = false; + + /* + * Free unused pipes during atomic_check. They might be picked up + * later, during pipes reallocation. The real checks will be executed + * later, from dpu_plane_real_atomic_check() called from + * dpu_crtc_atomic_check when the pipes are allocated. + */ + if (!new_plane_state->visible && + pstate->pipe_hw != NULL) { + /* + * If the pipe was statically allocated during dpu_plane_init, do not + * touch dpu_rm here. + */ + if (pdpu->pipe == SSPP_NONE) { + DRM_DEBUG_ATOMIC("PLANE %d released SSPP %d\n", plane->base.id, pstate->pipe_hw->idx); + dpu_rm_release_sspp(&dpu_kms->rm, global_state, plane); + pstate->pipe_hw = NULL; + } + } + + return 0; +} + +static bool dpu_plane_check_sspp_format(struct dpu_hw_pipe *pipe_hw, u32 format) +{ + int i; + + for (i = 0; i < pipe_hw->cap->sblk->num_formats; i++) { + if (format == pipe_hw->cap->sblk->format_list[i]) + return true; + } + + return false; +} + +int dpu_plane_real_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -939,10 +1010,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - min_scale = FRAC_16_16(1, pdpu->pipe_hw->cap->sblk->maxupscale); + min_scale = FRAC_16_16(1, pstate->pipe_hw->cap->sblk->maxupscale); ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, - pdpu->pipe_hw->cap->sblk->maxdwnscale << 16, + pstate->pipe_hw->cap->sblk->maxdwnscale << 16, true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); @@ -951,6 +1022,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; + if (!dpu_plane_check_sspp_format(pstate->pipe_hw, new_plane_state->fb->format->format)) { + DPU_ERROR("Format %p4cc not supported by the selected SSPP %d\n", + &new_plane_state->fb->format->format, pstate->pipe_hw->idx); + + return -EINVAL; + } + src.x1 = new_plane_state->src_x >> 16; src.y1 = new_plane_state->src_y >> 16; src.x2 = src.x1 + (new_plane_state->src_w >> 16); @@ -968,8 +1046,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; if (DPU_FORMAT_IS_YUV(fmt) && - (!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) || - !(pdpu->pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) { + (!(pstate->pipe_hw->cap->features & DPU_SSPP_SCALER) || + !(pstate->pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) { DPU_DEBUG_PLANE(pdpu, "plane doesn't have scaler/csc for yuv\n"); return -EINVAL; @@ -1030,8 +1108,8 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pdpu->pipe_hw && pdpu->csc_ptr && pdpu->pipe_hw->ops.setup_csc) - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, pdpu->csc_ptr); + else if (pstate->pipe_hw && pdpu->csc_ptr && pstate->pipe_hw->ops.setup_csc) + pstate->pipe_hw->ops.setup_csc(pstate->pipe_hw, pdpu->csc_ptr); /* flag h/w flush complete */ if (plane->state) @@ -1099,15 +1177,15 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) return; } - if (pdpu->pipe_hw->ops.setup_rects) { - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->pipe_hw->ops.setup_rects) { + pstate->pipe_hw->ops.setup_rects(pstate->pipe_hw, &pipe_cfg, pstate->multirect_index); } - if (pdpu->pipe_hw->ops.setup_pe && + if (pstate->pipe_hw->ops.setup_pe && (pstate->multirect_index != DPU_SSPP_RECT_1)) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + pstate->pipe_hw->ops.setup_pe(pstate->pipe_hw, &pstate->pixel_ext); /** @@ -1115,19 +1193,19 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pdpu->pipe_hw->ops.setup_scaler && + if (pstate->pipe_hw->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, + pstate->pipe_hw->ops.setup_scaler(pstate->pipe_hw, &pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); - if (pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect( - pdpu->pipe_hw, + if (pstate->pipe_hw->ops.setup_multirect) + pstate->pipe_hw->ops.setup_multirect( + pstate->pipe_hw, pstate->multirect_index, pstate->multirect_mode); - if (pdpu->pipe_hw->ops.setup_format) { + if (pstate->pipe_hw->ops.setup_format) { unsigned int rotation; src_flags = 0x0; @@ -1144,10 +1222,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_FLIP_UD; /* update format */ - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, + pstate->pipe_hw->ops.setup_format(pstate->pipe_hw, fmt, src_flags, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_cdp) { + if (pstate->pipe_hw->ops.setup_cdp) { struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg)); @@ -1161,7 +1239,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg); + pstate->pipe_hw->ops.setup_cdp(pstate->pipe_hw, cdp_cfg); } /* update csc */ @@ -1201,6 +1279,8 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) pstate->multirect_mode); pstate->pending = true; + + pstate->pipe_hw = NULL; } static void dpu_plane_atomic_update(struct drm_plane *plane, @@ -1357,11 +1437,6 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { .atomic_update = dpu_plane_atomic_update, }; -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) -{ - return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; -} - /* initialize plane */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, @@ -1387,19 +1462,22 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, plane = &pdpu->base; pdpu->pipe = pipe; - /* initialize underlying h/w driver */ - if (!kms->rm.sspp_blks[pipe - SSPP_NONE]) - goto clean_plane; - pdpu->pipe_hw = to_dpu_hw_pipe(kms->rm.sspp_blks[pipe - SSPP_NONE]); - - if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); - goto clean_plane; + if (pdpu->pipe == SSPP_NONE) { + format_list = kms->catalog->caps->format_list; + num_formats = kms->catalog->caps->num_formats; + } else if (pdpu->pipe < SSPP_MAX) { + struct dpu_hw_pipe *pipe_hw; + + if (!kms->rm.sspp_blks[pdpu->pipe - SSPP_NONE]) + return ERR_PTR(-EINVAL); + pipe_hw = to_dpu_hw_pipe(kms->rm.sspp_blks[pdpu->pipe - SSPP_NONE]); + format_list = pipe_hw->cap->sblk->format_list; + num_formats = pipe_hw->cap->sblk->num_formats; + } else { + return ERR_PTR(-EINVAL); } - format_list = pdpu->pipe_hw->cap->sblk->format_list; - num_formats = pdpu->pipe_hw->cap->sblk->num_formats; - + /* initialize underlying h/w driver */ ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, supported_format_modifiers, type, NULL); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index b0c08bd54170..0d964512f8e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -45,6 +45,8 @@ struct dpu_plane_state { struct dpu_hw_pipe_cdp_cfg cdp_cfg; u64 plane_fetch_bw; u64 plane_clk; + + struct dpu_hw_pipe *pipe_hw; }; /** @@ -60,22 +62,6 @@ struct dpu_multirect_plane_states { #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) -/** - * dpu_plane_pipe - return sspp identifier for the given plane - * @plane: Pointer to DRM plane object - * Returns: sspp identifier of the given plane - */ -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); - -/** - * dpu_plane_get_ctl_flush - get control flush mask - * @plane: Pointer to DRM plane object - * @ctl: Pointer to control hardware - * @flush_sspp: Pointer to sspp flush control word - */ -void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, - u32 *flush_sspp); - /** * dpu_plane_flush - final plane operations before commit flush * @plane: Pointer to drm plane structure @@ -129,4 +115,9 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable); static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {} #endif +int dpu_plane_set_pipe(struct drm_plane *plane, struct dpu_plane_state *pstate); + +int dpu_plane_real_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state); + #endif /* _DPU_PLANE_H_ */ From patchwork Thu Jun 24 14:57:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 466364 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp536963jao; Thu, 24 Jun 2021 07:57:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJziGeth24AHpetNV5Ye3gnCzow/bDGFkaTePuyJHD40RYWLn70KeAqn+7U9KLZhwKg/cdeM X-Received: by 2002:a05:6e02:1387:: with SMTP id d7mr3936094ilo.252.1624546676029; Thu, 24 Jun 2021 07:57:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624546676; cv=none; d=google.com; s=arc-20160816; b=xq73O+SBcIJRJAPC7zEBrL5+EmYI9JQnkvftod2NyFG00xWWmhPIUF59zFeBfL+p3Z cx1ux9aHVqvocfsubYhZttEEv7jyU+DWu/zkAG0JR0LhhWPxVOZ+o/Ah39m8bfw2eSyD YQWJCdstg4sR3A2koEiAq0vTx9wJe5XEiOeJs9NC/netObQ15Nvk5Ba69Mzj40IswA7k xwyq/ifltKX7GmEI0r/pQYgA8847Qkr8cXoBqc8roT8FwVHlqcN9YOhSYh6g4W139D7I VRrqTfAs1D2UOE533IsGou7Oumv+Gis/0/c8svwvwzK9LbKegRuLspyxMCEzzM7FfuX/ 1TcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7LSD+0UwStyFklWVh+hnsHGUn+QhdxgAc/M+GEYmbyE=; b=W/LZMyTDYofHUGq9MU32r8HNeq9wYIxJhBVyWdYdF6/nCGGHvZdgKFJgsMj5ivZGwa +0pxBk46ELCzsqO2/NjoKiDbI6r/vHp1TLAAooqmI0CxZvprHJFupZGLz7SuM78vEWZN qPKeYEbMI1uegierLTIES99GRgFhSqLwul1dIOUQ7V1d9h43BDwvN007KXymMfc+HxmK N6uijQ0vplQrsXk8LJN7AIvNRzrxQOwv4Fe/W2bttASOt5eppWI9h9eNn4uTB8GKmjug ZKvblJehz9zKUfSIgIAmtutycuDkfuCQzYw65FbMFZE2ZND2DDqxWEoC5aEBlLIfOC9X XQCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QgPVQOTt; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.30.2 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 66a1c8889cf3..08b47609a315 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -611,6 +611,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) for (i = 0; i < catalog->sspp_count; i++) { enum drm_plane_type type; +#if 0 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) && cursor_planes_idx < max_crtc_count) type = DRM_PLANE_TYPE_CURSOR; @@ -625,6 +626,19 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) plane = dpu_plane_init(dev, catalog->sspp[i].id, type, (1UL << max_crtc_count) - 1); +#else + if (primary_planes_idx < max_crtc_count) + type = DRM_PLANE_TYPE_PRIMARY; + else if (cursor_planes_idx < max_crtc_count) + type = DRM_PLANE_TYPE_CURSOR; + else + type = DRM_PLANE_TYPE_OVERLAY; + + DPU_DEBUG("Create virtual plane type %d \n", type); + + plane = dpu_plane_init(dev, SSPP_NONE, type, + (1UL << max_crtc_count) - 1); +#endif if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret = PTR_ERR(plane);