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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.03.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:03:53 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:19 +0200 Message-Id: <1534870966-9287-48-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PULL 47/74] hw/intc/apic: Switch away from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the apic away from using the old_mmio MemoryRegionOps accessor functions. Signed-off-by: Peter Maydell Message-Id: <20180803101943.23722-1-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/intc/apic.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) -- 1.8.3.1 diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 6fda52b..97ffdd8 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -650,31 +650,17 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } -static uint32_t apic_mem_readb(void *opaque, hwaddr addr) -{ - return 0; -} - -static uint32_t apic_mem_readw(void *opaque, hwaddr addr) -{ - return 0; -} - -static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val) -{ -} - -static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val) -{ -} - -static uint32_t apic_mem_readl(void *opaque, hwaddr addr) +static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) { DeviceState *dev; APICCommonState *s; uint32_t val; int index; + if (size < 4) { + return 0; + } + dev = cpu_get_current_apic(); if (!dev) { return 0; @@ -765,11 +751,17 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } -static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { DeviceState *dev; APICCommonState *s; int index = (addr >> 4) & 0xff; + + if (size < 4) { + return; + } + if (addr > 0xfff || !index) { /* MSI and MMIO APIC are at the same memory location, * but actually not on the global bus: MSI is on PCI bus @@ -880,10 +872,12 @@ static void apic_post_load(APICCommonState *s) } static const MemoryRegionOps apic_io_ops = { - .old_mmio = { - .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, - .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, }, - }, + .read = apic_mem_read, + .write = apic_mem_write, + .impl.min_access_size = 1, + .impl.max_access_size = 4, + .valid.min_access_size = 1, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, }; From patchwork Tue Aug 21 17:02:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144775 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5575244ljj; Tue, 21 Aug 2018 11:00:34 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYSex6LEhMMXH5yuJ/IvphXjRUKElZFawVtat+rqvj0HvjDenn4rqqQgfMDN2kWC0dL3CCh X-Received: by 2002:aed:25b4:: with SMTP id x49-v6mr6290230qtc.228.1534874434583; Tue, 21 Aug 2018 11:00:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534874434; cv=none; d=google.com; s=arc-20160816; b=ml0345gTXJK/9nmUXCFRx6Y482+ofQIpVXcWgP08Q9Tx7bUtKgNGNDt8S5wbtITwx/ PjcvEM7QFX9/7gM5yPL53i5q4CBSvFbsnZV6tLm9qA/jy1zKk3opI94YR7gL6kuyhuX6 x8tZsdUxooiTNlQngx8zwwJEgNGQc9msF/R+SyRZ6mdQ/N+xQvfzEW/GC0nUr5+ZGv5A pB9U3jKwl1p7ghOZDi3ac53+ubcdV1ivQ1lfCC3K3D3LjUJXcoPkxeA3LhnnH7wMnuGr vr9tDCeJ1mS/sRnwbJ8a2Ijf9L8cLdQ1BcTLgYGA+bHkBhe5csoLcq3cDR8HQaThvGex yyew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=XzdQb4myVIoMb9NuZHlHUKoiT3KZg77zsB0wbJSpUZA=; b=ZUWZFLF621Gy/Ux8gr+SvI5q9ZeugF8bKtfyUQnVPmO6xD0qJ+zTjtrPw7TJVJ3dWz CkjCw11gfu96d247PdG8yY4qOxcP3/3JzXlrbyuU7Zq7J3Kk3NBFJD15MV8hbxJlC5rq qNk4MYisn3uZEuHl3Z9m/KwdH6bxiNl2yuFP0aZWKPhyHPXFs8lnzGyIcn/7uyXYJzaj bkcLKllQ5fhESPVU/nBl4r7hd9cJE6AiXBdKfin6JJomCJ98ZqyKnNie1MOt7B+qXo3Z 5mS5ejApSPFsa9m9TqcYJWM8dSZlP/EGdvF2XnPcbHlS0U2zZjPcQYq5oCX3TptO525+ ynGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=JPIAALmX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:03 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:29 +0200 Message-Id: <1534870966-9287-58-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 57/74] ipmi: Use proper struct reference for BT vmstate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard The vmstate for isa_ipmi_bt was referencing into the bt structure, instead create a bt structure separate and use that. The version 1 of the BT transfer was fairly broken, if a migration occured during an IPMI operation, it is likely the migration would be corrupted because I misunderstood the VMSTATE_VBUFFER_UINT32() handling, I thought it handled transferring the length field, too. So I just remove support for that. I doubt anyone is using it at this point. This also removes the transfer of use_irq, since that should come from configuration. Signed-off-by: Corey Minyard Reviewed-by: Dr. David Alan Gilbert Message-Id: <1534798644-13587-1-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/ipmi/isa_ipmi_bt.c | 68 +++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 13 deletions(-) -- 1.8.3.1 diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c index e946030..8bbb1fa 100644 --- a/hw/ipmi/isa_ipmi_bt.c +++ b/hw/ipmi/isa_ipmi_bt.c @@ -22,6 +22,7 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qapi/error.h" #include "hw/hw.h" #include "hw/ipmi/ipmi.h" @@ -450,22 +451,63 @@ static void isa_ipmi_bt_realize(DeviceState *dev, Error **errp) isa_register_ioport(isadev, &iib->bt.io, iib->bt.io_base); } -static const VMStateDescription vmstate_ISAIPMIBTDevice = { - .name = TYPE_IPMI_INTERFACE, +static int ipmi_bt_vmstate_post_load(void *opaque, int version) +{ + IPMIBT *ib = opaque; + + /* Make sure all the values are sane. */ + if (ib->outpos >= MAX_IPMI_MSG_SIZE || ib->outlen >= MAX_IPMI_MSG_SIZE || + ib->outpos >= ib->outlen) { + qemu_log_mask(LOG_GUEST_ERROR, + "ipmi:bt: vmstate transfer received bad out values: %d %d\n", + ib->outpos, ib->outlen); + ib->outpos = 0; + ib->outlen = 0; + } + + if (ib->inlen >= MAX_IPMI_MSG_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, + "ipmi:bt: vmstate transfer received bad in value: %d\n", + ib->inlen); + ib->inlen = 0; + } + + return 0; +} + +const VMStateDescription vmstate_IPMIBT = { + .name = TYPE_IPMI_INTERFACE_PREFIX "bt", .version_id = 1, .minimum_version_id = 1, + .post_load = ipmi_bt_vmstate_post_load, + .fields = (VMStateField[]) { + VMSTATE_BOOL(obf_irq_set, IPMIBT), + VMSTATE_BOOL(atn_irq_set, IPMIBT), + VMSTATE_BOOL(irqs_enabled, IPMIBT), + VMSTATE_UINT32(outpos, IPMIBT), + VMSTATE_UINT32(outlen, IPMIBT), + VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE), + VMSTATE_UINT32(inlen, IPMIBT), + VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE), + VMSTATE_UINT8(control_reg, IPMIBT), + VMSTATE_UINT8(mask_reg, IPMIBT), + VMSTATE_UINT8(waiting_rsp, IPMIBT), + VMSTATE_UINT8(waiting_seq, IPMIBT), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_ISAIPMIBTDevice = { + .name = TYPE_IPMI_INTERFACE_PREFIX "isa-bt", + .version_id = 2, + .minimum_version_id = 2, + /* + * Version 1 had messed up the array transfer, it's not even usable + * because it used VMSTATE_VBUFFER_UINT32, but it did not transfer + * the buffer length, so random things would happen. + */ .fields = (VMStateField[]) { - VMSTATE_BOOL(bt.obf_irq_set, ISAIPMIBTDevice), - VMSTATE_BOOL(bt.atn_irq_set, ISAIPMIBTDevice), - VMSTATE_BOOL(bt.use_irq, ISAIPMIBTDevice), - VMSTATE_BOOL(bt.irqs_enabled, ISAIPMIBTDevice), - VMSTATE_UINT32(bt.outpos, ISAIPMIBTDevice), - VMSTATE_VBUFFER_UINT32(bt.outmsg, ISAIPMIBTDevice, 1, NULL, bt.outlen), - VMSTATE_VBUFFER_UINT32(bt.inmsg, ISAIPMIBTDevice, 1, NULL, bt.inlen), - VMSTATE_UINT8(bt.control_reg, ISAIPMIBTDevice), - VMSTATE_UINT8(bt.mask_reg, ISAIPMIBTDevice), - VMSTATE_UINT8(bt.waiting_rsp, ISAIPMIBTDevice), - VMSTATE_UINT8(bt.waiting_seq, ISAIPMIBTDevice), + VMSTATE_STRUCT(bt, ISAIPMIBTDevice, 1, vmstate_IPMIBT, IPMIBT), VMSTATE_END_OF_LIST() } }; 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:08 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:34 +0200 Message-Id: <1534870966-9287-63-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [PULL 62/74] i2c: pm_smbus: Clean up some style issues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard Fix some spacing issues, remove extraneous comments, add some defines instead of hard-coding numbers. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-2-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 58 ++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 20 deletions(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 0d26e0f..83c2377 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -22,8 +22,6 @@ #include "hw/i2c/pm_smbus.h" #include "hw/i2c/smbus.h" -/* no save/load? */ - #define SMBHSTSTS 0x00 #define SMBHSTCNT 0x02 #define SMBHSTCMD 0x03 @@ -32,19 +30,34 @@ #define SMBHSTDAT1 0x06 #define SMBBLKDAT 0x07 -#define STS_HOST_BUSY (1) -#define STS_INTR (1<<1) -#define STS_DEV_ERR (1<<2) -#define STS_BUS_ERR (1<<3) -#define STS_FAILED (1<<4) -#define STS_SMBALERT (1<<5) -#define STS_INUSE_STS (1<<6) -#define STS_BYTE_DONE (1<<7) +#define STS_HOST_BUSY (1 << 0) +#define STS_INTR (1 << 1) +#define STS_DEV_ERR (1 << 2) +#define STS_BUS_ERR (1 << 3) +#define STS_FAILED (1 << 4) +#define STS_SMBALERT (1 << 5) +#define STS_INUSE_STS (1 << 6) +#define STS_BYTE_DONE (1 << 7) /* Signs of successfully transaction end : * ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR ) */ -//#define DEBUG +#define CTL_INTREN (1 << 0) +#define CTL_KILL (1 << 1) +#define CTL_LAST_BYTE (1 << 5) +#define CTL_START (1 << 6) +#define CTL_PEC_EN (1 << 7) +#define CTL_RETURN_MASK 0x1f + +#define PROT_QUICK 0 +#define PROT_BYTE 1 +#define PROT_BYTE_DATA 2 +#define PROT_WORD_DATA 3 +#define PROT_PROC_CALL 4 +#define PROT_BLOCK_DATA 5 +#define PROT_I2C_BLOCK_DATA 6 + +/*#define DEBUG*/ #ifdef DEBUG # define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) @@ -70,11 +83,12 @@ static void smb_transaction(PMSMBus *s) if ((s->smb_stat & STS_DEV_ERR) != 0) { goto error; } + switch(prot) { - case 0x0: + case PROT_QUICK: ret = smbus_quick_command(bus, addr, read); goto done; - case 0x1: + case PROT_BYTE: if (read) { ret = smbus_receive_byte(bus, addr); goto data8; @@ -82,7 +96,7 @@ static void smb_transaction(PMSMBus *s) ret = smbus_send_byte(bus, addr, cmd); goto done; } - case 0x2: + case PROT_BYTE_DATA: if (read) { ret = smbus_read_byte(bus, addr, cmd); goto data8; @@ -91,16 +105,17 @@ static void smb_transaction(PMSMBus *s) goto done; } break; - case 0x3: + case PROT_WORD_DATA: if (read) { ret = smbus_read_word(bus, addr, cmd); goto data16; } else { - ret = smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0); + ret = smbus_write_word(bus, addr, cmd, + (s->smb_data1 << 8) | s->smb_data0); goto done; } break; - case 0x5: + case PROT_I2C_BLOCK_DATA: if (read) { ret = smbus_read_block(bus, addr, cmd, s->smb_data); goto data8; @@ -158,8 +173,9 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, break; case SMBHSTCNT: s->smb_ctl = val; - if (val & 0x40) + if (s->smb_ctl & CTL_START) { smb_transaction_start(s); + } break; case SMBHSTCMD: s->smb_cmd = val; @@ -198,7 +214,7 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) break; case SMBHSTCNT: s->smb_index = 0; - val = s->smb_ctl & 0x1f; + val = s->smb_ctl & CTL_RETURN_MASK; break; case SMBHSTCMD: val = s->smb_cmd; @@ -221,7 +237,9 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = 0; break; } - SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", addr, val); + SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", + addr, val); + return val; } From patchwork Tue Aug 21 17:02:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144774 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5572276ljj; Tue, 21 Aug 2018 10:57:29 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxtd5ojuu6r0l4KwqEzFcnhFNg4MMDOOFcOkullHOrqB7kNBwMoGUWbBl8ni8CswmhtRe23 X-Received: by 2002:a0c:80a8:: with SMTP id 37-v6mr46628612qvb.13.1534874248915; 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:09 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:35 +0200 Message-Id: <1534870966-9287-64-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [PULL 63/74] i2c: pm_smbus: Fix the semantics of block I2C transfers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard The I2C block transfer commands was not implemented correctly, it read a length byte and such like it was an smbus transfer. So fix the smbus_read_block() and smbus_write_block() functions so they can properly handle I2C transfers, and normal SMBus transfers (for upcoming changes). Pass in a transfer size and a bool to know whether to use the size byte (like SMBus) or use the length given (like I2C). Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-3-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 10 ++++++++-- hw/i2c/smbus.c | 37 ++++++++++++++++++++++++------------- include/hw/i2c/smbus.h | 17 +++++++++++++++-- 3 files changed, 47 insertions(+), 17 deletions(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 83c2377..f1fe889 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -117,10 +117,16 @@ static void smb_transaction(PMSMBus *s) break; case PROT_I2C_BLOCK_DATA: if (read) { - ret = smbus_read_block(bus, addr, cmd, s->smb_data); + int xfersize = s->smb_data0; + if (xfersize > sizeof(s->smb_data)) { + xfersize = sizeof(s->smb_data); + } + ret = smbus_read_block(bus, addr, s->smb_data1, s->smb_data, + xfersize, false, true); goto data8; } else { - ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); + ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0, + false); goto done; } break; diff --git a/hw/i2c/smbus.c b/hw/i2c/smbus.c index 587ce1a..6ff77c5 100644 --- a/hw/i2c/smbus.c +++ b/hw/i2c/smbus.c @@ -293,33 +293,42 @@ int smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data) return 0; } -int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data) +int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data, + int len, bool recv_len, bool send_cmd) { - int len; + int rlen; int i; - if (i2c_start_transfer(bus, addr, 0)) { - return -1; + if (send_cmd) { + if (i2c_start_transfer(bus, addr, 0)) { + return -1; + } + i2c_send(bus, command); } - i2c_send(bus, command); if (i2c_start_transfer(bus, addr, 1)) { - i2c_end_transfer(bus); + if (send_cmd) { + i2c_end_transfer(bus); + } return -1; } - len = i2c_recv(bus); - if (len > 32) { - len = 0; + if (recv_len) { + rlen = i2c_recv(bus); + } else { + rlen = len; } - for (i = 0; i < len; i++) { + if (rlen > len) { + rlen = 0; + } + for (i = 0; i < rlen; i++) { data[i] = i2c_recv(bus); } i2c_nack(bus); i2c_end_transfer(bus); - return len; + return rlen; } int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data, - int len) + int len, bool send_len) { int i; @@ -330,7 +339,9 @@ int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data, return -1; } i2c_send(bus, command); - i2c_send(bus, len); + if (send_len) { + i2c_send(bus, len); + } for (i = 0; i < len; i++) { i2c_send(bus, data[i]); } diff --git a/include/hw/i2c/smbus.h b/include/hw/i2c/smbus.h index 4fdba02..d8b1b9e 100644 --- a/include/hw/i2c/smbus.h +++ b/include/hw/i2c/smbus.h @@ -72,9 +72,22 @@ int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command); int smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t data); int smbus_read_word(I2CBus *bus, uint8_t addr, uint8_t command); int smbus_write_word(I2CBus *bus, uint8_t addr, uint8_t command, uint16_t data); -int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data); + +/* + * Do a block transfer from an I2C device. If recv_len is set, then the + * first received byte is a length field and is used to know how much data + * to receive. Otherwise receive "len" bytes. If send_cmd is set, send + * the command byte first before receiving the data. + */ +int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data, + int len, bool recv_len, bool send_cmd); + +/* + * Do a block transfer to an I2C device. If send_len is set, send the + * "len" value before the data. + */ int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data, - int len); + int len, bool send_len); void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf); void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, From patchwork Tue Aug 21 17:02:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144769 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5552391ljj; Tue, 21 Aug 2018 10:36:02 -0700 (PDT) X-Google-Smtp-Source: AA+uWPylN78lzbHgcUiNAQf7cWWQLGT2rh2vYZxwpOzuBGfebB1zMLF+4AlZgGkjrQQinhjDxTvi X-Received: by 2002:aed:3c8c:: with SMTP id d12-v6mr50620793qtf.203.1534872962541; Tue, 21 Aug 2018 10:36:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534872962; cv=none; d=google.com; s=arc-20160816; b=uQ+4AzRvbvGCXvCwP9mao70bQ14toaXfsDTc2kcQF0XbLAs/SJe3b1tEtyLfnhz8or zoI7SwjgQWeBWyH1ru0hZVpJuXTQG0jfiotFruGY7oh1LUovo7yNDuN8x2FZE5qhs29S 2WstOjyWlqXroS3OvFljwY+h3XOz2FP///cWqzrh53x3t5K8pZybi0JNtNRxwAX2Nc1N 4bzPtkQRaMIJDRZEIeE/XsRDT7pUzTRWFMSJFbk29WgnBK7jWA37oOX37b+88a0EqzcX w0lun9F+Wupv5uXbEhpzECgwhJzszY2JuHhFsapbSggjcmpTtSES7wXFlrpIu8god6s2 L+VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aCddtj7wtbHQ/2Fiq8Bm9lwizmGrolG52+XZv7pR4Xs=; b=xMn/pfHGGa7S1/Rq1eHSgz1uzvInKrUOKTIb5+u2u0JrjEG5lsrJiY9OCQWWMJIXHz PEnk8u/nVNMyQH+vyqyWgg7jBbJiDAu1thq8CrGjECnUm8wiBBjdw0YNepPh2Olklqk+ FnSFNFQ5aSDz2Lkr2I4eR1loJlrgnXEx4Wb36Ueg8WgKSbuovGi/MT+T5IQg/R9ctYBs RJWmxl4S5usnnAAolU/On74klerygK4M6+kdfdUUEZ88vxB9JEAbryW3kM/CsOEucF4+ lV6q/qA25zZ5wDJae6VtrGC/o2/9B2I2jIjPQE/+m+ScJel0xGpwRt3vP/RSAtm+sNjG fVrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b="C7eqro/7"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:36 +0200 Message-Id: <1534870966-9287-65-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 64/74] i2c: pm_smbus: Make the I2C block read command read-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard It did have write capability, but the manual says the behavior with write enabled is undefined. So just set an error in this case. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-4-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index f1fe889..dc61f2c 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -55,7 +55,7 @@ #define PROT_WORD_DATA 3 #define PROT_PROC_CALL 4 #define PROT_BLOCK_DATA 5 -#define PROT_I2C_BLOCK_DATA 6 +#define PROT_I2C_BLOCK_READ 6 /*#define DEBUG*/ @@ -115,7 +115,7 @@ static void smb_transaction(PMSMBus *s) goto done; } break; - case PROT_I2C_BLOCK_DATA: + case PROT_I2C_BLOCK_READ: if (read) { int xfersize = s->smb_data0; if (xfersize > sizeof(s->smb_data)) { @@ -125,9 +125,8 @@ static void smb_transaction(PMSMBus *s) xfersize, false, true); goto data8; } else { - ret = smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0, - false); - goto done; + /* The manual says the behavior is undefined, just set DEV_ERR. */ + goto error; } break; default: From patchwork Tue Aug 21 17:02:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144772 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5560138ljj; Tue, 21 Aug 2018 10:44:19 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxKV2z1xTG0geY6WOO8RnoOojKRPnLwO7A6cfeDsEcWZZs4neeXOXdV9HEE90AmNfkdILCk X-Received: by 2002:ae9:e009:: with SMTP id m9-v6mr45743110qkk.320.1534873459038; Tue, 21 Aug 2018 10:44:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534873459; cv=none; d=google.com; s=arc-20160816; b=YCtsRu1b1lLTP1f55S6TkFCz8XCeITD1spN3HYA1iXhf+ydbA8B6EO8oDCcp1K6FwV LVuwc2Ty/4seHtK4PkliVJWLLVmZnPpHdr+bB6FqmENMzpA8/bFo3NMX1ag0ROr7+rm5 9C/H/bQk34eO/jTZUFiBZkQQFh7xJcAKv2PNvLbDoFsR2KHQU8GR4mnTezdE1FHapocG RBWtdUh38ImBObWPQDAop/Gq1n7MkitLJHUa3P6pyq1/43e3ocyHRudKN6uCzTqlnSA5 2QRoI+xj1s2cduzGMBa2w94T+9LzxZkudOON+eLT1ri0I2F1X7OOiVS3SzO4qblhQkUE nJ1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=7zIh+LetOfjQtHl1scIepUduQ9PXIGTxzJ9ILSnVyFU=; b=lho/Jt88aXDe1xCqqldPUGCFTKxSDHwztb6/v5a+OV30JQMZs8lzwonu3+gwdoImJs Y0UAe2VY8PqSUQSgkPBIYxmUtovGbiroRAwwt6PLz+hD2QKuPYBHmICS/OJOG4EZ3/Nn 0rP7RmNyJUyMDr0pzOC9N+SqBx0a5qRHQhkdQ++2+/jh83nKanqI7f2Rj7JE+il7s3kV IniwJpg3ARxjiiJA/opCXudOI8bStlyxoh6XONMpu3vVWln7IMCbwfovugZHB82hTsdC IUZl9BJls32+hu0LJUZAp61VAIb8AJYP9mk03QAqbLLNngCbalTTHQUr6/T0Kcdll/iZ ITLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=vURUM9eW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:11 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:37 +0200 Message-Id: <1534870966-9287-66-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PULL 65/74] i2c: pm_smbus: Add block transfer capability X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard There was no block transfer code in pm_smbus.c, and it is needed for some devices. So add it. This adds both byte-by-byte block transfers and buffered block transfers. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-5-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 151 ++++++++++++++++++++++++++++++++++++++++++---- hw/i2c/smbus_ich9.c | 8 ++- include/hw/i2c/pm_smbus.h | 20 +++++- 3 files changed, 164 insertions(+), 15 deletions(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index dc61f2c..32132be 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -29,6 +29,7 @@ #define SMBHSTDAT0 0x05 #define SMBHSTDAT1 0x06 #define SMBBLKDAT 0x07 +#define SMBAUXCTL 0x0d #define STS_HOST_BUSY (1 << 0) #define STS_INTR (1 << 1) @@ -57,6 +58,10 @@ #define PROT_BLOCK_DATA 5 #define PROT_I2C_BLOCK_READ 6 +#define AUX_PEC (1 << 0) +#define AUX_BLK (1 << 1) +#define AUX_MASK 0x3 + /*#define DEBUG*/ #ifdef DEBUG @@ -129,6 +134,51 @@ static void smb_transaction(PMSMBus *s) goto error; } break; + case PROT_BLOCK_DATA: + if (read) { + ret = smbus_read_block(bus, addr, cmd, s->smb_data, + sizeof(s->smb_data), !s->i2c_enable, + !s->i2c_enable); + if (ret < 0) { + goto error; + } + s->smb_index = 0; + s->op_done = false; + if (s->smb_auxctl & AUX_BLK) { + s->smb_stat |= STS_INTR; + } else { + s->smb_blkdata = s->smb_data[0]; + s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; + } + s->smb_data0 = ret; + goto out; + } else { + if (s->smb_auxctl & AUX_BLK) { + if (s->smb_index != s->smb_data0) { + s->smb_index = 0; + goto error; + } + /* Data is already all written to the queue, just do + the operation. */ + s->smb_index = 0; + ret = smbus_write_block(bus, addr, cmd, s->smb_data, + s->smb_data0, !s->i2c_enable); + if (ret < 0) { + goto error; + } + s->op_done = true; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else { + s->op_done = false; + s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; + s->smb_data[0] = s->smb_blkdata; + s->smb_index = 0; + ret = 0; + } + goto out; + } + break; default: goto error; } @@ -148,13 +198,13 @@ done: if (ret < 0) { goto error; } - s->smb_stat |= STS_BYTE_DONE | STS_INTR; + s->smb_stat |= STS_INTR; +out: return; error: s->smb_stat |= STS_DEV_ERR; return; - } static void smb_transaction_start(PMSMBus *s) @@ -173,14 +223,61 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, " val=0x%02" PRIx64 "\n", addr, val); switch(addr) { case SMBHSTSTS: - s->smb_stat = (~(val & 0xff)) & s->smb_stat; - s->smb_index = 0; + s->smb_stat &= ~(val & ~STS_HOST_BUSY); + if (!s->op_done && !(s->smb_auxctl & AUX_BLK)) { + uint8_t read = s->smb_addr & 0x01; + + s->smb_index++; + if (!read && s->smb_index == s->smb_data0) { + uint8_t prot = (s->smb_ctl >> 2) & 0x07; + uint8_t cmd = s->smb_cmd; + uint8_t addr = s->smb_addr >> 1; + int ret; + + if (prot == PROT_I2C_BLOCK_READ) { + s->smb_stat |= STS_DEV_ERR; + goto out; + } + + ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data, + s->smb_data0, !s->i2c_enable); + if (ret < 0) { + s->smb_stat |= STS_DEV_ERR; + goto out; + } + s->op_done = true; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else if (!read) { + s->smb_data[s->smb_index] = s->smb_blkdata; + s->smb_stat |= STS_BYTE_DONE; + } else if (s->smb_ctl & CTL_LAST_BYTE) { + s->op_done = true; + s->smb_blkdata = s->smb_data[s->smb_index]; + s->smb_index = 0; + s->smb_stat |= STS_INTR; + s->smb_stat &= ~STS_HOST_BUSY; + } else { + s->smb_blkdata = s->smb_data[s->smb_index]; + s->smb_stat |= STS_BYTE_DONE; + } + } break; case SMBHSTCNT: - s->smb_ctl = val; - if (s->smb_ctl & CTL_START) { + s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */ + if (val & CTL_START) { + if (!s->op_done) { + s->smb_index = 0; + s->op_done = true; + } smb_transaction_start(s); } + if (s->smb_ctl & CTL_KILL) { + s->op_done = true; + s->smb_index = 0; + s->smb_stat |= STS_FAILED; + s->smb_stat &= ~STS_HOST_BUSY; + } break; case SMBHSTCMD: s->smb_cmd = val; @@ -195,13 +292,24 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, s->smb_data1 = val; break; case SMBBLKDAT: - s->smb_data[s->smb_index++] = val; - if (s->smb_index > 31) + if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { s->smb_index = 0; + } + if (s->smb_auxctl & AUX_BLK) { + s->smb_data[s->smb_index++] = val; + } else { + s->smb_blkdata = val; + } + break; + case SMBAUXCTL: + s->smb_auxctl = val & AUX_MASK; break; default: break; } + + out: + return; } static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) @@ -218,7 +326,6 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) } break; case SMBHSTCNT: - s->smb_index = 0; val = s->smb_ctl & CTL_RETURN_MASK; break; case SMBHSTCMD: @@ -234,9 +341,22 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = s->smb_data1; break; case SMBBLKDAT: - val = s->smb_data[s->smb_index++]; - if (s->smb_index > 31) + if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { s->smb_index = 0; + } + if (s->smb_auxctl & AUX_BLK) { + val = s->smb_data[s->smb_index++]; + if (!s->op_done && s->smb_index == s->smb_data0) { + s->op_done = true; + s->smb_index = 0; + s->smb_stat &= ~STS_HOST_BUSY; + } + } else { + val = s->smb_blkdata; + } + break; + case SMBAUXCTL: + val = s->smb_auxctl; break; default: val = 0; @@ -248,6 +368,13 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) return val; } +static void pm_smbus_reset(PMSMBus *s) +{ + s->op_done = true; + s->smb_index = 0; + s->smb_stat = 0; +} + static const MemoryRegionOps pm_smbus_ops = { .read = smb_ioport_readb, .write = smb_ioport_writeb, @@ -258,6 +385,8 @@ static const MemoryRegionOps pm_smbus_ops = { void pm_smbus_init(DeviceState *parent, PMSMBus *smb) { + smb->op_done = true; + smb->reset = pm_smbus_reset; smb->smbus = i2c_init_bus(parent, "i2c"); memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, "pm-smbus", 64); diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 007cb67..a66a114 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -61,12 +61,16 @@ static void ich9_smbus_write_config(PCIDevice *d, uint32_t address, pci_default_write_config(d, address, val, len); if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) { uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC]; - if ((hostc & ICH9_SMB_HOSTC_HST_EN) && - !(hostc & ICH9_SMB_HOSTC_I2C_EN)) { + if (hostc & ICH9_SMB_HOSTC_HST_EN) { memory_region_set_enabled(&s->smb.io, true); } else { memory_region_set_enabled(&s->smb.io, false); } + s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0; + if (hostc & ICH9_SMB_HOSTC_SSRESET) { + s->smb.reset(&s->smb); + s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET; + } } } diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index 2a837af..99d5489 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -1,6 +1,8 @@ #ifndef PM_SMBUS_H #define PM_SMBUS_H +#define PM_SMBUS_MAX_MSG_SIZE 32 + typedef struct PMSMBus { I2CBus *smbus; MemoryRegion io; @@ -11,8 +13,22 @@ typedef struct PMSMBus { uint8_t smb_addr; uint8_t smb_data0; uint8_t smb_data1; - uint8_t smb_data[32]; - uint8_t smb_index; + uint8_t smb_data[PM_SMBUS_MAX_MSG_SIZE]; + uint8_t smb_blkdata; + uint8_t smb_auxctl; + uint32_t smb_index; + + /* Set by pm_smbus.c */ + void (*reset)(struct PMSMBus *s); + + /* Set by the user. */ + bool i2c_enable; + + /* Internally used by pm_smbus. */ + + /* Set on block transfers after the last byte has been read, so the + INTR bit can be set at the right time. */ + bool op_done; } PMSMBus; void pm_smbus_init(DeviceState *parent, PMSMBus *smb); From patchwork Tue Aug 21 17:02:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144770 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5555312ljj; Tue, 21 Aug 2018 10:39:06 -0700 (PDT) X-Google-Smtp-Source: AA+uWPznbfmZiLlMDeSHsb2ghnmMZ1mOJYi/bVt/8jY9ypfmCVzYSm4/xwGTlw8dZFSsRkyRRnal X-Received: by 2002:ac8:2575:: with SMTP id 50-v6mr20914372qtn.88.1534873146116; Tue, 21 Aug 2018 10:39:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534873146; cv=none; d=google.com; s=arc-20160816; b=vs88G/8EUnd0zUQMD5V0CgMNosyjKQTL4PkrXiO2p+uRFeJlH3pryfAO1toSg84j55 9EqmZDx9+h3COWa/IEx8B6vmFnkj0QtJ2G1hMu+cdwmu7wnp+5tQMl4NgGUdQloHBDFf plnQQChk5jEzpWRY7QKamf6L3nqA72dQAGYnbMfOquonUxBCW2smofMUzJjidn8HWQyQ +gPp0YGytFVi/BSQxrAwQrgTBtN7xRzCyHxiAZ3XNy1sxB6oGdnh+PLLiR2arhMOPhAz PvlWQ6bFAc9OV92cmauAza5zb7LkfSSd1DF2CPDX7Go11zkk3Lcy5o0fE6raKIczBlCN Rirg== ARC-Message-Signature: i=1; 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:12 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:38 +0200 Message-Id: <1534870966-9287-67-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 66/74] i2c: pm_smbus: Add interrupt handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard Add the necessary code so that interrupts actually work from the pm_smbus device. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-7-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 14 +++++++++++++- hw/i2c/smbus_ich9.c | 16 ++++++++++++++++ include/hw/i2c/pm_smbus.h | 2 ++ 3 files changed, 31 insertions(+), 1 deletion(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 32132be..6322f07 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -214,6 +214,12 @@ static void smb_transaction_start(PMSMBus *s) s->smb_stat |= STS_HOST_BUSY; } +static bool +smb_irq_value(PMSMBus *s) +{ + return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN); +} + static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, unsigned width) { @@ -309,7 +315,9 @@ static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, } out: - return; + if (s->set_irq) { + s->set_irq(s, smb_irq_value(s)); + } } static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) @@ -365,6 +373,10 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", addr, val); + if (s->set_irq) { + s->set_irq(s, smb_irq_value(s)); + } + return val; } diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index a66a114..522a703 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -40,6 +40,8 @@ typedef struct ICH9SMBState { PCIDevice dev; + bool irq_enabled; + PMSMBus smb; } ICH9SMBState; @@ -109,11 +111,25 @@ static void ich9_smb_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; } +static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled) +{ + ICH9SMBState *s = pmsmb->opaque; + + if (enabled == s->irq_enabled) { + return; + } + + s->irq_enabled = enabled; + pci_set_irq(&s->dev, enabled); +} + I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base) { PCIDevice *d = pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE); ICH9SMBState *s = ICH9_SMB_DEVICE(d); + s->smb.set_irq = ich9_smb_set_irq; + s->smb.opaque = s; return s->smb.smbus; } diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index 99d5489..1afa3cf 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -23,6 +23,8 @@ typedef struct PMSMBus { /* Set by the user. */ bool i2c_enable; + void (*set_irq)(struct PMSMBus *s, bool enabled); + void *opaque; /* Internally used by pm_smbus. */ From patchwork Tue Aug 21 17:02:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144773 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5569884ljj; Tue, 21 Aug 2018 10:54:45 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbOtNOZfn9LP1kHlIopPsl9H2o4gyfn2VnyuHtUiEy5O/Tt471HCcE4Dg49kxUtTt2pSvJM X-Received: by 2002:ac8:179c:: with SMTP id o28-v6mr1353913qtj.98.1534874085386; Tue, 21 Aug 2018 10:54:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534874085; cv=none; d=google.com; s=arc-20160816; b=D3ybC3ah6ZmCS8WT4yO3QYnbUBJYSHFJltCsA+eBrw1aAijTRlEqGX8CZPNCX6F1K0 6Dt9AG/coWOoko42M+YAVkAo/udhtoFknsZR1SlCFsQOXkKnytogSZoAs8qODA4lI81w Ro5wZCYihbDamgu1pWi6EUEAWlLk+X8zSBMQcxPpBJezRhLjvujQpAoxkIs1r35Aj82B t2zMAO4hZw4z6tXj8Mj6uxtsI95edN6DflRS3R+lHsQAM7HsJ1Ezjg/LS3XGP1jZ5rDn /+2iV5Eh7SOjxRkqqOVQGB0shDbzVV+b+vkygawvPUDs2jV2nYH/2xBQpbKYPg9LjDm/ xxPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ADFFXom5iNIFTwymwNdZAOMCVy/8n3vmNA6fvWLZ6qY=; b=j8Ky1YlAqjXoqPZWbf+937ueYl++0eZWdGH6CsttHkgi5K8EbEUqHARPJvWJl9ayU6 YfgUPwFNnF5EJzohoLWslOwvOkcchrIhoHLMaoZZNhZfOjboyXQBAUXUcukuN9fLaeee zbKEcCWYnPCJgYANm3qT+TEE9yOGxSm4Bolm1Q1DhnF3eJePDpU0ZIeRATGDHh91aILG P3pFI37kUdFTPE2J11BjCYTaf5wI90Iw5WiFNf1+4K/crpCadBdyX2/IXj7PaqbZZ503 eW1OMYhZinizBSIEiBIvx6DsbLW2ydKFmYVa2jiBdiFIglMuMvhKPcZ2egufvqbNSl7n m+Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=HjMIk1RE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:39 +0200 Message-Id: <1534870966-9287-68-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 67/74] i2c: pm_smbus: Don't delay host status register busy bit when interrupts are enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard Change 880b1ffe6ec2f0ae "smbus: do not immediately complete commands" changed pm_smbus to delay setting the host busy bit until the status register was read, to work around a bug in AMIBIOS. Unfortunately, when interrupts are enabled, the status register will never get read and the processing will never happen. Modify the code to only delay setting the host busy bit if interrupts are not enabled. Signed-off-by: Corey Minyard Cc: Hervé Poussineau Cc: Philippe Mathieu-Daudé Message-Id: <1534796770-10295-8-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/i2c/pm_smbus.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) -- 1.8.3.1 diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 6322f07..91ee444 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -80,9 +80,6 @@ static void smb_transaction(PMSMBus *s) I2CBus *bus = s->smbus; int ret; - assert(s->smb_stat & STS_HOST_BUSY); - s->smb_stat &= ~STS_HOST_BUSY; - SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot); /* Transaction isn't exec if STS_DEV_ERR bit set */ if ((s->smb_stat & STS_DEV_ERR) != 0) { @@ -209,9 +206,18 @@ error: static void smb_transaction_start(PMSMBus *s) { - /* Do not execute immediately the command ; it will be - * executed when guest will read SMB_STAT register */ - s->smb_stat |= STS_HOST_BUSY; + if (s->smb_ctl & CTL_INTREN) { + smb_transaction(s); + } else { + /* Do not execute immediately the command; it will be + * executed when guest will read SMB_STAT register. This + * is to work around a bug in AMIBIOS (that is working + * around another bug in some specific hardware) where + * it waits for STS_HOST_BUSY to be set before waiting + * checking for status. If STS_HOST_BUSY doesn't get + * set, it gets stuck. */ + s->smb_stat |= STS_HOST_BUSY; + } } static bool @@ -330,6 +336,7 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = s->smb_stat; if (s->smb_stat & STS_HOST_BUSY) { /* execute command now */ + s->smb_stat &= ~STS_HOST_BUSY; smb_transaction(s); } break; From patchwork Tue Aug 21 17:02:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 144776 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5578518ljj; Tue, 21 Aug 2018 11:03:03 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzH7PxXh7Ojno5waMZJ91J2rtkONBGHV0PFKpnxYIv6iHyztasJMpCawp0Dl/fcYh872SjP X-Received: by 2002:ac8:3492:: with SMTP id w18-v6mr20026088qtb.239.1534874583424; Tue, 21 Aug 2018 11:03:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534874583; cv=none; d=google.com; s=arc-20160816; b=Tm3a+GGeCnEcPgDXUw8SOud2gnh/7X3ANAYH/ZXW2HQ6swyw6Wj9aRGp00ASTb5abI /bboCdMiYRAIuFfM+0eSxN/uHMQWRbuMfRPyx24nCA8Y3OzuwOAh7X4DodoGhKvspmz5 pD17i/KV5Agc8wJ2n4u7kR/PsrTnX1K5G9XSKwVfxfPfGmRFCn0A727mADjrkYPImekz k/fTqDcW5+r513UMRs0d1rmmouq6Eh1ydLaEzMex/Gfdv02lImAZkxODRv+sGyWDG21B q3apuyb3RTy9zmJgj65Qt/LBawnQY57BxXE+92biXuxV6Urny64VD7stJddgkP3zynmT xLgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=z8jk9MS8UwK1p+60JIxWOmieKXqcCKUHVXdjtGI1AVA=; b=Jg7yY7/F3kWMEdQeXQMME8MTQZqZlZiXx87mA60SuGcUrKeiqPVk3ElMgDvZOFxlxS kMEuhxiLFgrOY5pIihq+mrOLDjwasaGyZivq9W5ak2OXCDk+49+U8J95yAyx2DSvu9EZ l6PWmgOKYUXCF3Q4bGP2vX5NUMAvG52owqUXG1btF8OQKkiH+A4SPxJZ3eXO1gJgqG87 qCACziKr2h0cJI2bMRRCx1jkv/g/z4pufzHVPkq8wvc6NVj18MbfEdK1z/Fm9hatPNFE SXcX53RptUbIgGg3hAJOrp97qu8WT88o7LYAWdkmDsQxdOJzf5W7oq/Py7ScZppITnF2 rc5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=YSCWwKq+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[78.12.184.244]) by smtp.gmail.com with ESMTPSA id v6-v6sm2608955wmc.43.2018.08.21.10.04.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Aug 2018 10:04:14 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 21 Aug 2018 19:02:40 +0200 Message-Id: <1534870966-9287-69-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> References: <1534870966-9287-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PULL 68/74] i2c: pm_smbus: Add the ability to force block transfer enable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard The PIIX4 hardware has block transfer buffer always enabled in the hardware, but the i801 does not. Add a parameter to pm_smbus_init to force on the block transfer so the PIIX4 handler can enable this by default, as it was disabled by default before. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini Message-Id: <1534796770-10295-9-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini --- hw/acpi/piix4.c | 2 +- hw/i2c/pm_smbus.c | 5 ++++- hw/i2c/smbus_ich9.c | 2 +- hw/isa/vt82c686.c | 2 +- include/hw/i2c/pm_smbus.h | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) -- 1.8.3.1 diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 6404af5..e330f24 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -512,7 +512,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) pci_conf[0x90] = s->smb_io_base | 1; pci_conf[0x91] = s->smb_io_base >> 8; pci_conf[0xd2] = 0x09; - pm_smbus_init(DEVICE(dev), &s->smb); + pm_smbus_init(DEVICE(dev), &s->smb, true); memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base, &s->smb.io); diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 91ee444..685a237 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -402,11 +402,14 @@ static const MemoryRegionOps pm_smbus_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -void pm_smbus_init(DeviceState *parent, PMSMBus *smb) +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk) { smb->op_done = true; smb->reset = pm_smbus_reset; smb->smbus = i2c_init_bus(parent, "i2c"); + if (force_aux_blk) { + smb->smb_auxctl |= AUX_BLK; + } memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, "pm-smbus", 64); } diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index 522a703..2a8b49e 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -86,7 +86,7 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp) pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); /* TODO bar0, bar1: 64bit BAR support*/ - pm_smbus_init(&d->qdev, &s->smb); + pm_smbus_init(&d->qdev, &s->smb, false); pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO, &s->smb.io); } diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index cff1946..7302f6d 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -370,7 +370,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) pci_conf[0x90] = s->smb_io_base | 1; pci_conf[0x91] = s->smb_io_base >> 8; pci_conf[0xd2] = 0x90; - pm_smbus_init(&s->dev.qdev, &s->smb); + pm_smbus_init(&s->dev.qdev, &s->smb, false); memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); apm_init(dev, &s->apm, NULL, s); diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index 1afa3cf..060d3c6 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -33,6 +33,6 @@ typedef struct PMSMBus { bool op_done; } PMSMBus; -void pm_smbus_init(DeviceState *parent, PMSMBus *smb); +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk); #endif /* PM_SMBUS_H */