From patchwork Mon May 15 05:54:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99771 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1397191qge; Sun, 14 May 2017 22:55:27 -0700 (PDT) X-Received: by 10.98.57.212 with SMTP id u81mr4502286pfj.9.1494827727553; Sun, 14 May 2017 22:55:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494827727; cv=none; d=google.com; s=arc-20160816; b=W2oRi+YoQzcZXz8f/J+fC2RSOFKs7qPXlpCPWh8EjzHP8OxU7Olcy/CSD5KuCXURrn l5DaDAkmtElHbdTb+nOYMt+xg3fKn2Mv1vXttLht4clUlW38VJ9qzWkyUvpc4Nmm0VYK N6RPEnQJXv1WtVWHQ0XvRJHsdYzIP9XaUAQOHvW/TGTsZcnGeyMBfQETWUVamNynVKPE wWFMyl6HZ/1kq5jXjuheAdjA7WmIwytyUYy/Ia1MozEvk+Xb/AtmnL4SPHuaIu3mHgB0 WhJScHgt6Qc4MuFbjcblV4AYDKFGncX3CcmFi+WrBbqKhxLt4A9tcw/Vnifuovb/5SyG HK+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gYZU0wC8nBk3KWhRSKnWsdgRPBZjUjtXhsbpUphMBPs=; b=yfn595hTzcJ0AgHyLcEDsiFa3Ob1BSiaVFclkoi0WmrU8RAoxp20P4ibh7+c9QqLs6 z432GE7e7UdaFP8qmeWQbDotTLzrfXWd7pXRgU6s1MGrQkqJsMR2zL68qwm5hAFd+B+y q/dSTi28NpQRSxPf5lqslu8TJs2YuE9/BD6IKv8EFJp4NZ7mm4km70Y0C7m85xTkCzff Cu164fqz0cOwFi/7conR+OCbrXcH5za2tNaxAVfENO3Oc6FGl9OqFmwfHf8H/siN/87Q O/vE1zLDkxQ4LcjqBOS+MXyxm6AWNnFAlQeYerXmwQSLkUu/57DIv0cYhIXV19J2lK5a fjUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u5si9784026pfa.19.2017.05.14.22.55.27; Sun, 14 May 2017 22:55:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759353AbdEOFzG (ORCPT + 25 others); Mon, 15 May 2017 01:55:06 -0400 Received: from mail-pf0-f178.google.com ([209.85.192.178]:35929 "EHLO mail-pf0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759103AbdEOFzC (ORCPT ); Mon, 15 May 2017 01:55:02 -0400 Received: by mail-pf0-f178.google.com with SMTP id m17so57321943pfg.3 for ; Sun, 14 May 2017 22:55:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gYZU0wC8nBk3KWhRSKnWsdgRPBZjUjtXhsbpUphMBPs=; b=AvtRUP/9+3NjgFpOKTjLXq9bY3pEm4sDYhwlDv0xGRdfRHmznKDDoAoXglpfLc6ypg FfvFRxT681zc2DQFXF6/cDFiLOPADhomvnT8KPhnDW2pthnKZ/bo+GtuY0b7Fil4KUjg vPnYLJ8rwC6k4NtiabR8dV7V3WkbZjERgiGlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gYZU0wC8nBk3KWhRSKnWsdgRPBZjUjtXhsbpUphMBPs=; b=HfcRuLi5l9hgbDRflMSUF88ZQeJ6QiiFX0s1QG7eTYLFOPygp6pNScjXRwpYpF3gu9 4mjlXJOIVId/0fpw4/AsgVWFx+d0OxS6USNKf/9uvRYUcFtp0Cv4w1A5MQ2zN/DgJN1j V7p7IGzLIz5ITUGRdt7vd99v1wuNEpVQWc9r+00L3uTbj7fJ1iQKyJg0/1qBUcbeIvm+ udxJpkt/j/GTa3P5tBzurl8XCVCjKOlFQ4zLWTBP6eSAH8KOt2Bw81FX8JoYvKx5GaaB 3I2yBtaRPg6odpyCoh2VFx1QbEq2TGTRHviYGtA8cve64Td+LvV+VvRXNXjtbjZTYIhs +QhA== X-Gm-Message-State: AODbwcCbXNXh1bRekc77Zslq3HDGg26ctYu2fmjZ5d59mVbU6yj8naIJ 03H6bZD3XbCSmx9l X-Received: by 10.99.117.66 with SMTP id f2mr4480876pgn.58.1494827702197; Sun, 14 May 2017 22:55:02 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.87]) by smtp.gmail.com with ESMTPSA id t5sm17315105pgo.48.2017.05.14.22.54.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 14 May 2017 22:55:01 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, guodong.xu@linaro.org, chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] clk: hi3660: add clocks for video encoder and decoder Date: Mon, 15 May 2017 13:54:22 +0800 Message-Id: <20170515055423.1803-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170515055423.1803-1-guodong.xu@linaro.org> References: <20170515055423.1803-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Jun This patch adds clocks for video encoder and decoder. Signed-off-by: Chen Jun Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 23 +++++++++++++++++++++++ include/dt-bindings/clock/hi3660-clock.h | 10 ++++++++++ 2 files changed, 33 insertions(+) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 143ce0c..ffc765a 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -47,9 +47,12 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, }, { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 }, + { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, }, }; static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { + { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys", + CLK_SET_RATE_PARENT, 0x0, 0, 0, }, { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x0, 21, 0, }, { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus", @@ -120,6 +123,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = { CLK_SET_RATE_PARENT, 0x20, 27, 0, }, { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus", CLK_SET_RATE_PARENT, 0x30, 1, 0, }, + { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc", + CLK_SET_RATE_PARENT, 0x30, 10, 0, }, + { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec", + CLK_SET_RATE_PARENT, 0x30, 11, 0, }, { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus", CLK_SET_RATE_PARENT, 0x30, 12, 0, }, { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus", @@ -171,6 +178,10 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0", CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec", + CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, }, + { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc", + CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi", CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, }, { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll", @@ -239,6 +250,8 @@ static const char *const clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",}; static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; +static const char *const +clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, @@ -283,6 +296,12 @@ static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p, ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2, CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p, + ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2, + CLK_MUX_HIWORD_MASK, }, + { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p, + ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2, + CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p, ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2, CLK_MUX_HIWORD_MASK, }, @@ -318,6 +337,10 @@ static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = { CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi", CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc", + CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, + { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec", + CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt", CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, 0, }, { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m", diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h index 1c00b7f..2cf01b4 100644 --- a/include/dt-bindings/clock/hi3660-clock.h +++ b/include/dt-bindings/clock/hi3660-clock.h @@ -154,6 +154,16 @@ #define HI3660_CLK_DIV_UFSPERI 137 #define HI3660_CLK_DIV_AOMM 138 #define HI3660_CLK_DIV_IOPERI 139 +#define HI3660_VENC_VOLT_HOLD 140 +#define HI3660_PERI_VOLT_HOLD 141 +#define HI3660_CLK_GATE_VENC 142 +#define HI3660_CLK_GATE_VDEC 143 +#define HI3660_CLK_ANDGT_VENC 144 +#define HI3660_CLK_ANDGT_VDEC 145 +#define HI3660_CLK_MUX_VENC 146 +#define HI3660_CLK_MUX_VDEC 147 +#define HI3660_CLK_DIV_VENC 148 +#define HI3660_CLK_DIV_VDEC 149 /* clk in pmuctrl */ #define HI3660_GATE_ABB_192 0 From patchwork Mon May 15 05:54:23 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id u5si9784026pfa.19.2017.05.14.22.55.28; Sun, 14 May 2017 22:55:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759402AbdEOFzK (ORCPT + 25 others); Mon, 15 May 2017 01:55:10 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:35128 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759368AbdEOFzH (ORCPT ); Mon, 15 May 2017 01:55:07 -0400 Received: by mail-pg0-f45.google.com with SMTP id q125so35435920pgq.2 for ; Sun, 14 May 2017 22:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=VbRG6/1MyOHZGraKY81ZC3eDXA4Is0tmv9sjZ9BtGjCITCQ09cPsAIXsdBPJuTM8+w UslRvuGEIfdoExjcPav0YAUmeiSwDV54CK6pJXjSklArNbkyWJPsW3nBvAWJlC/0Abgm TmCHU6YwiDLKHbfgo74VzWBhlH9gX+T7brrBg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4FCBE8l0k4GVV0QK40T/3dwOs5p9c+YakAAbIFHRVe8=; b=EFnTXlqi/EC0+RUBUBfZ6aqFGFOnv7NphEUOplMisXLDqSuxlIsamuBawz0GH7NTbU qwEHvn+s/tDxx6jC8O8u7kPW50ayXh1Q+CYu75M6qo0Mu13OPVDqr2Igiyxsu+LQIMrw fyMQ/xqpMkBgF3uVbb+R2YgGyum6R58Ox42WrTEL8aK0WhIxfj6UzvtOjfkjpE6uhtjR 4fkMe+r6RJdn+BrKqP+Agc9cI5V6ZrAuRvm30N8AWOGgRS4CY0R0QeKhEWK0GJEK32Qc x1u/DB+pMJ3Nm5m9fRveZDLGRduLQHpF8H2Eug7eNt5Icu3W4ajcuv+RDfz2kxn/laKN ZfIw== X-Gm-Message-State: AODbwcAsh7CRKVj3umqsCapilPo1O1hpqSboi1Xt5tDqFuSmibCo+wr6 KJ/p13zH+I4xsStp X-Received: by 10.98.144.143 with SMTP id q15mr4449493pfk.200.1494827706826; Sun, 14 May 2017 22:55:06 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.87]) by smtp.gmail.com with ESMTPSA id t5sm17315105pgo.48.2017.05.14.22.55.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 14 May 2017 22:55:06 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com, guodong.xu@linaro.org, chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Zheng Shaobo Subject: [PATCH 3/3] clk: hi3660: Set PPLL2 to 2880M Date: Mon, 15 May 2017 13:54:23 +0800 Message-Id: <20170515055423.1803-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170515055423.1803-1-guodong.xu@linaro.org> References: <20170515055423.1803-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhong Kaihua Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua Signed-off-by: Zheng Shaobo --- drivers/clk/hisilicon/clk-hi3660.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index ffc765a..fd5ce7f 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -20,7 +20,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, }, { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, }, { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, }, - { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 960000000, }, + { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000, }, { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, }, { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, }, { HI3660_PCLK, "pclk", NULL, 0, 20000000, }, @@ -42,7 +42,7 @@ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, }, { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, }, { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, }, - { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 2, 0, }, + { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, }, { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, }, { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, }, { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },