From patchwork Tue May 16 10:25:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 99856 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1945141qge; Tue, 16 May 2017 03:26:33 -0700 (PDT) X-Received: by 10.99.127.26 with SMTP id a26mr11066187pgd.75.1494930393229; Tue, 16 May 2017 03:26:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494930393; cv=none; d=google.com; s=arc-20160816; b=VXscYYAVxUxil1jVWVD23lyZRO3gvfNeCgnnKtcbQLYgLw8AWyhAJeInKMeFadkEO9 Az/kXvDCe8D2aiIODWz2xVnKyh0uWb5fR4/7zzjLS3fLNg6usfqyAAPx2Y9NCfjQKPvc If6WxZR1fp6H+YgiQBujoxJSQHMKjLD9EmEJ0TQkhNM5VWNpzkZ1ZCtgfhYl7aHkcrHd BSo3AOBqhNMm49KDkvBD5Nzt8dYFdLHtdDGn7IKp7lKa/D0YuTwpqMVn+of7ibEZdKLH Bpyc99PvRyeFZx5gJkQ2KYSlDR3+7bPcm2G9RhEEwRkku0A01yYuGay3t1239OiqVpdK o6AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=e+kw8CSchKkSEOgsJNnSNqQKTxvtGpEuqhuB6T4eeaQ=; b=bKbwYFX9nQoI0uF4HLIHrzAgJsr5x+AfGXfc+R+xkK0JqzkUCmaZNXk6loR++Te58s qGCi/pZs9FxDRLLM8prjNdw0vDoJjYP3py5X/Ra6SwhydgW3fqspo2/RoZKukcfDfjfE xuLXO77nyIF3HbMy/uC9E1NDooJycX6wcEx+Iv7h7NAd+bccYzGaw5XkAhh926JwUqW1 sNZfv3ogHRGcKpLwMLSYN7KfwJ7y9zY2EU2PPijEGvYQOWPFJOcxH8es2Ip19acyaixj 2lOCesoTwHN2vkvKubonmXLa6o8oZVuFboh9pTBQA6xs5TjFEtLo5i2NL12yciAYbvwr JXRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e6si12976665plk.0.2017.05.16.03.26.32; Tue, 16 May 2017 03:26:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752571AbdEPK0P (ORCPT + 25 others); Tue, 16 May 2017 06:26:15 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:5953 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751530AbdEPK0K (ORCPT ); Tue, 16 May 2017 06:26:10 -0400 Received: from 172.30.72.57 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.57]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANR95767; Tue, 16 May 2017 18:26:06 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Tue, 16 May 2017 18:25:57 +0800 From: Gabriele Paoloni To: , CC: , , , , , Subject: [PATCH 1/2] PCI/portdrv: add support for different MSI interrupts for PCIe port services Date: Tue, 16 May 2017 11:25:41 +0100 Message-ID: <1494930342-7132-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> References: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.591AD3BE.01B1, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e9fc5742edc2302d80f5c96c69e4f0ee Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently PCIe port services are assigned with different interrutps only if MSI-x are supported by calling pcie_port_enable_msix(). If a root port supports MSI instead of MSI-x currently we fall back to use a single shared interrupt for all the services. This patch renames and extends pcie_port_enable_msix() to use MSI in case MSI-x allocation fails. Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv.h | 5 +++++ drivers/pci/pcie/portdrv_core.c | 33 +++++++++++++++++++++++++++------ 2 files changed, 32 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 587aef3..729ee90 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -18,6 +18,11 @@ */ #define PCIE_PORT_MAX_MSIX_ENTRIES 32 +/* According to the PCI Local Bus Specification REV. 3.0 the max number + * of MSI vectors per function is 32 + */ +#define PCIE_PORT_MAX_MSI_ENTRIES 32 + #define get_descriptor_id(type, service) (((type - 4) << 8) | service) extern struct bus_type pcie_port_bus_type; diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index cea504f..e2c7bfd 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -44,14 +44,16 @@ static void release_pcie_device(struct device *dev) } /** - * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port + * pcie_port_enable_msix_or_msi - try to set up MSI-X or MSI as interrupt mode + * for given port * @dev: PCI Express port to handle * @irqs: Array of interrupt vectors to populate * @mask: Bitmask of port capabilities returned by get_port_device_capability() * * Return value: 0 on success, error code on failure */ -static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) +static +int pcie_port_enable_msix_or_msi(struct pci_dev *dev, int *irqs, int mask) { int nr_entries, entry, nvec = 0; @@ -63,6 +65,10 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) */ nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES, PCI_IRQ_MSIX); + if (nr_entries < 0) /* MSI-x failed let's try with MSI */ + nr_entries = pci_alloc_irq_vectors(dev, 1, + PCIE_PORT_MAX_MSI_ENTRIES, + PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; @@ -77,7 +83,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * Number field in the PCI Express Capabilities register", where * according to Section 7.8.2 of the specification "For MSI-X, * the value in this field indicates which MSI-X Table entry is - * used to generate the interrupt message." + * used to generate the interrupt message." and "For MSI, the + * value in this field indicates the offset between the base + * Message Data and the interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * */ pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; @@ -100,7 +112,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * MSI/MSI-X vectors assigned to the port is going to be used * for AER, where "For MSI-X, the value in this register * indicates which MSI-X Table entry is used to generate the - * interrupt message." + * interrupt message." and "For MSI, the value + * in this field indicates the offset between the base Message + * Data and the interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); @@ -125,6 +143,9 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) /* Now allocate the MSI-X vectors for real */ nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec, PCI_IRQ_MSIX); + if (nr_entries < 0) /* MSI-x failed, let's try MSI*/ + nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec, + PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; } @@ -160,8 +181,8 @@ static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) { flags &= ~PCI_IRQ_MSI; } else { - /* Try to use MSI-X if supported */ - if (!pcie_port_enable_msix(dev, irqs, mask)) + /* Try to use MSI-X or MSI if supported */ + if (!pcie_port_enable_msix_or_msi(dev, irqs, mask)) return 0; } From patchwork Tue May 16 10:25:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 99858 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1945189qge; Tue, 16 May 2017 03:26:42 -0700 (PDT) X-Received: by 10.84.198.36 with SMTP id o33mr14896636pld.145.1494930402587; Tue, 16 May 2017 03:26:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494930402; cv=none; d=google.com; s=arc-20160816; b=XNGnViwyD80v0KYUaJw+bv9PLPGozJlmH5pwfFoR8py7V43vdRBIlIVD+vUR4SGy2Q 9JkzMgbyCHw1UPVtSuDpF6vc9X/v0K0CTomqI6Gj3RvH5zvs1eFIe+4thaqcAcJLatv8 Wl7cqH+9qwh69R97NGcBERNhcNcLxFYTl0QXLZLAFxE6/ZzBpli9IUjXIReYcnzqpvaX vVA62OGD5gb72iCOblKetfnK5WfU0jzGGsLOZmWH80oYzBofIQ0PZZ08tEvL7jJOeDdN 8mOHJGMPvxKi0Q+WZZEfBA9GQ0JzJian2YjwAB/5ikGNCWRd8HstTgyyFajyeiJxviHA Lz8A== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id 1si13398788pgp.311.2017.05.16.03.26.42; Tue, 16 May 2017 03:26:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752610AbdEPK0g (ORCPT + 25 others); Tue, 16 May 2017 06:26:36 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6305 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751943AbdEPK0M (ORCPT ); Tue, 16 May 2017 06:26:12 -0400 Received: from 172.30.72.56 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOP94150; Tue, 16 May 2017 18:26:08 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Tue, 16 May 2017 18:25:59 +0800 From: Gabriele Paoloni To: , CC: , , , , , Subject: [PATCH 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Tue, 16 May 2017 11:25:42 +0100 Message-ID: <1494930342-7132-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> References: <1494930342-7132-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.591AD3C1.0127, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ad04440f7dff792cf9c6f0d5cffca65e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv_core.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.7.4 Reviewed-by: Christoph Hellwig diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e2c7bfd..477bf14 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -131,6 +131,35 @@ int pcie_port_enable_msix_or_msi(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the