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Wed, 21 Jul 2021 13:43:18 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 01/44] arm: imx: add i.MX8ULP basic Kconfig option Date: Wed, 21 Jul 2021 22:16:42 +0800 Message-Id: <20210721141725.23346-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f9a87e89-6300-4086-8bf1-08d94c4d7f79 X-MS-TrafficTypeDiagnostic: DB8PR04MB5802: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:183; 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Signed-off-by: Peng Fan --- arch/arm/Kconfig | 11 +++++++++++ arch/arm/mach-imx/imx8ulp/Kconfig | 16 ++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 arch/arm/mach-imx/imx8ulp/Kconfig -- 2.30.0 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7f493a8e8f..57f5a1eff7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -800,6 +800,15 @@ config ARCH_IMX8M select SUPPORT_SPL imply CMD_DM +config ARCH_IMX8ULP + bool "NXP i.MX8ULP platform" + select ARM64 + select DM + select OF_CONTROL + select SUPPORT_SPL + select GPIO_EXTRA_HEADER + imply CMD_DM + config ARCH_IMXRT bool "NXP i.MXRT platform" select CPU_V7M @@ -1979,6 +1988,8 @@ source "arch/arm/mach-imx/imx8/Kconfig" source "arch/arm/mach-imx/imx8m/Kconfig" +source "arch/arm/mach-imx/imx8ulp/Kconfig" + source "arch/arm/mach-imx/imxrt/Kconfig" source "arch/arm/mach-imx/mxs/Kconfig" diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig new file mode 100644 index 0000000000..167dbb3fb1 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -0,0 +1,16 @@ +if ARCH_IMX8ULP + +config IMX8ULP + bool + select ARMV8_SPL_EXCEPTION_VECTORS + +config SYS_SOC + default "imx8ulp" + +choice + prompt "i.MX8ULP board select" + optional + +endchoice + +endif From patchwork Wed Jul 21 14:16:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483285 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6208895jao; Wed, 21 Jul 2021 06:43:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaiUdgYUfCjJshGgnFEFntjecjq5q6DVSUnC7U2SI3gm7VfnysK43GyMujAIrW7OIGrwa6 X-Received: by 2002:a17:907:1b06:: with SMTP id mp6mr39048573ejc.188.1626875033792; Wed, 21 Jul 2021 06:43:53 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875033; cv=pass; d=google.com; s=arc-20160816; b=PtZppylr3nXZQg8ZQFrKw+rdq1pJosVmyf1UVTs2tcVeGMb3AUF44cHEgkKOmCtUe4 fvUWjXhORAFCbBAj7O01/5quTlxWbR/ByJOO+Ir3X7nRxkjcLff1fQDyNsJXPTbL6zjs OFOL8gXIMAA4rujZ1u7+Cg59bqNKDBS/YzjOmlmJ5PWV9t+QBFEIs2FVX0RmeWnaRqZ4 wrfeYFyOYWGn+c1p3dYe4ANcsyAZ2/dczFVJqs7257IgLvXo95j6ReXkqJXusAoouIB7 aUounv8MZb725yAZ9da9hWKZbC1Ld6t+qP/CnWxBE8oEquKmCuOleEnFxZ6km/cgYCEG iQ9g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=nLPNCQf05qo5oajyeByhpEPz1JejFhT6x3aaIXolwak=; b=Xj6x9E+khY7oWSK7Lx6vyAxYzd+VwRXzaTEwkt7Uoc8CtCDnNdrLHF+nUvFuQzeQoh FO25DC/RCHrRAUX11Yc7t+jxiw/ZvfipyGwY+SrA7r/5Tn+NWsnPcX//94FkV2IZVgJe h3RfoBQdmzjYofO7nK8Mq16O/WlfgzfRsxkITcjlZflvJTnH+96Og3mT6Vchs2/3Qn7D izTLR0q2x4/Gfj4UrLMfN3akxlvnYQII2nv+HXsNqahnNlL6kGlSNX9K9hOIfFemPShb Buop2Bnal2In1LZ8So+jnr1tKZOszT+O5rla1mxgHOWQtLmu/ueiNIucRZ+XwXPh2q5r X8Tg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=KyPcV2Cr; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 4 ++++ arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 11 +++++++++++ arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 11 +++++++++++ 4 files changed, 27 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8ulp/sys_proto.h create mode 100644 arch/arm/mach-imx/imx8ulp/soc.c -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 267a094e5a..fe96378971 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,8 +50,12 @@ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ + +#define MXC_CPU_IMX8ULP 0xA1 /* dummy ID */ + #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ + #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h new file mode 100644 index 0000000000..cab12c218e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __ARCH_IMX8ULP_SYS_PROTO_H +#define __ARCH_NMX8ULP_SYS_PROTO_H + +#include + +#endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index b612189849..ad446940ff 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -51,6 +51,7 @@ struct bd_info; #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) +#define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP)) #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c new file mode 100644 index 0000000000..b3679aefcb --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include + +u32 get_cpu_rev(void) +{ + return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; +} From patchwork Wed Jul 21 14:16:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483284 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6208764jao; Wed, 21 Jul 2021 06:43:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkgkeFi4kejkTOUUgISducSCX0a16i+0/WUpXLhpAK9S+SsezahE5OFokN8Jqx+30cdzGo X-Received: by 2002:a05:6402:1768:: with SMTP id da8mr45387980edb.43.1626875023946; Wed, 21 Jul 2021 06:43:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875023; cv=pass; d=google.com; s=arc-20160816; b=ki/W3wRvwtA1dBc69b2TBAVbXORHCEBXCftB08fo7jBA4X9xAoCMtdP57z75ZJcs+f PwOxfiBpGkgTtnzESTrGc4zQBbJPM9b/XLqQewlz+G1lxCNoyunhKZZyp9UmXt/uOXov TUK8N3weAUHWsav+AFlM2VkSoU4Qbo5Dy6naqhuZ28yZe4d+dgeT5HreBery8rnfQgs4 V96MwEDytmSEUXJqciTooSxC1fobB+wSrSvatm0tfl4ToiKWwF2rPiiGhfv6AeKxbkCy aBNRKAGnx7Vkyne6B36D8lNEbYmePpusXtG2b6U7q/38DzTMZEQpGvklCpPXCRZy14Z2 48yw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=+g0uQfh3e0LkBYcAyp5M2RvHjrJ/skzm9O49D26rU44=; b=Y7bJSqLI8upSuhMDsGV/HrH3d9RBsaLDn2mGVP8oAV7Ovcyg70q1BLrw2OOShr33An OwjedI0d6uEbDRAx4+jK6OM/NmLlhrW52bishqMh21cKukSGVb4dvQVxin81mrnZDhMw /cCdLeaaQ3Q2nThxnA8lZaXaKSynhAvWYy3QKNzf4/WWbsjD66WbbjrCdoJ5qeU5xbsh gfHir+2o/QsxoSkM0r0MLL59Th8u0/4qTiiqkOoRqnaeKu2KOw2PiThCgH0dMvj4zX6t KxFBzgna6gi0RSzhEmtsOaQ78fn79Y5BdJsm4ksm/Gsi4ljGXsZ1V7zHGVbgPqoyG4Dz BL0g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=JZUiFf6L; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 9 --------- arch/arm/include/asm/mach-imx/sys_proto.h | 10 ++++++++++ 2 files changed, 10 insertions(+), 9 deletions(-) -- 2.30.0 diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h index 0e4c8ad15d..0daa922fad 100644 --- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -8,14 +8,5 @@ #include -#define BT0CFG_LPBOOT_MASK 0x1 -#define BT0CFG_DUALBOOT_MASK 0x2 - -enum bt_mode { - LOW_POWER_BOOT, /* LP_BT = 1 */ - DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ - SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ -}; - enum boot_device get_boot_device(void); #endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index ad446940ff..e3ee58c9f8 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -178,6 +178,16 @@ enum boot_dev_type_e { extern struct rom_api *g_rom_api; #endif +/* For i.MX ULP */ +#define BT0CFG_LPBOOT_MASK 0x1 +#define BT0CFG_DUALBOOT_MASK 0x2 + +enum bt_mode { + LOW_POWER_BOOT, /* LP_BT = 1 */ + DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ + SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ +}; + u32 get_nr_cpus(void); u32 get_cpu_rev(void); u32 get_cpu_speed_grade_hz(void); From patchwork Wed Jul 21 14:16:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483287 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6209273jao; Wed, 21 Jul 2021 06:44:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAf+rxxYzjv6ZoguS+wSbNWg8bwYguZP2edp0dpvFitec59Kq2uh1MdV1SyT2CBY6k4nRZ X-Received: by 2002:aa7:c38d:: with SMTP id k13mr47823871edq.178.1626875062956; Wed, 21 Jul 2021 06:44:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875062; cv=pass; d=google.com; s=arc-20160816; b=vwMmgJZs32/sJ8BZMIHweORyp7007l5zhkpsPEVfJSY8iS6lY/8i6Z+dyCJW0iMydY zqkU+ZLjeHVAi67jtPDNc3+f7+fnu3kqz66CYLRhKgtc+qTyxTVfTaRhMwMqg2BNjW1Y lCaKIintQsd2yc2ReBKfoNcmbUgrZ390QUHSGKl+X85pzRG989siHq7F40G2MXak1ezM w6allUk8Rj1Q4A/+17OkdXIlYUZPnOmJtQBl+szZkXtA5A2Pon8XM3zyJ17xQ993PUW+ Y5ZCqcWOxI2bIuqlSZAPJ2usSo+JvUe3M9bK1qxD6vMYWCqz8bM9mU8MX0inWvMfK9Ob rNCQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kwM/VFGliySbjojaIhmHRZrB+Fn+jSbCK0ooRc0id4w=; b=Xwb6Xq9Oii22spbL1JiThC7pPf/x+Sya1VtGTLAdAUI1N8WrBc1Cgr30qudY95UPc8 WZlxrTiV7lpI70EpYO697BRbYA+DBvvl30+eg2k4bnKDAaLKixtA0gqd4qwirzQ4WS0Z 6EBhr3MYpI0mubH8Px7NF6iIQF8jlSJ2F/ZcpYWXzKCgGo73KKjYx4HVKF1yfI9ObAnJ mFNXuLvt5frTzFREbSDs31ujYlYSXnD9V2m6mLRwGOJWa5geRnzJgigU3x+Q91pVG7Uk tFDycxJl/SQxCxpwj5T+AF8pJjeprbJdfhhaiGGaknUbLvetWVcoqml3mmYkoIZE5w7Q uChg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=kAA70sjc; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 21 Jul 2021 13:43:26 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 04/44] arm: imx8ulp: support print cpu info Date: Wed, 21 Jul 2021 22:16:45 +0800 Message-Id: <20210721141725.23346-5-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7393be51-497c-4500-19ff-08d94c4d83e3 X-MS-TrafficTypeDiagnostic: DB8PR04MB5802: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 3 + arch/arm/mach-imx/imx8ulp/soc.c | 59 +++++++++++++++++++ 2 files changed, 62 insertions(+) -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index cab12c218e..8894611a0f 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -8,4 +8,7 @@ #include +extern unsigned long rom_pointer[]; + +enum bt_mode get_boot_mode(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b3679aefcb..e6ac5f8d25 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -3,9 +3,68 @@ * Copyright 2021 NXP */ +#include +#include +#include #include +#include u32 get_cpu_rev(void) { return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; } + +enum bt_mode get_boot_mode(void) +{ + u32 bt0_cfg = 0; + + bt0_cfg = readl(CMC0_RBASE + 0x80); + bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); + + if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { + /* No low power boot */ + if (bt0_cfg & BT0CFG_DUALBOOT_MASK) + return DUAL_BOOT; + else + return SINGLE_BOOT; + } + + return LOW_POWER_BOOT; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +const char *get_imx_type(u32 imxtype) +{ + return "8ULP"; +} + +int print_cpuinfo(void) +{ + u32 cpurev; + char cause[18]; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + printf("Boot mode: "); + switch (get_boot_mode()) { + case LOW_POWER_BOOT: + printf("Low power boot\n"); + break; + case DUAL_BOOT: + printf("Dual boot\n"); + break; + case SINGLE_BOOT: + default: + printf("Single boot\n"); + break; + } + + return 0; +} +#endif + From patchwork Wed Jul 21 14:16:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483286 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6209024jao; Wed, 21 Jul 2021 06:44:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz35dQPp/wlmYNmwKOXCJndPDLbnaljhID+IIz5Q3hdMYP7v0DIjDAKZ30G9Dk8gHnT8AbI X-Received: by 2002:a17:906:a391:: with SMTP id k17mr39087080ejz.516.1626875044915; Wed, 21 Jul 2021 06:44:04 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875044; cv=pass; d=google.com; s=arc-20160816; b=vLR7PwvvIe1eH0kw9gC0x80hMcdEk7Tw2Pdi2/tnQKXG35rO+XUSmk6faNoEmt7qyN jDsg9zW7RwmktmD2D1a8xk1mVxrGsaercPZbjBJ0dBCdX+aECkCCi9Id7+vongekqJBs GKkMKsX/XjPXJEqggLS8twmtmv3VgBmpm4iarUXG5ttK/6ypgZY9l3abQwZTMUBieRgh YV1+oYnOrvMYMQZmyTt20h4XxmCbMGBPaMS/vmE7SNKWsxTWA1ifZPEpGlsX09rhQTpn j23Lm18GKYwX8MBuK+X0gHFL0sVRYy/UklFJLRTSmXtRJLwnxDzu/VtHt6THhVSB69f8 j7nA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=riev8FH2q2qYN2IoIOv5o5JHtbuAPDl7McYV7hBodWI=; b=OVLNxGITJxxjla9+sbll+iSOf3XaXO0uN9xyWhn6E5yQc+f6AawiKvM9jogr25SmYt aqefB5stGHmQlIYPl5YGqJlqFe1Qj06pvN7lnF8LaHOl6Qoa9E4jtF/TMtYeucx1cLbS 4kIYXcbyuAA0PsTI/rZC17iybdU6hmtJvoHkfD15L7gSyC/bxK9xFCwXpDWYf9QTkW0y d2DHOSzoz/9FJLag0mCmBpDXCGaxeJX5reoAE0GO8Y8OmIWkw+Y5EHy5O76+cwWgIXs5 8dcIS1M+jAX96Ctl8yYwyZ2hvCaWbQmQD1O45ObpgKtNaMqF/fVzaZ4RBX5CCjvml629 0K/g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b="YgEQE/+g"; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 21 Jul 2021 13:43:28 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 05/44] imx: imx8ulp: add get reset cause Date: Wed, 21 Jul 2021 22:16:46 +0800 Message-Id: <20210721141725.23346-6-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:26 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a1e28050-0e3a-4f93-4bf9-08d94c4d8563 X-MS-TrafficTypeDiagnostic: DB8PR04MB5802: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:93; 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Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e6ac5f8d25..383dbe6000 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -32,6 +32,73 @@ enum bt_mode get_boot_mode(void) return LOW_POWER_BOOT; } +#define CMC_SRS_TAMPER BIT(31) +#define CMC_SRS_SECURITY BIT(30) +#define CMC_SRS_TZWDG BIT(29) +#define CMC_SRS_JTAG_RST BIT(28) +#define CMC_SRS_CORE1 BIT(16) +#define CMC_SRS_LOCKUP BIT(15) +#define CMC_SRS_SW BIT(14) +#define CMC_SRS_WDG BIT(13) +#define CMC_SRS_PIN_RESET BIT(8) +#define CMC_SRS_WARM BIT(4) +#define CMC_SRS_HVD BIT(3) +#define CMC_SRS_LVD BIT(2) +#define CMC_SRS_POR BIT(1) +#define CMC_SRS_WUP BIT(0) + +static u32 reset_cause = -1; + +static char *get_reset_cause(char *ret) +{ + u32 cause1, cause = 0, srs = 0; + void __iomem *reg_ssrs = (void __iomem *)(SRC_BASE_ADDR + 0x88); + void __iomem *reg_srs = (void __iomem *)(SRC_BASE_ADDR + 0x80); + + if (!ret) + return "null"; + + srs = readl(reg_srs); + cause1 = readl(reg_ssrs); + + reset_cause = cause1; + + cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); + + switch (cause) { + case CMC_SRS_POR: + sprintf(ret, "%s", "POR"); + break; + case CMC_SRS_WUP: + sprintf(ret, "%s", "WUP"); + break; + case CMC_SRS_WARM: + cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | + CMC_SRS_JTAG_RST); + switch (cause) { + case CMC_SRS_WDG: + sprintf(ret, "%s", "WARM-WDG"); + break; + case CMC_SRS_SW: + sprintf(ret, "%s", "WARM-SW"); + break; + case CMC_SRS_JTAG_RST: + sprintf(ret, "%s", "WARM-JTAG"); + break; + default: + sprintf(ret, "%s", "WARM-UNKN"); + break; + } + break; + default: + sprintf(ret, "%s-%X", "UNKN", cause1); + break; + } + + debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1); + return ret; +} + #if defined(CONFIG_DISPLAY_CPUINFO) const char *get_imx_type(u32 imxtype) { @@ -50,6 +117,8 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause(cause)); + printf("Boot mode: "); switch (get_boot_mode()) { case LOW_POWER_BOOT: From patchwork Wed Jul 21 14:16:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483288 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6209524jao; Wed, 21 Jul 2021 06:44:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyu4I01y/UvVgdcSJ10uV8usOy63Pxa5+qT90ap0Fh8bFroZsa1DdG3hCM4cKjHLFayyihE X-Received: by 2002:a17:906:2755:: with SMTP id a21mr38290844ejd.488.1626875081872; Wed, 21 Jul 2021 06:44:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875081; cv=pass; d=google.com; s=arc-20160816; b=AhfGNyszVDiA2XgvZAEIfgfqwEGemCo7Oa2AbrzoElF/O7KTTcQKqDPIrhf8AFtqtS Z+esgXZtznswTOT1LfSYdWNBZfDGdqhwLx02OGJmRnbRkOYjU4IvsW0THyoMFYbqKoi+ +8i5kz3m8o1dMnqbh//VUrsqLLYRXBLGbSDn0NihZdaacYU622i6ITOxMKwrL9ta5YK5 3K18wgTQTE22iHe7T2f5113pftWdVfn99lcQWzcs0i5vYs7OILz1hP5DzUs2HuzBinXI sMQjFO3hpAP/330sEylyfYjAHaAmN/+nP/QkcwNUn7/wk0pzRTh67QGJbbWQlOA2zUIl QMOA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=YhliCfDqZi2E7Toa86Lo2SXWbhP3ZlbrNQ0krmojeLc=; b=ZLAH/TNspfPlHCSgAytnTNzIMo7GMQlMvnQIuSlPddfwHyzK9rblNOV389UL4+2KyG /2iWs0V9QjwHMG9cBh4bPDaHVjNY9i4o3UR3HVnoQvuvV7pq+6M7RL5TYULQOFa0XhIJ 8Jmyc/KzigDYuF/VuQpSP5eMCW9fVWJQiDo3ZU+d3aAJrI9kOslQzlGPxIdnuS7/oase WpGrH2c6hHNwotirkMxD4GyNwb8od2abDCgkkEvzjjiuF7ybDeD1kO+9XagfUiOgtUuD MnCWN6O7yAIz8grf3LhL2r+cwIfh+kI1qC3aIPv+5Z1QBWWIobqgyd1ZOwRWO/5er0wE 7M/Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=Gohj5V75; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 21 Jul 2021 13:43:31 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan , Ye Li Subject: [PATCH V4 06/44] arm: imx: basic i.MX8ULP support Date: Wed, 21 Jul 2021 22:16:47 +0800 Message-Id: <20210721141725.23346-7-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:29 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b9ae09d5-74e1-49bc-6ff8-08d94c4d86fb X-MS-TrafficTypeDiagnostic: DB8PR04MB5802: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/Makefile | 4 +- arch/arm/include/asm/arch-imx8ulp/clock.h | 34 ++++ arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 +++++ arch/arm/include/asm/arch-imx8ulp/gpio.h | 20 +++ arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 136 ++++++++++++++++ .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 60 +++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8ulp/Makefile | 7 + arch/arm/mach-imx/imx8ulp/clock.c | 27 +++ arch/arm/mach-imx/imx8ulp/iomux.c | 4 + arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 32 ++++ arch/arm/mach-imx/imx8ulp/soc.c | 154 +++++++++++++++++- 12 files changed, 513 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx8ulp/clock.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/ddr.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h create mode 100644 arch/arm/mach-imx/imx8ulp/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/clock.c create mode 100644 arch/arm/mach-imx/imx8ulp/iomux.c create mode 100644 arch/arm/mach-imx/imx8ulp/lowlevel_init.S -- 2.30.0 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 28b523b37c..c68e598a67 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -107,11 +107,11 @@ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt)) +ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) libs-y += arch/arm/mach-imx/ endif else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) libs-y += arch/arm/mach-imx/ endif endif diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h new file mode 100644 index 0000000000..e145c33f01 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/clock.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H +#define _ASM_ARCH_IMX8ULP_CLOCK_H + +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_AXI_CLK, + MXC_DDR_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_I2C_CLK, +}; + +u32 mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_IMX_LPI2C +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +u32 imx_get_i2cclk(unsigned int i2c_num); +#endif +#ifdef CONFIG_MXC_OCOTP +void enable_ocotp_clk(unsigned char enable); +#endif +void init_clk_usdhc(u32 index); +void clock_init(void); +#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/ddr.h b/arch/arm/include/asm/arch-imx8ulp/ddr.h new file mode 100644 index 0000000000..4544431b05 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/ddr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __ASM_ARCH_IMX8ULP_DDR_H +#define __ASM_ARCH_IMX8ULP_DDR_H + +#include +#include + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_timing_info2 { + /* ddr controller config */ + struct dram_cfg_param *ctl_cfg; + unsigned int ctl_cfg_num; + /* pi config */ + struct dram_cfg_param *pi_cfg; + unsigned int pi_cfg_num; + /* phy freq1 config */ + struct dram_cfg_param *phy_f1_cfg; + unsigned int phy_f1_cfg_num; + /* phy freq2 config */ + struct dram_cfg_param *phy_f2_cfg; + unsigned int phy_f2_cfg_num; + /* initialized drate table */ + unsigned int fsp_table[3]; +}; + +extern struct dram_timing_info2 dram_timing; + +int ddr_init(struct dram_timing_info2 *dram_timing); + +#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/gpio.h b/arch/arm/include/asm/arch-imx8ulp/gpio.h new file mode 100644 index 0000000000..b7563bb401 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __ASM_ARCH_IMX8ULP_GPIO_H +#define __ASM_ARCH_IMX8ULP_GPIO_H + +struct gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; + u32 gpio_pddr; + u32 gpio_pidr; + u8 gpio_pxdr[32]; +}; + +#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h new file mode 100644 index 0000000000..982f2a9b28 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef _IMX8ULP_REGS_H_ +#define _IMX8ULP_REGS_H_ +#define ARCH_MXC + +#include + +#define PBRIDGE0_BASE 0x28000000 + +#define CMC0_RBASE 0x28025000 + +#define CMC1_BASE_ADDR 0x29240000 + +#define SIM1_BASE_ADDR 0x29290000 + +#define WDG3_RBASE 0x292a0000UL + +#define SIM_SEC_BASE_ADDR 0x2802B000 + +#define CGC1_SOSCDIV_ADDR 0x292C0108 +#define CGC1_FRODIV_ADDR 0x292C0208 + +#define CFG1_PLL2CSR_ADDR 0x292C0500 +#define CFG1_PLL2CFG_ADDR 0x292C0510 + +#define PCC_XRDC_MGR_ADDR 0x292d00bc + +#define PCC3_RBASE 0x292d0000 +#define PCC4_RBASE 0x29800000 +#define PCC5_RBASE 0x2da70000 + +#define IOMUXC_BASE_ADDR 0x298c0000 + +#define LPUART4_RBASE 0x29390000 +#define LPUART5_RBASE 0x293a0000 +#define LPUART6_RBASE 0x29860000 +#define LPUART7_RBASE 0x29870000 + +#define LPUART_BASE LPUART5_RBASE + +#define FSB_BASE_ADDR 0x27010000 + +#define USBOTG0_RBASE 0x29900000 +#define USB_PHY0_BASE_ADDR 0x29910000 +#define USBOTG1_RBASE 0x29920000 +#define USB_PHY1_BASE_ADDR 0x29930000 +#define USB_BASE_ADDR USBOTG0_RBASE + +#define DDR_CTL_BASE_ADDR 0x2E060000 +#define DDR_PI_BASE_ADDR 0x2E062000 +#define DDR_PHY_BASE_ADDR 0x2E064000 +#define AVD_SIM_BASE_ADDR 0x2DA50000 +#define AVD_SIM_LPDDR_CTRL (AVD_SIM_BASE_ADDR + 0x14) +#define AVD_SIM_LPDDR_CTRL2 (AVD_SIM_BASE_ADDR + 0x18) + +#define FEC_QUIRK_ENET_MAC + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug; /* 0x050 */ + u32 usbphy_debug_set; /* 0x054 */ + u32 usbphy_debug_clr; /* 0x058 */ + u32 usbphy_debug_tog; /* 0x05c */ + u32 usbphy_debug0_status; /* 0x060 */ + u32 reserved1[3]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; +#endif + +#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h new file mode 100644 index 0000000000..d7c07f41b3 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __ASM_ARCH_IMX8ULP_PINS_H__ +#define __ASM_ARCH_IMX8ULP_PINS_H__ + +#include + +enum { + IMX8ULP_PAD_PTB7__PMIC0_MODE2 = IOMUX_PAD(0x009C, 0x009C, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTB8__PMIC0_MODE1 = IOMUX_PAD(0x00A0, 0x00A0, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTB9__PMIC0_MODE0 = IOMUX_PAD(0x00A4, 0x00A4, IOMUX_CONFIG_MPORTS | 0xA, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTB10__PMIC0_SDA = IOMUX_PAD(0x00A8, 0x00A8, IOMUX_CONFIG_MPORTS | 0xA, 0x0804, 0x2, 0), + IMX8ULP_PAD_PTB11__PMIC0_SCL = IOMUX_PAD(0x00AC, 0x00AC, IOMUX_CONFIG_MPORTS | 0xA, 0x0800, 0x2, 0), + + IMX8ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0000, 0x0000, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0004, 0x0004, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0008, 0x0008, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x000C, 0x000C, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0010, 0x0010, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0014, 0x0014, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0018, 0x0018, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x001C, 0x001C, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x0020, 0x0020, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x0024, 0x0024, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x0028, 0x0028, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x002C, 0x002C, 0x8, 0x0000, 0x0, 0), + + IMX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 = IOMUX_PAD(0x003c, 0x003c, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD18__FLEXSPI2_A_DQS = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 = IOMUX_PAD(0x004c, 0x004c, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 = IOMUX_PAD(0x0050, 0x0050, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 = IOMUX_PAD(0x0054, 0x0054, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 = IOMUX_PAD(0x0058, 0x0058, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B = IOMUX_PAD(0x005c, 0x005c, 0x9, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK = IOMUX_PAD(0x005c, 0x005c, 0xa, 0x0000, 0x0, 0), + + IMX8ULP_PAD_PTE19__ENET0_REFCLK = IOMUX_PAD(0x00CC, 0x00CC, 0xA, 0x0AF4, 0x1, 0), + IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN = IOMUX_PAD(0x0128, 0x0128, 0x9, 0x0AD0, 0x2, 0), + + IMX8ULP_PAD_PTF11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), + IMX8ULP_PAD_PTF3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0A60, 0x2, 0), + IMX8ULP_PAD_PTF2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0A5C, 0x2, 0), + IMX8ULP_PAD_PTF4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0A70, 0x2, 0), + IMX8ULP_PAD_PTF5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0A6C, 0x2, 0), + IMX8ULP_PAD_PTF0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0A68, 0x2, 0), + IMX8ULP_PAD_PTF1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0A64, 0x2, 0), + +}; +#endif /* __ASM_ARCH_IMX8ULP_PINS_H__ */ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 82aa39dee7..36224d8db9 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -227,6 +227,7 @@ obj-$(CONFIG_MX5) += mx5/ obj-$(CONFIG_MX6) += mx6/ obj-$(CONFIG_MX7) += mx7/ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/ +obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/ obj-$(CONFIG_IMX8M) += imx8m/ obj-$(CONFIG_ARCH_IMX8) += imx8/ obj-$(CONFIG_ARCH_IMXRT) += imxrt/ diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile new file mode 100644 index 0000000000..e8970dc04f --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 NXP +# + +obj-y += lowlevel_init.o +obj-y += soc.o clock.o iomux.o diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c new file mode 100644 index 0000000000..f866809fc2 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void clock_init(void) +{ +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + return 0; +} + +u32 get_lpuart_clk(void) +{ + return 24000000; +} diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c b/arch/arm/mach-imx/imx8ulp/iomux.c new file mode 100644 index 0000000000..c52ccdeaea --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/iomux.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S new file mode 100644 index 0000000000..7d81a75639 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#include + +.align 8 +.global rom_pointer +rom_pointer: + .space 256 + +/* + * Routine: save_boot_params (called after reset from start.S) + */ + +.global save_boot_params +save_boot_params: + /* The firmware provided ATAG/FDT address can be found in r2/x0 */ + adr x0, rom_pointer + stp x1, x2, [x0], #16 + stp x3, x4, [x0], #16 + + /* Returns */ + b save_boot_params_ret + +.global restore_boot_params +restore_boot_params: + adr x0, rom_pointer + ldp x1, x2, [x0], #16 + ldp x3, x4, [x0], #16 + ret diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 383dbe6000..f14c6b421a 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -7,8 +7,11 @@ #include #include #include +#include #include +DECLARE_GLOBAL_DATA_PTR; + u32 get_cpu_rev(void) { return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; @@ -52,8 +55,8 @@ static u32 reset_cause = -1; static char *get_reset_cause(char *ret) { u32 cause1, cause = 0, srs = 0; - void __iomem *reg_ssrs = (void __iomem *)(SRC_BASE_ADDR + 0x88); - void __iomem *reg_srs = (void __iomem *)(SRC_BASE_ADDR + 0x80); + void __iomem *reg_ssrs = (void __iomem *)(CMC1_BASE_ADDR + 0x88); + void __iomem *reg_srs = (void __iomem *)(CMC1_BASE_ADDR + 0x80); if (!ret) return "null"; @@ -137,3 +140,150 @@ int print_cpuinfo(void) } #endif +void init_wdog(void) +{ + /* TODO */ +} + +static struct mm_region imx8ulp_arm64_mem_map[] = { + { + /* ROM */ + .virt = 0x0, + .phys = 0x0, + .size = 0x40000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, + { + /* FLEXSPI0 */ + .virt = 0x04000000, + .phys = 0x04000000, + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* SSRAM (align with 2M) */ + .virt = 0x1FE00000UL, + .phys = 0x1FE00000UL, + .size = 0x400000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SRAM1 (align with 2M) */ + .virt = 0x21000000UL, + .phys = 0x21000000UL, + .size = 0x200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SRAM0 (align with 2M) */ + .virt = 0x22000000UL, + .phys = 0x22000000UL, + .size = 0x200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals */ + .virt = 0x27000000UL, + .phys = 0x27000000UL, + .size = 0x3000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals */ + .virt = 0x2D000000UL, + .phys = 0x2D000000UL, + .size = 0x1600000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* FLEXSPI1-2 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* + * empty entrie to split table entry 5 + * if needed when TEEs are used + */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx8ulp_arm64_mem_map; + +/* simplify the page table size to enhance boot speed */ +#define MAX_PTE_ENTRIES 512 +#define MAX_MEM_MAP_REGIONS 16 +u64 get_page_table_size(void) +{ + u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); + u64 size = 0; + + /* + * For each memory region, the max table size: + * 2 level 3 tables + 2 level 2 tables + 1 level 1 table + */ + size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; + + /* + * We need to duplicate our page table once to have an emergency pt to + * resort to when splitting page tables later on + */ + size *= 2; + + /* + * We may need to split page tables later on if dcache settings change, + * so reserve up to 4 (random pick) page tables for that. + */ + size += one_pt * 4; + + return size; +} + +void enable_caches(void) +{ + /* TODO: add TEE memmap region */ + + icache_enable(); + dcache_enable(); +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + /* TODO */ +} +#endif + +int arch_cpu_init(void) +{ + return 0; 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Signed-off-by: Peng Fan --- arch/arm/mach-imx/Kconfig | 13 +++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 13 ------------- 2 files changed, 13 insertions(+), 13 deletions(-) -- 2.30.0 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c089664375..653463ab46 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -172,3 +172,16 @@ config IMX_DCD_ADDR the ROM code to configure the device at early boot stage, is located. This information is shared with the user via mkimage -l just so the image can be signed. + +config SPL_LOAD_IMX_CONTAINER + bool "Enable SPL loading U-Boot as a i.MX Container image" + depends on SPL + help + This is to let SPL could load i.MX Container image + +config IMX_CONTAINER_CFG + string "i.MX Container config file" + depends on SPL + help + This is to specific the cfg file for generating container + image which will be loaded by SPL. diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 71221d8d06..b43739e5c6 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -31,19 +31,6 @@ config IMX8QXP config SYS_SOC default "imx8" -config SPL_LOAD_IMX_CONTAINER - bool "Enable SPL loading U-Boot as a i.MX Container image" - depends on SPL - help - This is to let SPL could load i.MX8 Container image - -config IMX_CONTAINER_CFG - string "i.MX Container config file" - depends on SPL - help - This is to specific the cfg file for generating container - image which will be loaded by SPL. - config BOOTAUX_RESERVED_MEM_BASE hex "i.MX auxiliary core dram memory base" default 0 From patchwork Wed Jul 21 14:16:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483291 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6210383jao; Wed, 21 Jul 2021 06:45:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWp2pRBJ7WcPA8DO7I4LrQMf8m+no+AxlG50s3NvibVTXvdFq/43F6zAD40rayUDddIeyg X-Received: by 2002:aa7:c458:: with SMTP id n24mr49264501edr.30.1626875149450; Wed, 21 Jul 2021 06:45:49 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875149; cv=pass; d=google.com; s=arc-20160816; b=aQZkeT3upVQFrWRn69jBfR2EWhuLY1sasOAXAeU7vnLOfA4JRjXE7n+aGwa8t8mbZZ wbmxkzBKGBeTw1b7oRantYzeGS3Eff5GSroZYHsYea2MpOdYY+q5we7/G4ihmBrFkfIB iMJeh6C3sy+B3lP3vIO8raz9Yq7ADN8jncmNPdMfx2bXdmjOME7b7FGmEC7kbmDJlr1z SIopwyBNH9q3BNzbtzvla5gK0XeO/rJ2omTpNadsoBo6Ec7pvbDY5B2d+Szte38eYFbU zehuVWQGn0BXzcJrkanyeQ8Ns1FD1aV+qFIqGh6qDaOw6bayIULH3UdaCC1m9zIS7lwh L30w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=QxLkGdoIWYs8pvM0clKGPdYKbzmC5CfmUW2vKb3a5eE=; b=0rJf1HW9QIGJh58JJREs1IWKAXVC0YI/dwLRcrbShJTLv3XS7PqLSHY4ywOnm/mMfJ sLY9w3TEzRY8D7ELXZzSKYJsyvoeHwNJmsKaleGzimriJHAuIwCSMEFmCn9eZo/RgXWz bdXCmKaME8TfR2Gur8ekRpFUQ06CtnjL7rvrW8P0C2V2jbgHjYGME5EefYbHM2F8VrLH vYBQ/UdRks6U9i3FVCdtbYx8/fP/xMQ7N7+Qw3MSPLyJ+gwPuMJCmB7n3nyuaI6K8zil jCo6yStftW8tnM98NOi1RmSEDSVci6Gca5rCAeUgbdES18j0jmscVkRsQuWl5UFIm0cn Mf8A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=G8142OT2; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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/* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); From patchwork Wed Jul 21 14:16:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483292 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6210743jao; Wed, 21 Jul 2021 06:46:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy49IrdtAPRDpECA2s91vIH2KO3X/qr2cQdBk8iconFNxdRc05AFKVoUKlREBRq2sUe/hRM X-Received: by 2002:a17:907:ab0:: with SMTP id bz16mr38708256ejc.33.1626875174287; Wed, 21 Jul 2021 06:46:14 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875174; cv=pass; d=google.com; s=arc-20160816; b=zZvcYH0qpNRWiUrbhtMBx80iuDqEy8Qi4ye9lP1ZIcFxjlAL5LzacdxafGydu1tFYC 3qsT5OKadxWlRPnUKkgzAaD6tzkJPqNz36XYXsoa0UUdn8IIGIagS7QlxiBXfP8VoDpT He/XaPvF26r5VpgnP5LkVFYMWOkemEUT6DAlRhBDNBRJJNnJ/3yn2lKo0n2/wZ7C5DeS cCqbZr6Un7yn/yp0Us1AhezgQcOUjYQFk4ErAA+eG2lymXV8EFSNQUO8a4qayXAZKhs/ /2J95gTqKqELcRx27jNdyIlXXmcWqPO9w4WhBVYLiXRwTbHu/HkVwhejcQqoc6/4GKm/ rzOw== ARC-Message-Signature: i=2; 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Wed, 21 Jul 2021 13:43:57 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 16/44] arm: imx8ulp: add clock support Date: Wed, 21 Jul 2021 22:16:57 +0800 Message-Id: <20210721141725.23346-17-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:55 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7e8cc832-9164-49d3-6697-08d94c4d9689 X-MS-TrafficTypeDiagnostic: DB7PR04MB4633: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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+ +struct cgc1_regs { + u32 verid; + u32 rsvd1[4]; + u32 ca35clk; + u32 rsvd2[2]; + u32 clkoutcfg; + u32 rsvd3[4]; + u32 nicclk; + u32 xbarclk; + u32 rsvd4[21]; + u32 clkdivrst; + u32 rsvd5[29]; + u32 soscdiv; + u32 rsvd6[63]; + u32 frodiv; + u32 rsvd7[189]; + u32 pll2csr; + u32 rsvd8[3]; + u32 pll2cfg; + u32 rsvd9; + u32 pll2denom; + u32 pll2num; + u32 pll2ss; + u32 rsvd10[55]; + u32 pll3csr; + u32 pll3div_vco; + u32 pll3div_pfd0; + u32 pll3div_pfd1; + u32 pll3cfg; + u32 pll3pfdcfg; + u32 pll3denom; + u32 pll3num; + u32 pll3ss; + u32 pll3lock; + u32 rsvd11[54]; + u32 enetstamp; + u32 rsvd12[67]; + u32 pllusbcfg; + u32 rsvd13[59]; + u32 aud_clk1; + u32 sai5_4_clk; + u32 tpm6_7clk; + u32 mqs1clk; + u32 rsvd14[60]; + u32 lvdscfg; +}; + +struct cgc2_regs { + u32 verid; + u32 rsvd1[4]; + u32 hificlk; + u32 rsvd2[2]; + u32 clkoutcfg; + u32 rsvd3[6]; + u32 niclpavclk; + u32 ddrclk; + u32 rsvd4[19]; + u32 clkdivrst; + u32 rsvd5[29]; + u32 soscdiv; + u32 rsvd6[63]; + u32 frodiv; + u32 rsvd7[253]; + u32 pll4csr; + u32 pll4div_vco; + u32 pll4div_pfd0; + u32 pll4div_pfd1; + u32 pll4cfg; + u32 pll4pfdcfg; + u32 pll4denom; + u32 pll4num; + u32 pll4ss; + u32 pll4lock; + u32 rsvd8[128]; + u32 aud_clk2; + u32 sai7_6_clk; + u32 tpm8clk; + u32 rsvd9[1]; + u32 spdifclk; + u32 rsvd10[59]; + u32 lvdscfg; +}; + +u32 cgc1_clk_get_rate(enum cgc1_clk clk); +void cgc1_pll3_init(void); +void cgc1_pll2_init(void); +void cgc1_soscdiv_init(void); +void cgc1_init_core_clk(void); +void cgc2_pll4_init(void); +void cgc2_ddrclk_config(u32 src, u32 div); +u32 cgc1_sosc_div(enum cgc1_clk clk); +#endif diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h index e145c33f01..58e3356e32 100644 --- a/arch/arm/include/asm/arch-imx8ulp/clock.h +++ b/arch/arm/include/asm/arch-imx8ulp/clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */ #ifndef _ASM_ARCH_IMX8ULP_CLOCK_H @@ -17,6 +17,7 @@ enum mxc_clock { MXC_DDR_CLK, MXC_ESDHC_CLK, MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, MXC_I2C_CLK, }; @@ -26,9 +27,15 @@ u32 get_lpuart_clk(void); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); u32 imx_get_i2cclk(unsigned int i2c_num); #endif +void enable_usboh3_clk(unsigned char enable); +int enable_usb_pll(ulong usb_phy_base); #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable); #endif void init_clk_usdhc(u32 index); +void init_clk_fspi(int index); +void init_clk_ddr(void); +int set_ddr_clk(u32 phy_freq_mhz); void clock_init(void); +void cgc1_enet_stamp_sel(u32 clk_src); #endif diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index 982f2a9b28..5231155089 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -7,6 +7,7 @@ #define _IMX8ULP_REGS_H_ #define ARCH_MXC +#include #include #define PBRIDGE0_BASE 0x28000000 diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h new file mode 100644 index 0000000000..091d0175dd --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef _ASM_ARCH_IMX8ULP_PCC_H +#define _ASM_ARCH_IMX8ULP_PCC_H + +#include + +enum pcc3_entry { + DMA1_MP_PCC3_SLOT = 1, + DMA1_CH0_PCC3_SLOT = 2, + DMA1_CH1_PCC3_SLOT = 3, + DMA1_CH2_PCC3_SLOT = 4, + DMA1_CH3_PCC3_SLOT = 5, + DMA1_CH4_PCC3_SLOT = 6, + DMA1_CH5_PCC3_SLOT = 7, + DMA1_CH6_PCC3_SLOT = 8, + DMA1_CH7_PCC3_SLOT = 9, + DMA1_CH8_PCC3_SLOT = 10, + DMA1_CH9_PCC3_SLOT = 11, + DMA1_CH10_PCC3_SLOT = 12, + DMA1_CH11_PCC3_SLOT = 13, + DMA1_CH12_PCC3_SLOT = 14, + DMA1_CH13_PCC3_SLOT = 15, + DMA1_CH14_PCC3_SLOT = 16, + DMA1_CH15_PCC3_SLOT = 17, + DMA1_CH16_PCC3_SLOT = 18, + DMA1_CH17_PCC3_SLOT = 19, + DMA1_CH18_PCC3_SLOT = 20, + DMA1_CH19_PCC3_SLOT = 21, + DMA1_CH20_PCC3_SLOT = 22, + DMA1_CH21_PCC3_SLOT = 23, + DMA1_CH22_PCC3_SLOT = 24, + DMA1_CH23_PCC3_SLOT = 25, + DMA1_CH24_PCC3_SLOT = 26, + DMA1_CH25_PCC3_SLOT = 27, + DMA1_CH26_PCC3_SLOT = 28, + DMA1_CH27_PCC3_SLOT = 29, + DMA1_CH28_PCC3_SLOT = 30, + DMA1_CH29_PCC3_SLOT = 31, + DMA1_CH30_PCC3_SLOT = 32, + DMA1_CH31_PCC3_SLOT = 33, + MU0_B_PCC3_SLOT = 34, + MU3_A_PCC3_SLOT = 35, + LLWU1_PCC3_SLOT = 38, + UPOWER_PCC3_SLOT = 40, + WDOG3_PCC3_SLOT = 42, + WDOG4_PCC3_SLOT = 43, + XRDC_MGR_PCC3_SLOT = 47, + SEMA42_1_PCC3_SLOT = 48, + ROMCP1_PCC3_SLOT = 49, + LPIT1_PCC3_SLOT = 50, + TPM4_PCC3_SLOT = 51, + TPM5_PCC3_SLOT = 52, + FLEXIO1_PCC3_SLOT = 53, + I3C2_PCC3_SLOT = 54, + LPI2C4_PCC3_SLOT = 55, + LPI2C5_PCC3_SLOT = 56, + LPUART4_PCC3_SLOT = 57, + LPUART5_PCC3_SLOT = 58, + LPSPI4_PCC3_SLOT = 59, + LPSPI5_PCC3_SLOT = 60, +}; + +enum pcc4_entry { + FLEXSPI2_PCC4_SLOT = 1, + TPM6_PCC4_SLOT = 2, + TPM7_PCC4_SLOT = 3, + LPI2C6_PCC4_SLOT = 4, + LPI2C7_PCC4_SLOT = 5, + LPUART6_PCC4_SLOT = 6, + LPUART7_PCC4_SLOT = 7, + SAI4_PCC4_SLOT = 8, + SAI5_PCC4_SLOT = 9, + PCTLE_PCC4_SLOT = 10, + PCTLF_PCC4_SLOT = 11, + SDHC0_PCC4_SLOT = 13, + SDHC1_PCC4_SLOT = 14, + SDHC2_PCC4_SLOT = 15, + USB0_PCC4_SLOT = 16, + USBPHY_PCC4_SLOT = 17, + USB1_PCC4_SLOT = 18, + USB1PHY_PCC4_SLOT = 19, + USB_XBAR_PCC4_SLOT = 20, + ENET_PCC4_SLOT = 21, + SFA1_PCC4_SLOT = 22, + RGPIOE_PCC4_SLOT = 30, + RGPIOF_PCC4_SLOT = 31, +}; + +/* PCC registers */ +#define PCC_PR_OFFSET 31 +#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) +#define PCC_CGC_OFFSET 30 +#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET) +#define PCC_INUSE_OFFSET 29 +#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) +#define PCC_PCS_OFFSET 24 +#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) +#define PCC_FRAC_OFFSET 3 +#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) +#define PCC_PCD_OFFSET 0 +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) + +enum pcc_clksrc_type { + CLKSRC_PER_PLAT = 0, + CLKSRC_PER_BUS = 1, + CLKSRC_NO_PCS = 2, +}; + +enum pcc_div_type { + PCC_HAS_DIV, + PCC_NO_DIV, +}; + +enum pcc_rst_b { + PCC_HAS_RST_B, + PCC_NO_RST_B, +}; + +/* This structure keeps info for each pcc slot */ +struct pcc_entry { + u32 pcc_base; + u32 pcc_slot; + enum pcc_clksrc_type clksrc; + enum pcc_div_type div; + enum pcc_rst_b rst_b; +}; + +int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable); +int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src); +int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div); +bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot); +int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src); +int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset); +u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot); +#endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index e8970dc04f..78c81d78bb 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -4,4 +4,4 @@ # obj-y += lowlevel_init.o -obj-y += soc.o clock.o iomux.o +obj-y += soc.o clock.o iomux.o pcc.o cgc.o diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c new file mode 100644 index 0000000000..7bfc3862cd --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL; +static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL; + +void cgc1_soscdiv_init(void) +{ + /* Configure SOSC/FRO DIV1 ~ DIV3 */ + clrbits_le32(&cgc1_regs->soscdiv, BIT(7)); + clrbits_le32(&cgc1_regs->soscdiv, BIT(15)); + clrbits_le32(&cgc1_regs->soscdiv, BIT(23)); + clrbits_le32(&cgc1_regs->soscdiv, BIT(31)); + + clrbits_le32(&cgc1_regs->frodiv, BIT(7)); +} + +void cgc1_pll2_init(void) +{ + u32 reg; + + if (readl(&cgc1_regs->pll2csr) & BIT(23)) + clrbits_le32(&cgc1_regs->pll2csr, BIT(23)); + + /* Disable PLL2 */ + clrbits_le32(&cgc1_regs->pll2csr, BIT(0)); + mdelay(1); + + /* wait valid bit false */ + while ((readl(&cgc1_regs->pll2csr) & BIT(24))) + ; + + /* Select SOSC as source, freq = 31 * 24 =744mhz */ + reg = 31 << 16; + writel(reg, &cgc1_regs->pll2cfg); + + /* Enable PLL2 */ + setbits_le32(&cgc1_regs->pll2csr, BIT(0)); + + /* Wait for PLL2 clock ready */ + while (!(readl(&cgc1_regs->pll2csr) & BIT(24))) + ; +} + +static void cgc1_set_a35_clk(u32 clk_src, u32 div_core) +{ + u32 reg; + + /* ulock */ + if (readl(&cgc1_regs->ca35clk) & BIT(31)) + clrbits_le32(&cgc1_regs->ca35clk, BIT(31)); + + reg = readl(&cgc1_regs->ca35clk); + reg &= ~GENMASK(29, 21); + reg |= ((clk_src & 0x3) << 28); + reg |= (((div_core - 1) & 0x3f) << 21); + writel(reg, &cgc1_regs->ca35clk); + + while (!(readl(&cgc1_regs->ca35clk) & BIT(27))) + ; +} + +void cgc1_init_core_clk(void) +{ + u32 reg = readl(&cgc1_regs->ca35clk); + + /* if already selected to PLL2, switch to FRO firstly */ + if (((reg >> 28) & 0x3) == 0x1) + cgc1_set_a35_clk(0, 1); + + /* Set pll2 to 750Mhz for 1V */ + cgc1_pll2_init(); + + /* Set A35 clock to pll2 */ + cgc1_set_a35_clk(1, 1); +} + +void cgc1_enet_stamp_sel(u32 clk_src) +{ + writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp); +} + +void cgc1_pll3_init(void) +{ + /* Gate off VCO */ + setbits_le32(&cgc1_regs->pll3div_vco, BIT(7)); + + /* Disable PLL3 */ + clrbits_le32(&cgc1_regs->pll3csr, BIT(0)); + + /* Gate off PFDxDIV */ + setbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31)); + setbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); + + /* Gate off PFDx */ + setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7)); + setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15)); + setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23)); + setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31)); + + /* Select SOSC as source */ + clrbits_le32(&cgc1_regs->pll3cfg, BIT(0)); + + //setbits_le32(&cgc1_regs->pll3cfg, 22 << 16); + writel(22 << 16, &cgc1_regs->pll3cfg); + + writel(578, &cgc1_regs->pll3num); + writel(1000, &cgc1_regs->pll3denom); + + /* Enable PLL3 */ + setbits_le32(&cgc1_regs->pll3csr, BIT(0)); + + /* Wait for PLL3 clock ready */ + while (!(readl(&cgc1_regs->pll3csr) & BIT(24))) + ; + /* Gate on VCO */ + clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7)); + + /* + * PFD0: 380MHz/396/396/328 + */ + clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F); + setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0); + clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7)); + while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6))) + ; + + clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8); + setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8); + clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15)); + while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14))) + ; + + clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16); + setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16); + clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23)); + while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22))) + ; + + clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24); + setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24); + clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31)); + while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30))) + ; + + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7)); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15)); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23)); + clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(31)); + + clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7)); + clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15)); + clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23)); + clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31)); +} + +void cgc2_pll4_init(void) +{ + /* Disable PFD DIV and clear DIV */ + writel(0x80808080, &cgc2_regs->pll4div_pfd0); + writel(0x80808080, &cgc2_regs->pll4div_pfd1); + + /* Gate off and clear PFD */ + writel(0x80808080, &cgc2_regs->pll4pfdcfg); + + /* Disable PLL4 */ + writel(0x0, &cgc2_regs->pll4csr); + + /* Configure PLL4 to 528Mhz and clock source from SOSC */ + writel(22 << 16, &cgc2_regs->pll4cfg); + writel(0x1, &cgc2_regs->pll4csr); + + /* wait for PLL4 output valid */ + while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) + ; + + /* Enable all 4 PFDs */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */ + setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8); + setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); + setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); + + clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31)); + + while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(30) | BIT(22) | BIT(14) | BIT(6))) + != (BIT(30) | BIT(22) | BIT(14) | BIT(6))) + ; + + /* Enable PFD DIV */ + clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31)); + clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31)); +} + +void cgc2_ddrclk_config(u32 src, u32 div) +{ + writel((src << 28) | (div << 21), &cgc2_regs->ddrclk); + /* wait for DDRCLK switching done */ + while (!(readl(&cgc2_regs->ddrclk) & BIT(27))) + ; +} + +u32 decode_pll(enum cgc1_clk pll) +{ + u32 reg, infreq, mult; + u32 num, denom; + + infreq = 24000000U; + /* + * Alought there are four choices for the bypass src, + * we choose SOSC 24M which is the default set in ROM. + * TODO: check more the comments + */ + switch (pll) { + case PLL2: + reg = readl(&cgc1_regs->pll2csr); + if (!(reg & BIT(24))) + return 0; + + reg = readl(&cgc1_regs->pll2cfg); + mult = (reg >> 16) & 0x7F; + denom = readl(&cgc1_regs->pll2denom) & 0x3FFFFFFF; + num = readl(&cgc1_regs->pll2num) & 0x3FFFFFFF; + + return (u64)infreq * mult + (u64)infreq * num / denom; + case PLL3: + reg = readl(&cgc1_regs->pll3csr); + if (!(reg & BIT(24))) + return 0; + + reg = readl(&cgc1_regs->pll3cfg); + mult = (reg >> 16) & 0x7F; + denom = readl(&cgc1_regs->pll3denom) & 0x3FFFFFFF; + num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF; + + return (u64)infreq * mult + (u64)infreq * num / denom; + default: + printf("Unsupported pll clocks %d\n", pll); + break; + } + + return 0; +} + +u32 cgc1_pll3_vcodiv_rate(void) +{ + u32 reg, gate, div; + + reg = readl(&cgc1_regs->pll3div_vco); + gate = BIT(7) & reg; + div = reg & 0x3F; + + return gate ? 0 : decode_pll(PLL3) / (div + 1); +} + +u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk) +{ + u32 index, gate, vld, reg; + + switch (clk) { + case PLL3_PFD0: + index = 0; + break; + case PLL3_PFD1: + index = 1; + break; + case PLL3_PFD2: + index = 2; + break; + case PLL3_PFD3: + index = 3; + break; + default: + return 0; + } + + reg = readl(&cgc1_regs->pll3pfdcfg); + gate = reg & (BIT(7) << (index * 8)); + vld = reg & (BIT(6) << (index * 8)); + + if (gate || !vld) + return 0; + + return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F); +} + +u32 cgc1_pll3_pfd_div(enum cgc1_clk clk) +{ + void __iomem *base; + u32 pfd, index, gate, reg; + + switch (clk) { + case PLL3_PFD0_DIV1: + base = &cgc1_regs->pll3div_pfd0; + pfd = PLL3_PFD0; + index = 0; + break; + case PLL3_PFD0_DIV2: + base = &cgc1_regs->pll3div_pfd0; + pfd = PLL3_PFD0; + index = 1; + break; + case PLL3_PFD1_DIV1: + base = &cgc1_regs->pll3div_pfd0; + pfd = PLL3_PFD1; + index = 2; + break; + case PLL3_PFD1_DIV2: + base = &cgc1_regs->pll3div_pfd0; + pfd = PLL3_PFD1; + index = 3; + break; + case PLL3_PFD2_DIV1: + base = &cgc1_regs->pll3div_pfd1; + pfd = PLL3_PFD2; + index = 0; + break; + case PLL3_PFD2_DIV2: + base = &cgc1_regs->pll3div_pfd1; + pfd = PLL3_PFD2; + index = 1; + break; + case PLL3_PFD3_DIV1: + base = &cgc1_regs->pll3div_pfd1; + pfd = PLL3_PFD3; + index = 2; + break; + case PLL3_PFD3_DIV2: + base = &cgc1_regs->pll3div_pfd1; + pfd = PLL3_PFD3; + index = 3; + break; + default: + return 0; + } + + reg = readl(base); + gate = reg & (BIT(7) << (index * 8)); + + if (gate) + return 0; + + return cgc1_pll3_pfd_rate(pfd) / (((reg >> (index * 8)) & 0x3F) + 1); +} + +u32 cgc1_sosc_div(enum cgc1_clk clk) +{ + u32 reg, gate, index; + + switch (clk) { + case SOSC: + return 24000000; + case SOSC_DIV1: + index = 0; + break; + case SOSC_DIV2: + index = 1; + break; + case SOSC_DIV3: + index = 2; + break; + default: + return 0; + } + + reg = readl(&cgc1_regs->soscdiv); + gate = reg & (BIT(7) << (index * 8)); + + if (gate) + return 0; + + return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1); +} + +u32 cgc1_fro_div(enum cgc1_clk clk) +{ + u32 reg, gate, vld, index; + + switch (clk) { + case FRO: + return 192000000; + case FRO_DIV1: + index = 0; + break; + case FRO_DIV2: + index = 1; + break; + case FRO_DIV3: + index = 2; + break; + default: + return 0; + } + + reg = readl(&cgc1_regs->frodiv); + gate = reg & (BIT(7) << (index * 8)); + vld = reg & (BIT(6) << (index * 8)); + + if (gate || !vld) + return 0; + + return 24000000 / (((reg >> (index * 8)) & 0x3F) + 1); +} + +u32 cgc1_clk_get_rate(enum cgc1_clk clk) +{ + switch (clk) { + case SOSC: + case SOSC_DIV1: + case SOSC_DIV2: + case SOSC_DIV3: + return cgc1_sosc_div(clk); + case FRO: + case FRO_DIV1: + case FRO_DIV2: + case FRO_DIV3: + return cgc1_fro_div(clk); + case PLL2: + return decode_pll(PLL2); + case PLL3: + return decode_pll(PLL3); + case PLL3_VCODIV: + return cgc1_pll3_vcodiv_rate(); + case PLL3_PFD0: + case PLL3_PFD1: + case PLL3_PFD2: + case PLL3_PFD3: + return cgc1_pll3_pfd_rate(clk); + case PLL3_PFD0_DIV1: + case PLL3_PFD0_DIV2: + case PLL3_PFD1_DIV1: + case PLL3_PFD1_DIV2: + case PLL3_PFD2_DIV1: + case PLL3_PFD2_DIV2: + case PLL3_PFD3_DIV1: + case PLL3_PFD3_DIV2: + return cgc1_pll3_pfd_div(clk); + default: + printf("Unsupported cgc1 clock: %d\n", clk); + return 0; + } +} diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index f866809fc2..ebbaad4106 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -4,24 +4,394 @@ */ #include +#include #include +#include #include #include #include +#include +#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) +#define PLL_USB_PWR_MASK (0x01 << 12) +#define PLL_USB_ENABLE_MASK (0x01 << 13) +#define PLL_USB_BYPASS_MASK (0x01 << 16) +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) +#define PLL_USB_LOCK_MASK (0x01 << 31) +#define PCC5_LPDDR4_ADDR 0x2da70108 + +static void lpuart_set_clk(u32 index, enum cgc1_clk clk) +{ + const u32 lpuart_pcc_slots[] = { + LPUART4_PCC3_SLOT, + LPUART5_PCC3_SLOT, + LPUART6_PCC4_SLOT, + LPUART7_PCC4_SLOT, + }; + + const u32 lpuart_pcc[] = { + 3, 3, 4, 4, + }; + + if (index > 3) + return; + + pcc_clock_enable(lpuart_pcc[index], lpuart_pcc_slots[index], false); + pcc_clock_sel(lpuart_pcc[index], lpuart_pcc_slots[index], clk); + pcc_clock_enable(lpuart_pcc[index], lpuart_pcc_slots[index], true); + + pcc_reset_peripheral(lpuart_pcc[index], lpuart_pcc_slots[index], false); +} + +static void init_clk_lpuart(void) +{ + u32 index = 0, i; + + const u32 lpuart_array[] = { + LPUART4_RBASE, + LPUART5_RBASE, + LPUART6_RBASE, + LPUART7_RBASE, + }; + + for (i = 0; i < 4; i++) { + if (lpuart_array[i] == LPUART_BASE) { + index = i; + break; + } + } + + lpuart_set_clk(index, SOSC_DIV2); +} + +void init_clk_fspi(int index) +{ + pcc_clock_enable(4, FLEXSPI2_PCC4_SLOT, false); + pcc_clock_sel(4, FLEXSPI2_PCC4_SLOT, PLL3_PFD2_DIV1); + pcc_clock_div_config(4, FLEXSPI2_PCC4_SLOT, false, 8); + pcc_clock_enable(4, FLEXSPI2_PCC4_SLOT, true); + pcc_reset_peripheral(4, FLEXSPI2_PCC4_SLOT, false); +} + +void setclkout_ddr(void) +{ + writel(0x12800000, 0x2DA60020); + writel(0xa00, 0x298C0000); /* PTD0 */ +} + +void ddrphy_pll_lock(void) +{ + writel(0x00011542, 0x2E065964); + writel(0x00011542, 0x2E06586C); + + writel(0x00000B01, 0x2E062000); + writel(0x00000B01, 0x2E060000); +} + +void init_clk_ddr(void) +{ + /* enable pll4 and ddrclk*/ + cgc2_pll4_init(); + cgc2_ddrclk_config(1, 1); + + /* enable ddr pcc */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); + + /* for debug */ + /* setclkout_ddr(); */ +} + +int set_ddr_clk(u32 phy_freq_mhz) +{ + debug("%s %u\n", __func__, phy_freq_mhz); + + if (phy_freq_mhz == 48) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(2, 0); /* 24Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else if (phy_freq_mhz == 384) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(0, 0); /* 192Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else if (phy_freq_mhz == 528) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(4, 1); /* 264Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else if (phy_freq_mhz == 264) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(4, 3); /* 132Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else if (phy_freq_mhz == 192) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(0, 1); /* 96Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else if (phy_freq_mhz == 96) { + writel(0x90000000, PCC5_LPDDR4_ADDR); /* disable ddr pcc */ + cgc2_ddrclk_config(0, 3); /* 48Mhz DDR clock */ + writel(0xd0000000, PCC5_LPDDR4_ADDR); /* enable ddr pcc */ + } else { + printf("ddr phy clk %uMhz is not supported\n", phy_freq_mhz); + return -EINVAL; + } + + return 0; +} + void clock_init(void) { + cgc1_soscdiv_init(); + cgc1_init_core_clk(); + + init_clk_lpuart(); + + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); + + /* Enable upower mu1 clk */ + pcc_clock_enable(3, UPOWER_PCC3_SLOT, true); + + /* + * Enable clock division + * TODO: may not needed after ROM ready. + */ +} + +#if IS_ENABLED(CONFIG_SYS_I2C_IMX_LPI2C) +int enable_i2c_clk(unsigned char enable, u32 i2c_num) +{ + /* Set parent to FIRC DIV2 clock */ + const u32 lpi2c_pcc_clks[] = { + LPI2C4_PCC3_SLOT << 8 | 3, + LPI2C5_PCC3_SLOT << 8 | 3, + LPI2C6_PCC4_SLOT << 8 | 4, + LPI2C7_PCC4_SLOT << 8 | 4, + }; + + if (i2c_num < 4 || i2c_num > 7) + return -EINVAL; + + if (enable) { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8, false); + pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8, SOSC_DIV2); + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8, true); + pcc_reset_peripheral(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8, false); + } else { + pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8, false); + } + return 0; +} + +u32 imx_get_i2cclk(u32 i2c_num) +{ + const u32 lpi2c_pcc_clks[] = { + LPI2C4_PCC3_SLOT << 8 | 3, + LPI2C5_PCC3_SLOT << 8 | 3, + LPI2C6_PCC4_SLOT << 8 | 4, + LPI2C7_PCC4_SLOT << 8 | 4, + }; + + if (i2c_num < 4 || i2c_num > 7) + return 0; + + return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4] & 0xff, + lpi2c_pcc_clks[i2c_num - 4] >> 8); +} +#endif + +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + pcc_clock_enable(4, USB0_PCC4_SLOT, true); + pcc_clock_enable(4, USBPHY_PCC4_SLOT, true); + pcc_reset_peripheral(4, USB0_PCC4_SLOT, false); + pcc_reset_peripheral(4, USBPHY_PCC4_SLOT, false); + +#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT + if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { + pcc_clock_enable(4, USB1_PCC4_SLOT, true); + pcc_clock_enable(4, USB1PHY_PCC4_SLOT, true); + pcc_reset_peripheral(4, USB1_PCC4_SLOT, false); + pcc_reset_peripheral(4, USB1PHY_PCC4_SLOT, false); + } +#endif + + pcc_clock_enable(4, USB_XBAR_PCC4_SLOT, true); + } else { + pcc_clock_enable(4, USB0_PCC4_SLOT, false); + pcc_clock_enable(4, USB1_PCC4_SLOT, false); + pcc_clock_enable(4, USBPHY_PCC4_SLOT, false); + pcc_clock_enable(4, USB1PHY_PCC4_SLOT, false); + pcc_clock_enable(4, USB_XBAR_PCC4_SLOT, false); + } } -unsigned int mxc_get_clock(enum mxc_clock clk) +int enable_usb_pll(ulong usb_phy_base) { + u32 sosc_rate; + s32 timeout = 1000000; + + struct usbphy_regs *usbphy = + (struct usbphy_regs *)usb_phy_base; + + sosc_rate = cgc1_sosc_div(SOSC); + if (!sosc_rate) + return -EPERM; + + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { + writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr); + + switch (sosc_rate) { + case 24000000: + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); + break; + + case 30000000: + writel(0x800000, &usbphy->usb1_pll_480_ctrl_set); + break; + + case 19200000: + writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set); + break; + + default: + writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set); + break; + } + + /* Enable the regulator first */ + writel(PLL_USB_REG_ENABLE_MASK, + &usbphy->usb1_pll_480_ctrl_set); + + /* Wait at least 15us */ + udelay(15); + + /* Enable the power */ + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); + + /* Wait lock */ + while (timeout--) { + if (readl(&usbphy->usb1_pll_480_ctrl) & + PLL_USB_LOCK_MASK) + break; + } + + if (timeout <= 0) { + /* If timeout, we power down the pll */ + writel(PLL_USB_PWR_MASK, + &usbphy->usb1_pll_480_ctrl_clr); + return -ETIME; + } + } + + /* Clear the bypass */ + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); + + /* Enable the PLL clock out to USB */ + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK), + &usbphy->usb1_pll_480_ctrl_set); + return 0; } +u32 mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ESDHC_CLK: + return pcc_clock_get_rate(4, SDHC0_PCC4_SLOT); + case MXC_ESDHC2_CLK: + return pcc_clock_get_rate(4, SDHC1_PCC4_SLOT); + case MXC_ESDHC3_CLK: + return pcc_clock_get_rate(4, SDHC2_PCC4_SLOT); + case MXC_ARM_CLK: + return cgc1_clk_get_rate(PLL2); + default: + return 0; + } +} + u32 get_lpuart_clk(void) { - return 24000000; + int index = 0; + + const u32 lpuart_array[] = { + LPUART4_RBASE, + LPUART5_RBASE, + LPUART6_RBASE, + LPUART7_RBASE, + }; + + const u32 lpuart_pcc_slots[] = { + LPUART4_PCC3_SLOT, + LPUART5_PCC3_SLOT, + LPUART6_PCC4_SLOT, + LPUART7_PCC4_SLOT, + }; + + const u32 lpuart_pcc[] = { + 3, 3, 4, 4, + }; + + for (index = 0; index < 4; index++) { + if (lpuart_array[index] == LPUART_BASE) + break; + } + + if (index > 3) + return 0; + + return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]); +} + +#ifndef CONFIG_SPL_BUILD +/* + * Dump some core clockes. + */ +int do_mx8ulp_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("SDHC0 %8d MHz\n", pcc_clock_get_rate(4, SDHC0_PCC4_SLOT) / 1000000); + printf("SDHC1 %8d MHz\n", pcc_clock_get_rate(4, SDHC1_PCC4_SLOT) / 1000000); + printf("SDHC2 %8d MHz\n", pcc_clock_get_rate(4, SDHC2_PCC4_SLOT) / 1000000); + + printf("SOSC %8d MHz\n", cgc1_clk_get_rate(SOSC) / 1000000); + printf("FRO %8d MHz\n", cgc1_clk_get_rate(FRO) / 1000000); + printf("PLL2 %8d MHz\n", cgc1_clk_get_rate(PLL2) / 1000000); + printf("PLL3 %8d MHz\n", cgc1_clk_get_rate(PLL3) / 1000000); + printf("PLL3_VCODIV %8d MHz\n", cgc1_clk_get_rate(PLL3_VCODIV) / 1000000); + printf("PLL3_PFD0 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD0) / 1000000); + printf("PLL3_PFD1 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD1) / 1000000); + printf("PLL3_PFD2 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD2) / 1000000); + printf("PLL3_PFD3 %8d MHz\n", cgc1_clk_get_rate(PLL3_PFD3) / 1000000); + + return 0; } + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mx8ulp_showclocks, + "display clocks", + "" +); +#endif diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c new file mode 100644 index 0000000000..711b685cd7 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define cgc1_clk_TYPES 2 +#define cgc1_clk_NUM 8 + +static enum cgc1_clk pcc3_clksrc[][8] = { + { + }, + { DUMMY0_CLK, + LPOSC, + SOSC_DIV2, + FRO_DIV2, + XBAR_BUSCLK, + PLL3_PFD1_DIV1, + PLL3_PFD0_DIV2, + PLL3_PFD0_DIV1 + } +}; + +static enum cgc1_clk pcc4_clksrc[][8] = { + { + DUMMY0_CLK, + SOSC_DIV1, + FRO_DIV1, + PLL3_PFD3_DIV2, + PLL3_PFD3_DIV1, + PLL3_PFD2_DIV2, + PLL3_PFD2_DIV1, + PLL3_PFD1_DIV2 + }, + { + DUMMY0_CLK, + DUMMY1_CLK, + LPOSC, + SOSC_DIV2, + FRO_DIV2, + XBAR_BUSCLK, + PLL3_VCODIV, + PLL3_PFD0_DIV1 + } +}; + +static struct pcc_entry pcc3_arrays[] = { + {PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH1_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH2_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH3_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH4_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH5_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH6_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH7_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH8_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH9_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH10_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH11_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH12_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH13_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH14_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH15_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH16_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH17_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH18_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH19_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH20_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH21_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH22_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH23_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH24_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH25_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH26_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH27_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH28_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH29_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH30_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, DMA1_CH31_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, MU0_B_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, MU3_A_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, LLWU1_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, UPOWER_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, WDOG3_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, WDOG4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, XRDC_MGR_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, SEMA42_1_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, ROMCP1_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, + {PCC3_RBASE, LPIT1_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, TPM4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, TPM5_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, FLEXIO1_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, I3C2_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPI2C4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPI2C5_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPUART4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPUART5_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPSPI4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {PCC3_RBASE, LPSPI5_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B}, + {} +}; + +static struct pcc_entry pcc4_arrays[] = { + {PCC4_RBASE, FLEXSPI2_PCC4_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, TPM6_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, TPM7_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, LPI2C6_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, LPI2C7_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, LPUART6_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, LPUART7_PCC4_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, SAI4_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, SAI5_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, PCTLE_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC4_RBASE, PCTLF_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC4_RBASE, SDHC0_PCC4_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, SDHC1_PCC4_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, SDHC2_PCC4_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, USB0_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, USBPHY_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, USB1_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, USB1PHY_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, USB_XBAR_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC4_RBASE, ENET_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B }, + {PCC4_RBASE, SFA1_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC4_RBASE, RGPIOE_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {PCC4_RBASE, RGPIOF_PCC4_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B }, + {} +}; + +static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry **out) +{ + struct pcc_entry *pcc_array; + int index = 0; + + switch (pcc_controller) { + case 3: + pcc_array = pcc3_arrays; + *out = &pcc3_arrays[0]; + break; + case 4: + pcc_array = pcc4_arrays; + *out = &pcc4_arrays[0]; + break; + default: + printf("Not supported pcc_controller: %d\n", pcc_controller); + return -EINVAL; + } + + while (pcc_array->pcc_base) { + if (pcc_array->pcc_slot == pcc_clk_slot) + return index; + + pcc_array++; + index++; + } + + return -ENOENT; +} + +int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable) +{ + u32 val; + void __iomem *reg; + int clk; + struct pcc_entry *pcc_array; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + + val = readl(reg); + + debug("%s: clk %d, reg 0x%p, val 0x%x, enable %d\n", __func__, clk, reg, val, enable); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK)) + return -EPERM; + + if (enable) + val |= PCC_CGC_MASK; + else + val &= ~PCC_CGC_MASK; + + writel(val, reg); + + debug("%s: val 0x%x\n", __func__, val); + + return 0; +} + +/* The clock source select needs clock is disabled */ +int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src) +{ + u32 val, i, clksrc_type; + void __iomem *reg; + struct pcc_entry *pcc_array; + enum cgc1_clk *cgc1_clk_array; + int clk; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + + clksrc_type = pcc_array[clk].clksrc; + if (clksrc_type >= CLKSRC_NO_PCS) { + printf("No PCS field for the PCC %d, clksrc type %d\n", + clk, clksrc_type); + return -EPERM; + } + + if (pcc_controller == 3) + cgc1_clk_array = pcc3_clksrc[clksrc_type]; + else + cgc1_clk_array = pcc4_clksrc[clksrc_type]; + + for (i = 0; i < cgc1_clk_NUM; i++) { + if (cgc1_clk_array[i] == src) { + /* Find the clock src, then set it to PCS */ + break; + } + } + + if (i == cgc1_clk_NUM) { + printf("No parent in PCS of PCC %d, invalid scg_clk %d\n", clk, src); + return -EINVAL; + } + + val = readl(reg); + + debug("%s: clk %d, reg 0x%p, val 0x%x, clksrc_type %d\n", + __func__, clk, reg, val, clksrc_type); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || + (val & PCC_CGC_MASK)) { + printf("Not permit to select clock source val = 0x%x\n", val); + return -EPERM; + } + + val &= ~PCC_PCS_MASK; + val |= i << PCC_PCS_OFFSET; + + writel(val, reg); + + debug("%s: val 0x%x\n", __func__, val); + + return 0; +} + +int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div) +{ + u32 val; + void __iomem *reg; + struct pcc_entry *pcc_array; + int clk; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + + if (div > 8 || (div == 1 && frac != 0)) + return -EINVAL; + + if (pcc_array[clk].div >= PCC_NO_DIV) { + printf("No DIV/FRAC field for the PCC %d\n", clk); + return -EPERM; + } + + val = readl(reg); + + if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) || + (val & PCC_CGC_MASK)) { + printf("Not permit to set div/frac val = 0x%x\n", val); + return -EPERM; + } + + if (frac) + val |= PCC_FRAC_MASK; + else + val &= ~PCC_FRAC_MASK; + + val &= ~PCC_PCD_MASK; + val |= (div - 1) & PCC_PCD_MASK; + + writel(val, reg); + + return 0; +} + +bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot) +{ + u32 val; + void __iomem *reg; + struct pcc_entry *pcc_array; + int clk; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + val = readl(reg); + + if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK)) + return true; + + return false; +} + +int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src) +{ + u32 val, clksrc_type; + void __iomem *reg; + struct pcc_entry *pcc_array; + int clk; + enum cgc1_clk *cgc1_clk_array; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + clksrc_type = pcc_array[clk].clksrc; + if (clksrc_type >= CLKSRC_NO_PCS) { + printf("No PCS field for the PCC %d, clksrc type %d\n", + pcc_clk_slot, clksrc_type); + return -EPERM; + } + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + + val = readl(reg); + + debug("%s: clk %d, reg 0x%p, val 0x%x, type %d\n", + __func__, pcc_clk_slot, reg, val, clksrc_type); + + if (!(val & PCC_PR_MASK)) { + printf("This pcc slot is not present = 0x%x\n", val); + return -EPERM; + } + + val &= PCC_PCS_MASK; + val = (val >> PCC_PCS_OFFSET); + + if (!val) { + printf("Clock source is off\n"); + return -EIO; + } + + if (pcc_controller == 3) + cgc1_clk_array = pcc3_clksrc[clksrc_type]; + else + cgc1_clk_array = pcc4_clksrc[clksrc_type]; + + *src = cgc1_clk_array[val]; + + debug("%s: parent cgc1 clk %d\n", __func__, *src); + + return 0; +} + +int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset) +{ + u32 val; + void __iomem *reg; + struct pcc_entry *pcc_array; + int clk; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + if (pcc_array[clk].rst_b == PCC_NO_RST_B) + return 0; + + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + pcc_array[clk].pcc_slot * 4); + + val = readl(reg); + + debug("%s: clk %d, reg 0x%p, val 0x%x\n", __func__, pcc_clk_slot, reg, val); + + if (!(val & PCC_PR_MASK)) { + printf("This pcc slot is not present = 0x%x\n", val); + return -EPERM; + } + + if (reset) + val &= ~BIT(28); + else + val |= BIT(28); + + writel(val, reg); + + debug("%s: clk %d, reg 0x%p, val 0x%x\n", __func__, pcc_clk_slot, reg, val); + + return 0; +} + +u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot) +{ + u32 val, rate, frac, div; + void __iomem *reg; + enum cgc1_clk parent; + int ret; + int clk; + struct pcc_entry *pcc_array; + + clk = find_pcc_entry(pcc_controller, pcc_clk_slot, &pcc_array); + if (clk < 0) + return -EINVAL; + + ret = pcc_clock_get_clksrc(pcc_controller, pcc_clk_slot, &parent); + if (ret) + return 0; + + rate = cgc1_clk_get_rate(parent); + + debug("%s: parent rate %u\n", __func__, rate); + + if (pcc_array[clk].div == PCC_HAS_DIV) { + reg = (void __iomem *)(uintptr_t)(pcc_array[clk].pcc_base + + pcc_array[clk].pcc_slot * 4); + val = readl(reg); + + frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; + div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET; + + /* + * Theoretically don't have overflow in the calc, + * the rate won't exceed 2G + */ + rate = rate * (frac + 1) / (div + 1); + } + + debug("%s: rate %u\n", __func__, rate); + return rate; +} diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 3029589d5f..6f4b506386 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -287,5 +287,8 @@ void get_board_serial(struct tag_serialnr *serialnr) int arch_cpu_init(void) { + if (IS_ENABLED(CONFIG_SPL_BUILD)) + clock_init(); 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Wed, 21 Jul 2021 13:44:00 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 17/44] drivers: mmc: fsl_esdhc_imx: support i.MX8ULP Date: Wed, 21 Jul 2021 22:16:58 +0800 Message-Id: <20210721141725.23346-18-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:43:58 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ad28f45b-6ab1-4554-dd11-08d94c4d981f X-MS-TrafficTypeDiagnostic: DB7PR04MB4633: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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Signed-off-by: Peng Fan --- drivers/mmc/Kconfig | 2 +- drivers/mmc/fsl_esdhc_imx.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) -- 2.30.0 diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 717ce5a62f..1569e8c44a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -832,7 +832,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 465d935daf..aabf39535f 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -291,7 +291,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, { int timeout; struct fsl_esdhc *regs = priv->esdhc_regs; -#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \ + defined(CONFIG_IMX8ULP) dma_addr_t addr; #endif uint wml_value; @@ -304,7 +305,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \ + defined(CONFIG_IMX8ULP) addr = virt_to_phys((void *)(data->dest)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -341,7 +343,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, wml_value << 16); #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO -#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \ + defined(CONFIG_IMX8ULP) addr = virt_to_phys((void *)(data->src)); if (upper_32_bits(addr)) printf("Error found for upper 32 bits\n"); @@ -406,7 +409,8 @@ static void check_and_invalidate_dcache_range unsigned end = 0; unsigned size = roundup(ARCH_DMA_MINALIGN, data->blocks*data->blocksize); -#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) +#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \ + defined(CONFIG_IMX8ULP) dma_addr_t addr; addr = virt_to_phys((void *)(data->dest)); From patchwork Wed Jul 21 14:17:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483295 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6211798jao; Wed, 21 Jul 2021 06:47:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhKR6sxr6WeXYdyDsfJgj1THnyhk7/x3NM7Kpg6mG2H1KtaU4fYvzIW1l87tMTYz7an7Tl X-Received: by 2002:aa7:c458:: with SMTP id n24mr49273423edr.30.1626875245856; Wed, 21 Jul 2021 06:47:25 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875245; cv=pass; d=google.com; s=arc-20160816; b=nc4eUpXEGSGyeisIBXdDYCBZJ4qxyNKGXRcZwi44qYmmOo56r5K7lLew+h4rbNQu5l xZm53ahsObU2oasdagq8KyzQYocBMqbE6JWDDSyEkN8awqrxaSlII9koZWwJCoW+l4cB 1KYpdGlrr2PYoLgbnGo+TqF0lTDrAVajtu3d7lnH7WhyQ7ilZ1lHxjwG6TodBFp8+c+O RAtjIoYl0jVTj7qKhPMXLlALunWW9GRCJ4HrGzRAQozSvHlGu5WpEwYsmgfAuXScLSaE YbHVS+tZliRm0EXm13mv6E1CLDj9jZdP4qMbOHLylV9j4R7uh+CRTVGd8gppTctSba4y N4+A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=cNnsAIW7am4/EyhfDfCEZegNaceeUtF2nfS6EfZVEmo=; b=xyCOijtUeAcU7a1Y8PdaVPoHXBR0y5JndKlKEfXNw/hCrYAzmDiv2XDYYQPAlABjs7 WyqD9r8+ZuSCpxufTSwy13ybAElfldCAiTXKtbm42P4JMx5oSucP5Lmb44Lkm2ICmraR RVwKBQE7RCBVDdoU17zQ1OuPLCvKucq6QDj/YFN+zCKhzWVUMyHSr450LBO+gIArW7n0 3cWtybe+5MBG8y9P8y/g1Z4Q1vVW8YnyBFpQJ+K2qv0IF8M+3+ZJptOhrLLYGt58Z+RJ 5GGnqah2Dl8QgpYd+XKji9WnZVGnfzPpggcpS0L/+oi7OtFxBLLqCRpZxJb2IZ+L6FCf B9bQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=ZJyzQq6s; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 21 Jul 2021 13:44:07 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 20/44] arm: imx8ulp: disable wdog3 Date: Wed, 21 Jul 2021 22:17:01 +0800 Message-Id: <20210721141725.23346-21-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:44:05 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b4d6ff9b-b273-47fd-a628-08d94c4d9cb5 X-MS-TrafficTypeDiagnostic: DB7PR04MB4633: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1247; 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+ + if (!(val_cs & 0x80)) + return; + + dmb(); + __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); + dmb(); + + if (!(val_cs & 800)) { + dmb(); + __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); + __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x800)) + ; + } + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ + + while (!(readl(wdog_base + 0x00) & 0x400)) + ; +} + void init_wdog(void) { - /* TODO */ + disable_wdog((void __iomem *)WDG3_RBASE); } static struct mm_region imx8ulp_arm64_mem_map[] = { From patchwork Wed Jul 21 14:17:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483296 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6212838jao; 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Wed, 21 Jul 2021 13:44:26 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 27/44] arm: imx8ulp: add rdc support Date: Wed, 21 Jul 2021 22:17:08 +0800 Message-Id: <20210721141725.23346-28-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:44:24 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9d3fd455-3702-475c-1a21-08d94c4da797 X-MS-TrafficTypeDiagnostic: DB6PR0402MB2757: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1332; 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 2 + arch/arm/mach-imx/imx8ulp/Makefile | 2 +- arch/arm/mach-imx/imx8ulp/rdc.c | 144 ++++++++++++++++++ 3 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-imx/imx8ulp/rdc.c -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index a8f632f45e..47ee46bdf4 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -13,4 +13,6 @@ extern unsigned long rom_pointer[]; ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf); ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); enum bt_mode get_boot_mode(void); +int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); +int xrdc_config_pdac_openacc(u32 bridge, u32 index); #endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 78c81d78bb..1ef6cd5c91 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -4,4 +4,4 @@ # obj-y += lowlevel_init.o -obj-y += soc.o clock.o iomux.o pcc.o cgc.o +obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c new file mode 100644 index 0000000000..7a098718da --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define XRDC_ADDR 0x292f0000 +#define MRC_OFFSET 0x2000 +#define MRC_STEP 0x200 + +#define SP(X) ((X) << 9) +#define SU(X) ((X) << 6) +#define NP(X) ((X) << 3) +#define NU(X) ((X) << 0) + +#define RWX 7 +#define RW 6 +#define R 4 +#define X 1 + +#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX)) +#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX)) +#define D5SEL_CODE (SP(RW) | SU(RWX)) +#define D4SEL_CODE SP(RWX) +#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X)) +#define D0SEL_CODE 0 + +#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW)) +#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW)) +#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R)) +#define D4SEL_DAT (SP(RW) | SU(RW)) +#define D3SEL_DAT SP(RW) + +union dxsel_perm { + struct { + u8 dx; + u8 perm; + }; + + u32 dom_perm; +}; + +int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel) +{ + ulong w2_addr; + u32 val = 0; + + w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8; + + val = (readl(w2_addr) & (~(7 << (3 * dom)))) | (dxsel << (3 * dom)); + writel(val, w2_addr); + + return 0; +} + +int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size) +{ + ulong w0_addr, w1_addr; + + w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20; + w1_addr = w0_addr + 4; + + if ((size % 32) != 0) + return -EINVAL; + + writel(w0 & ~0x1f, w0_addr); + writel(w0 + size - 1, w1_addr); + + return 0; +} + +int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4) +{ + ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC; + ulong w4_addr = w3_addr + 4; + + writel(w3, w3_addr); + writel(w4, w4_addr); + + return 0; +} + +int xrdc_config_pdac_openacc(u32 bridge, u32 index) +{ + ulong w0_addr; + u32 val; + + switch (bridge) { + case 3: + w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index; + break; + case 4: + w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index; + break; + case 5: + w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index; + break; + default: + return -EINVAL; + } + writel(0xffffff, w0_addr); + + val = readl(w0_addr + 4); + writel(val | BIT(31), w0_addr + 4); + + return 0; +} + +int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) +{ + ulong w0_addr; + u32 val; + + switch (bridge) { + case 3: + w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index; + break; + case 4: + w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index; + break; + case 5: + w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index; + break; + default: + return -EINVAL; + } + val = readl(w0_addr); + writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr); + + val = readl(w0_addr + 4); + writel(val | BIT(31), w0_addr + 4); + + return 0; +} From patchwork Wed Jul 21 14:17:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483297 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6213015jao; Wed, 21 Jul 2021 06:48:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuhSZBbHBzOwYyb4EtDtHha7fHwobBqMdvS+2u1ZkkvPFvNgmULC0AGCnEU1dhq5evDELo X-Received: by 2002:a05:6402:17c4:: with SMTP id s4mr8282157edy.101.1626875331107; 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Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 62c02a6223..43fe62c2fd 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -344,17 +344,23 @@ static void set_core0_reset_vector(u32 entry) setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); } -static int release_xrdc(void) +enum rdc_type { + RDC_TRDC, + RDC_XRDC, +}; + +static int release_rdc(enum rdc_type type) { ulong s_mu_base = 0x27020000UL; struct imx8ulp_s400_msg msg; int ret; + u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; msg.version = AHAB_VERSION; msg.tag = AHAB_CMD_TAG; msg.size = 2; msg.command = AHAB_RELEASE_RDC_REQ_CID; - msg.data[0] = (0x78 << 8) | 0x2; /* A35 XRDC */ + msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ mu_hal_init(s_mu_base); mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); @@ -363,13 +369,12 @@ static int release_xrdc(void) ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); if (!ret) { ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); - if (!ret) - return ret; + if (!ret) { + if ((msg.data[0] & 0xff) == 0xd6) + return 0; + } - if ((msg.data[0] & 0xff) == 0) - return 0; - else - return -EIO; + return -EIO; } return ret; @@ -423,8 +428,11 @@ int arch_cpu_init(void) /* Disable wdog */ init_wdog(); + if (get_boot_mode() == SINGLE_BOOT) + release_rdc(RDC_TRDC); + /* release xrdc, then allow A35 to write SRAM2 */ - release_xrdc(); + release_rdc(RDC_XRDC); xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); clock_init(); From patchwork Wed Jul 21 14:17:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483298 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6213170jao; Wed, 21 Jul 2021 06:49:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwKdNaErVjt56nJIxdHKB0lJ1bEG8Pak7rFVe0gHlM5hbO1LmOeW5qym1gR0pJZIqNZwnPc X-Received: by 2002:a17:906:990f:: with SMTP id zl15mr38870248ejb.34.1626875341418; Wed, 21 Jul 2021 06:49:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875341; cv=pass; d=google.com; s=arc-20160816; b=YVQ3iwsfPoo9Xi6NMITl9R41C2gdZuXbgecUFND4LdapWtNQMAvzMR9851BlD2vn3b CbLOYE5D9ppPH1aB4BMl/9cF/9dj4DiycAQ543M91uA9q8QmmIlLMCdpPeS3wVhfYnUL 4h2NL9EFPvihWJaIbhC6/US2snrRWz+/ZapsX3R9PmuXenXLwVU1+IFzbKkHPuzD6io+ uYAkVzWY4RXjc3xsAPrbMmoED4XZXtM0ZdxTBhdvXvbpdgtBcb+rDDmBqEH9hy3+UuqK t1cwoABTIHdj1KUHQ2lYIeTSmnNcyAVfjvj1QnwugDzl4sBg19mEKe72GbJsif7MmTrz lfag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=SM7wQoZPfTof5cvek/LTF2Bsmyn/joESbzZf4Z6F0fI=; b=hccimzDFULjQznn6bGQgclHYSn8ClX3ws+9r2ap4WVn9eX1JI2Yn/k4fXx+ltoZPH6 oaHHNHelZceuAdAzrBWo9ljVWb+yW46skaEXKjItR08rMxL+gsXhuT6QtqbzPK3gYaJZ f5KBX/YRS3GYboAjxPaUDJj/FeLcxOySS/H/4yxnkIIe4WvyM3a+48WWC3sDUJEnlT+N mKyfTHiPhQfvZx/ongqtUSiuk3CALe9lhl00JVlKpIq5XSD6vnSvUxFtHhZD4qFKyFy8 uOkG4aR408IYJqEoPH0kRrhn/37SPehGatPxjYdSBFfa7tZn2ADXRmtza74JwioIDdF/ 4UOg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=kXEZwHCo; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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Wed, 21 Jul 2021 13:44:31 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan , Ye Li Subject: [PATCH V4 29/44] arm: imx8ulp: release trdc and assign lpav from RTD to APD Date: Wed, 21 Jul 2021 22:17:10 +0800 Message-Id: <20210721141725.23346-30-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:44:28 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 34c8c882-0a6f-4e34-ee72-08d94c4daaa2 X-MS-TrafficTypeDiagnostic: DB6PR0402MB2757: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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Signed-off-by: Peng Fan Signed-off-by: Ye Li --- arch/arm/mach-imx/imx8ulp/soc.c | 104 +++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 43fe62c2fd..29f7d5be02 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -380,6 +380,102 @@ static int release_rdc(enum rdc_type type) return ret; } +struct mbc_mem_dom { + u32 mem_glbcfg[4]; + u32 nse_blk_index; + u32 nse_blk_set; + u32 nse_blk_clr; + u32 nsr_blk_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + u32 mem0_blk_cfg_w[64]; + u32 mem0_blk_nse_w[16]; + u32 mem1_blk_cfg_w[8]; + u32 mem1_blk_nse_w[2]; + u32 mem2_blk_cfg_w[8]; + u32 mem2_blk_nse_w[2]; + u32 mem3_blk_cfg_w[8]; + u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ + u32 reserved[2]; +}; + +struct trdc { + u8 res0[0x1000]; + struct mbc_mem_dom mem_dom[4][8]; +}; + +/* MBC[m]_[d]_MEM[s]_BLK_CFG_W[w] */ +int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, u32 perm) +{ + struct trdc *trdc_base = (struct trdc *)0x28031000U; + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w, *nse_w; + u32 index, offset, val; + + mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = readl((void __iomem *)cfg_w); + + val &= ~(0xFU << offset); + + if (perm == 0x7700) { + val |= (0x0 << offset); + writel(perm, (void __iomem *)cfg_w); + } else if (perm == 0x0077) { + val |= (0x8 << offset); /* nse bit set */ + writel(val, (void __iomem *)cfg_w); + } else { + return -EINVAL; + } + + return 0; +} + +int trdc_set_access(void) +{ + /* + * CGC0: PBridge0 slot 47 + * trdc_mbc_set_access(2, 7, 0, 47, 0x7700); + * For secure access, default single boot already support, + * For non-secure access, need add in future per usecase. + */ + trdc_mbc_set_access(2, 7, 0, 49, 0x7700); + trdc_mbc_set_access(2, 7, 0, 50, 0x7700); + trdc_mbc_set_access(2, 7, 0, 51, 0x7700); + trdc_mbc_set_access(2, 7, 0, 52, 0x7700); + + trdc_mbc_set_access(2, 7, 0, 47, 0x0077); + + /* iomuxc 0 */ + trdc_mbc_set_access(2, 7, 1, 33, 0x7700); + + return 0; +} + static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access) { ulong xrdc_base = 0x292f0000, off; @@ -428,8 +524,14 @@ int arch_cpu_init(void) /* Disable wdog */ init_wdog(); - if (get_boot_mode() == SINGLE_BOOT) + if (get_boot_mode() == SINGLE_BOOT) { release_rdc(RDC_TRDC); + trdc_set_access(); + /* LPAV to APD */ + setbits_le32(0x2802B044, BIT(7)); + /* GPU 2D/3D to APD */ + setbits_le32(0x2802B04C, BIT(1) | BIT(2)); + } /* release xrdc, then allow A35 to write SRAM2 */ release_rdc(RDC_XRDC); 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+ +int release_rdc(enum rdc_type type); +void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access); +int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel); +int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size); +int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4); +int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm); +int xrdc_config_pdac_openacc(u32 bridge, u32 index); +int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access); +int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access); + +void xrdc_init_mda(void); +void xrdc_init_mrc(void); + +#endif diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index 7a098718da..e2eca0633e 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -1,18 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 NXP + * Copyright 2021 NXP */ #include -#include -#include #include -#include -#include +#include +#include #include -#include - -DECLARE_GLOBAL_DATA_PTR; +#include +#include +#include +#include #define XRDC_ADDR 0x292f0000 #define MRC_OFFSET 0x2000 @@ -41,6 +40,45 @@ DECLARE_GLOBAL_DATA_PTR; #define D4SEL_DAT (SP(RW) | SU(RW)) #define D3SEL_DAT SP(RW) +struct mbc_mem_dom { + u32 mem_glbcfg[4]; + u32 nse_blk_index; + u32 nse_blk_set; + u32 nse_blk_clr; + u32 nsr_blk_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + u32 mem0_blk_cfg_w[64]; + u32 mem0_blk_nse_w[16]; + u32 mem1_blk_cfg_w[8]; + u32 mem1_blk_nse_w[2]; + u32 mem2_blk_cfg_w[8]; + u32 mem2_blk_nse_w[2]; + u32 mem3_blk_cfg_w[8]; + u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ + u32 reserved[2]; +}; + +struct mrc_rgn_dom { + u32 mrc_glbcfg[4]; + u32 nse_rgn_indirect; + u32 nse_rgn_set; + u32 nse_rgn_clr; + u32 nse_rgn_clr_all; + u32 memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + u32 rgn_desc_words[8][2]; /* 8 regions, 2 words per region */ + u32 reserved[16]; + u32 rgn_nse; + u32 reserved2[15]; +}; + +struct trdc { + u8 res0[0x1000]; + struct mbc_mem_dom mem_dom[4][8]; + struct mrc_rgn_dom mrc_dom[2][8]; +}; + union dxsel_perm { struct { u8 dx; @@ -142,3 +180,232 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm) return 0; } + +int release_rdc(enum rdc_type type) +{ + ulong s_mu_base = 0x27020000UL; + struct imx8ulp_s400_msg msg; + int ret; + u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; + + msg.version = AHAB_VERSION; + msg.tag = AHAB_CMD_TAG; + msg.size = 2; + msg.command = AHAB_RELEASE_RDC_REQ_CID; + msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ + + mu_hal_init(s_mu_base); + mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); + mu_hal_sendmsg(s_mu_base, 1, msg.data[0]); + + ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); + if (!ret) { + ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); + if (!ret) { + if ((msg.data[0] & 0xff) == 0xd6) + return 0; + } + + return -EIO; + } + + return ret; +} + +void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access) +{ + ulong xrdc_base = 0x292f0000, off; + u32 mrgd[5]; + u8 mrcfg, j, region_num; + u8 dsel; + + mrcfg = readb(xrdc_base + 0x140 + mrc_index); + region_num = mrcfg & 0x1f; + + for (j = 0; j < region_num; j++) { + off = 0x2000 + mrc_index * 0x200 + j * 0x20; + + mrgd[0] = readl(xrdc_base + off); + mrgd[1] = readl(xrdc_base + off + 4); + mrgd[2] = readl(xrdc_base + off + 8); + mrgd[3] = readl(xrdc_base + off + 0xc); + mrgd[4] = readl(xrdc_base + off + 0x10); + + debug("MRC [%u][%u]\n", mrc_index, j); + debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", + mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]); + + /* hit */ + if (addr >= mrgd[0] && addr <= mrgd[1]) { + /* find domain 7 DSEL */ + dsel = (mrgd[2] >> 21) & 0x7; + if (dsel == 1) { + mrgd[4] &= ~0xFFF; + mrgd[4] |= (access & 0xFFF); + } else if (dsel == 2) { + mrgd[4] &= ~0xFFF0000; + mrgd[4] |= ((access & 0xFFF) << 16); + } + + /* not handle other cases, since S400 only set ACCESS1 and 2 */ + writel(mrgd[4], xrdc_base + off + 0x10); + return; + } + } +} + +void xrdc_init_mda(void) +{ + ulong xrdc_base = XRDC_ADDR, off; + u32 i = 0; + + /* Set MDA3-5 for PXP, ENET, CAAM to DID 1*/ + for (i = 3; i <= 5; i++) { + off = 0x800 + i * 0x20; + writel(0x200000A1, xrdc_base + off); + writel(0xA00000A1, xrdc_base + off); + } + + /* Set MDA10 -15 to DID 3 for video */ + for (i = 10; i <= 15; i++) { + off = 0x800 + i * 0x20; + writel(0x200000A3, xrdc_base + off); + writel(0xA00000A3, xrdc_base + off); + } +} + +void xrdc_init_mrc(void) +{ + /* The MRC8 is for SRAM1 */ + xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000); + /* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */ + xrdc_config_mrc_dx_perm(8, 0, 0, 1); + xrdc_config_mrc_dx_perm(8, 0, 1, 1); + xrdc_config_mrc_dx_perm(8, 0, 2, 1); + xrdc_config_mrc_dx_perm(8, 0, 3, 1); + xrdc_config_mrc_dx_perm(8, 0, 4, 1); + xrdc_config_mrc_dx_perm(8, 0, 5, 1); + xrdc_config_mrc_dx_perm(8, 0, 6, 1); + xrdc_config_mrc_dx_perm(8, 0, 7, 1); + xrdc_config_mrc_w3_w4(8, 0, 0x0, 0x80000FFF); + + /* The MRC6 is for video modules to ddr */ + xrdc_config_mrc_w0_w1(6, 0, 0x80000000, 0x80000000); + xrdc_config_mrc_dx_perm(6, 0, 3, 1); /* allow for domain 3 video */ + xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF); +} + +int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access) +{ + struct trdc *trdc_base = (struct trdc *)0x28031000U; + struct mbc_mem_dom *mbc_dom; + u32 *cfg_w, *nse_w; + u32 index, offset, val; + + mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = readl((void __iomem *)cfg_w); + + val &= ~(0xFU << offset); + + /* MBC0-3 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MBC0_MEMN_GLBAC0 + */ + if (sec_access) { + val |= (0x0 << offset); + writel(val, (void __iomem *)cfg_w); + } else { + val |= (0x8 << offset); /* nse bit set */ + writel(val, (void __iomem *)cfg_w); + } + + return 0; +} + +int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access) +{ + struct trdc *trdc_base = (struct trdc *)0x28031000U; + struct mrc_rgn_dom *mrc_dom; + u32 *desc_w; + u32 start, end; + u32 i, free = 8; + bool vld, hit = false; + + mrc_dom = &trdc_base->mrc_dom[mrc_x][dom_x]; + + for (i = 0; i < 8; i++) { + desc_w = &mrc_dom->rgn_desc_words[i][0]; + + start = readl((void __iomem *)desc_w) & 0xfff; + end = readl((void __iomem *)(desc_w + 1)); + vld = end & 0x1; + end = end & 0xfff; + + if (start == 0 && end == 0 && !vld && free >= 8) + free = i; + + /* Check all the region descriptors, even overlap */ + if (addr_start >= end || addr_end <= start || !vld) + continue; + + /* MRC0,1 + * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it. + * So select MRCx_MEMN_GLBAC0 + */ + if (sec_access) { + writel(start, (void __iomem *)desc_w); + writel(end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(start, (void __iomem *)desc_w); + writel((end | 0x1 | 0x10), (void __iomem *)(desc_w + 1)); + } + + if (addr_start >= start && addr_end <= end) + hit = true; + } + + if (!hit) { + if (free >= 8) + return -EFAULT; + + desc_w = &mrc_dom->rgn_desc_words[free][0]; + + addr_start &= ~0xfff; + addr_end &= ~0xfff; + + if (sec_access) { + writel(addr_start, (void __iomem *)desc_w); + writel(addr_end | 0x1, (void __iomem *)(desc_w + 1)); + } else { + writel(addr_start, (void __iomem *)desc_w); + writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1)); + } + } + + return 0; +} diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 29f7d5be02..c5e20408c6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -344,180 +345,29 @@ static void set_core0_reset_vector(u32 entry) setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); } -enum rdc_type { - RDC_TRDC, - RDC_XRDC, -}; - -static int release_rdc(enum rdc_type type) -{ - ulong s_mu_base = 0x27020000UL; - struct imx8ulp_s400_msg msg; - int ret; - u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; - msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ - - mu_hal_init(s_mu_base); - mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); - mu_hal_sendmsg(s_mu_base, 1, msg.data[0]); - - ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); - if (!ret) { - ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); - if (!ret) { - if ((msg.data[0] & 0xff) == 0xd6) - return 0; - } - - return -EIO; - } - - return ret; -} - -struct mbc_mem_dom { - u32 mem_glbcfg[4]; - u32 nse_blk_index; - u32 nse_blk_set; - u32 nse_blk_clr; - u32 nsr_blk_clr_all; - u32 memn_glbac[8]; - /* The upper only existed in the beginning of each MBC */ - u32 mem0_blk_cfg_w[64]; - u32 mem0_blk_nse_w[16]; - u32 mem1_blk_cfg_w[8]; - u32 mem1_blk_nse_w[2]; - u32 mem2_blk_cfg_w[8]; - u32 mem2_blk_nse_w[2]; - u32 mem3_blk_cfg_w[8]; - u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ - u32 reserved[2]; -}; - -struct trdc { - u8 res0[0x1000]; - struct mbc_mem_dom mem_dom[4][8]; -}; - -/* MBC[m]_[d]_MEM[s]_BLK_CFG_W[w] */ -int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, u32 perm) -{ - struct trdc *trdc_base = (struct trdc *)0x28031000U; - struct mbc_mem_dom *mbc_dom; - u32 *cfg_w, *nse_w; - u32 index, offset, val; - - mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x]; - - switch (mem_x) { - case 0: - cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; - break; - case 1: - cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; - break; - case 2: - cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; - break; - case 3: - cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; - break; - default: - return -EINVAL; - }; - - index = blk_x % 8; - offset = index * 4; - - val = readl((void __iomem *)cfg_w); - - val &= ~(0xFU << offset); - - if (perm == 0x7700) { - val |= (0x0 << offset); - writel(perm, (void __iomem *)cfg_w); - } else if (perm == 0x0077) { - val |= (0x8 << offset); /* nse bit set */ - writel(val, (void __iomem *)cfg_w); - } else { - return -EINVAL; - } - - return 0; -} - -int trdc_set_access(void) +static int trdc_set_access(void) { /* - * CGC0: PBridge0 slot 47 - * trdc_mbc_set_access(2, 7, 0, 47, 0x7700); - * For secure access, default single boot already support, - * For non-secure access, need add in future per usecase. + * TRDC mgr + 4 MBC + 2 MRC. + * S400 should already configure when release RDC + * A35 only map non-secure region for pbridge0 and 1, set sec_access to false */ - trdc_mbc_set_access(2, 7, 0, 49, 0x7700); - trdc_mbc_set_access(2, 7, 0, 50, 0x7700); - trdc_mbc_set_access(2, 7, 0, 51, 0x7700); - trdc_mbc_set_access(2, 7, 0, 52, 0x7700); + trdc_mbc_set_access(2, 7, 0, 49, false); + trdc_mbc_set_access(2, 7, 0, 50, false); + trdc_mbc_set_access(2, 7, 0, 51, false); + trdc_mbc_set_access(2, 7, 0, 52, false); + trdc_mbc_set_access(2, 7, 0, 53, false); + trdc_mbc_set_access(2, 7, 0, 54, false); - trdc_mbc_set_access(2, 7, 0, 47, 0x0077); + /* CGC0: PBridge0 slot 47 */ + trdc_mbc_set_access(2, 7, 0, 47, false); - /* iomuxc 0 */ - trdc_mbc_set_access(2, 7, 1, 33, 0x7700); + /* Iomuxc0: : PBridge1 slot 33 */ + trdc_mbc_set_access(2, 7, 1, 33, false); return 0; } -static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access) -{ - ulong xrdc_base = 0x292f0000, off; - u32 mrgd[5]; - u8 mrcfg, j, region_num; - u8 dsel; - - mrcfg = readb(xrdc_base + 0x140 + mrc_index); - region_num = mrcfg & 0x1f; - - for (j = 0; j < region_num; j++) { - off = 0x2000 + mrc_index * 0x200 + j * 0x20; - - mrgd[0] = readl(xrdc_base + off); - mrgd[1] = readl(xrdc_base + off + 4); - mrgd[2] = readl(xrdc_base + off + 8); - mrgd[3] = readl(xrdc_base + off + 0xc); - mrgd[4] = readl(xrdc_base + off + 0x10); - - debug("MRC [%u][%u]\n", mrc_index, j); - debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", - mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]); - - /* hit */ - if (addr >= mrgd[0] && addr <= mrgd[1]) { - /* find domain 7 DSEL */ - dsel = (mrgd[2] >> 21) & 0x7; - if (dsel == 1) { - mrgd[4] &= ~0xFFF; - mrgd[4] |= (access & 0xFFF); - } else if (dsel == 2) { - mrgd[4] &= ~0xFFF0000; - mrgd[4] |= ((access & 0xFFF) << 16); - } - - /* not handle other cases, since S400 only set ACCESS1 and 2 */ - writel(mrgd[4], xrdc_base + off + 0x10); - return; - } - } -} - int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { From patchwork Wed Jul 21 14:17:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483305 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6215246jao; Wed, 21 Jul 2021 06:51:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHB+78JkENWoGI1YNZ5iswEeoNCFvD2KwQtsdcFmCIPjKYRA/BSbCFEJLufanUsGsf2FDN X-Received: by 2002:a05:6402:6cf:: with SMTP id n15mr36124303edy.362.1626875498301; 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+ +#define MUX_CTRL_OFS_SHIFT 0 +#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) +#define MUX_SEL_INPUT_OFS_SHIFT 16 +#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << MUX_SEL_INPUT_OFS_SHIFT) + +#define MUX_MODE_SHIFT 32 +#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) +#define MUX_SEL_INPUT_SHIFT 38 +#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_PAD_CTRL_SHIFT 42 +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) + +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) + +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, pad_ctrl) \ + (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ + ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ + ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ + ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ + ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) + +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) + +#define IOMUX_CONFIG_MPORTS 0x20 +#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ MUX_MODE_SHIFT) + +/* Bit definition below needs to be fixed acccording to ulp rm */ + +#define NO_PAD_CTRL BIT(18) +#define PAD_CTL_OBE_ENABLE BIT(17) +#define PAD_CTL_IBE_ENABLE BIT(16) +#define PAD_CTL_DSE BIT(6) +#define PAD_CTL_ODE BIT(5) +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW BIT(2) +#define PAD_CTL_PUE BIT(1) +#define PAD_CTL_PUS_UP (BIT(0) | PAD_CTL_PUE) +#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) + +#define IOMUXC_PCR_MUX_ALT0 (0 << 8) +#define IOMUXC_PCR_MUX_ALT1 (1 << 8) +#define IOMUXC_PCR_MUX_ALT2 (2 << 8) +#define IOMUXC_PCR_MUX_ALT3 (3 << 8) +#define IOMUXC_PCR_MUX_ALT4 (4 << 8) +#define IOMUXC_PCR_MUX_ALT5 (5 << 8) +#define IOMUXC_PCR_MUX_ALT6 (6 << 8) +#define IOMUXC_PCR_MUX_ALT7 (7 << 8) +#define IOMUXC_PCR_MUX_ALT8 (8 << 8) +#define IOMUXC_PCR_MUX_ALT9 (9 << 8) +#define IOMUXC_PCR_MUX_ALT10 (10 << 8) +#define IOMUXC_PCR_MUX_ALT11 (11 << 8) +#define IOMUXC_PCR_MUX_ALT12 (12 << 8) +#define IOMUXC_PCR_MUX_ALT13 (13 << 8) +#define IOMUXC_PCR_MUX_ALT14 (14 << 8) +#define IOMUXC_PCR_MUX_ALT15 (15 << 8) + +#define IOMUXC_PSMI_IMUX_ALT0 (0x0) +#define IOMUXC_PSMI_IMUX_ALT1 (0x1) +#define IOMUXC_PSMI_IMUX_ALT2 (0x2) +#define IOMUXC_PSMI_IMUX_ALT3 (0x3) +#define IOMUXC_PSMI_IMUX_ALT4 (0x4) +#define IOMUXC_PSMI_IMUX_ALT5 (0x5) +#define IOMUXC_PSMI_IMUX_ALT6 (0x6) +#define IOMUXC_PSMI_IMUX_ALT7 (0x7) + +#define IOMUXC_PCR_MUX_ALT_SHIFT (8) +#define IOMUXC_PCR_MUX_ALT_MASK (0xF00) +#define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) + +void imx8ulp_iomux_setup_pad(iomux_cfg_t pad); +void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned int count); +#endif diff --git a/arch/arm/mach-imx/imx8ulp/iomux.c b/arch/arm/mach-imx/imx8ulp/iomux.c index c52ccdeaea..c6d20f5468 100644 --- a/arch/arm/mach-imx/imx8ulp/iomux.c +++ b/arch/arm/mach-imx/imx8ulp/iomux.c @@ -1,4 +1,58 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ + +#include +#include +#include +#include + +static void *base = (void *)IOMUXC_BASE_ADDR; +static void *base_mports = (void *)(0x280A1000); + +/* + * configures a single pad in the iomuxer + */ +void imx8ulp_iomux_setup_pad(iomux_cfg_t pad) +{ + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = mux_ctrl_ofs; + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + if (mux_mode & IOMUX_CONFIG_MPORTS) { + mux_mode &= ~IOMUX_CONFIG_MPORTS; + base = base_mports; + } else { + base = (void *)IOMUXC_BASE_ADDR; + } + + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & + IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs); + + if (sel_input_ofs) + __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), base + sel_input_ofs); + + if (!(pad_ctrl & NO_PAD_CTRL)) + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & + IOMUXC_PCR_MUX_ALT_MASK) | + (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)), + base + pad_ctrl_ofs); +} + +/* configures a list of pads within declared with IOMUX_PADS macro */ +void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count) +{ + iomux_cfg_t const *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + imx8ulp_iomux_setup_pad(*p); + p++; + } +} From patchwork Wed Jul 21 14:17:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483300 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6213744jao; 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Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot. Reviewed-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) -- 2.30.0 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 0728cb9847..9bdbe3c846 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -149,8 +149,6 @@ enum bt_mode get_boot_mode(void) #define CMC_SRS_POR BIT(1) #define CMC_SRS_WUP BIT(0) -static u32 reset_cause = -1; - static char *get_reset_cause(char *ret) { u32 cause1, cause = 0, srs = 0; @@ -163,9 +161,7 @@ static char *get_reset_cause(char *ret) srs = readl(reg_srs); cause1 = readl(reg_ssrs); - reset_cause = cause1; - - cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); + cause = srs & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); switch (cause) { case CMC_SRS_POR: @@ -175,7 +171,7 @@ static char *get_reset_cause(char *ret) sprintf(ret, "%s", "WUP"); break; case CMC_SRS_WARM: - cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | + cause = srs & (CMC_SRS_WDG | CMC_SRS_SW | CMC_SRS_JTAG_RST); switch (cause) { case CMC_SRS_WDG: @@ -193,7 +189,7 @@ static char *get_reset_cause(char *ret) } break; default: - sprintf(ret, "%s-%X", "UNKN", cause1); + sprintf(ret, "%s-%X", "UNKN", srs); break; } From patchwork Wed Jul 21 14:17:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483302 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6214591jao; Wed, 21 Jul 2021 06:50:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyv6IqazaVCXnFvnd+jEG5/QdjYJLRrp5k82gE3ll8FBz58bgPDB4duxKKfAjbcJfCthjTO X-Received: by 2002:aa7:d34a:: with SMTP id m10mr48173619edr.12.1626875442254; Wed, 21 Jul 2021 06:50:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1626875442; cv=pass; d=google.com; s=arc-20160816; b=IvtHKrXJ2ztJo9Txy0csF8BO2Ey/bPPwBzB+Alg/3QGoBY0BrwOt1AEkcm9sg7OLlU 3nshc5KKG99hEL12LeVIjSjAE148vrYB1XnX+oxL1zNpx7l3MKA7MwPmjEIxI8TREsyl lg0C0kqwCFcnroSXvJmTiUxX9XOzGceFHFd4jScqUEIdPqCsfEbkro/1jLL193iw72Vz /r9f5s6BWCQTA9pfH3/IZgRef9ZxgfBVUgX8Z1Uyc9rqcarw9knexaEnwQApru5OmQeL J2CFaA9LsiqUxR6kVCgSBrHxyIy9fO2O8blZzQL4CnTRlVFFROO3vh0B5AJBhgxrK0gc ZGTA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version :content-transfer-encoding:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=eAWRDIxHXGJB1uyXbBztSac5e1FzM0AwnfIG49R+JFM=; b=yrMrcIDq9tqGHxjw0gEcmexzZwRhxDMRNJPgJOygySP17yXQjmQooDYAKRDgXxvcSH zKORzqBCg5vF8k/buNFYPbHDHmOJz5O3QsfwiAIjLHdYy5RrUEH20nVGV5+AGSoFXT4p IfWd2i5YexC22nOqTZfQptf64I1GswqqPqd88JtCv/5BZDw7pzAeAmaoYwzUS1CcQMPQ 0medrWSuLs4EIXX0+zAAftEGwUow/7sJdMHQPlcPzXiC5cBm7spbegkC6VO1plBi3ygp npnzOiICewyEBFPx6B6KYMXlXteXvVTFNz7wcEoTM9oih3HK98/lEmrQ9dpqRdMnwdsB BmZA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=IYOw7Zi3; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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+ u32 par; + u32 cr; + u32 sr; + u32 reserved0[60]; + u32 fcr; + u32 fsr; + u32 reserved1[2]; + u32 gier; + u32 gcr; + u32 gsr; + u32 reserved2; + u32 tcr; + u32 tsr; + u32 rcr; + u32 rsr; + u32 reserved3[52]; + u32 tr[16]; + u32 reserved4[16]; + u32 rr[16]; + u32 reserved5[14]; + u32 mu_attr; +}; + struct usbphy_regs { u32 usbphy_pwd; /* 0x000 */ u32 usbphy_pwd_set; /* 0x004 */ diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/imx8ulp/imx8ulp_mu.c index 913ebe7ad3..333ebdf576 100644 --- a/drivers/misc/imx8ulp/imx8ulp_mu.c +++ b/drivers/misc/imx8ulp/imx8ulp_mu.c @@ -10,29 +10,12 @@ #include #include #include +#include #include #include DECLARE_GLOBAL_DATA_PTR; -struct mu_type { - u32 ver; - u32 par; - u32 cr; - u32 sr; - u32 reserved0[68]; - u32 tcr; - u32 tsr; - u32 rcr; - u32 rsr; - u32 reserved1[52]; - u32 tr[16]; - u32 reserved2[16]; - u32 rr[16]; - u32 reserved4[14]; - u32 mu_attr; -}; - struct imx8ulp_mu { struct mu_type *base; }; From patchwork Wed Jul 21 14:17:22 2021 Content-Type: text/plain; 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Wed, 21 Jul 2021 13:45:01 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 41/44] imx8ulp: add upower api support Date: Wed, 21 Jul 2021 22:17:22 +0800 Message-Id: <20210721141725.23346-42-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:44:59 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abdb2f79-70fb-43c2-0a81-08d94c4dbcf5 X-MS-TrafficTypeDiagnostic: DB6PR0402MB2757: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:612; 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx8ulp/upower.h | 15 + arch/arm/mach-imx/imx8ulp/Makefile | 4 + arch/arm/mach-imx/imx8ulp/upower/Makefile | 6 + arch/arm/mach-imx/imx8ulp/upower/upower_api.c | 486 ++++++++++++++++++ arch/arm/mach-imx/imx8ulp/upower/upower_api.h | 258 ++++++++++ arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 180 +++++++ 6 files changed, 949 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8ulp/upower.h create mode 100644 arch/arm/mach-imx/imx8ulp/upower/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.c create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.h create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx8ulp/upower.h b/arch/arm/include/asm/arch-imx8ulp/upower.h new file mode 100644 index 0000000000..0f1875bbd6 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/upower.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __ASM_ARCH_IMX8ULP_UPOWER_H +#define __ASM_ARCH_IMX8ULP_UPOWER_H + +#include + +int upower_init(void); +int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val); +int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val); + +#endif diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 1ef6cd5c91..2c9938fcdf 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -5,3 +5,7 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y += upower/ +endif diff --git a/arch/arm/mach-imx/imx8ulp/upower/Makefile b/arch/arm/mach-imx/imx8ulp/upower/Makefile new file mode 100644 index 0000000000..f8b5da2ad3 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/upower/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 NXP +# + +obj-y += upower_api.o upower_hal.o diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api.c b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c new file mode 100644 index 0000000000..7e94ed9c77 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c @@ -0,0 +1,486 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include "upower_api.h" + +enum upwr_api_state api_state; +enum soc_domain pwr_domain; +void *sh_buffer[UPWR_SG_COUNT]; +struct upwr_code_vers fw_rom_version; +struct upwr_code_vers fw_ram_version; +u32 fw_launch_option; +u32 sg_busy; +struct mu_type *mu; +upwr_up_max_msg sg_rsp_msg[UPWR_SG_COUNT]; +upwr_callb user_callback[UPWR_SG_COUNT]; +UPWR_RX_CALLB_FUNC_T sgrp_callback[UPWR_SG_COUNT]; +u32 sg_rsp_siz[UPWR_SG_COUNT]; + +#define UPWR_MU_MSG_SIZE (2) +#define UPWR_SG_BUSY(sg) (sg_busy & (1 << (sg))) +#define UPWR_USR_CALLB(sg, cb) \ + do { \ + user_callback[sg] = cb; \ + } while (0) +#define UPWR_MSG_HDR(hdr, sg, fn) \ + (hdr).domain = (u32)pwr_domain; \ + (hdr).srvgrp = sg; \ + (hdr).function = fn + +static u32 upwr_ptr2offset(u64 ptr, enum upwr_sg sg, size_t siz, size_t offset, const void *vptr) +{ + if (ptr >= UPWR_DRAM_SHARED_BASE_ADDR && + ((ptr - UPWR_DRAM_SHARED_BASE_ADDR) < UPWR_DRAM_SHARED_SIZE)) { + return (u32)(ptr - UPWR_DRAM_SHARED_BASE_ADDR); + } + + /* pointer is outside the shared memory, copy the struct to buffer */ + memcpy(offset + (char *)sh_buffer[sg], (void *)vptr, siz); + + return (u32)((u64)sh_buffer[sg] + offset - UPWR_DRAM_SHARED_BASE_ADDR); +} + +enum upwr_req_status upwr_req_status(enum upwr_sg sg, u32 *sgfptr, enum upwr_resp *errptr, + int *retptr) +{ + enum upwr_req_status status; + + status = (sg_rsp_msg[sg].hdr.errcode == UPWR_RESP_OK) ? UPWR_REQ_OK : UPWR_REQ_ERR; + + return status; +} + +void upwr_copy2tr(struct mu_type *mu, const u32 *msg, u32 size) +{ + int i; + + for (i = size - 1; i > -1; i--) + writel(msg[i], &mu->tr[i]); +} + +int upwr_tx(const u32 *msg, u32 size) +{ + if (size > UPWR_MU_MSG_SIZE) + return -2; + if (!size) + return -2; + + if (readl(&mu->tsr) != UPWR_MU_TSR_EMPTY) + return -1; /* not all TE bits in 1: some data to send still */ + + upwr_copy2tr(mu, msg, size); + writel(1 << (size - 1), &mu->tcr); + + return 0; +} + +void upwr_srv_req(enum upwr_sg sg, u32 *msg, u32 size) +{ + sg_busy |= 1 << sg; + + upwr_tx(msg, size); +} + +int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb callb) +{ + upwr_pwm_pwron_msg txmsg; + u64 ptrval; /* needed for X86, ARM64 */ + size_t stsize = 0; + + if (api_state != UPWR_API_READY) + return -3; + if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) + return -1; + + UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb); + + UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_PWR_ON); + + if (!swton) + txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */ + else + txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT, + (stsize = UPWR_PMC_SWT_WORDS * 4), 0, swton); + + if (!memon) + txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */ + else + txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT, UPWR_PMC_MEM_WORDS * 4, + stsize, memon); + + upwr_srv_req(UPWR_SG_PWRMGMT, (u32 *)&txmsg, sizeof(txmsg) / 4); + + return 0; +} + +enum upwr_req_status upwr_poll_req_status(enum upwr_sg sg, u32 *sgfptr, + enum upwr_resp *errptr, int *retptr, + u32 attempts) +{ + u32 i; + enum upwr_req_status ret; + + if (!attempts) { + ret = UPWR_REQ_BUSY; + while (ret == UPWR_REQ_BUSY) + ret = upwr_req_status(sg, sgfptr, errptr, retptr); + return ret; + } + + for (i = 0; i < attempts; i++) { + ret = upwr_req_status(sg, sgfptr, errptr, retptr); + if (ret != UPWR_REQ_BUSY) + break; + } + + return ret; +} + +int upwr_xcp_i2c_access(u16 addr, int8_t data_size, uint8_t subaddr_size, u32 subaddr, + u32 wdata, const upwr_callb callb) +{ + u64 ptrval = (u64)sh_buffer[UPWR_SG_EXCEPT]; + struct upwr_i2c_access *i2c_acc_ptr = (struct upwr_i2c_access *)ptrval; + struct upwr_pointer_msg txmsg; + + if (api_state != UPWR_API_READY) + return -3; + if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) + return -1; + + UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb); + + UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_I2C); + + i2c_acc_ptr->addr = addr; + i2c_acc_ptr->subaddr = subaddr; + i2c_acc_ptr->subaddr_size = subaddr_size; + i2c_acc_ptr->data = wdata; + i2c_acc_ptr->data_size = data_size; + + txmsg.ptr = upwr_ptr2offset(ptrval, + UPWR_SG_EXCEPT, + (size_t)sizeof(struct upwr_i2c_access), + 0, + i2c_acc_ptr); + + upwr_srv_req(UPWR_SG_EXCEPT, (u32 *)&txmsg, sizeof(txmsg) / 4); + + return 0; +} + +int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb) +{ + union upwr_down_1w_msg txmsg; + + if (api_state != UPWR_API_READY) + return -3; + if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) + return -1; + + UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb); + + UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SET_DDR_RETN); + txmsg.hdr.domain = (u32)domain; + txmsg.hdr.arg = (u32)enable; + + upwr_srv_req(UPWR_SG_EXCEPT, (u32 *)&txmsg, sizeof(txmsg) / 4); + + return 0; +} + +int upwr_rx(u32 *msg, u32 *size) +{ + u32 len = readl(&mu->rsr); + + len = (len == 0x0) ? 0 : + (len == 0x1) ? 1 : + #if UPWR_MU_MSG_SIZE > 1 + (len == 0x3) ? 2 : + #if UPWR_MU_MSG_SIZE > 2 + (len == 0x7) ? 3 : + #if UPWR_MU_MSG_SIZE > 3 + (len == 0xF) ? 4 : + #endif + #endif + #endif + 0xFFFFFFFF; /* something wrong */ + + if (len == 0xFFFFFFFF) + return -3; + + *size = len; + if (!len) + return -1; + + /* copy the received message to the rx queue, so the interrupts are cleared; */ + for (u32 i = 0; i < len; i++) + msg[i] = readl(&mu->rr[i]); + + return 0; +} + +void msg_copy(u32 *dest, u32 *src, u32 size) +{ + *dest = *src; + if (size > 1) + *(dest + 1) = *(src + 1); +} + +void upwr_mu_int_callback(void) +{ + enum upwr_sg sg; /* service group number */ + UPWR_RX_CALLB_FUNC_T sg_callb; /* service group callback */ + struct upwr_up_2w_msg rxmsg; + u32 size; /* in words */ + + if (upwr_rx((u32 *)&rxmsg, &size) < 0) { + UPWR_API_ASSERT(0); + return; + } + + sg = (enum upwr_sg)rxmsg.hdr.srvgrp; + + /* copy msg to the service group buffer */ + msg_copy((u32 *)&sg_rsp_msg[sg], (u32 *)&rxmsg, size); + sg_rsp_siz[sg] = size; + sg_busy &= ~(1 << sg); + + sg_callb = sgrp_callback[sg]; + if (!sg_callb) { + upwr_callb user_callb = user_callback[sg]; + + /* no service group callback; call the user callback if any */ + if (!user_callb) + goto done; /* no user callback */ + + /* make the user callback */ + user_callb(sg, rxmsg.hdr.function, (enum upwr_resp)rxmsg.hdr.errcode, + (int)(size == 2) ? rxmsg.word2 : rxmsg.hdr.ret); + goto done; + } + + /* finally make the group callback */ + sg_callb(); + /* don't uninstall the group callback, it's permanent */ +done: + if (rxmsg.hdr.errcode == UPWR_RESP_SHUTDOWN) /* shutdown error: */ + api_state = UPWR_API_INITLZED; +} + +void upwr_txrx_isr(void) +{ + if (readl(&mu->rsr)) + upwr_mu_int_callback(); +} + +void upwr_start_callb(void) +{ + switch (api_state) { + case UPWR_API_START_WAIT: + { + upwr_rdy_callb start_callb = (upwr_rdy_callb)user_callback[UPWR_SG_EXCEPT]; + + union upwr_ready_msg *msg = (union upwr_ready_msg *)&sg_rsp_msg[UPWR_SG_EXCEPT]; + + /* message sanity check */ + UPWR_API_ASSERT(msg->hdr.srvgrp == UPWR_SG_EXCEPT); + UPWR_API_ASSERT(msg->hdr.function == UPWR_XCP_START); + UPWR_API_ASSERT(msg->hdr.errcode == UPWR_RESP_OK); + + fw_ram_version.soc_id = fw_rom_version.soc_id; + fw_ram_version.vmajor = msg->args.vmajor; + fw_ram_version.vminor = msg->args.vminor; + fw_ram_version.vfixes = msg->args.vfixes; + + /* + * vmajor == vminor == vfixes == 0 indicates start error + * in this case, go back to the INITLZED state + */ + + if (fw_ram_version.vmajor || fw_ram_version.vminor || fw_ram_version.vfixes) { + api_state = UPWR_API_READY; + + /* initialization is over: uninstall the callbacks just in case */ + UPWR_USR_CALLB(UPWR_SG_EXCEPT, NULL); + sgrp_callback[UPWR_SG_EXCEPT] = NULL; + + if (!fw_launch_option) { + /* launched ROM firmware: RAM fw versions must be all 0s */ + fw_ram_version.vmajor = + fw_ram_version.vminor = + fw_ram_version.vfixes = 0; + } + } else { + api_state = UPWR_API_INITLZED; + } + + start_callb(msg->args.vmajor, msg->args.vminor, msg->args.vfixes); + } + break; + + default: + UPWR_API_ASSERT(0); + break; + } +} + +int upwr_init(enum soc_domain domain, struct mu_type *muptr) +{ + u32 dom_buffer_base = ((UPWR_API_BUFFER_ENDPLUS + UPWR_API_BUFFER_BASE) / 2); + union upwr_init_msg *msg = (union upwr_init_msg *)&sg_rsp_msg[UPWR_SG_EXCEPT]; + enum upwr_sg sg; /* service group number */ + u32 size; /* in words */ + int j; + + mu = muptr; + writel(0, &mu->tcr); + writel(0, &mu->rcr); + + api_state = UPWR_API_INIT_WAIT; + pwr_domain = domain; + sg_busy = 0; + + /* initialize the versions, in case they are polled */ + fw_rom_version.soc_id = + fw_rom_version.vmajor = + fw_rom_version.vminor = + fw_rom_version.vfixes = 0; + + fw_ram_version.soc_id = + fw_ram_version.vmajor = + fw_ram_version.vminor = + fw_ram_version.vfixes = 0; + + sh_buffer[UPWR_SG_EXCEPT] = (void *)(ulong)dom_buffer_base; + sh_buffer[UPWR_SG_PWRMGMT] = (void *)(ulong)(dom_buffer_base + + sizeof(union upwr_xcp_union)); + sh_buffer[UPWR_SG_DELAYM] = NULL; + sh_buffer[UPWR_SG_VOLTM] = NULL; + sh_buffer[UPWR_SG_CURRM] = NULL; + sh_buffer[UPWR_SG_TEMPM] = NULL; + sh_buffer[UPWR_SG_DIAG] = NULL; + /* (no buffers service groups other than xcp and pwm for now) */ + + for (j = 0; j < UPWR_SG_COUNT; j++) { + user_callback[j] = NULL; + /* service group Exception gets the initialization callbacks */ + sgrp_callback[j] = (j == UPWR_SG_EXCEPT) ? upwr_start_callb : NULL; + + /* response messages with an initial consistent content */ + sg_rsp_msg[j].hdr.errcode = UPWR_RESP_SHUTDOWN; + } + + if (readl(&mu->fsr) & BIT(0)) { + /* send a ping message down to get the ROM version back */ + upwr_xcp_ping_msg ping_msg; + + ping_msg.hdr.domain = pwr_domain; + ping_msg.hdr.srvgrp = UPWR_SG_EXCEPT; + ping_msg.hdr.function = UPWR_XCP_PING; + + if (readl(&mu->rsr) & BIT(0)) /* first clean any Rx message left over */ + upwr_rx((u32 *)msg, &size); + + while (readl(&mu->tsr) != UPWR_MU_TSR_EMPTY) + ; + + /* + * now send the ping message; + * do not use upwr_tx, which needs API initilized; + * just write to the MU TR register(s) + */ + setbits_le32(&mu->fcr, BIT(0)); /* flag urgency status */ + upwr_copy2tr(mu, (u32 *)&ping_msg, sizeof(ping_msg) / 4); + } + + do { + /* poll for the MU Rx status: wait for an init message, either + * 1st sent from uPower after reset or as a response to a ping + */ + while (!readl(&mu->rsr) & BIT(0)) + ; + + clrbits_le32(&mu->fcr, BIT(0)); + + if (upwr_rx((u32 *)msg, &size) < 0) + return -4; + + if (size != (sizeof(union upwr_init_msg) / 4)) { + if (readl(&mu->fsr) & BIT(0)) + continue; /* discard left over msg */ + else + return -4; + } + + sg = (enum upwr_sg)msg->hdr.srvgrp; + if (sg != UPWR_SG_EXCEPT) { + if (readl(&mu->fsr) & BIT(0)) + continue; + else + return -4; + } + + if ((enum upwr_xcp_f)msg->hdr.function != UPWR_XCP_INIT) { + if (readl(&mu->fsr) & BIT(0)) + continue; + else + return -4; + } + + break; + } while (true); + + fw_rom_version.soc_id = msg->args.soc; + fw_rom_version.vmajor = msg->args.vmajor; + fw_rom_version.vminor = msg->args.vminor; + fw_rom_version.vfixes = msg->args.vfixes; + + api_state = UPWR_API_INITLZED; + + return 0; +} /* upwr_init */ + +int upwr_start(u32 launchopt, const upwr_rdy_callb rdycallb) +{ + upwr_start_msg txmsg; + + if (api_state != UPWR_API_INITLZED) + return -3; + + UPWR_USR_CALLB(UPWR_SG_EXCEPT, (upwr_callb)rdycallb); + + UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_START); + + txmsg.hdr.arg = launchopt; + fw_launch_option = launchopt; + + if (upwr_tx((u32 *)&txmsg, sizeof(txmsg) / 4) < 0) { + /* catastrophic error, but is it possible to happen? */ + UPWR_API_ASSERT(0); + return -1; + } + + api_state = UPWR_API_START_WAIT; + + return 0; +} + +u32 upwr_rom_version(u32 *vmajor, u32 *vminor, u32 *vfixes) +{ + u32 soc; + + soc = fw_rom_version.soc_id; + *vmajor = fw_rom_version.vmajor; + *vminor = fw_rom_version.vminor; + *vfixes = fw_rom_version.vfixes; + + return soc; +} + diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api.h b/arch/arm/mach-imx/imx8ulp/upower/upower_api.h new file mode 100644 index 0000000000..5cd7802a3d --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright 2020 NXP + */ + +enum soc_domain { + RTD_DOMAIN = 0, + APD_DOMAIN = 1, + UPWR_MAIN_DOMAINS, /* RTD, AVD */ + AVD_DOMAIN = UPWR_MAIN_DOMAINS, + UPWR_DOMAIN_COUNT, /* RTD, APD, AVD */ + PSD_DOMAIN = UPWR_DOMAIN_COUNT, + UPWR_ALL_DOMAINS /* RTD, APD, AVD, PSD */ +}; + +enum upwr_api_state { + UPWR_API_INIT_WAIT, /* waiting for ROM firmware initialization */ + UPWR_API_INITLZED, /* ROM firmware initialized */ + UPWR_API_START_WAIT, /* waiting for start services */ + UPWR_API_READY /* ready to receive service requests */ +}; + +enum upwr_sg { /* Service Groups in priority order, high to low */ + UPWR_SG_EXCEPT, /* 0 = exception */ + UPWR_SG_PWRMGMT, /* 1 = power management */ + UPWR_SG_DELAYM, /* 2 = delay measurement */ + UPWR_SG_VOLTM, /* 3 = voltage measurement */ + UPWR_SG_CURRM, /* 4 = current measurement */ + UPWR_SG_TEMPM, /* 5 = temperature measurement */ + UPWR_SG_DIAG, /* 6 = diagnostic */ + UPWR_SG_COUNT +}; + +enum upwr_xcp_f { /* Exception Functions */ + /* 0 = init msg (not a service request itself) */ + UPWR_XCP_INIT, + /* 0 = also ping request, since its response is an init msg */ + UPWR_XCP_PING = UPWR_XCP_INIT, + UPWR_XCP_START, /* 1 = service start: upwr_start (not a service request itself) */ + UPWR_XCP_SHUTDOWN, /* 2 = service shutdown: upwr_xcp_shutdown */ + UPWR_XCP_CONFIG, /* 3 = uPower configuration: upwr_xcp_config */ + UPWR_XCP_SW_ALARM, /* 4 = uPower software alarm: upwr_xcp_sw_alarm */ + UPWR_XCP_I2C, /* 5 = I2C access: upwr_xcp_i2c_access */ + UPWR_XCP_SPARE_6, /* 6 = spare */ + UPWR_XCP_SET_DDR_RETN, /* 7 = set/clear ddr retention */ + UPWR_XCP_SPARE_8, /* 8 = spare */ + UPWR_XCP_SPARE_9, /* 9 = spare */ + UPWR_XCP_SPARE_10, /* 10 = spare */ + UPWR_XCP_SPARE_11, /* 11 = spare */ + UPWR_XCP_SPARE_12, /* 12 = spare */ + UPWR_XCP_SPARE_13, /* 13 = spare */ + UPWR_XCP_SPARE_14, /* 14 = spare */ + UPWR_XCP_SPARE_15, /* 15 = spare */ + UPWR_XCP_F_COUNT +}; + +enum upwr_resp { /* response error codes */ + UPWR_RESP_OK = 0, /* no error */ + UPWR_RESP_SG_BUSY, /* service group is busy */ + UPWR_RESP_SHUTDOWN, /* services not up or shutting down */ + UPWR_RESP_BAD_REQ, /* invalid request */ + UPWR_RESP_BAD_STATE, /* system state doesn't allow perform the request */ + UPWR_RESP_UNINSTALLD, /* service or function not installed */ + UPWR_RESP_UNINSTALLED = + UPWR_RESP_UNINSTALLD, /* service or function not installed (alias) */ + UPWR_RESP_RESOURCE, /* resource not available */ + UPWR_RESP_TIMEOUT, /* service timeout */ + UPWR_RESP_COUNT +}; + +#define UPWR_SRVGROUP_BITS (4) +#define UPWR_FUNCTION_BITS (4) +#define UPWR_PWDOMAIN_BITS (4) +#define UPWR_HEADER_BITS (UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS + UPWR_PWDOMAIN_BITS) +#define UPWR_ARG_BITS (32 - UPWR_HEADER_BITS) + +#define UPWR_DUAL_OFFSET_BITS ((UPWR_ARG_BITS + 32) >> 1) + +struct upwr_msg_hdr { + u32 domain :UPWR_PWDOMAIN_BITS; /* power domain */ + u32 srvgrp :UPWR_SRVGROUP_BITS; /* service group */ + u32 function :UPWR_FUNCTION_BITS; /* function */ + u32 arg :UPWR_ARG_BITS; /* function-specific argument */ +}; + +union upwr_down_1w_msg { + struct upwr_msg_hdr hdr; + u32 word; /* message first word */ +}; + +#define upwr_start_msg union upwr_down_1w_msg +#define upwr_xcp_ping_msg union upwr_down_1w_msg + +#define UPWR_RESP_ERR_BITS (4) +#define UPWR_RESP_HDR_BITS (UPWR_RESP_ERR_BITS + \ + UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS) +#define UPWR_RESP_RET_BITS (32 - UPWR_RESP_HDR_BITS) + +struct upwr_resp_hdr { + u32 errcode :UPWR_RESP_ERR_BITS; + u32 srvgrp :UPWR_SRVGROUP_BITS; /* service group */ + u32 function:UPWR_FUNCTION_BITS; + u32 ret :UPWR_RESP_RET_BITS; /* return value, if any */ +}; + +struct upwr_up_2w_msg { + struct upwr_resp_hdr hdr; + u32 word2; /* message second word */ +}; + +#define upwr_up_max_msg struct upwr_up_2w_msg + +union upwr_2pointer_msg { + struct upwr_msg_hdr hdr; + struct { + u64:UPWR_HEADER_BITS; + u64 ptr0:UPWR_DUAL_OFFSET_BITS; + u64 ptr1:UPWR_DUAL_OFFSET_BITS; + } ptrs; +}; + +#define upwr_pwm_pwron_msg union upwr_2pointer_msg + +struct upwr_pointer_msg { + struct upwr_msg_hdr hdr; + u32 ptr; /* config struct offset */ +}; + +struct upwr_i2c_access { /* structure pointed by message upwr_xcp_i2c_msg */ + u16 addr; + s8 data_size; + u8 subaddr_size; + u32 subaddr; + u32 data; +}; + +enum upwr_req_status { + UPWR_REQ_OK, /* request succeeded */ + UPWR_REQ_ERR, /* request failed */ + UPWR_REQ_BUSY /* request execution ongoing */ +}; + +#define UPWR_SOC_BITS (7) +#define UPWR_VMINOR_BITS (4) +#define UPWR_VFIXES_BITS (4) +#define UPWR_VMAJOR_BITS \ + (32 - UPWR_HEADER_BITS - UPWR_SOC_BITS - UPWR_VMINOR_BITS - UPWR_VFIXES_BITS) +union upwr_init_msg { + struct upwr_resp_hdr hdr; + struct { + u32 rsv:UPWR_RESP_HDR_BITS; + u32 soc:UPWR_SOC_BITS; /* SoC identification */ + u32 vmajor:UPWR_VMAJOR_BITS; /* firmware major version */ + u32 vminor:UPWR_VMINOR_BITS; /* firmware minor version */ + u32 vfixes:UPWR_VFIXES_BITS; /* firmware fixes version */ + } args; +}; + +#define UPWR_RAM_VMINOR_BITS (7) +#define UPWR_RAM_VFIXES_BITS (6) +#define UPWR_RAM_VMAJOR_BITS (32 - UPWR_HEADER_BITS - UPWR_RAM_VFIXES_BITS - UPWR_RAM_VMINOR_BITS) + +union upwr_ready_msg { + struct upwr_resp_hdr hdr; + struct { + u32 rsv:UPWR_RESP_HDR_BITS; + u32 vmajor:UPWR_RAM_VMAJOR_BITS; /* RAM fw major version */ + u32 vminor:UPWR_RAM_VMINOR_BITS; /* RAM fw minor version */ + u32 vfixes:UPWR_RAM_VFIXES_BITS; /* RAM fw fixes version */ + } args; +}; + +struct upwr_reg_access_t { + u32 addr; + u32 data; + u32 mask; /* mask=0 commands read */ +}; + +union upwr_xcp_union { + struct upwr_reg_access_t reg_access; +}; + +enum { /* Power Management Functions */ + UPWR_PWM_REGCFG, /* 0 = regulator config: upwr_pwm_reg_config */ + UPWR_PWM_DEVMODE = UPWR_PWM_REGCFG, /* deprecated, for old compile */ + UPWR_PWM_VOLT, /* 1 = voltage change: upwr_pwm_chng_reg_voltage */ + UPWR_PWM_SWITCH, /* 2 = switch control: upwr_pwm_chng_switch_mem */ + UPWR_PWM_PWR_ON, /* 3 = switch/RAM/ROM power on: upwr_pwm_power_on */ + UPWR_PWM_PWR_OFF, /* 4 = switch/RAM/ROM power off: upwr_pwm_power_off */ + UPWR_PWM_RETAIN, /* 5 = retain memory array: upwr_pwm_mem_retain */ + UPWR_PWM_DOM_BIAS, /* 6 = Domain bias control: upwr_pwm_chng_dom_bias */ + UPWR_PWM_MEM_BIAS, /* 7 = Memory bias control: upwr_pwm_chng_mem_bias */ + UPWR_PWM_PMICCFG, /* 8 = PMIC configuration: upwr_pwm_pmic_config */ + UPWR_PWM_PMICMOD = UPWR_PWM_PMICCFG, /* deprecated, for old compile */ + UPWR_PWM_PES, /* 9 = Power Event Sequencer */ + UPWR_PWM_CONFIG, /* 10= apply power mode defined configuration */ + UPWR_PWM_CFGPTR, /* 11= configuration pointer */ + UPWR_PWM_DOM_PWRON, /* 12 = domain power on: upwr_pwm_dom_power_on */ + UPWR_PWM_BOOT, /* 13 = boot start: upwr_pwm_boot_start */ + UPWR_PWM_FREQ, /* 14 = domain frequency setup */ + UPWR_PWM_PARAM, /* 15 = power management parameters */ + UPWR_PWM_F_COUNT +}; + +#ifndef UPWR_PMC_SWT_WORDS +#define UPWR_PMC_SWT_WORDS (1) +#endif + +#ifndef UPWR_PMC_MEM_WORDS +#define UPWR_PMC_MEM_WORDS (2) +#endif + +#define UPWR_API_ASSERT(c) do { } while (0) + +struct upwr_code_vers { + u32 soc_id; + u32 vmajor; + u32 vminor; + u32 vfixes; +}; + +#define UPWR_MU_MSG_SIZE (2) + +#define UPWR_MU_TSR_EMPTY ((u32)((1 << UPWR_MU_MSG_SIZE) - 1)) + +#ifndef UPWR_DRAM_SHARED_BASE_ADDR +#define UPWR_DRAM_SHARED_BASE_ADDR (0x28330000) +#endif + +#ifndef UPWR_DRAM_SHARED_SIZE +#define UPWR_DRAM_SHARED_SIZE (2048) +#endif + +#define UPWR_DRAM_SHARED_ENDPLUS (UPWR_DRAM_SHARED_BASE_ADDR + UPWR_DRAM_SHARED_SIZE) + +#ifndef UPWR_API_BUFFER_BASE +#define UPWR_API_BUFFER_BASE (0x28330600) +#endif + +#ifndef UPWR_API_BUFFER_ENDPLUS +#define UPWR_API_BUFFER_ENDPLUS (UPWR_DRAM_SHARED_ENDPLUS - 64) +#endif + +typedef void (*upwr_rdy_callb)(u32 vmajor, u32 vminor, u32 vfixes); +typedef void (*upwr_callb)(enum upwr_sg sg, u32 func, enum upwr_resp errcode, int ret); +int upwr_init(enum soc_domain domain, struct mu_type *muptr); +int upwr_start(u32 launchopt, const upwr_rdy_callb rdycallb); +u32 upwr_rom_version(u32 *vmajor, u32 *vminor, u32 *vfixes); +typedef void (*UPWR_RX_CALLB_FUNC_T)(void); + +int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb); +int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb callb); +int upwr_xcp_i2c_access(u16 addr, s8 data_size, u8 subaddr_size, u32 subaddr, + u32 wdata, const upwr_callb callb); +enum upwr_req_status upwr_poll_req_status(enum upwr_sg sg, u32 *sgfptr, + enum upwr_resp *errptr, int *retptr, + u32 attempts); +void upwr_txrx_isr(void); diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c new file mode 100644 index 0000000000..b6811d56c9 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include + +#include "upower_api.h" + +#define UPOWER_AP_MU1_ADDR 0x29280000 +static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR; + +void upower_wait_resp(void) +{ + while (!(readl(&muptr->rsr) & BIT(0))) { + debug("%s: poll the mu:%x\n", __func__, readl(&muptr->rsr)); + udelay(100); + } + + upwr_txrx_isr(); +} + +u32 upower_status(int status) +{ + u32 ret = -1; + + switch (status) { + case 0: + debug("%s: finished successfully!\n", __func__); + ret = 0; + break; + case -1: + printf("%s: memory allocation or resource failed!\n", __func__); + break; + case -2: + printf("%s: invalid argument!\n", __func__); + break; + case -3: + printf("%s: called in an invalid API state!\n", __func__); + break; + default: + printf("%s: invalid return status\n", __func__); + break; + } + return ret; +} + +void user_upwr_rdy_callb(u32 soc, u32 vmajor, u32 vminor) +{ + printf("%s: soc=%x\n", __func__, soc); + printf("%s: RAM version:%d.%d\n", __func__, vmajor, vminor); +} + +int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val) +{ + int ret, ret_val; + enum upwr_resp err_code; + + ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL); + if (ret) { + printf("pmic i2c write failed ret %d\n", ret); + return ret; + } + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000); + if (ret != UPWR_REQ_OK) { + printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + return ret; + } + + debug("PMIC write reg[0x%x], val[0x%x]\n", reg_addr, reg_val); + + return 0; +} + +int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val) +{ + int ret, ret_val; + enum upwr_resp err_code; + + if (!reg_val) + return -1; + + ret = upwr_xcp_i2c_access(0x32, -1, 1, reg_addr, 0, NULL); + if (ret) { + printf("pmic i2c read failed ret %d\n", ret); + return ret; + } + + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000); + if (ret != UPWR_REQ_OK) { + printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val); + return ret; + } + + *reg_val = ret_val; + + debug("PMIC read reg[0x%x], val[0x%x]\n", reg_addr, *reg_val); + + return 0; +} + +int upower_init(void) +{ + u32 fw_major, fw_minor, fw_vfixes; + u32 soc_id; + int status; + + u32 swton; + u64 memon; + int ret, ret_val; + + do { + status = upwr_init(1, muptr); + if (upower_status(status)) { + printf("%s: upower init failure\n", __func__); + break; + } + + soc_id = upwr_rom_version(&fw_major, &fw_minor, &fw_vfixes); + if (!soc_id) { + printf("%s:, soc_id not initialized\n", __func__); + break; + } + + printf("%s: soc_id=%d\n", __func__, soc_id); + printf("%s: version:%d.%d.%d\n", __func__, fw_major, fw_minor, fw_vfixes); + + printf("%s: start uPower RAM service\n", __func__); + status = upwr_start(1, user_upwr_rdy_callb); + upower_wait_resp(); + if (upower_status(status)) { + printf("%s: upower init failure\n", __func__); + break; + } + } while (0); + + swton = 0xfff80; + ret = upwr_pwm_power_on(&swton, NULL, NULL); + if (ret) + printf("Turn on switches fail %d\n", ret); + else + printf("Turn on switches ok\n"); + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + if (ret != UPWR_REQ_OK) + printf("Failure %d\n", ret); + + memon = 0x3FFFFFFFFFFFFCUL; + ret = upwr_pwm_power_on(NULL, (const u32 *)&memon, NULL); + if (ret) + printf("Turn on memories fail %d\n", ret); + else + printf("Turn on memories ok\n"); + upower_wait_resp(); + ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000); + if (ret != UPWR_REQ_OK) + printf("Failure %d\n", ret); + + mdelay(1); + + ret = upwr_xcp_set_ddr_retention(APD_DOMAIN, 0, NULL); + if (ret) + printf("Clear DDR retention fail %d\n", ret); + else + printf("Clear DDR retention ok\n"); + + upower_wait_resp(); + + ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000); + if (ret != UPWR_REQ_OK) + printf("Failure %d\n", ret); + + return 0; +} From patchwork Wed Jul 21 14:17:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483306 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6215384jao; 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0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Peng Fan Add i.MX8ULP dtsi Signed-off-by: Peng Fan --- arch/arm/dts/imx8ulp-pinfunc.h | 978 ++++++++++++++++++++++ arch/arm/dts/imx8ulp.dtsi | 728 ++++++++++++++++ include/dt-bindings/clock/imx8ulp-clock.h | 247 ++++++ 3 files changed, 1953 insertions(+) create mode 100644 arch/arm/dts/imx8ulp-pinfunc.h create mode 100644 arch/arm/dts/imx8ulp.dtsi create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h -- 2.30.0 diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h new file mode 100644 index 0000000000..c21c3b644e --- /dev/null +++ b/arch/arm/dts/imx8ulp-pinfunc.h @@ -0,0 +1,978 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __DTS_IMX8ULP_PINFUNC_H +#define __DTS_IMX8ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 +#define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 +#define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD1__PTD1 0x0004 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD1__I2S6_RX_FS 0x0004 0x0B48 0x7 0x1 +#define MX8ULP_PAD_PTD1__SDHC0_CMD 0x0004 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD1__FLEXSPI2_B_DATA7 0x0004 0x0970 0x9 0x1 +#define MX8ULP_PAD_PTD1__EPDC0_SDCLK 0x0004 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD1__DPI0_PCLK 0x0004 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX0_1 0x0004 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD1__DEBUG_MUX1_1 0x0004 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD2__PTD2 0x0008 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD2__I2S6_RXD0 0x0008 0x0B34 0x7 0x1 +#define MX8ULP_PAD_PTD2__SDHC0_CLK 0x0008 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD2__FLEXSPI2_B_DATA6 0x0008 0x096C 0x9 0x1 +#define MX8ULP_PAD_PTD2__EPDC0_SDLE 0x0008 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD2__DPI0_HSYNC 0x0008 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX0_2 0x0008 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD2__DEBUG_MUX1_2 0x0008 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD3__PTD3 0x000C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD3__I2S6_RXD1 0x000C 0x0B38 0x7 0x1 +#define MX8ULP_PAD_PTD3__SDHC0_D7 0x000C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD3__FLEXSPI2_B_DATA5 0x000C 0x0968 0x9 0x1 +#define MX8ULP_PAD_PTD3__EPDC0_GDSP 0x000C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD3__DPI0_VSYNC 0x000C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX0_3 0x000C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD3__DEBUG_MUX1_3 0x000C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD4__PTD4 0x0010 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD4__EXT_AUD_MCLK3 0x0010 0x0B14 0x4 0x1 +#define MX8ULP_PAD_PTD4__SDHC0_VS 0x0010 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD4__TPM8_CH5 0x0010 0x0B2C 0x6 0x1 +#define MX8ULP_PAD_PTD4__I2S6_MCLK 0x0010 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD4__SDHC0_D6 0x0010 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD4__FLEXSPI2_B_DATA4 0x0010 0x0964 0x9 0x1 +#define MX8ULP_PAD_PTD4__EPDC0_SDCE0 0x0010 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD4__DPI0_DE 0x0010 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX0_4 0x0010 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD4__DEBUG_MUX1_4 0x0010 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD5__PTD5 0x0014 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD5__SDHC0_CD 0x0014 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD5__TPM8_CH4 0x0014 0x0B28 0x6 0x1 +#define MX8ULP_PAD_PTD5__I2S6_TX_BCLK 0x0014 0x0B4C 0x7 0x1 +#define MX8ULP_PAD_PTD5__SDHC0_D5 0x0014 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SS0_B 0x0014 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD5__FLEXSPI2_B_SCLK_B 0x0014 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD5__EPDC0_D0 0x0014 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD5__DPI0_D0 0x0014 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX0_5 0x0014 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD5__DEBUG_MUX1_5 0x0014 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD6__PTD6 0x0018 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD6__SDHC0_WP 0x0018 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD6__TPM8_CH3 0x0018 0x0B24 0x6 0x1 +#define MX8ULP_PAD_PTD6__I2S6_TX_FS 0x0018 0x0B50 0x7 0x1 +#define MX8ULP_PAD_PTD6__SDHC0_D4 0x0018 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD6__FLEXSPI2_B_SCLK 0x0018 0x0978 0x9 0x1 +#define MX8ULP_PAD_PTD6__EPDC0_D1 0x0018 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD6__DPI0_D1 0x0018 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX0_6 0x0018 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD6__DEBUG_MUX1_6 0x0018 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD7__PTD7 0x001C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD7__TPM8_CH2 0x001C 0x0B20 0x6 0x1 +#define MX8ULP_PAD_PTD7__I2S6_TXD0 0x001C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD7__SDHC0_D3 0x001C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD7__FLEXSPI2_B_DATA3 0x001C 0x0960 0x9 0x1 +#define MX8ULP_PAD_PTD7__EPDC0_D2 0x001C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD7__DPI0_D2 0x001C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX0_7 0x001C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD7__DEBUG_MUX1_7 0x001C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD8__PTD8 0x0020 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD8__TPM8_CH1 0x0020 0x0B1C 0x6 0x1 +#define MX8ULP_PAD_PTD8__I2S6_TXD1 0x0020 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD8__SDHC0_D2 0x0020 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD8__FLEXSPI2_B_DATA2 0x0020 0x095C 0x9 0x1 +#define MX8ULP_PAD_PTD8__EPDC0_D3 0x0020 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD8__DPI0_D3 0x0020 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD8__LP_APD_DBG_MUX_8 0x0020 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD8__DEBUG_MUX1_8 0x0020 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD9__PTD9 0x0024 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD9__TPM8_CLKIN 0x0024 0x0B30 0x6 0x1 +#define MX8ULP_PAD_PTD9__I2S6_TXD2 0x0024 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD9__SDHC0_D1 0x0024 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD9__FLEXSPI2_B_DATA1 0x0024 0x0958 0x9 0x1 +#define MX8ULP_PAD_PTD9__EPDC0_D4 0x0024 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD9__DPI0_D4 0x0024 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD9__LP_APD_DBG_MUX_9 0x0024 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD9__DEBUG_MUX1_9 0x0024 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD10__PTD10 0x0028 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD10__TPM8_CH0 0x0028 0x0B18 0x6 0x1 +#define MX8ULP_PAD_PTD10__I2S6_TXD3 0x0028 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD10__SDHC0_D0 0x0028 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD10__FLEXSPI2_B_DATA0 0x0028 0x0954 0x9 0x1 +#define MX8ULP_PAD_PTD10__EPDC0_D5 0x0028 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD10__DPI0_D5 0x0028 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD10__LP_APD_DBG_MUX_10 0x0028 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTD10__DEBUG_MUX1_10 0x0028 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD11__PTD11 0x002C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD11__TPM8_CH5 0x002C 0x0B2C 0x6 0x2 +#define MX8ULP_PAD_PTD11__I2S6_RXD2 0x002C 0x0B3C 0x7 0x1 +#define MX8ULP_PAD_PTD11__SDHC0_DQS 0x002C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_B_SS0_B 0x002C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD11__FLEXSPI2_A_SS1_B 0x002C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD11__EPDC0_D6 0x002C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD11__DPI0_D6 0x002C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD11__LP_APD_DBG_MUX_11 0x002C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD12__PTD12 0x0030 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD12__USB0_ID 0x0030 0x0AC8 0x5 0x1 +#define MX8ULP_PAD_PTD12__SDHC2_D3 0x0030 0x0AA4 0x6 0x1 +#define MX8ULP_PAD_PTD12__I2S7_RX_BCLK 0x0030 0x0B64 0x7 0x1 +#define MX8ULP_PAD_PTD12__SDHC1_DQS 0x0030 0x0A84 0x8 0x1 +#define MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x0030 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD12__FLEXSPI2_B_SS1_B 0x0030 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD12__EPDC0_D7 0x0030 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD12__DPI0_D7 0x0030 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD12__LP_APD_DBG_MUX_12 0x0030 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD13__PTD13 0x0034 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD13__SPDIF_IN3 0x0034 0x0B80 0x4 0x1 +#define MX8ULP_PAD_PTD13__USB0_PWR 0x0034 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD13__SDHC2_D2 0x0034 0x0AA0 0x6 0x1 +#define MX8ULP_PAD_PTD13__I2S7_RX_FS 0x0034 0x0B68 0x7 0x1 +#define MX8ULP_PAD_PTD13__SDHC1_RESET_B 0x0034 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x0034 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT2 0x0034 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD13__EPDC0_D8 0x0034 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD13__DPI0_D8 0x0034 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD13__LP_APD_DBG_MUX_13 0x0034 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD14__PTD14 0x0038 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD14__SPDIF_OUT3 0x0038 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD14__USB0_OC 0x0038 0x0AC0 0x5 0x1 +#define MX8ULP_PAD_PTD14__SDHC2_D1 0x0038 0x0A9C 0x6 0x1 +#define MX8ULP_PAD_PTD14__I2S7_RXD0 0x0038 0x0B54 0x7 0x1 +#define MX8ULP_PAD_PTD14__SDHC1_D7 0x0038 0x0A80 0x8 0x1 +#define MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x0038 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD14__TRACE0_D7 0x0038 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD14__EPDC0_D9 0x0038 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD14__DPI0_D9 0x0038 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD14__LP_APD_DBG_MUX_14 0x0038 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD15__PTD15 0x003C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD15__SPDIF_IN2 0x003C 0x0B7C 0x4 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_VS 0x003C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD15__SDHC2_D0 0x003C 0x0A98 0x6 0x1 +#define MX8ULP_PAD_PTD15__I2S7_TX_BCLK 0x003C 0x0B6C 0x7 0x1 +#define MX8ULP_PAD_PTD15__SDHC1_D6 0x003C 0x0A7C 0x8 0x1 +#define MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x003C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD15__TRACE0_D6 0x003C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD15__EPDC0_D10 0x003C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD15__DPI0_D10 0x003C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD15__LP_APD_DBG_MUX_15 0x003C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD16__PTD16 0x0040 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD16__FXIO1_D31 0x0040 0x08A0 0x2 0x1 +#define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 +#define MX8ULP_PAD_PTD16__SPDIF_OUT2 0x0040 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD16__SDHC1_CD 0x0040 0x0A58 0x5 0x1 +#define MX8ULP_PAD_PTD16__SDHC2_CLK 0x0040 0x0A90 0x6 0x1 +#define MX8ULP_PAD_PTD16__I2S7_TX_FS 0x0040 0x0B70 0x7 0x1 +#define MX8ULP_PAD_PTD16__SDHC1_D5 0x0040 0x0A78 0x8 0x1 +#define MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x0040 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD16__TRACE0_D5 0x0040 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD16__EPDC0_D11 0x0040 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD16__DPI0_D11 0x0040 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD16__LP_APD_DBG_MUX_16 0x0040 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD17__PTD17 0x0044 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD17__FXIO1_D30 0x0044 0x089C 0x2 0x1 +#define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 +#define MX8ULP_PAD_PTD17__EXT_AUD_MCLK3 0x0044 0x0B14 0x4 0x2 +#define MX8ULP_PAD_PTD17__SDHC1_WP 0x0044 0x0A88 0x5 0x1 +#define MX8ULP_PAD_PTD17__SDHC2_CMD 0x0044 0x0A94 0x6 0x1 +#define MX8ULP_PAD_PTD17__I2S7_TXD0 0x0044 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD17__SDHC1_D4 0x0044 0x0A74 0x8 0x1 +#define MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x0044 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD17__TRACE0_D4 0x0044 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD17__EPDC0_D12 0x0044 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD17__DPI0_D12 0x0044 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD17__LP_APD_DBG_MUX_17 0x0044 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD18__PTD18 0x0048 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD18__FXIO1_D29 0x0048 0x0894 0x2 0x1 +#define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 +#define MX8ULP_PAD_PTD18__SPDIF_CLK 0x0048 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 +#define MX8ULP_PAD_PTD18__TPM8_CH0 0x0048 0x0B18 0x6 0x2 +#define MX8ULP_PAD_PTD18__I2S7_MCLK 0x0048 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD18__SDHC1_D3 0x0048 0x0A70 0x8 0x1 +#define MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x0048 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD18__TRACE0_D3 0x0048 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD18__EPDC0_D13 0x0048 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD18__DPI0_D13 0x0048 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD18__LP_APD_DBG_MUX_18 0x0048 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD19__PTD19 0x004C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD19__FXIO1_D28 0x004C 0x0890 0x2 0x1 +#define MX8ULP_PAD_PTD19__SPDIF_IN0 0x004C 0x0B74 0x4 0x1 +#define MX8ULP_PAD_PTD19__TPM8_CH1 0x004C 0x0B1C 0x6 0x2 +#define MX8ULP_PAD_PTD19__I2S6_RXD3 0x004C 0x0B40 0x7 0x1 +#define MX8ULP_PAD_PTD19__SDHC1_D2 0x004C 0x0A6C 0x8 0x1 +#define MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x004C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD19__TRACE0_D2 0x004C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD19__EPDC0_D14 0x004C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD19__DPI0_D14 0x004C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD19__LP_APD_DBG_MUX_19 0x004C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD20__PTD20 0x0050 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD20__FXIO1_D27 0x0050 0x088C 0x2 0x1 +#define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 +#define MX8ULP_PAD_PTD20__SPDIF_OUT0 0x0050 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD20__TPM8_CLKIN 0x0050 0x0B30 0x6 0x2 +#define MX8ULP_PAD_PTD20__I2S7_RXD1 0x0050 0x0B58 0x7 0x1 +#define MX8ULP_PAD_PTD20__SDHC1_D1 0x0050 0x0A68 0x8 0x1 +#define MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x0050 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD20__TRACE0_D1 0x0050 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD20__EPDC0_D15 0x0050 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTD20__DPI0_D15 0x0050 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD20__LP_APD_DBG_MUX_20 0x0050 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD21__PTD21 0x0054 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD21__FXIO1_D26 0x0054 0x0888 0x2 0x1 +#define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 +#define MX8ULP_PAD_PTD21__SPDIF_IN1 0x0054 0x0B78 0x4 0x1 +#define MX8ULP_PAD_PTD21__USB1_PWR 0x0054 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTD21__TPM8_CH2 0x0054 0x0B20 0x6 0x2 +#define MX8ULP_PAD_PTD21__I2S7_TXD1 0x0054 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD21__SDHC1_D0 0x0054 0x0A64 0x8 0x1 +#define MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x0054 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD21__TRACE0_D0 0x0054 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD21__DPI0_D16 0x0054 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTD21__LP_APD_DBG_MUX_21 0x0054 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD22__PTD22 0x0058 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD22__FXIO1_D25 0x0058 0x0884 0x2 0x1 +#define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 +#define MX8ULP_PAD_PTD22__SPDIF_OUT1 0x0058 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTD22__USB1_OC 0x0058 0x0AC4 0x5 0x1 +#define MX8ULP_PAD_PTD22__TPM8_CH3 0x0058 0x0B24 0x6 0x2 +#define MX8ULP_PAD_PTD22__I2S7_TXD2 0x0058 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD22__SDHC1_CLK 0x0058 0x0A5C 0x8 0x1 +#define MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x0058 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD22__TRACE0_CLKOUT 0x0058 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD22__DPI0_D17 0x0058 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD22__LP_APD_DBG_MUX_22 0x0058 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTD23__PTD23 0x005C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTD23__FXIO1_D24 0x005C 0x0880 0x2 0x1 +#define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 +#define MX8ULP_PAD_PTD23__USB1_ID 0x005C 0x0ACC 0x5 0x1 +#define MX8ULP_PAD_PTD23__TPM8_CH4 0x005C 0x0B28 0x6 0x2 +#define MX8ULP_PAD_PTD23__I2S7_TXD3 0x005C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTD23__SDHC1_CMD 0x005C 0x0A60 0x8 0x1 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SS0_B 0x005C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTD23__FLEXSPI2_A_SCLK_B 0x005C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTD23__DPI0_D18 0x005C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTD23__LP_APD_DBG_MUX_23 0x005C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE0__PTE0 0x0080 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE0__FXIO1_D23 0x0080 0x087C 0x2 0x1 +#define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 +#define MX8ULP_PAD_PTE0__LPUART4_CTS_B 0x0080 0x08DC 0x4 0x1 +#define MX8ULP_PAD_PTE0__LPI2C4_SCL 0x0080 0x08C8 0x5 0x1 +#define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 +#define MX8ULP_PAD_PTE0__I2S7_RXD2 0x0080 0x0B5C 0x7 0x1 +#define MX8ULP_PAD_PTE0__SDHC2_D1 0x0080 0x0A9C 0x8 0x2 +#define MX8ULP_PAD_PTE0__FLEXSPI2_B_DQS 0x0080 0x0974 0x9 0x2 +#define MX8ULP_PAD_PTE0__ENET0_CRS 0x0080 0x0AE8 0xa 0x1 +#define MX8ULP_PAD_PTE0__DBI0_WRX 0x0080 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE0__DPI0_D19 0x0080 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE0__WUU1_P0 0x0080 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX0_8 0x0080 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE0__DEBUG_MUX1_11 0x0080 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE1__PTE1 0x0084 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE1__FXIO1_D22 0x0084 0x0878 0x2 0x1 +#define MX8ULP_PAD_PTE1__SPDIF_OUT3 0x0084 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE1__LPUART4_RTS_B 0x0084 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE1__LPI2C4_SDA 0x0084 0x08CC 0x5 0x1 +#define MX8ULP_PAD_PTE1__TPM8_CH0 0x0084 0x0B18 0x6 0x3 +#define MX8ULP_PAD_PTE1__I2S7_RXD3 0x0084 0x0B60 0x7 0x1 +#define MX8ULP_PAD_PTE1__SDHC2_D0 0x0084 0x0A98 0x8 0x2 +#define MX8ULP_PAD_PTE1__FLEXSPI2_B_DATA7 0x0084 0x0970 0x9 0x2 +#define MX8ULP_PAD_PTE1__ENET0_COL 0x0084 0x0AE4 0xa 0x1 +#define MX8ULP_PAD_PTE1__DBI0_CSX 0x0084 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE1__DPI0_D20 0x0084 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE1__WUU1_P1 0x0084 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX0_9 0x0084 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE1__DEBUG_MUX1_12 0x0084 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE2__PTE2 0x0088 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE2__FXIO1_D21 0x0088 0x0874 0x2 0x1 +#define MX8ULP_PAD_PTE2__SPDIF_IN2 0x0088 0x0B7C 0x3 0x2 +#define MX8ULP_PAD_PTE2__LPUART4_TX 0x0088 0x08E4 0x4 0x1 +#define MX8ULP_PAD_PTE2__LPI2C4_HREQ 0x0088 0x08C4 0x5 0x1 +#define MX8ULP_PAD_PTE2__TPM8_CH1 0x0088 0x0B1C 0x6 0x3 +#define MX8ULP_PAD_PTE2__EXT_AUD_MCLK3 0x0088 0x0B14 0x7 0x4 +#define MX8ULP_PAD_PTE2__SDHC2_CLK 0x0088 0x0A90 0x8 0x2 +#define MX8ULP_PAD_PTE2__FLEXSPI2_B_DATA6 0x0088 0x096C 0x9 0x2 +#define MX8ULP_PAD_PTE2__ENET0_TXER 0x0088 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE2__DBI0_DCX 0x0088 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE2__DPI0_D21 0x0088 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE2__LP_HV_DBG_MUX_0 0x0088 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX0_10 0x0088 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE2__DEBUG_MUX1_13 0x0088 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE3__PTE3 0x008C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE3__FXIO1_D20 0x008C 0x0870 0x2 0x1 +#define MX8ULP_PAD_PTE3__SPDIF_OUT2 0x008C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE3__LPUART4_RX 0x008C 0x08E0 0x4 0x1 +#define MX8ULP_PAD_PTE3__TPM8_CH2 0x008C 0x0B20 0x6 0x3 +#define MX8ULP_PAD_PTE3__I2S6_MCLK 0x008C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE3__SDHC2_CMD 0x008C 0x0A94 0x8 0x2 +#define MX8ULP_PAD_PTE3__FLEXSPI2_B_DATA5 0x008C 0x0968 0x9 0x2 +#define MX8ULP_PAD_PTE3__ENET0_TXCLK 0x008C 0x0B10 0xa 0x1 +#define MX8ULP_PAD_PTE3__DBI0_RWX 0x008C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE3__DPI0_D22 0x008C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE3__WUU1_P2 0x008C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX0_11 0x008C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE3__DEBUG_MUX1_14 0x008C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE4__PTE4 0x0090 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE4__FXIO1_D19 0x0090 0x0868 0x2 0x1 +#define MX8ULP_PAD_PTE4__SPDIF_CLK 0x0090 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE4__LPUART5_CTS_B 0x0090 0x08E8 0x4 0x1 +#define MX8ULP_PAD_PTE4__LPI2C5_SCL 0x0090 0x08D4 0x5 0x1 +#define MX8ULP_PAD_PTE4__TPM8_CH3 0x0090 0x0B24 0x6 0x3 +#define MX8ULP_PAD_PTE4__I2S6_RX_BCLK 0x0090 0x0B44 0x7 0x2 +#define MX8ULP_PAD_PTE4__SDHC2_D3 0x0090 0x0AA4 0x8 0x2 +#define MX8ULP_PAD_PTE4__FLEXSPI2_B_DATA4 0x0090 0x0964 0x9 0x2 +#define MX8ULP_PAD_PTE4__ENET0_TXD3 0x0090 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE4__DBI0_E 0x0090 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE4__DPI0_D23 0x0090 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE4__WUU1_P3 0x0090 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX0_12 0x0090 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE4__DEBUG_MUX1_15 0x0090 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE5__PTE5 0x0094 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE5__FXIO1_D18 0x0094 0x0864 0x2 0x1 +#define MX8ULP_PAD_PTE5__SPDIF_IN0 0x0094 0x0B74 0x3 0x2 +#define MX8ULP_PAD_PTE5__LPUART5_RTS_B 0x0094 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE5__LPI2C5_SDA 0x0094 0x08D8 0x5 0x1 +#define MX8ULP_PAD_PTE5__TPM8_CH4 0x0094 0x0B28 0x6 0x3 +#define MX8ULP_PAD_PTE5__I2S6_RX_FS 0x0094 0x0B48 0x7 0x2 +#define MX8ULP_PAD_PTE5__SDHC2_D2 0x0094 0x0AA0 0x8 0x2 +#define MX8ULP_PAD_PTE5__FLEXSPI2_B_SS0_B 0x0094 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE5__ENET0_TXD2 0x0094 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE5__DBI0_D0 0x0094 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE5__LP_HV_DBG_MUX_1 0x0094 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX0_13 0x0094 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE5__DEBUG_MUX1_16 0x0094 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE6__PTE6 0x0098 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE6__FXIO1_D17 0x0098 0x0860 0x2 0x1 +#define MX8ULP_PAD_PTE6__SPDIF_OUT0 0x0098 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE6__LPUART5_TX 0x0098 0x08F0 0x4 0x1 +#define MX8ULP_PAD_PTE6__LPI2C5_HREQ 0x0098 0x08D0 0x5 0x1 +#define MX8ULP_PAD_PTE6__TPM8_CH5 0x0098 0x0B2C 0x6 0x3 +#define MX8ULP_PAD_PTE6__I2S6_RXD0 0x0098 0x0B34 0x7 0x2 +#define MX8ULP_PAD_PTE6__SDHC2_D4 0x0098 0x0AA8 0x8 0x1 +#define MX8ULP_PAD_PTE6__FLEXSPI2_B_SCLK 0x0098 0x0978 0x9 0x2 +#define MX8ULP_PAD_PTE6__ENET0_RXCLK 0x0098 0x0B0C 0xa 0x1 +#define MX8ULP_PAD_PTE6__DBI0_D1 0x0098 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE6__LP_HV_DBG_MUX_2 0x0098 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE6__WDOG5_RST 0x0098 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX0_14 0x0098 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE6__DEBUG_MUX1_17 0x0098 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE7__PTE7 0x009C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE7__FXIO1_D16 0x009C 0x085C 0x2 0x1 +#define MX8ULP_PAD_PTE7__SPDIF_IN1 0x009C 0x0B78 0x3 0x2 +#define MX8ULP_PAD_PTE7__LPUART5_RX 0x009C 0x08EC 0x4 0x1 +#define MX8ULP_PAD_PTE7__LPI2C6_HREQ 0x009C 0x09B4 0x5 0x1 +#define MX8ULP_PAD_PTE7__TPM4_CLKIN 0x009C 0x081C 0x6 0x1 +#define MX8ULP_PAD_PTE7__I2S6_RXD1 0x009C 0x0B38 0x7 0x2 +#define MX8ULP_PAD_PTE7__SDHC2_D5 0x009C 0x0AAC 0x8 0x1 +#define MX8ULP_PAD_PTE7__FLEXSPI2_B_DATA3 0x009C 0x0960 0x9 0x2 +#define MX8ULP_PAD_PTE7__ENET0_RXD3 0x009C 0x0B04 0xa 0x1 +#define MX8ULP_PAD_PTE7__DBI0_D2 0x009C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE7__EPDC0_BDR1 0x009C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE7__WUU1_P4 0x009C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX0_15 0x009C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE7__DEBUG_MUX1_18 0x009C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE8__PTE8 0x00A0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE8__FXIO1_D15 0x00A0 0x0858 0x2 0x1 +#define MX8ULP_PAD_PTE8__LPSPI4_PCS1 0x00A0 0x08F8 0x3 0x2 +#define MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x00A0 0x09CC 0x4 0x1 +#define MX8ULP_PAD_PTE8__LPI2C6_SCL 0x00A0 0x09B8 0x5 0x1 +#define MX8ULP_PAD_PTE8__TPM4_CH0 0x00A0 0x0804 0x6 0x1 +#define MX8ULP_PAD_PTE8__I2S6_RXD2 0x00A0 0x0B3C 0x7 0x2 +#define MX8ULP_PAD_PTE8__SDHC2_D6 0x00A0 0x0AB0 0x8 0x1 +#define MX8ULP_PAD_PTE8__FLEXSPI2_B_DATA2 0x00A0 0x095C 0x9 0x2 +#define MX8ULP_PAD_PTE8__ENET0_RXD2 0x00A0 0x0B00 0xa 0x1 +#define MX8ULP_PAD_PTE8__DBI0_D3 0x00A0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE8__EPDC0_BDR0 0x00A0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE8__LP_HV_DBG_MUX_3 0x00A0 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE8__DEBUG_MUX1_19 0x00A0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE9__PTE9 0x00A4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE9__FXIO1_D14 0x00A4 0x0854 0x2 0x1 +#define MX8ULP_PAD_PTE9__LPSPI4_PCS2 0x00A4 0x08FC 0x3 0x2 +#define MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x00A4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE9__LPI2C6_SDA 0x00A4 0x09BC 0x5 0x1 +#define MX8ULP_PAD_PTE9__TPM4_CH1 0x00A4 0x0808 0x6 0x1 +#define MX8ULP_PAD_PTE9__I2S6_RXD3 0x00A4 0x0B40 0x7 0x2 +#define MX8ULP_PAD_PTE9__SDHC2_D7 0x00A4 0x0AB4 0x8 0x1 +#define MX8ULP_PAD_PTE9__FLEXSPI2_B_DATA1 0x00A4 0x0958 0x9 0x2 +#define MX8ULP_PAD_PTE9__ENET0_1588_TMR3 0x00A4 0x0AE0 0xa 0x1 +#define MX8ULP_PAD_PTE9__DBI0_D4 0x00A4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE9__EPDC0_VCOM1 0x00A4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE9__LP_HV_DBG_MUX_4 0x00A4 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE9__DEBUG_MUX1_20 0x00A4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE10__PTE10 0x00A8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE10__FXIO1_D13 0x00A8 0x0850 0x2 0x1 +#define MX8ULP_PAD_PTE10__LPSPI4_PCS3 0x00A8 0x0900 0x3 0x2 +#define MX8ULP_PAD_PTE10__LPUART6_TX 0x00A8 0x09D4 0x4 0x1 +#define MX8ULP_PAD_PTE10__I3C2_SCL 0x00A8 0x08BC 0x5 0x1 +#define MX8ULP_PAD_PTE10__TPM4_CH2 0x00A8 0x080C 0x6 0x1 +#define MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x00A8 0x0B4C 0x7 0x2 +#define MX8ULP_PAD_PTE10__SDHC2_DQS 0x00A8 0x0AB8 0x8 0x1 +#define MX8ULP_PAD_PTE10__FLEXSPI2_B_DATA0 0x00A8 0x0954 0x9 0x2 +#define MX8ULP_PAD_PTE10__ENET0_1588_TMR2 0x00A8 0x0ADC 0xa 0x1 +#define MX8ULP_PAD_PTE10__DBI0_D5 0x00A8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE10__EPDC0_VCOM0 0x00A8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE10__LP_HV_DBG_MUX_5 0x00A8 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTE10__DEBUG_MUX1_21 0x00A8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE11__PTE11 0x00AC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE11__FXIO1_D12 0x00AC 0x084C 0x2 0x1 +#define MX8ULP_PAD_PTE11__SPDIF_OUT1 0x00AC 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTE11__LPUART6_RX 0x00AC 0x09D0 0x4 0x1 +#define MX8ULP_PAD_PTE11__I3C2_SDA 0x00AC 0x08C0 0x5 0x1 +#define MX8ULP_PAD_PTE11__TPM4_CH3 0x00AC 0x0810 0x6 0x1 +#define MX8ULP_PAD_PTE11__I2S6_TX_FS 0x00AC 0x0B50 0x7 0x2 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SCLK_B 0x00AC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE11__FLEXSPI2_B_SS0_B 0x00AC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE11__ENET0_1588_TMR1 0x00AC 0x0AD8 0xa 0x1 +#define MX8ULP_PAD_PTE11__DBI0_D6 0x00AC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE11__EPDC0_PWRCTRL0 0x00AC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE11__LP_HV_DBG_MUX_6 0x00AC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE12__PTE12 0x00B0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE12__FXIO1_D11 0x00B0 0x0848 0x2 0x1 +#define MX8ULP_PAD_PTE12__LPSPI4_SIN 0x00B0 0x0908 0x3 0x2 +#define MX8ULP_PAD_PTE12__LPUART7_CTS_B 0x00B0 0x09D8 0x4 0x1 +#define MX8ULP_PAD_PTE12__LPI2C7_SCL 0x00B0 0x09C4 0x5 0x1 +#define MX8ULP_PAD_PTE12__TPM4_CH4 0x00B0 0x0814 0x6 0x1 +#define MX8ULP_PAD_PTE12__I2S6_TXD0 0x00B0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE12__SDHC2_RESET_B 0x00B0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE12__FLEXSPI2_B_SS1_B 0x00B0 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE12__ENET0_1588_TMR0 0x00B0 0x0AD4 0xa 0x1 +#define MX8ULP_PAD_PTE12__DBI0_D7 0x00B0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE12__EPDC0_PWRCTRL1 0x00B0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE12__WUU1_P5 0x00B0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE13__PTE13 0x00B4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE13__FXIO1_D10 0x00B4 0x0844 0x2 0x1 +#define MX8ULP_PAD_PTE13__LPSPI4_SOUT 0x00B4 0x090C 0x3 0x2 +#define MX8ULP_PAD_PTE13__LPUART7_RTS_B 0x00B4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE13__LPI2C7_SDA 0x00B4 0x09C8 0x5 0x1 +#define MX8ULP_PAD_PTE13__TPM4_CH5 0x00B4 0x0818 0x6 0x1 +#define MX8ULP_PAD_PTE13__I2S6_TXD1 0x00B4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE13__SDHC1_WP 0x00B4 0x0A88 0x8 0x2 +#define MX8ULP_PAD_PTE13__ENET0_1588_CLKIN 0x00B4 0x0AD0 0xa 0x1 +#define MX8ULP_PAD_PTE13__DBI0_D8 0x00B4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE13__EPDC0_PWRCTRL2 0x00B4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE13__LP_HV_DBG_MUX_7 0x00B4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE14__PTE14 0x00B8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE14__FXIO1_D9 0x00B8 0x08B8 0x2 0x1 +#define MX8ULP_PAD_PTE14__LPSPI4_SCK 0x00B8 0x0904 0x3 0x2 +#define MX8ULP_PAD_PTE14__LPUART7_TX 0x00B8 0x09E0 0x4 0x1 +#define MX8ULP_PAD_PTE14__LPI2C7_HREQ 0x00B8 0x09C0 0x5 0x1 +#define MX8ULP_PAD_PTE14__TPM5_CLKIN 0x00B8 0x0838 0x6 0x1 +#define MX8ULP_PAD_PTE14__I2S6_TXD2 0x00B8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE14__SDHC1_CD 0x00B8 0x0A58 0x8 0x2 +#define MX8ULP_PAD_PTE14__ENET0_MDIO 0x00B8 0x0AF0 0xa 0x1 +#define MX8ULP_PAD_PTE14__DBI0_D9 0x00B8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE14__EPDC0_PWRCTRL3 0x00B8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE14__LP_HV_DBG_MUX_8 0x00B8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE15__PTE15 0x00BC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE15__FXIO1_D8 0x00BC 0x08B4 0x2 0x1 +#define MX8ULP_PAD_PTE15__LPSPI4_PCS0 0x00BC 0x08F4 0x3 0x2 +#define MX8ULP_PAD_PTE15__LPUART7_RX 0x00BC 0x09DC 0x4 0x1 +#define MX8ULP_PAD_PTE15__I3C2_PUR 0x00BC 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTE15__TPM5_CH0 0x00BC 0x0820 0x6 0x1 +#define MX8ULP_PAD_PTE15__I2S6_TXD3 0x00BC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE15__MQS1_LEFT 0x00BC 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE15__ENET0_MDC 0x00BC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE15__DBI0_D10 0x00BC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE15__EPDC0_PWRCOM 0x00BC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE15__WUU1_P6 0x00BC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__PTE16 0x00C0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE16__FXIO1_D7 0x00C0 0x08B0 0x2 0x1 +#define MX8ULP_PAD_PTE16__LPSPI5_PCS1 0x00C0 0x0914 0x3 0x1 +#define MX8ULP_PAD_PTE16__LPUART4_CTS_B 0x00C0 0x08DC 0x4 0x2 +#define MX8ULP_PAD_PTE16__LPI2C4_SCL 0x00C0 0x08C8 0x5 0x2 +#define MX8ULP_PAD_PTE16__TPM5_CH1 0x00C0 0x0824 0x6 0x1 +#define MX8ULP_PAD_PTE16__MQS1_LEFT 0x00C0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE16__MQS1_RIGHT 0x00C0 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE16__USB0_ID 0x00C0 0x0AC8 0x9 0x2 +#define MX8ULP_PAD_PTE16__ENET0_TXEN 0x00C0 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE16__DBI0_D11 0x00C0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE16__EPDC0_PWRIRQ 0x00C0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE16__WDOG3_RST 0x00C0 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE16__LP_HV_DBG_MUX_9 0x00C0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE17__PTE17 0x00C4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE17__FXIO1_D6 0x00C4 0x08AC 0x2 0x1 +#define MX8ULP_PAD_PTE17__LPSPI5_PCS2 0x00C4 0x0918 0x3 0x1 +#define MX8ULP_PAD_PTE17__LPUART4_RTS_B 0x00C4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE17__LPI2C4_SDA 0x00C4 0x08CC 0x5 0x2 +#define MX8ULP_PAD_PTE17__MQS1_RIGHT 0x00C4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE17__SDHC1_VS 0x00C4 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTE17__USB0_PWR 0x00C4 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE17__ENET0_RXER 0x00C4 0x0B08 0xa 0x1 +#define MX8ULP_PAD_PTE17__DBI0_D12 0x00C4 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE17__EPDC0_PWRSTAT 0x00C4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE17__LP_HV_DBG_MUX_10 0x00C4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE18__PTE18 0x00C8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE18__FXIO1_D5 0x00C8 0x08A8 0x2 0x1 +#define MX8ULP_PAD_PTE18__LPSPI5_PCS3 0x00C8 0x091C 0x3 0x1 +#define MX8ULP_PAD_PTE18__LPUART4_TX 0x00C8 0x08E4 0x4 0x2 +#define MX8ULP_PAD_PTE18__LPI2C4_HREQ 0x00C8 0x08C4 0x5 0x2 +#define MX8ULP_PAD_PTE18__I2S7_TX_BCLK 0x00C8 0x0B6C 0x7 0x2 +#define MX8ULP_PAD_PTE18__USB0_OC 0x00C8 0x0AC0 0x9 0x2 +#define MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x00C8 0x0AEC 0xa 0x1 +#define MX8ULP_PAD_PTE18__DBI0_D13 0x00C8 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE18__EPDC0_PWRWAKE 0x00C8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE18__LP_HV_DBG_MUX_11 0x00C8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE19__PTE19 0x00CC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE19__FXIO1_D4 0x00CC 0x08A4 0x2 0x1 +#define MX8ULP_PAD_PTE19__LPUART4_RX 0x00CC 0x08E0 0x4 0x2 +#define MX8ULP_PAD_PTE19__LPI2C5_HREQ 0x00CC 0x08D0 0x5 0x2 +#define MX8ULP_PAD_PTE19__I3C2_PUR 0x00CC 0x0000 0x6 0x0 +#define MX8ULP_PAD_PTE19__I2S7_TX_FS 0x00CC 0x0B70 0x7 0x2 +#define MX8ULP_PAD_PTE19__USB1_PWR 0x00CC 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTE19__ENET0_REFCLK 0x00CC 0x0AF4 0xa 0x1 +#define MX8ULP_PAD_PTE19__DBI0_D14 0x00CC 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE19__EPDC0_GDCLK 0x00CC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE19__WUU1_P7 0x00CC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE20__PTE20 0x00D0 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE20__FXIO1_D3 0x00D0 0x0898 0x2 0x1 +#define MX8ULP_PAD_PTE20__LPSPI5_SIN 0x00D0 0x0924 0x3 0x1 +#define MX8ULP_PAD_PTE20__LPUART5_CTS_B 0x00D0 0x08E8 0x4 0x2 +#define MX8ULP_PAD_PTE20__LPI2C5_SCL 0x00D0 0x08D4 0x5 0x2 +#define MX8ULP_PAD_PTE20__I2S7_TXD0 0x00D0 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE20__USB1_OC 0x00D0 0x0AC4 0x9 0x2 +#define MX8ULP_PAD_PTE20__ENET0_RXD1 0x00D0 0x0AFC 0xa 0x1 +#define MX8ULP_PAD_PTE20__DBI0_D15 0x00D0 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTE20__EPDC0_GDOE 0x00D0 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE20__LP_HV_DBG_MUX_12 0x00D0 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE21__PTE21 0x00D4 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE21__FXIO1_D2 0x00D4 0x086C 0x2 0x1 +#define MX8ULP_PAD_PTE21__LPSPI5_SOUT 0x00D4 0x0928 0x3 0x1 +#define MX8ULP_PAD_PTE21__LPUART5_RTS_B 0x00D4 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTE21__LPI2C5_SDA 0x00D4 0x08D8 0x5 0x2 +#define MX8ULP_PAD_PTE21__TPM6_CLKIN 0x00D4 0x0994 0x6 0x1 +#define MX8ULP_PAD_PTE21__I2S7_TXD1 0x00D4 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE21__USB1_ID 0x00D4 0x0ACC 0x9 0x2 +#define MX8ULP_PAD_PTE21__ENET0_RXD0 0x00D4 0x0AF8 0xa 0x1 +#define MX8ULP_PAD_PTE21__EPDC0_GDRL 0x00D4 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE21__WDOG4_RST 0x00D4 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE21__LP_HV_DBG_MUX_13 0x00D4 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE22__PTE22 0x00D8 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE22__FXIO1_D1 0x00D8 0x0840 0x2 0x1 +#define MX8ULP_PAD_PTE22__LPSPI5_SCK 0x00D8 0x0920 0x3 0x1 +#define MX8ULP_PAD_PTE22__LPUART5_TX 0x00D8 0x08F0 0x4 0x2 +#define MX8ULP_PAD_PTE22__I3C2_SCL 0x00D8 0x08BC 0x5 0x2 +#define MX8ULP_PAD_PTE22__TPM6_CH0 0x00D8 0x097C 0x6 0x1 +#define MX8ULP_PAD_PTE22__I2S7_TXD2 0x00D8 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE22__EXT_AUD_MCLK3 0x00D8 0x0B14 0x9 0x5 +#define MX8ULP_PAD_PTE22__ENET0_TXD1 0x00D8 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE22__EPDC0_SDOED 0x00D8 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE22__CLKOUT2 0x00D8 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE22__LP_HV_DBG_MUX_14 0x00D8 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTE23__PTE23 0x00DC 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTE23__FXIO1_D0 0x00DC 0x083C 0x2 0x1 +#define MX8ULP_PAD_PTE23__LPSPI5_PCS0 0x00DC 0x0910 0x3 0x1 +#define MX8ULP_PAD_PTE23__LPUART5_RX 0x00DC 0x08EC 0x4 0x2 +#define MX8ULP_PAD_PTE23__I3C2_SDA 0x00DC 0x08C0 0x5 0x2 +#define MX8ULP_PAD_PTE23__TPM6_CH1 0x00DC 0x0980 0x6 0x1 +#define MX8ULP_PAD_PTE23__I2S7_TXD3 0x00DC 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTE23__EXT_AUD_MCLK2 0x00DC 0x0800 0x9 0x1 +#define MX8ULP_PAD_PTE23__ENET0_TXD0 0x00DC 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTE23__EPDC0_SDOEZ 0x00DC 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTE23__CLKOUT1 0x00DC 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTE23__LP_HV_DBG_MUX_15 0x00DC 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF0__PTF0 0x0100 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF0__FXIO1_D0 0x0100 0x083C 0x2 0x2 +#define MX8ULP_PAD_PTF0__LPUART6_CTS_B 0x0100 0x09CC 0x4 0x2 +#define MX8ULP_PAD_PTF0__LPI2C6_SCL 0x0100 0x09B8 0x5 0x2 +#define MX8ULP_PAD_PTF0__I2S7_RX_BCLK 0x0100 0x0B64 0x7 0x2 +#define MX8ULP_PAD_PTF0__SDHC1_D1 0x0100 0x0A68 0x8 0x2 +#define MX8ULP_PAD_PTF0__ENET0_RXD1 0x0100 0x0AFC 0x9 0x2 +#define MX8ULP_PAD_PTF0__USB1_ID 0x0100 0x0ACC 0xa 0x3 +#define MX8ULP_PAD_PTF0__EPDC0_SDOE 0x0100 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF0__DPI0_D23 0x0100 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF0__WUU1_P8 0x0100 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__PTF1 0x0104 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF1__FXIO1_D1 0x0104 0x0840 0x2 0x2 +#define MX8ULP_PAD_PTF1__LPUART6_RTS_B 0x0104 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF1__LPI2C6_SDA 0x0104 0x09BC 0x5 0x2 +#define MX8ULP_PAD_PTF1__I2S7_RX_FS 0x0104 0x0B68 0x7 0x2 +#define MX8ULP_PAD_PTF1__SDHC1_D0 0x0104 0x0A64 0x8 0x2 +#define MX8ULP_PAD_PTF1__ENET0_RXD0 0x0104 0x0AF8 0x9 0x2 +#define MX8ULP_PAD_PTF1__LP_HV_DBG_MUX_16 0x0104 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF1__EPDC0_SDSHR 0x0104 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF1__DPI0_D22 0x0104 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF1__WDOG3_RST 0x0104 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX0_16 0x0104 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF1__DEBUG_MUX1_22 0x0104 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF2__PTF2 0x0108 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF2__FXIO1_D2 0x0108 0x086C 0x2 0x2 +#define MX8ULP_PAD_PTF2__LPUART6_TX 0x0108 0x09D4 0x4 0x2 +#define MX8ULP_PAD_PTF2__LPI2C6_HREQ 0x0108 0x09B4 0x5 0x2 +#define MX8ULP_PAD_PTF2__I2S7_RXD0 0x0108 0x0B54 0x7 0x2 +#define MX8ULP_PAD_PTF2__SDHC1_CLK 0x0108 0x0A5C 0x8 0x2 +#define MX8ULP_PAD_PTF2__ENET0_TXD1 0x0108 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF2__USB0_ID 0x0108 0x0AC8 0xa 0x3 +#define MX8ULP_PAD_PTF2__EPDC0_SDCE9 0x0108 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF2__DPI0_D21 0x0108 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF2__LP_HV_DBG_MUX_17 0x0108 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX0_17 0x0108 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF2__DEBUG_MUX1_23 0x0108 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF3__PTF3 0x010C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF3__FXIO1_D3 0x010C 0x0898 0x2 0x2 +#define MX8ULP_PAD_PTF3__LPUART6_RX 0x010C 0x09D0 0x4 0x2 +#define MX8ULP_PAD_PTF3__LPI2C7_HREQ 0x010C 0x09C0 0x5 0x2 +#define MX8ULP_PAD_PTF3__I2S7_RXD1 0x010C 0x0B58 0x7 0x2 +#define MX8ULP_PAD_PTF3__SDHC1_CMD 0x010C 0x0A60 0x8 0x2 +#define MX8ULP_PAD_PTF3__ENET0_TXD0 0x010C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF3__USB0_PWR 0x010C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF3__EPDC0_SDCE8 0x010C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF3__DPI0_D20 0x010C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF3__WUU1_P9 0x010C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF3__DEBUG_MUX1_24 0x010C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF4__PTF4 0x0110 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF4__FXIO1_D4 0x0110 0x08A4 0x2 0x2 +#define MX8ULP_PAD_PTF4__LPSPI4_PCS1 0x0110 0x08F8 0x3 0x3 +#define MX8ULP_PAD_PTF4__LPUART7_CTS_B 0x0110 0x09D8 0x4 0x2 +#define MX8ULP_PAD_PTF4__LPI2C7_SCL 0x0110 0x09C4 0x5 0x2 +#define MX8ULP_PAD_PTF4__TPM7_CLKIN 0x0110 0x09B0 0x6 0x1 +#define MX8ULP_PAD_PTF4__I2S7_RXD2 0x0110 0x0B5C 0x7 0x2 +#define MX8ULP_PAD_PTF4__SDHC1_D3 0x0110 0x0A70 0x8 0x2 +#define MX8ULP_PAD_PTF4__ENET0_TXEN 0x0110 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF4__USB0_OC 0x0110 0x0AC0 0xa 0x3 +#define MX8ULP_PAD_PTF4__EPDC0_SDCE7 0x0110 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF4__DPI0_D19 0x0110 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF4__WUU1_P10 0x0110 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF4__DEBUG_MUX1_25 0x0110 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF5__PTF5 0x0114 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF5__FXIO1_D5 0x0114 0x08A8 0x2 0x2 +#define MX8ULP_PAD_PTF5__LPSPI4_PCS2 0x0114 0x08FC 0x3 0x3 +#define MX8ULP_PAD_PTF5__LPUART7_RTS_B 0x0114 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF5__LPI2C7_SDA 0x0114 0x09C8 0x5 0x2 +#define MX8ULP_PAD_PTF5__TPM7_CH0 0x0114 0x0998 0x6 0x1 +#define MX8ULP_PAD_PTF5__I2S7_RXD3 0x0114 0x0B60 0x7 0x2 +#define MX8ULP_PAD_PTF5__SDHC1_D2 0x0114 0x0A6C 0x8 0x2 +#define MX8ULP_PAD_PTF5__ENET0_RXER 0x0114 0x0B08 0x9 0x2 +#define MX8ULP_PAD_PTF5__USB1_PWR 0x0114 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF5__EPDC0_SDCE6 0x0114 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF5__DPI0_D18 0x0114 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF5__LP_HV_DBG_MUX_18 0x0114 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX0_18 0x0114 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF5__DEBUG_MUX1_26 0x0114 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF6__LP_HV_DBG_MUX_19 0x0118 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF6__PTF6 0x0118 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF6__FXIO1_D6 0x0118 0x08AC 0x2 0x2 +#define MX8ULP_PAD_PTF6__LPSPI4_PCS3 0x0118 0x0900 0x3 0x3 +#define MX8ULP_PAD_PTF6__LPUART7_TX 0x0118 0x09E0 0x4 0x2 +#define MX8ULP_PAD_PTF6__I3C2_SCL 0x0118 0x08BC 0x5 0x3 +#define MX8ULP_PAD_PTF6__TPM7_CH1 0x0118 0x099C 0x6 0x1 +#define MX8ULP_PAD_PTF6__I2S7_MCLK 0x0118 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF6__SDHC1_D4 0x0118 0x0A74 0x8 0x2 +#define MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x0118 0x0AEC 0x9 0x2 +#define MX8ULP_PAD_PTF6__USB1_OC 0x0118 0x0AC4 0xa 0x3 +#define MX8ULP_PAD_PTF6__EPDC0_SDCE5 0x0118 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF6__DPI0_D17 0x0118 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF6__WDOG4_RST 0x0118 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX0_19 0x0118 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF6__DEBUG_MUX1_27 0x0118 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF7__PTF7 0x011C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF7__FXIO1_D7 0x011C 0x08B0 0x2 0x2 +#define MX8ULP_PAD_PTF7__LPUART7_RX 0x011C 0x09DC 0x4 0x2 +#define MX8ULP_PAD_PTF7__I3C2_SDA 0x011C 0x08C0 0x5 0x3 +#define MX8ULP_PAD_PTF7__TPM7_CH2 0x011C 0x09A0 0x6 0x1 +#define MX8ULP_PAD_PTF7__MQS1_LEFT 0x011C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF7__SDHC1_D5 0x011C 0x0A78 0x8 0x2 +#define MX8ULP_PAD_PTF7__ENET0_REFCLK 0x011C 0x0AF4 0x9 0x2 +#define MX8ULP_PAD_PTF7__TRACE0_D15 0x011C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF7__EPDC0_SDCE4 0x011C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF7__DPI0_D16 0x011C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF7__WUU1_P11 0x011C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF7__DEBUG_MUX1_28 0x011C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF8__PTF8 0x0120 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF8__FXIO1_D8 0x0120 0x08B4 0x2 0x2 +#define MX8ULP_PAD_PTF8__LPSPI4_SIN 0x0120 0x0908 0x3 0x3 +#define MX8ULP_PAD_PTF8__LPUART4_CTS_B 0x0120 0x08DC 0x4 0x3 +#define MX8ULP_PAD_PTF8__LPI2C4_SCL 0x0120 0x08C8 0x5 0x3 +#define MX8ULP_PAD_PTF8__TPM7_CH3 0x0120 0x09A4 0x6 0x1 +#define MX8ULP_PAD_PTF8__MQS1_RIGHT 0x0120 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF8__SDHC1_D6 0x0120 0x0A7C 0x8 0x2 +#define MX8ULP_PAD_PTF8__ENET0_MDIO 0x0120 0x0AF0 0x9 0x2 +#define MX8ULP_PAD_PTF8__TRACE0_D14 0x0120 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF8__EPDC0_D15 0x0120 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF8__DPI0_D15 0x0120 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF8__LP_HV_DBG_MUX_24 0x0120 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF8__DEBUG_MUX1_29 0x0120 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF9__PTF9 0x0124 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF9__FXIO1_D9 0x0124 0x08B8 0x2 0x2 +#define MX8ULP_PAD_PTF9__LPSPI4_SOUT 0x0124 0x090C 0x3 0x3 +#define MX8ULP_PAD_PTF9__LPUART4_RTS_B 0x0124 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF9__LPI2C4_SDA 0x0124 0x08CC 0x5 0x3 +#define MX8ULP_PAD_PTF9__TPM7_CH4 0x0124 0x09A8 0x6 0x1 +#define MX8ULP_PAD_PTF9__EXT_AUD_MCLK2 0x0124 0x0800 0x7 0x2 +#define MX8ULP_PAD_PTF9__SDHC1_D7 0x0124 0x0A80 0x8 0x2 +#define MX8ULP_PAD_PTF9__ENET0_MDC 0x0124 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF9__TRACE0_D13 0x0124 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF9__EPDC0_D14 0x0124 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF9__DPI0_D14 0x0124 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF9__LP_HV_DBG_MUX_25 0x0124 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF9__DEBUG_MUX1_30 0x0124 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF10__LP_HV_DBG_MUX_26 0x0128 0x0000 0x0 0x0 +#define MX8ULP_PAD_PTF10__PTF10 0x0128 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF10__FXIO1_D10 0x0128 0x0844 0x2 0x2 +#define MX8ULP_PAD_PTF10__LPSPI4_SCK 0x0128 0x0904 0x3 0x3 +#define MX8ULP_PAD_PTF10__LPUART4_TX 0x0128 0x08E4 0x4 0x3 +#define MX8ULP_PAD_PTF10__LPI2C4_HREQ 0x0128 0x08C4 0x5 0x3 +#define MX8ULP_PAD_PTF10__TPM7_CH5 0x0128 0x09AC 0x6 0x1 +#define MX8ULP_PAD_PTF10__I2S4_RX_BCLK 0x0128 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF10__SDHC1_DQS 0x0128 0x0A84 0x8 0x2 +#define MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x0128 0x0AD0 0x9 0x2 +#define MX8ULP_PAD_PTF10__TRACE0_D12 0x0128 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF10__EPDC0_D13 0x0128 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF10__DPI0_D13 0x0128 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX0_20 0x0128 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF10__DEBUG_MUX1_31 0x0128 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF11__PTF11 0x012C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF11__FXIO1_D11 0x012C 0x0848 0x2 0x2 +#define MX8ULP_PAD_PTF11__LPSPI4_PCS0 0x012C 0x08F4 0x3 0x3 +#define MX8ULP_PAD_PTF11__LPUART4_RX 0x012C 0x08E0 0x4 0x3 +#define MX8ULP_PAD_PTF11__TPM4_CLKIN 0x012C 0x081C 0x6 0x2 +#define MX8ULP_PAD_PTF11__I2S4_RX_FS 0x012C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF11__ENET0_1588_TMR0 0x012C 0x0AD4 0x9 0x2 +#define MX8ULP_PAD_PTF11__TRACE0_D11 0x012C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF11__EPDC0_D12 0x012C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF11__DPI0_D12 0x012C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF11__LP_HV_DBG_MUX_27 0x012C 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF11__DEBUG_MUX1_32 0x012C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF12__PTF12 0x0130 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF12__FXIO1_D12 0x0130 0x084C 0x2 0x2 +#define MX8ULP_PAD_PTF12__LPSPI5_PCS1 0x0130 0x0914 0x3 0x2 +#define MX8ULP_PAD_PTF12__LPUART5_CTS_B 0x0130 0x08E8 0x4 0x3 +#define MX8ULP_PAD_PTF12__LPI2C5_SCL 0x0130 0x08D4 0x5 0x3 +#define MX8ULP_PAD_PTF12__TPM4_CH0 0x0130 0x0804 0x6 0x2 +#define MX8ULP_PAD_PTF12__I2S4_RXD0 0x0130 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF12__SDHC2_WP 0x0130 0x0ABC 0x8 0x1 +#define MX8ULP_PAD_PTF12__ENET0_1588_TMR1 0x0130 0x0AD8 0x9 0x2 +#define MX8ULP_PAD_PTF12__TRACE0_D10 0x0130 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF12__EPDC0_D11 0x0130 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF12__DPI0_D11 0x0130 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF12__LP_HV_DBG_MUX_28 0x0130 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF12__DEBUG_MUX1_33 0x0130 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF13__PTF13 0x0134 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF13__FXIO1_D13 0x0134 0x0850 0x2 0x2 +#define MX8ULP_PAD_PTF13__LPSPI5_PCS2 0x0134 0x0918 0x3 0x2 +#define MX8ULP_PAD_PTF13__LPUART5_RTS_B 0x0134 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF13__LPI2C5_SDA 0x0134 0x08D8 0x5 0x3 +#define MX8ULP_PAD_PTF13__TPM4_CH1 0x0134 0x0808 0x6 0x2 +#define MX8ULP_PAD_PTF13__I2S4_RXD1 0x0134 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF13__SDHC2_CD 0x0134 0x0A8C 0x8 0x1 +#define MX8ULP_PAD_PTF13__ENET0_1588_TMR2 0x0134 0x0ADC 0x9 0x2 +#define MX8ULP_PAD_PTF13__TRACE0_D9 0x0134 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF13__EPDC0_D10 0x0134 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF13__DPI0_D10 0x0134 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF13__DEBUG_MUX0_21 0x0134 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF13__LP_HV_DBG_MUX_29 0x0134 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF14__PTF14 0x0138 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF14__FXIO1_D14 0x0138 0x0854 0x2 0x2 +#define MX8ULP_PAD_PTF14__LPSPI5_PCS3 0x0138 0x091C 0x3 0x2 +#define MX8ULP_PAD_PTF14__LPUART5_TX 0x0138 0x08F0 0x4 0x3 +#define MX8ULP_PAD_PTF14__LPI2C5_HREQ 0x0138 0x08D0 0x5 0x3 +#define MX8ULP_PAD_PTF14__TPM4_CH2 0x0138 0x080C 0x6 0x2 +#define MX8ULP_PAD_PTF14__I2S4_MCLK 0x0138 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF14__SDHC2_VS 0x0138 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF14__ENET0_1588_TMR3 0x0138 0x0AE0 0x9 0x2 +#define MX8ULP_PAD_PTF14__TRACE0_D8 0x0138 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF14__EPDC0_D9 0x0138 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF14__DPI0_D9 0x0138 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF14__DEBUG_MUX0_22 0x0138 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF14__LP_HV_DBG_MUX_30 0x0138 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF15__PTF15 0x013C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF15__FXIO1_D15 0x013C 0x0858 0x2 0x2 +#define MX8ULP_PAD_PTF15__LPUART5_RX 0x013C 0x08EC 0x4 0x3 +#define MX8ULP_PAD_PTF15__TPM4_CH3 0x013C 0x0810 0x6 0x2 +#define MX8ULP_PAD_PTF15__I2S4_TX_BCLK 0x013C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF15__SDHC2_D1 0x013C 0x0A9C 0x8 0x3 +#define MX8ULP_PAD_PTF15__ENET0_RXD2 0x013C 0x0B00 0x9 0x2 +#define MX8ULP_PAD_PTF15__TRACE0_D7 0x013C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF15__EPDC0_D8 0x013C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF15__DPI0_D8 0x013C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF15__LP_HV_DBG_MUX_31 0x013C 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF16__PTF16 0x0140 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF16__FXIO1_D16 0x0140 0x085C 0x2 0x2 +#define MX8ULP_PAD_PTF16__LPSPI5_SIN 0x0140 0x0924 0x3 0x2 +#define MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x0140 0x09CC 0x4 0x3 +#define MX8ULP_PAD_PTF16__LPI2C6_SCL 0x0140 0x09B8 0x5 0x3 +#define MX8ULP_PAD_PTF16__TPM4_CH4 0x0140 0x0814 0x6 0x2 +#define MX8ULP_PAD_PTF16__I2S4_TX_FS 0x0140 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF16__SDHC2_D0 0x0140 0x0A98 0x8 0x3 +#define MX8ULP_PAD_PTF16__ENET0_RXD3 0x0140 0x0B04 0x9 0x2 +#define MX8ULP_PAD_PTF16__TRACE0_D6 0x0140 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF16__EPDC0_D7 0x0140 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF16__DPI0_D7 0x0140 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF16__LP_HV_DBG_MUX_32 0x0140 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF17__PTF17 0x0144 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF17__FXIO1_D17 0x0144 0x0860 0x2 0x2 +#define MX8ULP_PAD_PTF17__LPSPI5_SOUT 0x0144 0x0928 0x3 0x2 +#define MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x0144 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF17__LPI2C6_SDA 0x0144 0x09BC 0x5 0x3 +#define MX8ULP_PAD_PTF17__TPM4_CH5 0x0144 0x0818 0x6 0x2 +#define MX8ULP_PAD_PTF17__I2S4_TXD0 0x0144 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF17__SDHC2_CLK 0x0144 0x0A90 0x8 0x3 +#define MX8ULP_PAD_PTF17__ENET0_RXCLK 0x0144 0x0B0C 0x9 0x2 +#define MX8ULP_PAD_PTF17__TRACE0_D5 0x0144 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF17__EPDC0_D6 0x0144 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF17__DPI0_D6 0x0144 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF17__DEBUG_MUX0_23 0x0144 0x0000 0xe 0x0 +#define MX8ULP_PAD_PTF17__LP_HV_DBG_MUX_33 0x0144 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF18__PTF18 0x0148 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF18__FXIO1_D18 0x0148 0x0864 0x2 0x2 +#define MX8ULP_PAD_PTF18__LPSPI5_SCK 0x0148 0x0920 0x3 0x2 +#define MX8ULP_PAD_PTF18__LPUART6_TX 0x0148 0x09D4 0x4 0x3 +#define MX8ULP_PAD_PTF18__LPI2C6_HREQ 0x0148 0x09B4 0x5 0x3 +#define MX8ULP_PAD_PTF18__TPM5_CLKIN 0x0148 0x0838 0x6 0x2 +#define MX8ULP_PAD_PTF18__I2S4_TXD1 0x0148 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF18__SDHC2_CMD 0x0148 0x0A94 0x8 0x3 +#define MX8ULP_PAD_PTF18__ENET0_TXD2 0x0148 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF18__TRACE0_D4 0x0148 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF18__EPDC0_D5 0x0148 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF18__DPI0_D5 0x0148 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF19__PTF19 0x014C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF19__FXIO1_D19 0x014C 0x0868 0x2 0x2 +#define MX8ULP_PAD_PTF19__LPSPI5_PCS0 0x014C 0x0910 0x3 0x2 +#define MX8ULP_PAD_PTF19__LPUART6_RX 0x014C 0x09D0 0x4 0x3 +#define MX8ULP_PAD_PTF19__TPM5_CH0 0x014C 0x0820 0x6 0x2 +#define MX8ULP_PAD_PTF19__I2S5_RX_BCLK 0x014C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF19__SDHC2_D3 0x014C 0x0AA4 0x8 0x3 +#define MX8ULP_PAD_PTF19__ENET0_TXD3 0x014C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF19__TRACE0_D3 0x014C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF19__EPDC0_D4 0x014C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF19__DPI0_D4 0x014C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF20__PTF20 0x0150 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF20__FXIO1_D20 0x0150 0x0870 0x2 0x2 +#define MX8ULP_PAD_PTF20__LPUART7_CTS_B 0x0150 0x09D8 0x4 0x3 +#define MX8ULP_PAD_PTF20__LPI2C7_SCL 0x0150 0x09C4 0x5 0x3 +#define MX8ULP_PAD_PTF20__TPM5_CH1 0x0150 0x0824 0x6 0x2 +#define MX8ULP_PAD_PTF20__I2S5_RX_FS 0x0150 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF20__SDHC2_D2 0x0150 0x0AA0 0x8 0x3 +#define MX8ULP_PAD_PTF20__ENET0_TXCLK 0x0150 0x0B10 0x9 0x2 +#define MX8ULP_PAD_PTF20__TRACE0_D2 0x0150 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF20__EPDC0_D3 0x0150 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF20__DPI0_D3 0x0150 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF21__PTF21 0x0154 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF21__FXIO1_D21 0x0154 0x0874 0x2 0x2 +#define MX8ULP_PAD_PTF21__SPDIF_CLK 0x0154 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF21__LPUART7_RTS_B 0x0154 0x0000 0x4 0x0 +#define MX8ULP_PAD_PTF21__LPI2C7_SDA 0x0154 0x09C8 0x5 0x3 +#define MX8ULP_PAD_PTF21__TPM6_CLKIN 0x0154 0x0994 0x6 0x2 +#define MX8ULP_PAD_PTF21__I2S5_RXD0 0x0154 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF21__SDHC2_D4 0x0154 0x0AA8 0x8 0x2 +#define MX8ULP_PAD_PTF21__ENET0_CRS 0x0154 0x0AE8 0x9 0x2 +#define MX8ULP_PAD_PTF21__TRACE0_D1 0x0154 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF21__EPDC0_D2 0x0154 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF21__DPI0_D2 0x0154 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF22__PTF22 0x0158 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF22__FXIO1_D22 0x0158 0x0878 0x2 0x2 +#define MX8ULP_PAD_PTF22__SPDIF_IN0 0x0158 0x0B74 0x3 0x3 +#define MX8ULP_PAD_PTF22__LPUART7_TX 0x0158 0x09E0 0x4 0x3 +#define MX8ULP_PAD_PTF22__LPI2C7_HREQ 0x0158 0x09C0 0x5 0x3 +#define MX8ULP_PAD_PTF22__TPM6_CH0 0x0158 0x097C 0x6 0x2 +#define MX8ULP_PAD_PTF22__I2S5_RXD1 0x0158 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF22__SDHC2_D5 0x0158 0x0AAC 0x8 0x2 +#define MX8ULP_PAD_PTF22__ENET0_COL 0x0158 0x0AE4 0x9 0x2 +#define MX8ULP_PAD_PTF22__TRACE0_D0 0x0158 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF22__EPDC0_D1 0x0158 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF22__DPI0_D1 0x0158 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF23__PTF23 0x015C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF23__FXIO1_D23 0x015C 0x087C 0x2 0x2 +#define MX8ULP_PAD_PTF23__SPDIF_OUT0 0x015C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF23__LPUART7_RX 0x015C 0x09DC 0x4 0x3 +#define MX8ULP_PAD_PTF23__I3C2_PUR 0x015C 0x0000 0x5 0x0 +#define MX8ULP_PAD_PTF23__TPM6_CH1 0x015C 0x0980 0x6 0x2 +#define MX8ULP_PAD_PTF23__I2S5_RXD2 0x015C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF23__SDHC2_D6 0x015C 0x0AB0 0x8 0x2 +#define MX8ULP_PAD_PTF23__ENET0_TXER 0x015C 0x0000 0x9 0x0 +#define MX8ULP_PAD_PTF23__TRACE0_CLKOUT 0x015C 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF23__EPDC0_D0 0x015C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF23__DPI0_D0 0x015C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__PTF24 0x0160 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF24__FXIO1_D24 0x0160 0x0880 0x2 0x2 +#define MX8ULP_PAD_PTF24__SPDIF_IN1 0x0160 0x0B78 0x3 0x3 +#define MX8ULP_PAD_PTF24__I3C2_SCL 0x0160 0x08BC 0x5 0x4 +#define MX8ULP_PAD_PTF24__I2S5_RXD3 0x0160 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF24__SDHC2_D7 0x0160 0x0AB4 0x8 0x2 +#define MX8ULP_PAD_PTF24__DBI0_WRX 0x0160 0x0000 0xa 0x0 +#define MX8ULP_PAD_PTF24__EPDC0_SDCLK 0x0160 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF24__DPI0_PCLK 0x0160 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF24__WUU1_P12 0x0160 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF25__PTF25 0x0164 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF25__FXIO1_D25 0x0164 0x0884 0x2 0x2 +#define MX8ULP_PAD_PTF25__SPDIF_OUT1 0x0164 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF25__I3C2_SDA 0x0164 0x08C0 0x5 0x4 +#define MX8ULP_PAD_PTF25__TPM7_CH5 0x0164 0x09AC 0x6 0x2 +#define MX8ULP_PAD_PTF25__I2S5_MCLK 0x0164 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF25__SDHC2_DQS 0x0164 0x0AB8 0x8 0x2 +#define MX8ULP_PAD_PTF25__EXT_AUD_MCLK2 0x0164 0x0800 0x9 0x3 +#define MX8ULP_PAD_PTF25__EPDC0_GDSP 0x0164 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF25__DPI0_VSYNC 0x0164 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF25__WUU1_P13 0x0164 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF26__PTF26 0x0168 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF26__FXIO1_D26 0x0168 0x0888 0x2 0x2 +#define MX8ULP_PAD_PTF26__SPDIF_IN2 0x0168 0x0B7C 0x3 0x3 +#define MX8ULP_PAD_PTF26__TPM7_CLKIN 0x0168 0x09B0 0x6 0x2 +#define MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x0168 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF26__SDHC2_RESET_B 0x0168 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF26__EPDC0_SDLE 0x0168 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF26__DPI0_HSYNC 0x0168 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF26__WUU1_P14 0x0168 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF27__PTF27 0x016C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF27__FXIO1_D27 0x016C 0x088C 0x2 0x2 +#define MX8ULP_PAD_PTF27__SPDIF_OUT2 0x016C 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF27__TPM7_CH0 0x016C 0x0998 0x6 0x2 +#define MX8ULP_PAD_PTF27__I2S5_TX_FS 0x016C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF27__SDHC2_WP 0x016C 0x0ABC 0x8 0x2 +#define MX8ULP_PAD_PTF27__EPDC0_SDCE0 0x016C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF27__DPI0_DE 0x016C 0x0000 0xc 0x0 +#define MX8ULP_PAD_PTF27__WUU1_P15 0x016C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF28__PTF28 0x0170 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF28__FXIO1_D28 0x0170 0x0890 0x2 0x2 +#define MX8ULP_PAD_PTF28__SPDIF_IN3 0x0170 0x0B80 0x3 0x3 +#define MX8ULP_PAD_PTF28__TPM7_CH1 0x0170 0x099C 0x6 0x2 +#define MX8ULP_PAD_PTF28__I2S5_TXD0 0x0170 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF28__SDHC2_CD 0x0170 0x0A8C 0x8 0x2 +#define MX8ULP_PAD_PTF28__EPDC0_SDCLK_B 0x0170 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF28__LP_HV_DBG_MUX_20 0x0170 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF29__PTF29 0x0174 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF29__FXIO1_D29 0x0174 0x0894 0x2 0x2 +#define MX8ULP_PAD_PTF29__SPDIF_OUT3 0x0174 0x0000 0x3 0x0 +#define MX8ULP_PAD_PTF29__TPM7_CH2 0x0174 0x09A0 0x6 0x2 +#define MX8ULP_PAD_PTF29__I2S5_TXD1 0x0174 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF29__SDHC2_VS 0x0174 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF29__EPDC0_SDCE1 0x0174 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF29__WDOG3_RST 0x0174 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF29__LP_HV_DBG_MUX_21 0x0174 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF30__PTF30 0x0178 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF30__FXIO1_D30 0x0178 0x089C 0x2 0x2 +#define MX8ULP_PAD_PTF30__TPM7_CH3 0x0178 0x09A4 0x6 0x2 +#define MX8ULP_PAD_PTF30__I2S5_TXD2 0x0178 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF30__MQS1_LEFT 0x0178 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF30__EPDC0_SDCE2 0x0178 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF30__WDOG4_RST 0x0178 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF30__LP_HV_DBG_MUX_22 0x0178 0x0000 0xf 0x0 +#define MX8ULP_PAD_PTF31__PTF31 0x017C 0x0000 0x1 0x0 +#define MX8ULP_PAD_PTF31__FXIO1_D31 0x017C 0x08A0 0x2 0x2 +#define MX8ULP_PAD_PTF31__TPM7_CH4 0x017C 0x09A8 0x6 0x2 +#define MX8ULP_PAD_PTF31__I2S5_TXD3 0x017C 0x0000 0x7 0x0 +#define MX8ULP_PAD_PTF31__MQS1_RIGHT 0x017C 0x0000 0x8 0x0 +#define MX8ULP_PAD_PTF31__EPDC0_SDCE3 0x017C 0x0000 0xb 0x0 +#define MX8ULP_PAD_PTF31__WDOG5_RST 0x017C 0x0000 0xd 0x0 +#define MX8ULP_PAD_PTF31__LP_HV_DBG_MUX_23 0x017C 0x0000 0xf 0x0 +#define MX8ULP_PAD_BOOT_MODE0__BOOT_MODE0 0x0400 0x0000 0x0 0x0 +#define MX8ULP_PAD_BOOT_MODE1__BOOT_MODE1 0x0404 0x0000 0x0 0x0 + +#endif /* __DTS_IMX8ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi new file mode 100644 index 0000000000..d3b16bd2fe --- /dev/null +++ b/arch/arm/dts/imx8ulp.dtsi @@ -0,0 +1,728 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include "imx8ulp-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpiod; + gpio1 = &gpioe; + gpio2 = &gpiof; + serial0 = &lpuart5; + mmc0 = &usdhc0; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + spi0 = &flexspi0; + spi2 = &flexspi2; + ethernet0 = &fec; + i2c7 = &lpi2c7; + usbphy0 = &usbphy0; + usb0 = &usbotg0; + usbphy1 = &usbphy1; + usb1 = &usbotg1; + }; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 1 clusters with 4 Cortex-A35 cores */ + A35_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; + }; + + A35_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A35_L2>; + clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>; + }; + + A35_L2: l2-cache0 { + compatible = "cache"; + }; + }; + + a35_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <800000>; + clock-latency-ns = <150000>; + }; + + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + s400_mu: mu@27020000 { + u-boot,dm-spl; + compatible = "fsl,imx8ulp-mu"; + reg = <0 0x27020000 0 0x10000>; + status = "okay"; + }; + + gic: interrupt-controller@2d400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ + <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + frosc: clock-frosc { + compatible = "fixed-clock"; + clock-frequency = <192000000>; + clock-output-names = "frosc"; + #clock-cells = <0>; + }; + + lposc: clock-lposc { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "lposc"; + #clock-cells = <0>; + }; + + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + }; + + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + }; + + sram@0x2201f000 { + compatible = "mmio-sram"; + reg = <0x0 0x2201f000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2201f000 0x1000>; + + /* TODO: split or unify */ + scmi_pd: scmi_pd@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_pd>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + }; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>; + + per_bridge0: bus@28000000 { + compatible = "simple-bus"; + reg = <0x28000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flexspi0: flexspi@28039000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8ulp-fspi"; + reg = <0x28039000 0x10000>, + <0x04000000 0x7ffffff>; + reg-names = "fspi_base", "fspi_mmap"; + status = "disabled"; + }; + }; + + per_bridge3: bus@29000000 { + compatible = "simple-bus"; + reg = <0x29000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x10000>, + <0x29020000 0x10000>, <0x29030000 0x10000>, + <0x29040000 0x10000>, <0x29050000 0x10000>, + <0x29060000 0x10000>, <0x29070000 0x10000>, + <0x29080000 0x10000>, <0x29090000 0x10000>, + <0x290a0000 0x10000>, <0x290b0000 0x10000>, + <0x290c0000 0x10000>, <0x290d0000 0x10000>, + <0x290e0000 0x10000>, <0x290f0000 0x10000>, + <0x29100000 0x10000>, <0x29110000 0x10000>, + <0x29120000 0x10000>, <0x29130000 0x10000>, + <0x29140000 0x10000>, <0x29150000 0x10000>, + <0x29160000 0x10000>, <0x29170000 0x10000>, + <0x29180000 0x10000>, <0x29190000 0x10000>, + <0x291a0000 0x10000>, <0x291b0000 0x10000>, + <0x291c0000 0x10000>, <0x291d0000 0x10000>, + <0x291e0000 0x10000>, <0x291f0000 0x10000>, + <0x29200000 0x10000>, <0x29210000 0x10000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx", + "edma1-chan2-tx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan6-tx", "edma1-chan7-tx", + "edma1-chan8-tx", "edma1-chan9-tx", + "edma1-chan10-tx", "edma1-chan11-tx", + "edma1-chan12-tx", "edma1-chan13-tx", + "edma1-chan14-tx", "edma1-chan15-tx", + "edma1-chan16-tx", "edma1-chan17-tx", + "edma1-chan18-tx", "edma1-chan19-tx", + "edma1-chan20-tx", "edma1-chan21-tx", + "edma1-chan22-tx", "edma1-chan23-tx", + "edma1-chan24-tx", "edma1-chan25-tx", + "edma1-chan26-tx", "edma1-chan27-tx", + "edma1-chan28-tx", "edma1-chan29-tx", + "edma1-chan30-tx", "edma1-chan31-tx"; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; + clock-names = "edma-mp-clk", + "edma1-chan0-clk", "edma1-chan1-clk", + "edma1-chan2-clk", "edma1-chan3-clk", + "edma1-chan4-clk", "edma1-chan5-clk", + "edma1-chan6-clk", "edma1-chan7-clk", + "edma1-chan8-clk", "edma1-chan9-clk", + "edma1-chan10-clk", "edma1-chan11-clk", + "edma1-chan12-clk", "edma1-chan13-clk", + "edma1-chan14-clk", "edma1-chan15-clk", + "edma1-chan16-clk", "edma1-chan17-clk", + "edma1-chan18-clk", "edma1-chan19-clk", + "edma1-chan20-clk", "edma1-chan21-clk", + "edma1-chan22-clk", "edma1-chan23-clk", + "edma1-chan24-clk", "edma1-chan25-clk", + "edma1-chan26-clk", "edma1-chan27-clk", + "edma1-chan28-clk", "edma1-chan29-clk", + "edma1-chan30-clk", "edma1-chan31-clk"; + status = "okay"; + }; + + wdog3: watchdog@292a0000 { + compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; + reg = <0x292a0000 0x10000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; + assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + timeout-sec = <40>; + }; + + cgc1: clock-controller@292c0000 { + compatible = "fsl,imx8ulp-cgc1"; + reg = <0x292c0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; + clock-names = "rosc", "sosc", "frosc", "lposc"; + #clock-cells = <1>; + }; + + pcc3: clock-controller@292d0000 { + compatible = "fsl,imx8ulp-pcc3"; + reg = <0x292d0000 0x10000>; + #clock-cells = <1>; + }; + + tpm5: tpm@29340000 { + compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; + reg = <0x29340000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_TPM5>, + <&pcc3 IMX8ULP_CLK_TPM5>; + clock-names = "ipg", "per"; + }; + + lpuart4: serial@29390000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x29390000 0x1000>; + interrupts = ; + clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@293a0000 { + compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x293a0000 0x1000>; + clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + clock-names = "ipg"; + status = "disabled"; + }; + }; + + per_bridge4: bus@29800000 { + compatible = "simple-bus"; + reg = <0x29800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcc4: clock-controller@29800000 { + compatible = "fsl,imx8ulp-pcc4"; + reg = <0x29800000 0x10000>; + #clock-cells = <1>; + }; + + lpi2c6: lpi2c6@29840000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29840000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, + <&pcc4 IMX8ULP_CLK_LPI2C6>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpi2c7: lpi2c7@29850000 { + compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x29850000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, + <&pcc4 IMX8ULP_CLK_LPI2C7>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + flexspi2: flexspi@29810000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8ulp-fspi"; + reg = <0x29810000 0x10000>, + <0x60000000 0xfffffff>; + reg-names = "fspi_base", "fspi_mmap"; + status = "disabled"; + }; + + flexspi2_nand: flexspi2_nand@29810000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8-fspi-nand"; + reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; + reg-names = "FlexSPI", "FlexSPI-memory"; + status = "disabled"; + }; + + iomuxc1: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + fsl,mux_mask = <0xf00>; + }; + + usdhc0: mmc@298d0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + reg = <0x298d0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc1: mmc@298e0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc"; + reg = <0x298e0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: mmc@298f0000 { + compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x298f0000 0x10000>; + interrupts = ; + clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, + <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>; + assigned-clock-rates = <396000000>, <396000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + bus-width = <4>; + status = "disabled"; + }; + + usbotg0: usb@29900000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x29900000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0>; + fsl,usbphy = <&usbphy0>; + fsl,usbmisc = <&usbmisc0 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc0: usbmisc@29900200 { + #index-cells = <1>; + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29900200 0x200>; + }; + + usbphy0: usbphy@29910000 { + compatible = "fsl,imx8ulp-usbphy", + "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; + reg = <0x29910000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; + }; + + usbotg1: usb@29920000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", + "fsl,imx27-usb"; + reg = <0x29920000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@29920200 { + #index-cells = <1>; + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29920200 0x200>; + }; + + usbphy1: usbphy@29930000 { + compatible = "fsl,imx8ulp-usbphy", + "fsl,imx7ulp-usbphy", "fsl,imx23-usbphy"; + reg = <0x29930000 0x1000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; + }; + + fec: ethernet@29950000 { + compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec"; + reg = <0x29950000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_ENET>, + <&pcc4 IMX8ULP_CLK_ENET>, + <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>, + <&pcc4 IMX8ULP_CLK_ENET>, + <&pcc4 IMX8ULP_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + }; + + gpioe: gpio@2d000000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x2d000080 0x1000 0x2d000040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, + <&pcc4 IMX8ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 24>; + }; + + gpiof: gpio@2d010000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x2d010080 0x1000 0x2d010040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, + <&pcc4 IMX8ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 24>; + }; + + per_bridge5: bus@2d800000 { + compatible = "simple-bus"; + reg = <0x2d800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@2d800000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x2d800000 0x10000>, + <0x2d810000 0x10000>, <0x2d820000 0x10000>, + <0x2d830000 0x10000>, <0x2d840000 0x10000>, + <0x2d850000 0x10000>, <0x2d860000 0x10000>, + <0x2d870000 0x10000>, <0x2d880000 0x10000>, + <0x2d890000 0x10000>, <0x2d8a0000 0x10000>, + <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>, + <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>, + <0x2d8f0000 0x10000>, <0x2d900000 0x10000>, + <0x2d910000 0x10000>, <0x2d920000 0x10000>, + <0x2d930000 0x10000>, <0x2d940000 0x10000>, + <0x2d950000 0x10000>, <0x2d960000 0x10000>, + <0x2d970000 0x10000>, <0x2d980000 0x10000>, + <0x2d990000 0x10000>, <0x2d9a0000 0x10000>, + <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>, + <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>, + <0x2d9f0000 0x10000>, <0x2da00000 0x10000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx", + "edma2-chan2-tx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-tx", "edma2-chan7-tx", + "edma2-chan8-tx", "edma2-chan9-tx", + "edma2-chan10-tx", "edma2-chan11-tx", + "edma2-chan12-tx", "edma2-chan13-tx", + "edma2-chan14-tx", "edma2-chan15-tx", + "edma2-chan16-tx", "edma2-chan17-tx", + "edma2-chan18-tx", "edma2-chan19-tx", + "edma2-chan20-tx", "edma2-chan21-tx", + "edma2-chan22-tx", "edma2-chan23-tx", + "edma2-chan24-tx", "edma2-chan25-tx", + "edma2-chan26-tx", "edma2-chan27-tx", + "edma2-chan28-tx", "edma2-chan29-tx", + "edma2-chan30-tx", "edma2-chan31-tx"; + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; + clock-names = "edma-mp-clk", + "edma2-chan0-clk", "edma2-chan1-clk", + "edma2-chan2-clk", "edma2-chan3-clk", + "edma2-chan4-clk", "edma2-chan5-clk", + "edma2-chan6-clk", "edma2-chan7-clk", + "edma2-chan8-clk", "edma2-chan9-clk", + "edma2-chan10-clk", "edma2-chan11-clk", + "edma2-chan12-clk", "edma2-chan13-clk", + "edma2-chan14-clk", "edma2-chan15-clk", + "edma2-chan16-clk", "edma2-chan17-clk", + "edma2-chan18-clk", "edma2-chan19-clk", + "edma2-chan20-clk", "edma2-chan21-clk", + "edma2-chan22-clk", "edma2-chan23-clk", + "edma2-chan24-clk", "edma2-chan25-clk", + "edma2-chan26-clk", "edma2-chan27-clk", + "edma2-chan28-clk", "edma2-chan29-clk", + "edma2-chan30-clk", "edma2-chan31-clk"; + status = "okay"; + }; + + cgc2: clock-controller@2da60000 { + compatible = "fsl,imx8ulp-cgc2"; + reg = <0x2da60000 0x10000>; + clocks = <&sosc>, <&frosc>; + clock-names = "sosc", "frosc"; + #clock-cells = <1>; + }; + + pcc5: clock-controller@2da70000 { + compatible = "fsl,imx8ulp-pcc5"; + reg = <0x2da70000 0x10000>; + #clock-cells = <1>; + }; + }; + + gpiod: gpio@2e200000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x2e200080 0x1000 0x2e200040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, + <&pcc5 IMX8ULP_CLK_RGPIOD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 24>; + }; + }; +}; diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h new file mode 100644 index 0000000000..49166a1830 --- /dev/null +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2020 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H +#define __DT_BINDINGS_CLOCK_IMX8ULP_H + +#define IMX8ULP_CLK_DUMMY 0 +#define IMX8ULP_CLK_ROSC 1 +#define IMX8ULP_CLK_FROSC 2 +#define IMX8ULP_CLK_LPOSC 3 +#define IMX8ULP_CLK_SOSC 4 +#define IMX8ULP_CLK_SPLL2 5 +#define IMX8ULP_CLK_SPLL3 6 +#define IMX8ULP_CLK_A35_SEL 7 +#define IMX8ULP_CLK_A35_DIV 8 +#define IMX8ULP_CLK_SPLL2_PRE_SEL 9 +#define IMX8ULP_CLK_SPLL3_PRE_SEL 10 +#define IMX8ULP_CLK_SPLL3_PFD0 11 +#define IMX8ULP_CLK_SPLL3_PFD1 12 +#define IMX8ULP_CLK_SPLL3_PFD2 13 +#define IMX8ULP_CLK_SPLL3_PFD3 14 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22 +#define IMX8ULP_CLK_NIC_SEL 23 +#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24 +#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25 +#define IMX8ULP_CLK_XBAR_SEL 26 +#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27 +#define IMX8ULP_CLK_XBAR_DIVBUS 28 +#define IMX8ULP_CLK_XBAR_AD_SLOW 29 +#define IMX8ULP_CLK_SOSC_DIV1 30 +#define IMX8ULP_CLK_SOSC_DIV2 31 +#define IMX8ULP_CLK_SOSC_DIV3 32 +#define IMX8ULP_CLK_FROSC_DIV1 33 +#define IMX8ULP_CLK_FROSC_DIV2 34 +#define IMX8ULP_CLK_FROSC_DIV3 35 +#define IMX8ULP_CLK_SPLL3_VCODIV 36 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37 +#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39 +#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE 41 +#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE 42 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE 43 +#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE 44 +#define IMX8ULP_CLK_SOSC_DIV1_GATE 45 +#define IMX8ULP_CLK_SOSC_DIV2_GATE 46 +#define IMX8ULP_CLK_SOSC_DIV3_GATE 47 +#define IMX8ULP_CLK_FROSC_DIV1_GATE 48 +#define IMX8ULP_CLK_FROSC_DIV2_GATE 49 +#define IMX8ULP_CLK_FROSC_DIV3_GATE 50 +#define IMX8ULP_CLK_ENETSTAMP_SEL 51 +#define IMX8ULP_CLK_SAI4_SEL 52 +#define IMX8ULP_CLK_SAI5_SEL 53 +#define IMX8ULP_CLK_AUD_CLK1 54 +#define IMX8ULP_CLK_ARM 55 + +#define IMX8ULP_CLK_CGC1_END 56 + +#define IMX8ULP_CLK_PLL4_PRE_SEL 0 +#define IMX8ULP_CLK_PLL4 1 +#define IMX8ULP_CLK_PLL4_VCODIV 2 +#define IMX8ULP_CLK_DDR_SEL 3 +#define IMX8ULP_CLK_DDR_DIV 4 +#define IMX8ULP_CLK_LPAV_AXI_SEL 5 +#define IMX8ULP_CLK_LPAV_AXI_DIV 6 +#define IMX8ULP_CLK_LPAV_AHB_DIV 7 +#define IMX8ULP_CLK_LPAV_BUS_DIV 8 +#define IMX8ULP_CLK_PLL4_PFD0 9 +#define IMX8ULP_CLK_PLL4_PFD1 10 +#define IMX8ULP_CLK_PLL4_PFD2 11 +#define IMX8ULP_CLK_PLL4_PFD3 12 +#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE 13 +#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE 14 +#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE 15 +#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE 16 +#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE 17 +#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18 +#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE 19 +#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE 20 +#define IMX8ULP_CLK_PLL4_PFD0_DIV1 21 +#define IMX8ULP_CLK_PLL4_PFD0_DIV2 22 +#define IMX8ULP_CLK_PLL4_PFD1_DIV1 23 +#define IMX8ULP_CLK_PLL4_PFD1_DIV2 24 +#define IMX8ULP_CLK_PLL4_PFD2_DIV1 25 +#define IMX8ULP_CLK_PLL4_PFD2_DIV2 26 +#define IMX8ULP_CLK_PLL4_PFD3_DIV1 27 +#define IMX8ULP_CLK_PLL4_PFD3_DIV2 28 +#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE 29 +#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE 30 +#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE 31 +#define IMX8ULP_CLK_CGC2_SOSC_DIV1 32 +#define IMX8ULP_CLK_CGC2_SOSC_DIV2 33 +#define IMX8ULP_CLK_CGC2_SOSC_DIV3 34 +#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE 35 +#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE 36 +#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE 37 +#define IMX8ULP_CLK_CGC2_FROSC_DIV1 38 +#define IMX8ULP_CLK_CGC2_FROSC_DIV2 39 +#define IMX8ULP_CLK_CGC2_FROSC_DIV3 40 +#define IMX8ULP_CLK_AUD_CLK2 41 +#define IMX8ULP_CLK_SAI6_SEL 42 +#define IMX8ULP_CLK_SAI7_SEL 43 +#define IMX8ULP_CLK_SPDIF_SEL 44 + +#define IMX8ULP_CLK_CGC2_END 45 + +/* PCC3 */ +#define IMX8ULP_CLK_WDOG3 0 +#define IMX8ULP_CLK_WDOG4 1 +#define IMX8ULP_CLK_LPIT1 2 +#define IMX8ULP_CLK_TPM4 3 +#define IMX8ULP_CLK_TPM5 4 +#define IMX8ULP_CLK_FLEXIO1 5 +#define IMX8ULP_CLK_I3C2 6 +#define IMX8ULP_CLK_LPI2C4 7 +#define IMX8ULP_CLK_LPI2C5 8 +#define IMX8ULP_CLK_LPUART4 9 +#define IMX8ULP_CLK_LPUART5 10 +#define IMX8ULP_CLK_LPSPI4 11 +#define IMX8ULP_CLK_LPSPI5 12 +#define IMX8ULP_CLK_DMA1_MP 13 +#define IMX8ULP_CLK_DMA1_CH0 14 +#define IMX8ULP_CLK_DMA1_CH1 15 +#define IMX8ULP_CLK_DMA1_CH2 16 +#define IMX8ULP_CLK_DMA1_CH3 17 +#define IMX8ULP_CLK_DMA1_CH4 18 +#define IMX8ULP_CLK_DMA1_CH5 19 +#define IMX8ULP_CLK_DMA1_CH6 20 +#define IMX8ULP_CLK_DMA1_CH7 21 +#define IMX8ULP_CLK_DMA1_CH8 22 +#define IMX8ULP_CLK_DMA1_CH9 23 +#define IMX8ULP_CLK_DMA1_CH10 24 +#define IMX8ULP_CLK_DMA1_CH11 25 +#define IMX8ULP_CLK_DMA1_CH12 26 +#define IMX8ULP_CLK_DMA1_CH13 27 +#define IMX8ULP_CLK_DMA1_CH14 28 +#define IMX8ULP_CLK_DMA1_CH15 29 +#define IMX8ULP_CLK_DMA1_CH16 30 +#define IMX8ULP_CLK_DMA1_CH17 31 +#define IMX8ULP_CLK_DMA1_CH18 32 +#define IMX8ULP_CLK_DMA1_CH19 33 +#define IMX8ULP_CLK_DMA1_CH20 34 +#define IMX8ULP_CLK_DMA1_CH21 35 +#define IMX8ULP_CLK_DMA1_CH22 36 +#define IMX8ULP_CLK_DMA1_CH23 37 +#define IMX8ULP_CLK_DMA1_CH24 38 +#define IMX8ULP_CLK_DMA1_CH25 39 +#define IMX8ULP_CLK_DMA1_CH26 40 +#define IMX8ULP_CLK_DMA1_CH27 41 +#define IMX8ULP_CLK_DMA1_CH28 42 +#define IMX8ULP_CLK_DMA1_CH29 43 +#define IMX8ULP_CLK_DMA1_CH30 44 +#define IMX8ULP_CLK_DMA1_CH31 45 + +#define IMX8ULP_CLK_PCC3_END 46 + +#define IMX8ULP_CLK_FLEXSPI2 0 +#define IMX8ULP_CLK_TPM6 1 +#define IMX8ULP_CLK_TPM7 2 +#define IMX8ULP_CLK_LPI2C6 3 +#define IMX8ULP_CLK_LPI2C7 4 +#define IMX8ULP_CLK_LPUART6 5 +#define IMX8ULP_CLK_LPUART7 6 +#define IMX8ULP_CLK_SAI4 7 +#define IMX8ULP_CLK_SAI5 8 +#define IMX8ULP_CLK_PCTLE 9 +#define IMX8ULP_CLK_PCTLF 10 +#define IMX8ULP_CLK_USDHC0 11 +#define IMX8ULP_CLK_USDHC1 12 +#define IMX8ULP_CLK_USDHC2 13 +#define IMX8ULP_CLK_USB0 14 +#define IMX8ULP_CLK_USB0_PHY 15 +#define IMX8ULP_CLK_USB1 16 +#define IMX8ULP_CLK_USB1_PHY 17 +#define IMX8ULP_CLK_USB_XBAR 18 +#define IMX8ULP_CLK_ENET 19 +#define IMX8ULP_CLK_SFA1 20 +#define IMX8ULP_CLK_RGPIOE 21 +#define IMX8ULP_CLK_RGPIOF 22 + +#define IMX8ULP_CLK_PCC4_END 23 + +#define IMX8ULP_CLK_TPM8 0 +#define IMX8ULP_CLK_SAI6 1 +#define IMX8ULP_CLK_SAI7 2 +#define IMX8ULP_CLK_SPDIF 3 +#define IMX8ULP_CLK_ISI 4 +#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_PCTLD 6 +#define IMX8ULP_CLK_CSI 7 +#define IMX8ULP_CLK_DSI 8 +#define IMX8ULP_CLK_WDOG5 9 +#define IMX8ULP_CLK_EPDC 10 +#define IMX8ULP_CLK_PXP 11 +#define IMX8ULP_CLK_SFA2 12 +#define IMX8ULP_CLK_GPU2D 13 +#define IMX8ULP_CLK_GPU3D 14 +#define IMX8ULP_CLK_DC_NANO 15 +#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_ESC 17 +#define IMX8ULP_CLK_RGPIOD 18 +#define IMX8ULP_CLK_DMA2_MP 19 +#define IMX8ULP_CLK_DMA2_CH0 20 +#define IMX8ULP_CLK_DMA2_CH1 21 +#define IMX8ULP_CLK_DMA2_CH2 22 +#define IMX8ULP_CLK_DMA2_CH3 23 +#define IMX8ULP_CLK_DMA2_CH4 24 +#define IMX8ULP_CLK_DMA2_CH5 25 +#define IMX8ULP_CLK_DMA2_CH6 26 +#define IMX8ULP_CLK_DMA2_CH7 27 +#define IMX8ULP_CLK_DMA2_CH8 28 +#define IMX8ULP_CLK_DMA2_CH9 29 +#define IMX8ULP_CLK_DMA2_CH10 30 +#define IMX8ULP_CLK_DMA2_CH11 31 +#define IMX8ULP_CLK_DMA2_CH12 32 +#define IMX8ULP_CLK_DMA2_CH13 33 +#define IMX8ULP_CLK_DMA2_CH14 34 +#define IMX8ULP_CLK_DMA2_CH15 35 +#define IMX8ULP_CLK_DMA2_CH16 36 +#define IMX8ULP_CLK_DMA2_CH17 37 +#define IMX8ULP_CLK_DMA2_CH18 38 +#define IMX8ULP_CLK_DMA2_CH19 39 +#define IMX8ULP_CLK_DMA2_CH20 40 +#define IMX8ULP_CLK_DMA2_CH21 41 +#define IMX8ULP_CLK_DMA2_CH22 42 +#define IMX8ULP_CLK_DMA2_CH23 43 +#define IMX8ULP_CLK_DMA2_CH24 44 +#define IMX8ULP_CLK_DMA2_CH25 45 +#define IMX8ULP_CLK_DMA2_CH26 46 +#define IMX8ULP_CLK_DMA2_CH27 47 +#define IMX8ULP_CLK_DMA2_CH28 48 +#define IMX8ULP_CLK_DMA2_CH29 49 +#define IMX8ULP_CLK_DMA2_CH30 50 +#define IMX8ULP_CLK_DMA2_CH31 51 + +#define IMX8ULP_CLK_PCC5_END 52 + +#endif From patchwork Wed Jul 21 14:17:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 483304 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP 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Wed, 21 Jul 2021 13:45:09 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V4 44/44] arm: imx: add i.MX8ULP EVK support Date: Wed, 21 Jul 2021 22:17:25 +0800 Message-Id: <20210721141725.23346-45-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210721141725.23346-1-peng.fan@oss.nxp.com> References: <20210721141725.23346-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0401CA0015.apcprd04.prod.outlook.com (2603:1096:3:1::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; Wed, 21 Jul 2021 13:45:07 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 96c8f49c-7540-4733-a7d4-08d94c4dc195 X-MS-TrafficTypeDiagnostic: DBBPR04MB7930: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:446; 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U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 40 + arch/arm/dts/imx8ulp-evk.dts | 223 ++++ arch/arm/mach-imx/imx8ulp/Kconfig | 7 + board/freescale/imx8ulp_evk/Kconfig | 14 + board/freescale/imx8ulp_evk/MAINTAINERS | 6 + board/freescale/imx8ulp_evk/Makefile | 7 + board/freescale/imx8ulp_evk/ddr_init.c | 207 ++++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 ++ board/freescale/imx8ulp_evk/lpddr4_timing.c | 1159 +++++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 105 ++ configs/imx8ulp_evk_defconfig | 103 ++ include/configs/imx8ulp_evk.h | 107 ++ 13 files changed, 2048 insertions(+) create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8ulp-evk.dts create mode 100644 board/freescale/imx8ulp_evk/Kconfig create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS create mode 100644 board/freescale/imx8ulp_evk/Makefile create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8ulp_evk/spl.c create mode 100644 configs/imx8ulp_evk_defconfig create mode 100644 include/configs/imx8ulp_evk.h -- 2.30.0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 90e3004dbe..91228b7032 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -859,6 +859,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \ imx8-deneb.dtb \ imx8-giedi.dtb +dtb-$(CONFIG_ARCH_IMX8ULP) += \ + imx8ulp-evk.dtb + dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi new file mode 100644 index 0000000000..7c1dab2acf --- /dev/null +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +&{/soc@0} { + u-boot,dm-spl; +}; + +&per_bridge3 { + u-boot,dm-spl; +}; + +&per_bridge4 { + u-boot,dm-spl; +}; + +&iomuxc1 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart5 { + u-boot,dm-spl; +}; + +&s400_mu { + u-boot,dm-spl; +}; + +&lpuart5 { + u-boot,dm-spl; +}; + +&usdhc0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc0 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts new file mode 100644 index 0000000000..da09ff48ff --- /dev/null +++ b/arch/arm/dts/imx8ulp-evk.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp.dtsi" + +/ { + model = "FSL i.MX8ULP EVK"; + compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + + chosen { + stdout-path = &lpuart5; + bootargs = "console=ttyLP1,115200 earlycon"; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>; + }; +}; + +&lpuart5 { + /* console */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpuart5>; + pinctrl-1 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&iomuxc1 { + pinctrl_lpuart5: lpuart5grp { + fsl,pins = < + MX8ULP_PAD_PTF14__LPUART5_TX 0x03 + MX8ULP_PAD_PTF15__LPUART5_RX 0x03 + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27 + MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43 + MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 + MX8ULP_PAD_PTD10__SDHC0_D0 0x43 + MX8ULP_PAD_PTD9__SDHC0_D1 0x43 + MX8ULP_PAD_PTD8__SDHC0_D2 0x43 + MX8ULP_PAD_PTD7__SDHC0_D3 0x43 + MX8ULP_PAD_PTD6__SDHC0_D4 0x43 + MX8ULP_PAD_PTD5__SDHC0_D5 0x43 + MX8ULP_PAD_PTD4__SDHC0_D6 0x43 + MX8ULP_PAD_PTD3__SDHC0_D7 0x43 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + >; + }; + + pinctrl_usdhc2_pte: usdhc2ptegrp { + fsl,pins = < + MX8ULP_PAD_PTE1__SDHC2_D0 0x43 + MX8ULP_PAD_PTE0__SDHC2_D1 0x43 + MX8ULP_PAD_PTE5__SDHC2_D2 0x43 + MX8ULP_PAD_PTE4__SDHC2_D3 0x43 + MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042 + MX8ULP_PAD_PTE3__SDHC2_CMD 0x43 + MX8ULP_PAD_PTE7__PTE7 0x10003 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 + MX8ULP_PAD_PTE15__ENET0_MDC 0x43 + MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043 + >; + }; + + pinctrl_usbotg0_id: otg0idgrp { + fsl,pins = < + MX8ULP_PAD_PTF2__USB0_ID 0x10003 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + >; + }; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_pte>; + pinctrl-1 = <&pinctrl_usdhc2_pte>; + pinctrl-2 = <&pinctrl_usdhc2_pte>; + pinctrl-3 = <&pinctrl_usdhc2_pte>; + mmc-pwrseq = <&usdhc2_pwrseq>; + max-frequency = <100000000>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; + + wifi_wake_host { + compatible = "nxp,wifi-wake-host"; + interrupt-parent = <&gpioe>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexspi0 { + status = "okay"; + + flash0: atxp032@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + }; +}; + +&flexspi2 { + status = "okay"; + + flash1: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + micrel,led-mode = <1>; + }; + }; +}; + +&usbotg0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg0_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy0 { + fsl,tx-d-cal = <88>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <88>; +}; diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 167dbb3fb1..963fc93d34 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -11,6 +11,13 @@ choice prompt "i.MX8ULP board select" optional +config TARGET_IMX8ULP_EVK + bool "imx8ulp_evk" + select IMX8ULP + select SUPPORT_SPL + endchoice +source "board/freescale/imx8ulp_evk/Kconfig" + endif diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig new file mode 100644 index 0000000000..1e461ee1da --- /dev/null +++ b/board/freescale/imx8ulp_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8ULP_EVK + +config SYS_BOARD + default "imx8ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8ulp_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8ulp_evk/MAINTAINERS b/board/freescale/imx8ulp_evk/MAINTAINERS new file mode 100644 index 0000000000..267b7b0caa --- /dev/null +++ b/board/freescale/imx8ulp_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8ULP EVK BOARD +M: Peng Fan +S: Maintained +F: board/freescale/imx8ulp_evk/ +F: include/configs/imx8ulp_evk.h +F: configs/imx8ulp_evk_defconfig diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile new file mode 100644 index 0000000000..b2e72b4e85 --- /dev/null +++ b/board/freescale/imx8ulp_evk/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += imx8ulp_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o ddr_init.o lpddr4_timing.o +endif diff --git a/board/freescale/imx8ulp_evk/ddr_init.c b/board/freescale/imx8ulp_evk/ddr_init.c new file mode 100644 index 0000000000..f4238d29b3 --- /dev/null +++ b/board/freescale/imx8ulp_evk/ddr_init.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + */ +#include +#include +#include +#include +#include + +#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR) +#define CTL_START 0x1 + +#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3) +#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197) +#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250) +#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251) +#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266) +#define DFI_INIT_COMPLETE 0x2 + +#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614) +#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615) + +#define DENALI_PI_00 (DDR_PI_BASE_ADDR) +#define PI_START 0x1 + +#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4) +#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11) +#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12) +#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23) +#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) + +#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624) +#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537) +#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8) +#define PHY_FREQ_SEL_INDEX(X) ((X) << 16) + +#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547) +#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555) +#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564) +#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565) + +int ddr_calibration(unsigned int fsp_table[3]) +{ + u32 reg_val; + u32 int_status_init, phy_freq_req, phy_freq_type; + u32 lock_0, lock_1, lock_2; + u32 freq_chg_pt, freq_chg_cnt; + + reg_val = readl(DENALI_CTL_250); + if (((reg_val >> 16) & 0x3) == 1) + freq_chg_cnt = 2; + else + freq_chg_cnt = 3; + + reg_val = readl(DENALI_PI_12); + if (reg_val == 0x3) { + freq_chg_pt = 1; + } else if (reg_val == 0x7) { + freq_chg_pt = 2; + } else { + printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + return -1; + } + + debug("%s\n", __func__); + + /* Assert PI_START parameter and then assert START parameter in Controller. */ + reg_val = readl(DENALI_PI_00) | PI_START; + writel(reg_val, DENALI_PI_00); + + reg_val = readl(DENALI_CTL_00) | CTL_START; + writel(reg_val, DENALI_CTL_00); + + /* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */ + do { + if (!freq_chg_cnt) { + int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff; + /* DDR subsystem is ready for traffic. */ + if (int_status_init & DFI_INIT_COMPLETE) { + printf("complete\n"); + break; + } + } + + /* + * During leveling, PHY will request for freq change and SoC clock + * logic should provide requested frequency, Polling SIM LPDDR_CTRL2 + * Bit phy_freq_chg_req until be 1'b1 + */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + phy_freq_req = (reg_val >> 7) & 0x1; + + if (phy_freq_req) { + phy_freq_type = reg_val & 0x1F; + if (!phy_freq_type) { + printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + } else if (phy_freq_type == 0x01) { + printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 1) + freq_chg_cnt--; + } else if (phy_freq_type == 0x02) { + printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 2) + freq_chg_cnt--; + } + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + } + } while (1); + + /* Check PLL lock status */ + lock_0 = readl(DENALI_PHY_1564) & 0xffff; + lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff; + lock_2 = readl(DENALI_PHY_1565) & 0xffff; + + if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) { + printf("De-Skew PLL failed to lock\n"); + printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2); + return -1; + } + + printf("De-Skew PLL is locked and ready\n"); + return 0; +} + +int ddr_init(struct dram_timing_info2 *dram_timing) +{ + int i; + + debug("%s\n", __func__); + + set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */ + + /* Initialize CTL registers */ + for (i = 0; i < dram_timing->ctl_cfg_num; i++) + writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg); + + /* Initialize PI registers */ + for (i = 0; i < dram_timing->pi_cfg_num; i++) + writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg); + + /* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f1_cfg_num; i++) + writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg); + + /* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f2_cfg_num; i++) + writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg); + + /* Re-enable MULTICAST mode */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + + return ddr_calibration(dram_timing->fsp_table); +} + +void enable_bypass_mode(void) +{ + u32 reg_val; + + /* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */ + reg_val = readl(DENALI_PI_04) & ~0x1; + writel(reg_val, DENALI_PI_04); + + /* PI_FREQ_MAP=0x1 (DENALI_PI_12) */ + writel(0x1, DENALI_PI_12); + + /* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */ + reg_val = readl(DENALI_PI_11) & ~(0x1f << 8); + writel(reg_val, DENALI_PI_11); + + /* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */ + reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24); + writel(reg_val, DENALI_CTL_23); + + /* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */ + reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8); + writel(reg_val, DENALI_PHY_1547); + + /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */ + reg_val = readl(DENALI_PHY_1624) | 0x1; + writel(reg_val, DENALI_PHY_1624); + + /* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */ + reg_val = readl(DENALI_PHY_1555) | 0x1; + writel(reg_val, DENALI_PHY_1555); + + /* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */ + reg_val = 0x020100; + writel(reg_val, DENALI_CTL_25); +} diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c new file mode 100644 index 0000000000..3ff4d43c99 --- /dev/null +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_FEC_MXC) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE) +static iomux_cfg_t const enet_clk_pads[] = { + IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +static int setup_fec(void) +{ + /* + * Since ref clock and timestamp clock are from external, + * set the iomux prior the clock enablement + */ + imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads)); + + /* Select enet time stamp clock: 001 - External Timestamp Clock */ + cgc1_enet_stamp_sel(1); + + /* enable FEC PCC */ + pcc_clock_enable(4, ENET_PCC4_SLOT, true); + pcc_reset_peripheral(4, ENET_PCC4_SLOT, false); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c new file mode 100644 index 0000000000..fa7f15e7f3 --- /dev/null +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + * + * Generated code from MX8M_DDR_tool + * + */ + +#include +#include + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0xce3f }, /* 14 */ + { 0x2e06003c, 0x80e70 }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0x210 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x2011001 }, /* 23 */ + { 0x2e060060, 0x2010000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x160b }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040614 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0xc0011 }, /* 46 */ + { 0x2e0600bc, 0xb0509 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4002432 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x5040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a06 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x4150b }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x4a }, /* 67 */ + { 0x2e060110, 0x3fd }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0x25000f }, /* 73 */ + { 0x2e060128, 0x4a0078 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x8070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x4c004c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x4050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0xff40 }, /* 113 */ + { 0x2e0601c8, 0xff40 }, /* 114 */ + { 0x2e0601cc, 0xff40 }, /* 115 */ + { 0x2e0601d0, 0xff40 }, /* 116 */ + { 0x2e0601d4, 0xff40 }, /* 117 */ + { 0x2e0601dc, 0x1beb }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0x1b0035 }, /* 173 */ + { 0x2e0602b8, 0x4040042 }, /* 174 */ + { 0x2e0602bc, 0x42 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x30000914 }, /* 183 */ + { 0x2e0602e0, 0x3030 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x30303000 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20002 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80108 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0xe0003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x8080505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x102 }, /* 309 */ + { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x7fa }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x17ee }, /* 591 */ + { 0x2e060940, 0x4fc4 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020406 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3040100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c06 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x201 }, /* 11 */ + { 0x2e062030, 0x7 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x6010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x36 }, /* 164 */ + { 0x2e062294, 0x2003c }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1406 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x4a }, /* 170 */ + { 0x2e0622ac, 0x3fd }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0018 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010805 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2060404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x340009 }, /* 189 */ + { 0x2e0622f8, 0x36000c }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1004201 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x430100 }, /* 196 */ + { 0x2e062314, 0x1000043 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x11000d }, /* 208 */ + { 0x2e062344, 0x140042 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0056 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x6090506 }, /* 222 */ + { 0x2e06237c, 0x2093 }, /* 223 */ + { 0x2e062380, 0x2001000c }, /* 224 */ + { 0x2e062384, 0x80a0a04 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x7fa }, /* 232 */ + { 0x2e0623a4, 0x4fc4 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x4c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0xce3f }, /* 243 */ + { 0x2e0623d0, 0x80e70 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0x210 }, /* 246 */ + { 0x2e0623dc, 0x4c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x101cdf }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10002 }, /* 254 */ + { 0x2e0623fc, 0x1080040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44300004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19443000 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194430 }, /* 281 */ + { 0x2e062468, 0x30000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44300004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19443009 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194430 }, /* 288 */ + { 0x2e062484, 0x30000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44300914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19443000 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194430 }, /* 295 */ + { 0x2e0624a0, 0x30091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x9bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000000 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c1201 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x143 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56417032 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2c302c3 }, /* 100 */ + { 0x2e064194, 0x2c302c3 }, /* 101 */ + { 0x2e064198, 0x2c302c3 }, /* 102 */ + { 0x2e06419c, 0x2c302c3 }, /* 103 */ + { 0x2e0641a0, 0x2c3 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x6b0080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x9bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000000 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c1201 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x143 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x30217465 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2c302c3 }, /* 356 */ + { 0x2e064594, 0x2c302c3 }, /* 357 */ + { 0x2e064598, 0x2c302c3 }, /* 358 */ + { 0x2e06459c, 0x2c302c3 }, /* 359 */ + { 0x2e0645a0, 0x2c3 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x6b0080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x9bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000000 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c1201 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x143 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x75436012 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2c302c3 }, /* 612 */ + { 0x2e064994, 0x2c302c3 }, /* 613 */ + { 0x2e064998, 0x2c302c3 }, /* 614 */ + { 0x2e06499c, 0x2c302c3 }, /* 615 */ + { 0x2e0649a0, 0x2c3 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x6b0080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x9bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000000 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c1201 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x143 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x32017465 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2c302c3 }, /* 868 */ + { 0x2e064d94, 0x2c302c3 }, /* 869 */ + { 0x2e064d98, 0x2c302c3 }, /* 870 */ + { 0x2e064d9c, 0x2c302c3 }, /* 871 */ + { 0x2e064da0, 0x2c3 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x6b0080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241b42 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x96 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11542 }, /* 1625 */ + { 0x2e065968, 0x30209bf }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x4bf77 }, /* 1635 */ + { 0x2e065990, 0x77 }, /* 1636 */ + { 0x2e065994, 0x27f }, /* 1637 */ + { 0x2e06599c, 0x27f }, /* 1639 */ + { 0x2e0659a4, 0x27f00 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x27fcc }, /* 1643 */ + { 0x2e0659b4, 0x27f00 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x27f00 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x27f00 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x27f00 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { + { 0x2e064168, 0x3020000 }, /* 90 */ + { 0x2e064170, 0xc043e42 }, /* 92 */ + { 0x2e064174, 0xf0c1701 }, /* 93 */ + { 0x2e064180, 0x187 }, /* 96 */ + { 0x2e064184, 0x3010203 }, /* 97 */ + { 0x2e064190, 0x3070307 }, /* 100 */ + { 0x2e064194, 0x3070307 }, /* 101 */ + { 0x2e064198, 0x3070307 }, /* 102 */ + { 0x2e06419c, 0x3070307 }, /* 103 */ + { 0x2e0641a0, 0x307 }, /* 104 */ + { 0x2e0641c8, 0x1bd0080 }, /* 114 */ + { 0x2e064568, 0x3020000 }, /* 346 */ + { 0x2e064570, 0xc043e42 }, /* 348 */ + { 0x2e064574, 0xf0c1701 }, /* 349 */ + { 0x2e064580, 0x187 }, /* 352 */ + { 0x2e064584, 0x3010203 }, /* 353 */ + { 0x2e064590, 0x3070307 }, /* 356 */ + { 0x2e064594, 0x3070307 }, /* 357 */ + { 0x2e064598, 0x3070307 }, /* 358 */ + { 0x2e06459c, 0x3070307 }, /* 359 */ + { 0x2e0645a0, 0x307 }, /* 360 */ + { 0x2e0645c8, 0x1bd0080 }, /* 370 */ + { 0x2e064968, 0x3020000 }, /* 602 */ + { 0x2e064970, 0xc043e42 }, /* 604 */ + { 0x2e064974, 0xf0c1701 }, /* 605 */ + { 0x2e064980, 0x187 }, /* 608 */ + { 0x2e064984, 0x3010203 }, /* 609 */ + { 0x2e064990, 0x3070307 }, /* 612 */ + { 0x2e064994, 0x3070307 }, /* 613 */ + { 0x2e064998, 0x3070307 }, /* 614 */ + { 0x2e06499c, 0x3070307 }, /* 615 */ + { 0x2e0649a0, 0x307 }, /* 616 */ + { 0x2e0649c8, 0x1bd0080 }, /* 626 */ + { 0x2e064d68, 0x3020000 }, /* 858 */ + { 0x2e064d70, 0xc043e42 }, /* 860 */ + { 0x2e064d74, 0xf0c1701 }, /* 861 */ + { 0x2e064d80, 0x187 }, /* 864 */ + { 0x2e064d84, 0x3010203 }, /* 865 */ + { 0x2e064d90, 0x3070307 }, /* 868 */ + { 0x2e064d94, 0x3070307 }, /* 869 */ + { 0x2e064d98, 0x3070307 }, /* 870 */ + { 0x2e064d9c, 0x3070307 }, /* 871 */ + { 0x2e064da0, 0x307 }, /* 872 */ + { 0x2e064dc8, 0x1bd0080 }, /* 882 */ + { 0x2e06509c, 0x33e }, /* 1063 */ + { 0x2e06549c, 0x33e }, /* 1319 */ + { 0x2e065878, 0x10703 }, /* 1566 */ + { 0x2e065964, 0x1342 }, /* 1625 */ +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 528, 1056 }, +}; + diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c new file mode 100644 index 0000000000..faece336ef --- /dev/null +++ b/board/freescale/imx8ulp_evk/spl.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + init_clk_ddr(); + ddr_init(&dram_timing); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +int power_init_board(void) +{ + u32 pmic_reg; + + /* PMIC set bucks1-4 to PWM mode */ + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + upower_pmic_i2c_write(0x10, 0x3d); + upower_pmic_i2c_write(0x14, 0x7d); + upower_pmic_i2c_write(0x21, 0x7d); + upower_pmic_i2c_write(0x2e, 0x3d); + + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + /* Set buck3 to 1.1v OD */ + upower_pmic_i2c_write(0x22, 0x28); + return 0; +} + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + preloader_console_init(); + + puts("Normal Boot\n"); + + /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ + + upower_init(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* This must place after upower init, so access to MDA and MRC are valid */ + /* Init XRDC MDA */ + xrdc_init_mda(); + + /* Init XRDC MRC for VIDEO, DSP domains */ + xrdc_init_mrc(); +} + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig new file mode 100644 index 0000000000..eebe6a7b93 --- /dev/null +++ b/configs/imx8ulp_evk_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8ULP=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IMX8ULP_EVK=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0x22020000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTDELAY=0 +CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk" +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +#CONFIG_SPL_RAM_SUPPORT=y +#CONFIG_SPL_RAM_DEVICE=y +#CONFIG_SPL_MMC_SUPPORT=y + +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 + +CONFIG_HUSH_PARSER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk" +CONFIG_SPL_DM=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8ULP=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y +CONFIG_CMD_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_MISC=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" + +CONFIG_CMD_I2C=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_READ=y +CONFIG_BAUDRATE=115200 + +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y + +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=0 + +CONFIG_ULP_WATCHDOG=y +CONFIG_SPL_WATCHDOG_SUPPORT=y + +CONFIG_CMD_SF=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_IMX_RGPIO2P=y +CONFIG_USE_ARCH_MEMCPY=y + +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y + +CONFIG_EFI_PARTITION=y + +CONFIG_DM_PCA953X=y diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h new file mode 100644 index 0000000000..32f8773b24 --- /dev/null +++ b/include/configs/imx8ulp_evk.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8ULP_EVK_H +#define __IMX8ULP_EVK_H + +#include +#include + +#define CONFIG_SYS_BOOTM_LEN (SZ_64M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x22050000 +#define CONFIG_SPL_BSS_START_ADDR 0x22048000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x22040000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */ + +#define CONFIG_MALLOC_F_ADDR 0x22040000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#endif + +#define CONFIG_SERIAL_TAG + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +/* ENET Config */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define IMX_FEC_BASE 0x29950000 +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#else +#define BOOTENV +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=Image\0" \ + "console=ttyLP1,115200 earlycon\0" \ + "fdt_addr_r=0x83000000\0" \ + "boot_fit=no\0" \ + "fdtfile=imx8ulp-evk.dtb\0" \ + "initrd_addr=0x83800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MMCROOT "/dev/mmcblk2p2" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_RBASE +#endif