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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:11 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: msm/dp: Change reg definition Date: Wed, 21 Jul 2021 19:42:23 -0700 Message-Id: <20210722024227.3313096-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org reg was defined as one region covering the entire DP block, but the memory map is actually split in 4 regions and obviously the size of these regions differs between platforms. Switch the reg to require that all four regions are specified instead. It is expected that the implementation will handle existing DTBs, even though the schema defines the new layout. Signed-off-by: Bjorn Andersson --- .../bindings/display/msm/dp-controller.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- 2.29.2 diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 64d8d9e5e47a..a6e41be038fc 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -19,7 +19,11 @@ properties: - qcom,sc7180-dp reg: - maxItems: 1 + items: + - description: ahb register block + - description: aux register block + - description: link register block + - description: p0 register block interrupts: maxItems: 1 @@ -100,7 +104,10 @@ examples: displayport-controller@ae90000 { compatible = "qcom,sc7180-dp"; - reg = <0xae90000 0x1400>; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0xc00>, + <0xae91000 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From patchwork Thu Jul 22 02:42:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 483853 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6762837jao; Wed, 21 Jul 2021 19:44:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjQg+ED8PJ1zuZAjONlqJwuZhZ5hyBApcGru3UciC/PuW93Xck+2fDnphfvLktf5g+eE7Z X-Received: by 2002:a6b:e417:: with SMTP id u23mr17910151iog.91.1626921858512; Wed, 21 Jul 2021 19:44:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626921858; cv=none; d=google.com; s=arc-20160816; b=cytZNhy4Nh8W8KJi22pkFbKoZLix6GLOurTl4us9Qdjtw5+hRf6qllDIlU4onNZ1Pw 5qJwdkxBvPWNk2GODmYKDWZ27FHUPG4/dLUE1lmkh6QltdtxTpezyh/Dftenw6kd58DV ykkxsDZCUTJhDarly4QTHW6qhzv1I8DTYxTLhYhf1V/0+lUvIIN1frZIijxeSLt9mfqD ONAp7xkSTFdEv+20mHyUpS6GAeQXv6bUpHdDsCM70D95+QecksG1YOZ8dVg8hZOakHzB FesK38dHGWXu3Zd6c3lTAwuzFZiNL6IDOP7tZkIElZzPIXH6iVqOI+Rlq3AGh01GOwks OxyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xKV8hlv55ixpHr/xWlsCOYWKdqHbAXYcZUW9Pc8iaEA=; b=Nx4WSgj2BD1nWU60QDCAH/IuTJ6nxOBBBwbmp9091XaWA23PaiWVotJp9JX2GnIu4G cMLul1q1yFz8QEzmXbfvKvh2ruAgSqK911pGPhJni6kvA9pkCaV9YPCwArkt9mW3FSOS noKRi9Pzu1bNKDORE4nmJ246SMGrmaBo0wsXj6aKgj46apLIElm2iSixGtHJakzFoRnF nveQT+DtjMpAWRAnCBa3SPxF4QVZqo7n/q6iw5s0hgiGCcEPB92iMjoPUk9dkwDZK4b+ 76YmAJz+OSamiTMNreiiiz3EqHZVFCg/G7XwGvCW7SQ6ycSEu3rmc1hcBsUjXMJ9QkJz bnCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IzorDbfi; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:12 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] drm/msm/dp: Use devres for ioremap() Date: Wed, 21 Jul 2021 19:42:24 -0700 Message-Id: <20210722024227.3313096-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The non-devres version of ioremap is used, which requires manual cleanup. But the code paths leading here is mixed with other devres users, so rely on this for ioremap as well to simplify the code. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_parser.c | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) -- 2.29.2 Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 0519dd3ac3c3..c064ced78278 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -32,7 +32,7 @@ static int msm_dss_ioremap(struct platform_device *pdev, } io_data->len = (u32)resource_size(res); - io_data->base = ioremap(res->start, io_data->len); + io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len); if (!io_data->base) { DRM_ERROR("%pS->%s: ioremap failed\n", __builtin_return_address(0), __func__); @@ -42,22 +42,6 @@ static int msm_dss_ioremap(struct platform_device *pdev, return 0; } -static void msm_dss_iounmap(struct dss_io_data *io_data) -{ - if (io_data->base) { - iounmap(io_data->base); - io_data->base = NULL; - } - io_data->len = 0; -} - -static void dp_parser_unmap_io_resources(struct dp_parser *parser) -{ - struct dp_io *io = &parser->io; - - msm_dss_iounmap(&io->dp_controller); -} - static int dp_parser_ctrl_res(struct dp_parser *parser) { int rc = 0; @@ -67,19 +51,14 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) rc = msm_dss_ioremap(pdev, &io->dp_controller); if (rc) { DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc); - goto err; + return rc; } io->phy = devm_phy_get(&pdev->dev, "dp"); - if (IS_ERR(io->phy)) { - rc = PTR_ERR(io->phy); - goto err; - } + if (IS_ERR(io->phy)) + return PTR_ERR(io->phy); return 0; -err: - dp_parser_unmap_io_resources(parser); - return rc; } static int dp_parser_misc(struct dp_parser *parser) From patchwork Thu Jul 22 02:42:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 484058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DD25C6377E for ; Thu, 22 Jul 2021 02:44:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D00761353 for ; Thu, 22 Jul 2021 02:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbhGVCDp (ORCPT ); Wed, 21 Jul 2021 22:03:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230463AbhGVCDj (ORCPT ); Wed, 21 Jul 2021 22:03:39 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACF30C0613CF for ; Wed, 21 Jul 2021 19:44:14 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id t143so5080971oie.8 for ; Wed, 21 Jul 2021 19:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jLfCGQhZ9sWWK6V+miB0xsO475S4ojkH6KbRA6dRnQ4=; b=enHglQkCfAeXdX2XT+ADILAHKBjtUZAqEoRhEBxzapVPkQhqIWS4apVqPKtTnx1joi DUSrlS4z6vYBIliupHyaFkUYPcxR+vNP+ZTXKQGHizjl1Za4cj0ULDNdh/4QJ6mb04R2 pWEduzwKUx6sLfFmqgaATyOIG0mu6tz6Q3xLkfRSaJc5YtrouH65Gx5tcTnUxe9HaSoR 6ZV5KKvwbTZ7Gyl1p9XR70JT+nDqO+JwqJi/XLILzYdQgKS+XsKPhgcb6caDZu/5kcOD 9/fg43z7lKyi7sw/geLrThpfA9raDy0MbPgbweomzYD4vNs7x6OIMlw8Rw/qJhvsr0h+ 5VVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jLfCGQhZ9sWWK6V+miB0xsO475S4ojkH6KbRA6dRnQ4=; b=mJRjwzWO3v4JxWl2psZAFLaiieoPwGw0VnKXj9muDG8xL5fgjQ8KLX8Ky96t6nuHnL L6zAdNkEC9/Ag7s6cKgADoFC0gylSOKTp3xZ0UpgmqU+a3aL5JC1Ky48fVeRAA55+T6C Ow1Oslvsn7kko8vpTLwoWdKcsDf4g8+rtr7GkCPPbGjji1MBA26bb9rCXvCmg0PfAWpt RxyUz5IuvSBGfR99npUcgpXKNSIQgbAjfNLY79RXW3uk0Qq0oMBd9z4Onkc3jejDMwmg ragmtEs9oezOfsiRK4L6eVKnDECIgrvVYF7MMzsr/eYaJThQ+PobBF2b6QnlUdijY+kD bCxg== X-Gm-Message-State: AOAM5331xvFNFnBznmpXV97zdOd7lUh3ZG3hv+fovFNt+9/UUHyajJlU weRrDu5mF2fne3BaHisP6PUPFQ== X-Google-Smtp-Source: ABdhPJxv5tX28bUZMIQ2i4FRhBPM5G8KFvgAH21RAfpzAtTS4CaoeIjq0CgLpSyBZVsVug8cKsefIQ== X-Received: by 2002:aca:1e11:: with SMTP id m17mr4309603oic.104.1626921854077; Wed, 21 Jul 2021 19:44:14 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:13 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] drm/msm/dp: Refactor ioremap wrapper Date: Wed, 21 Jul 2021 19:42:25 -0700 Message-Id: <20210722024227.3313096-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to deal with multiple memory ranges in the following commit change the ioremap wrapper to not poke directly into the dss_io_data struct. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_parser.c | 28 ++++++++++++++-------------- drivers/gpu/drm/msm/dp/dp_parser.h | 2 +- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index c064ced78278..e68dacef547c 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -19,39 +19,39 @@ static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { }, }; -static int msm_dss_ioremap(struct platform_device *pdev, - struct dss_io_data *io_data) +static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { struct resource *res = NULL; + void __iomem *base; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource(pdev, IORESOURCE_MEM, idx); if (!res) { DRM_ERROR("%pS->%s: msm_dss_get_res failed\n", __builtin_return_address(0), __func__); - return -ENODEV; + return ERR_PTR(-ENODEV); } - io_data->len = (u32)resource_size(res); - io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len); - if (!io_data->base) { + base = devm_ioremap_resource(&pdev->dev, res); + if (!base) { DRM_ERROR("%pS->%s: ioremap failed\n", __builtin_return_address(0), __func__); - return -EIO; + return ERR_PTR(-EIO); } - return 0; + *len = resource_size(res); + return base; } static int dp_parser_ctrl_res(struct dp_parser *parser) { - int rc = 0; struct platform_device *pdev = parser->pdev; struct dp_io *io = &parser->io; + struct dss_io_data *dss = &io->dp_controller; - rc = msm_dss_ioremap(pdev, &io->dp_controller); - if (rc) { - DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc); - return rc; + dss->base = dp_ioremap(pdev, 0, &dss->len); + if (IS_ERR(dss->base)) { + DRM_ERROR("unable to remap dp io region: %pe\n", dss->base); + return PTR_ERR(dss->base); } io->phy = devm_phy_get(&pdev->dev, "dp"); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 34b49628bbaf..dc62e70b1640 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -26,7 +26,7 @@ enum dp_pm_type { }; struct dss_io_data { - u32 len; + size_t len; void __iomem *base; }; From patchwork Thu Jul 22 02:42:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 484057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D66E5C63797 for ; Thu, 22 Jul 2021 02:44:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC5B661283 for ; Thu, 22 Jul 2021 02:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230527AbhGVCDp (ORCPT ); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:14 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] drm/msm/dp: Store each subblock in the io region Date: Wed, 21 Jul 2021 19:42:26 -0700 Message-Id: <20210722024227.3313096-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So dss_io_data into representing each of the sub-regions, to make it possible in the next patch to specify each of the sub-regions individually. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_catalog.c | 64 +++++++++-------------------- drivers/gpu/drm/msm/dp/dp_parser.c | 30 ++++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.h | 10 ++++- 3 files changed, 54 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index ca96e3514790..23458b0ddc37 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -24,15 +24,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000 -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200 -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200 -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200 -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400 -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00 -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000 -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400 - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_I2C_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -66,82 +57,77 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *dss = &catalog->io->dp_controller; - msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len, - catalog->io->dp_controller.base, "dp_ctrl"); + msm_disp_snapshot_add_block(disp_state, dss->ahb_len, dss->ahb, "dp_ahb"); + msm_disp_snapshot_add_block(disp_state, dss->aux_len, dss->aux, "dp_aux"); + msm_disp_snapshot_add_block(disp_state, dss->link_len, dss->link, "dp_link"); + msm_disp_snapshot_add_block(disp_state, dss->p0_len, dss->p0, "dp_p0"); } static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.aux + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.aux + offset); } static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.ahb + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.ahb + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.link + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.link + offset); } /* aux related catalog functions */ @@ -276,29 +262,21 @@ static void dump_regs(void __iomem *base, int len) void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { - u32 offset, len; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *io = &catalog->io->dp_controller; pr_info("AHB regs\n"); - offset = MSM_DP_CONTROLLER_AHB_OFFSET; - len = MSM_DP_CONTROLLER_AHB_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->ahb, io->ahb_len); pr_info("AUXCLK regs\n"); - offset = MSM_DP_CONTROLLER_AUX_OFFSET; - len = MSM_DP_CONTROLLER_AUX_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->aux, io->aux_len); pr_info("LCLK regs\n"); - offset = MSM_DP_CONTROLLER_LINK_OFFSET; - len = MSM_DP_CONTROLLER_LINK_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->link, io->link_len); pr_info("P0CLK regs\n"); - offset = MSM_DP_CONTROLLER_P0_OFFSET; - len = MSM_DP_CONTROLLER_P0_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->p0, io->p0_len); } u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -492,8 +470,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -540,8 +517,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readl_poll_timeout(catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index e68dacef547c..1a10901ae574 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -11,6 +11,15 @@ #include "dp_parser.h" #include "dp_reg.h" +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { .num = 2, .regs = { @@ -48,12 +57,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) struct dp_io *io = &parser->io; struct dss_io_data *dss = &io->dp_controller; - dss->base = dp_ioremap(pdev, 0, &dss->len); - if (IS_ERR(dss->base)) { - DRM_ERROR("unable to remap dp io region: %pe\n", dss->base); - return PTR_ERR(dss->base); + dss->ahb = dp_ioremap(pdev, 0, &dss->ahb_len); + if (IS_ERR(dss->ahb)) { + DRM_ERROR("unable to remap ahb region: %pe\n", dss->ahb); + return PTR_ERR(dss->ahb); } + if (dss->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb_len = DP_DEFAULT_AHB_SIZE; + dss->aux = dss->ahb + DP_DEFAULT_AUX_OFFSET; + dss->aux_len = DP_DEFAULT_AUX_SIZE; + dss->link = dss->ahb + DP_DEFAULT_LINK_OFFSET; + dss->link_len = DP_DEFAULT_LINK_SIZE; + dss->p0 = dss->ahb + DP_DEFAULT_P0_OFFSET; + dss->p0_len = DP_DEFAULT_P0_SIZE; + io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy)) return PTR_ERR(io->phy); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index dc62e70b1640..3266b529c090 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -26,8 +26,14 @@ enum dp_pm_type { }; struct dss_io_data { - size_t len; - void __iomem *base; + void __iomem *ahb; + size_t ahb_len; + void __iomem *aux; + size_t aux_len; + void __iomem *link; + size_t link_len; + void __iomem *p0; + size_t p0_len; }; static inline const char *dp_parser_pm_name(enum dp_pm_type module) From patchwork Thu Jul 22 02:42:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 483855 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp6762895jao; Wed, 21 Jul 2021 19:44:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2m0pr6aodJst1w/l1E0Hj1zGRcBxV5IUZuJmzuAwK4fsTYOkX2W66RiNbZFS6YA9x/qBY X-Received: by 2002:a02:90d0:: with SMTP id c16mr33479569jag.106.1626921864998; Wed, 21 Jul 2021 19:44:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626921864; cv=none; d=google.com; s=arc-20160816; b=ZSPma24o3GxefTE9Fzg60kMd50sq2R9TS1WVkKHIXCD/rguMoqLJSiNwBhqgRu3WJn 8iNh9QtIJ3wu242UIoALNOrQetSZsS0kjPTq3RJukjZqlfeqOl4BSmYyS1hFcFSe8EEK sTrmPZdSHKarpZNaxCVB/KBhZNUgFpryCsi9mAuYAvmii+gAW67KMkLBogPWXPyy0m+q bAmG9mtjFsNbmOk5rNTKRLxgaIvuhTP8cUlnMQWg1bwGJfosB4TD59mDiPJHqlcOTGxW IC3sXF6ehFMOlP2YHIudaEAsKHm+y1rk41/lxow0GCx1iZC06lVPT2d5eqWx9D+NpSNy QLHQ== ARC-Message-Signature: i=1; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id u18sm5346519oif.9.2021.07.21.19.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 19:44:15 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Stephen Boyd , Abhinav Kumar Cc: Kuogee Hsieh , Tanmay Shah , Chandan Uddaraju , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] drm/msm/dp: Allow sub-regions to be specified in DT Date: Wed, 21 Jul 2021 19:42:27 -0700 Message-Id: <20210722024227.3313096-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210722024227.3313096-1-bjorn.andersson@linaro.org> References: <20210722024227.3313096-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Not all platforms has P0 at an offset of 0x1000 from the base address, so add support for specifying each sub-region in DT. The code falls back to the predefined offsets in the case that only a single reg is specified, in order to support existing DT. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_parser.c | 49 +++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 11 deletions(-) -- 2.29.2 Reviewed-by: Stephen Boyd Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 1a10901ae574..fc8a6452f641 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -63,18 +63,45 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) return PTR_ERR(dss->ahb); } - if (dss->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { - DRM_ERROR("legacy memory region not large enough\n"); - return -EINVAL; - } + dss->aux = dp_ioremap(pdev, 1, &dss->aux_len); + if (IS_ERR(dss->aux)) { + /* + * The initial binding had a single reg, but in order to + * support variation in the sub-region sizes this was split. + * dp_ioremap() will fail with -ENODEV here if only a single + * reg is specified, so fill in the sub-region offsets and + * lengths based on this single region. + */ + if (PTR_ERR(dss->aux) == -ENODEV) { + if (dss->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb_len = DP_DEFAULT_AHB_SIZE; + dss->aux = dss->ahb + DP_DEFAULT_AUX_OFFSET; + dss->aux_len = DP_DEFAULT_AUX_SIZE; + dss->link = dss->ahb + DP_DEFAULT_LINK_OFFSET; + dss->link_len = DP_DEFAULT_LINK_SIZE; + dss->p0 = dss->ahb + DP_DEFAULT_P0_OFFSET; + dss->p0_len = DP_DEFAULT_P0_SIZE; + } else { + DRM_ERROR("unable to remap aux region: %pe\n", dss->aux); + return PTR_ERR(dss->aux); + } + } else { + dss->link = dp_ioremap(pdev, 2, &dss->link_len); + if (IS_ERR(dss->link)) { + DRM_ERROR("unable to remap link region: %pe\n", dss->link); + return PTR_ERR(dss->link); + } - dss->ahb_len = DP_DEFAULT_AHB_SIZE; - dss->aux = dss->ahb + DP_DEFAULT_AUX_OFFSET; - dss->aux_len = DP_DEFAULT_AUX_SIZE; - dss->link = dss->ahb + DP_DEFAULT_LINK_OFFSET; - dss->link_len = DP_DEFAULT_LINK_SIZE; - dss->p0 = dss->ahb + DP_DEFAULT_P0_OFFSET; - dss->p0_len = DP_DEFAULT_P0_SIZE; + dss->p0 = dp_ioremap(pdev, 3, &dss->p0_len); + if (IS_ERR(dss->p0)) { + DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0); + return PTR_ERR(dss->p0); + } + } io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy))