From patchwork Thu May 18 09:01:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100058 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp620051qge; Thu, 18 May 2017 02:02:39 -0700 (PDT) X-Received: by 10.99.170.66 with SMTP id x2mr3333181pgo.121.1495098159110; Thu, 18 May 2017 02:02:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495098159; cv=none; d=google.com; s=arc-20160816; b=Ju7tnSuSRWyFgTHpW+Zxm/ILZEWwXrIkANtbDcJAcWJ7ToD1cd0U7a/0fXIoICa58J +S4KZdke1mdD8qTqw429kLLpRxEg+Kq55llOFrQ3y0dNqtQL/ivIkxkFsmsGVx5cdHHX P5a5oxQLC0ZDPVH2jfTBZhxUGfFo8NVTBFvCtizJG2Y1GLACfyYFr9d1/laJXj3Cw47r 0DMJxxdWrdUUULlTib2M5abRhsVoxvpf6c19VxgoNfT+9SdZ/E+sAKxxlpl/RFvqVKEJ D/9NVlZLHSbjdKDpKyqHYDy0IHvF2GL6jkk2b7C3/JfIagwCz4u9HlYtQK2Oo14PqmAd 3ifQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=3SKAy/Z5Mo2b3njlckIHFh59F1/g95t0b8wAUckliLI=; b=t4Gew23/sOc4OnkjAgBwa9OH4zZO/wE2crpIf/ebz+M511oLpObXWlopQlB6fPGe9i xeheJ1fWxODHwtNKF5++h3AM2edP75U/VC+EgvnrIlMt/CjDh8yQ32D6baz59BE/eDVK yyPEkogIifAr5HwinfbVc3d92NeeXT5nNywUrtaMsxDx03bhiEF1OLeodjtfASr3ZNcm s1WgTdYi+JQBTnLLJ8+7x81ai5HZBk6PxLr4nppp5ubqZV2WdIXdfSxeHSk70qk/Y8Jj 4udax8vRqE3dBN3H/kEIsAuwtiIU8DF7AcuPRckosl2y6BAemppT7MwULtkzZLQ14z8O 7VGg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y133si4684726pfg.257.2017.05.18.02.02.38; Thu, 18 May 2017 02:02:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754325AbdERJCP (ORCPT + 25 others); Thu, 18 May 2017 05:02:15 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6352 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751398AbdERJCL (ORCPT ); Thu, 18 May 2017 05:02:11 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANU67982; Thu, 18 May 2017 17:02:05 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Thu, 18 May 2017 17:01:54 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v2 1/2] PCI/portdrv: add support for different MSI interrupts for PCIe port services Date: Thu, 18 May 2017 10:01:37 +0100 Message-ID: <1495098098-1984-2-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.591D630E.0023, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 826fb3513e9a6cca0793654d346ca147 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently PCIe port services are assigned with different interrutps only if MSI-x are supported by calling pcie_port_enable_msix(). If a root port supports MSI instead of MSI-x currently we fall back to use a single shared interrupt for all the services. This patch renames and extends pcie_port_enable_msix() to use MSI in case MSI-x allocation fails. Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv.h | 8 ++++--- drivers/pci/pcie/portdrv_core.c | 46 +++++++++++++++++++++++++---------------- 2 files changed, 33 insertions(+), 21 deletions(-) -- 2.7.4 Reviewed-by: Christoph Hellwig diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 587aef3..1993e2c 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -13,10 +13,12 @@ #define PCIE_PORT_DEVICE_MAXSERVICES 5 /* - * According to the PCI Express Base Specification 2.0, the indices of - * the MSI-X table entries used by port services must not exceed 31 + * According to the PCI Express Base Specification REV. 3.1 and according + * to the PCI Local Bus Specification REV. 3.0 respectively, the indices of + * the MSI-X table entries or the max number of MSI vectors used by port + * services must not exceed 31 */ -#define PCIE_PORT_MAX_MSIX_ENTRIES 32 +#define PCIE_PORT_MAX_MSI_ENTRIES 32 #define get_descriptor_id(type, service) (((type - 4) << 8) | service) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index cea504f..254bc73 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -44,14 +44,15 @@ static void release_pcie_device(struct device *dev) } /** - * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port + * pcie_port_enable_msix_or_msi - try to set up MSI-X or MSI as interrupt mode + * for given port * @dev: PCI Express port to handle * @irqs: Array of interrupt vectors to populate * @mask: Bitmask of port capabilities returned by get_port_device_capability() * * Return value: 0 on success, error code on failure */ -static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) +static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) { int nr_entries, entry, nvec = 0; @@ -61,8 +62,8 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * equal to the number of entries this port actually uses, we'll happily * go through without any tricks. */ - nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES, - PCI_IRQ_MSIX); + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES, + PCI_IRQ_MSIX | PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; @@ -77,7 +78,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * Number field in the PCI Express Capabilities register", where * according to Section 7.8.2 of the specification "For MSI-X, * the value in this field indicates which MSI-X Table entry is - * used to generate the interrupt message." + * used to generate the interrupt message." and "For MSI, the + * value in this field indicates the offset between the base + * Message Data and the interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * */ pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9; @@ -100,7 +107,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) * MSI/MSI-X vectors assigned to the port is going to be used * for AER, where "For MSI-X, the value in this register * indicates which MSI-X Table entry is used to generate the - * interrupt message." + * interrupt message." and "For MSI, the value + * in this field indicates the offset between the base Message + * Data and the interrupt message that is generated." + * + * pci_irq_vector() below is able to handle entry differently + * depending on MSI vs MSI-x case + * */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); @@ -124,7 +137,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) /* Now allocate the MSI-X vectors for real */ nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec, - PCI_IRQ_MSIX); + PCI_IRQ_MSIX | PCI_IRQ_MSI); if (nr_entries < 0) return nr_entries; } @@ -146,26 +159,23 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask) */ static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) { - unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI; int ret, i; for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) irqs[i] = -1; /* - * If MSI cannot be used for PCIe PME or hotplug, we have to use - * INTx or other interrupts, e.g. system shared interrupt. + * Make sure MSI can be used for PCIe PME or hotplug. otherwise we have + * to use INTx or other interrupts, e.g. system shared interrupt. */ - if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) || - ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) { - flags &= ~PCI_IRQ_MSI; - } else { - /* Try to use MSI-X if supported */ - if (!pcie_port_enable_msix(dev, irqs, mask)) + if (!((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) && + !((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) + /* Try to use MSI-X or MSI if supported */ + if (!pcie_port_enable_irq_vec(dev, irqs, mask)) return 0; - } - ret = pci_alloc_irq_vectors(dev, 1, 1, flags); + /* fall back to legacy IRQ */ + ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); if (ret < 0) return -ENODEV; From patchwork Thu May 18 09:01:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100059 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp620056qge; Thu, 18 May 2017 02:02:39 -0700 (PDT) X-Received: by 10.99.172.9 with SMTP id v9mr3333302pge.60.1495098159506; Thu, 18 May 2017 02:02:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495098159; cv=none; d=google.com; s=arc-20160816; b=E9rjeVNaV+1LHgSz8+K0y8juBScQUSkcvxGawteZ8QS3Fr9PYKPobbSxOQ1tasVb0M UANQ6g8qQ9ABFo89zjKhSFJj3SSVMlXGZtdok7v66k49XIw9gregqiDp0macf0qFHTZA OaTliUQU8RIPyHCxwTHIt0y7qJw8uR7JRuT9hYpGFV4BNi86zgMmyV+/7CmAg3KpyEUC hhNoQoCm73/e3b6WHwZNkkMdOxk7GhEe8FdBcDMlgGnt8IDSO10rAW3qc6TZ62OFbjUN ijP557UgyAkwmZzLDkRWXOM5m5YTnMnRzRRhHyFEHMZAJb2/H1zSCJyeMHuBKZzRHt6+ nkMQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id y133si4684726pfg.257.2017.05.18.02.02.39; Thu, 18 May 2017 02:02:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754567AbdERJCR (ORCPT + 25 others); Thu, 18 May 2017 05:02:17 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6351 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751486AbdERJCM (ORCPT ); Thu, 18 May 2017 05:02:12 -0400 Received: from 172.30.72.54 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.54]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANU67978; Thu, 18 May 2017 17:02:05 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.162) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Thu, 18 May 2017 17:01:58 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v2 2/2] PCI/portdrv: allocate MSI/MSIx vector for DPC RP service Date: Thu, 18 May 2017 10:01:38 +0100 Message-ID: <1495098098-1984-3-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 In-Reply-To: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> References: <1495098098-1984-1-git-send-email-gabriele.paoloni@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.162] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.591D630E.0014, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 48800a22a1dbad301fcbd233ca3c176b Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni Currently the MSI/MSIx vectors for the root port services are allocated calling pcie_init_service_irqs(). At the moment these vectors are only allocated for AER, PME, HP. This patch allocate an MSI/MSIx vector also for DPC. Signed-off-by: Liudongdong Signed-off-by: Gabriele Paoloni --- drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) -- 2.7.4 Reviewed-by: Christoph Hellwig diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 254bc73..4a8a1df 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -126,6 +126,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * The code below follows Section 6.2.10.1 of the PCI Express + * Base Specification 4.0 stating that bits 4-0 of DPC + * Capability Register contain a value indicating which of the + * MSI/MSI-X vectors assigned to the port is going to be used + * for DPC, where "For MSI-X, the value in this register + * indicates which MSI-X Table entry is used to generate the + * interrupt message." and "For MSI, the value in this field + * indicates the offset between the base Message Data and the + * interrupt message that is generated." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the