From patchwork Mon Sep 17 10:36:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146842 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3602611ljw; Mon, 17 Sep 2018 03:37:55 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaK8gdcKkHSGN9qHiePBzAe/pAFNTIHkPOinYrhwHpxFBAYXACwbS8G1osUJq3LeFyKViiQ X-Received: by 2002:a1c:9d02:: with SMTP id g2-v6mr10436062wme.122.1537180675379; Mon, 17 Sep 2018 03:37:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180675; cv=none; d=google.com; s=arc-20160816; b=w0yR9SbPhPEBBMPcdA+4sXSKzlluB0+G42l6GTzrHCCtnfU0koQRPDrvoamLy3uR6L pyAjavwERW0uU7D8pWIVUypzoeu0aMj0A/b1fLrFDMdFnyFuUrdraVywW9SW09ac+uba TSgt2+XctOnLy/VRPUrYJc1QozTOKWt0YDYhmB5cH/SWSltbmK9i4KlYF1YKtRpNw3qS CHXaqCrUz2o8ixqMoJ8APybZK5crrLqNYL3ysmeUfvj6CPlDv7mloIP5yfSE5i+8YlrY H6wCMl8aNMCXTda2UbkH+24xSviPPuLkye+SMxD/0cYcfBt6mc8h02ygsRKrk+CRArHg K4pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=QQKvPT6RlMt5xy+nZMqgY8XWnFSu6xuQQSk68qwvrdI=; b=sF+gnnGDt7jDhpgArOs9PHrKD7D1QPVUWXifU6urEewA53tbdM3JaXitO9b2nMRwsI I43hY4cCTg37+Yc11OUyLEIgwgH7elhmKF25dzSVjy80xEgSjj/25AiK8L6OIi+JKs/r 6rTV7fphAxPYNFnGf5dKuVVN/nKO0R6WrhKcD2AFSrE8pGIzq/y9+Haj72wWlHaZqoAC kFkWkLChoT6oSzUOZmzH8f6rddQsWoJO4BvlT1/lvup51DIv7JtdbjQGMfyjvwvVcx/3 XBia4QC1Ojc5pA+xprabI6CVrrXjrNH/5tqB4D934DkJrWHwDqPDwybzYhV3Ujk0ItsA 19Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=aaIpK5ro; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id e144-v6si6494378wme.57.2018.09.17.03.37.55; Mon, 17 Sep 2018 03:37:55 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=aaIpK5ro; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4CB424F90; Mon, 17 Sep 2018 12:37:51 +0200 (CEST) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0048.outbound.protection.outlook.com [104.47.1.48]) by dpdk.org (Postfix) with ESMTP id A26A811A4 for ; Mon, 17 Sep 2018 12:37:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QQKvPT6RlMt5xy+nZMqgY8XWnFSu6xuQQSk68qwvrdI=; b=aaIpK5rovLp/ruGkSurFjLFTem/3pQlj90qzPGeKMUub4bwTBkrp2jKxL8xsdeQcLqincyDJ6Twd6mtOR3gIZTNKIHYs1clQO+jzGYdE+SWfBemA3Tfd6Ye7R76buSUmD1zZM75Q16Ykm3MHUhFViGSTFG03ejup/7vRMTFb7VQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:46 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Hemant Agrawal Date: Mon, 17 Sep 2018 16:06:21 +0530 Message-Id: <20180917103631.32304-2-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5d303685-9330-4624-b618-08d61c899c3e X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:uc/dScj9FX3lB+s448E1UX8vwXTYHgkkEVEpEQZY8HBu9zr0AS5TXLa0ltYxXuC0dFX8pnVGfiXLGktrdXFJYJMuSHQwzC3mxlot4/grW243aBnp8mIbxRkKngFhgj/Qx+vnI4S1zWCBNK/lN9P7P5cPw5c1kX0wYNXyx/PzuU5F+GxZG4yPasE+N5odEFqnQzrQlhaZ/umkl6r262w6hMAou8Ci6bzfM2UrnC5HX4cCV2+r0sxEV2rc+pLxzJUV; 25:IcxDVr91t7Zy5tUX/p+buEXfp0OijVJHV2PDNJV2pZ98hSkX7SJsYAylsjZocG9D8eVgpTau5t9pOH6m2ZWo1dbvYAg+RXi8ByVk2zh2kvK9S3E4Hsbz0arC4Ae2NVAy9MfvBDDQ4Jsw7MWLAuTEnsA7D9mgkTVZFRj7qF7uQ4A/Lwxojal7aQUQGISFiCsom0R7VWTSRP4uEzvcKLSQ33N0xxYgQ2tzFSf9zUrYFeBbTr/H1gpzKm+pL+7GSstDDLoIjIrXBwfmWUALTpGqCLZl3Ipx0LTOr/QoaW4+Lq3kPnyzA5weZ+aS5VFzuy0mh5HKf6ihvDkkj0Jqsc6WMA==; 31:PZjwASTJT/xQ94QtiHdZuOq1IdvUwJ7wEC++5YdYqEZclCrvGJ8VDEQylz14S2UyleB0e4EysL7B7jxEYCZXC3a8F5GWDzRQXbrxpy2ckEhm5pP/L/G7Us+N+RwGlQME+FtWUoJzu7miqq4XUldPWmZc8qXX98MvH4cOQS+b19Mp/SrBTRFW0DuKTKN2SazSVDX96/myTE20hCneGg4YoZG1eKsoC7JWOf1KqjDM034= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:dlvaInYRtUKhrFbSKOiFMRgvgEdkOuTiRfY3R39KS25JX4aeTrdw+FzbBvHHM4S/tpUOIZe6rQ80tiKbZ8EixHwr9bE1cJpD3qV3qdMRsqyYkv6NDUigfJIwxXyjKkUtKc5Db8RELWA7fbKU6gaFXsSCFlBeC+wFL57UTQKIXpE3h2jsC4RbvmW8L4jKMArd9CxAIf0t2pqgqSjqUKldYRtzSzLSnP3KfCKiAVAFQqIxgdCLLdfpuZyPISkKH6t2zhRe/9IrnTeOCqTbWvwJW5u4Io6ERgYjH8JQ1KBZjf3DAMfav79WmKc6nCBG8LTKg0pUARGbhakWaebBmFVMAPGZtI1gFqrjl/aR8It6QqCI84WyQQtF4gJYLtme/2Ql3jzhzWC25C3O9C3qXNV9xKIBea0zlx/HDCEwN1HB7k4TyFPYTtX4itiepxERom1PgS372Xr9FM5M9ka2qsWF46j7pc7JxO1mUTlw+T6HebYpkCdBxJOO+3RDOgfoA+m7; 4:umRwSOR8jEm5W1hD34mJ7pCgzG3KQ9qSfznVtFuwZBz+JiZHa0UHQsyuh/g5+x0b4VASZBOX9eBA6bxvjBbKx+oa+JANRKH1PkJPZbrJTd3r6rsbb2LpcvKnun2b804VSfwKqDYPbA3jNOAQc86Omicmb/XbwhsVRLfBraMhmxVYF5ds9MjGetT7A0lnaTVdFr83PCT8DEhG+8wrc2zQUMtpcDlBrU0wRrKN7ypfvzYy3W4TZj0aYlBuX+AKEQKZWnb1uXI0RbeGeTKcIb+cZRe61qLsi0XusXJcH6Lamba2FYXzjFYqr0NSM3QoGgp6aohzT30xJb9IOzsEv65QCxB9/FftE1GBpKiySlDrkIo= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:7bU5Ev9bjNRjmUK4LvrIPL1UdHlKq8yjw2zt+SkNE?= WEC9+Tc8V2n1Ovb+FWUx0Q6mZ2oeFWhAQsVa1LcwBBmIxk3xKCaaaFXDAjjWnYNUO8AkHvC7VP7vx2S4/J9Sg4AcjzJhbw0mnYpVXxK9pFd4Yv7jRqzOVA1RoVw1GFJ4/roE3zhKyzhVfdnxawbqNoK4A1pSZTq/PengHRFzm3OqzU5BV0TuPUF7NTO5Jrsxb0NhULMtZ9EpYOSI1aTf/SDHrItlcppIMDT4oFR9gMx9IOYKwXkRq8PIVMQ9xDvcCb4liHx/oaYxz9LO9KS8xhp5pUuOQRh6JUMdXql6z06oY2XtKSpVCliLwdulLy3JVg5BPi/fE93pVFhz7/ritFjw3Q38FKb1D3FQ2eWx6DDKTW9JsEsf+I+H+p7nfDwXZh3Va+Ushg70/KrAQwfcmCMfvqh7Di7j7FVz2GTyInbCOvax7Z812+GkuzVv7r8VAAmG3TEyhojdiXPRXXsWtr4+BDJQ7bbSaVvDEOyi1JHpYVycUT5V9Xr3hUTbG90C8fswUhCNtc0rtVksnYkecoCN6EG1vVPrsKi+0hSP/wtl9EEFIsP/kmiETOs8WMLCtCSYlbGvuVS5ynttve4aoc0jA3R5Aja7RK8E0megngEeq/S1PjHR/FmPQ7WQRensPmJI3ZWuVvGAhxUIb6KAreFwlCHl1iMfcU3Gyisyq0EogpsyxtuBM1jdWARzdP9CgnXAdIUh7UgjcZ6wMhWFjeyz36Pl6aqd6ZQo7PgCRYRbgzoL1yuayc0m2f8UrvuoAh19cpHOLcjER3QEJDlfUIm5BWASYvPuppDkDMs/AXP/Hf/DhTdsSnw8js9h9IdhUX49lYRObH5uskKNNsVNU+J1EIsCzb1rJbeKFNf0olKGvwxwxJ3t12lyGLqV/JmyWGSFhKQkYWtfm6rYi2kxvz8AeRTMevBz/ivQ/x4gfzAmw4OKsltbhtyBAMFdIzZS1OVTq2tBSJba03pXdeF1BLzAfTeRzxKp2wxlB3hSvFoE4eT1ABWqGaeDjrKk1UPNf9hBrE6XWr6q3R+1g5JIz4kf5b5dKxvRMwoLX/Cj3ALtNN2Rgil8Rl8wMgk0zmVhQBA0gMSE6AtVJynNEF60mHy+r1V/6n9uIo8e7H9215KwibzU8qQmNXCSCper4x3/2Ye48t5tXu3OJX6n6Ndne+tj1vkmWva1obzO+89c2Oh6+NcL6Uxkb6HCSa28EK64IINPM1RfsWET/ATn1htP2sz X-Microsoft-Antispam-Message-Info: t8MsOm8xnF6spnHwvsNOreGLrrhof4ybegcQEozp6n8RhUnewO5qQB51R8h1xRtPPhKytQB9XVXEDOWp4QAtRXC98KSHOjvhM9eNWX0JIJx1Xh3cQoe3W8V2mLqq7H1HBc/IdtXMKXiPmaVX4WuJs8gPjqTVFE++6X/4cr+1XT9tKZxzBPNZpOHvlbh7RP/hHoi3adEbKbEjNQvTz1p+da99S2dCMzCDXNJhNsEoOo4tm4vFH9y/PeiS8e2Z6++Z5GnlbJSVYyUthsFVZD/RHEHVZg7E+d7OvHR/TYgpvb6Sy+PgJXg4/wzGcv+jwzwaLxwiyMITnzw0hCJaaXFe324fknMzzBPp0XxFgM7xpvg= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:qQGEc4IQ/gQvw7hj5ku92BI/FSE67qHwTfqrUfeNqqOoCcAcTZMFx87tFJcV6UOPfT02LL8KblFnn6OBFOGyG6V6Kz3vWAHDJUVPe8wzHJgIkHC0+v5uancXrGObkYVVgM3fGsOpPzQyTZ5CnHBa33PKVaS8agWksqomyam0uSkpURzj9auac03FMKMXZppWEfUf91cAkqHQCKz2qa+qLHLi/8PQVgDnsuB0OnJ/aMqjGlVRjbTeRTY6q0aEtMX74RgTClhybnTepHlPjM3bfrgpKxtFqEqryo+ixZ335mUgC7s8ioZDbwaaIhLNFmAj9hZvBUUpoF2LJ5sP4oGzwMT6UmZcqaEzGSsZr87cDYgyTpvPW99auiZJVx2dqu//wUEza0E4Wj5PRM0y5ruFCbhdF43TcxdWr6DiOBEc6eoTQGdic1+YjCA1RKdAfntzvVpT79LDH/BzvM5IgJdLsw==; 5:ICMdqnk4bFt50Ioxp1At8kWw6gh8SrKhfSibsJr5QrRhgFctEe+s9aqSkZyPBj3+6vCHjkSPj7jWsHTBSE9fIqFcV85i3SN4XATNyIAcvcZozqOCwMPPJ1WCmP6YGIxZ1TSDcD0QdWlxnz120Ujtn9FGooE/rfwEHE+igw0kuGc=; 7:U9dpk6VF564uTKceWwE1sDs1PawMOobClkpt9WCgWgv0wkwa8v7qhqDGAwZJl/G6NlqPgvMWZxpyORSfadLejVtrR/yvt/4oYExX/SunUuGMwSBoyiOVLi6y/lD07WxLOIhoGI1QdOorM3MyoS98kaVQ8yaP8WbAeV404Y52HLLRW4/pdVv6tA4bHRWqU6072dByWr8LhyOCxvQf/gTixDo06j+7Dp2JopsYiU2NRVlzzytRxZG9cjP9+AoLtcl5 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:46.9612 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d303685-9330-4624-b618-08d61c899c3e X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 01/11] bus/fslmc: upgrade mc FW APIs to 10.10.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/mc/dpbp.c | 10 ++++++++++ drivers/bus/fslmc/mc/dpci.c | 25 +++++++++++++++++++++++++ drivers/bus/fslmc/mc/dpio.c | 9 +++++++++ drivers/bus/fslmc/mc/fsl_dpbp.h | 1 + drivers/bus/fslmc/mc/fsl_dpbp_cmd.h | 16 +++++++++------- drivers/bus/fslmc/mc/fsl_dpci.h | 10 +++++++++- drivers/bus/fslmc/mc/fsl_dpci_cmd.h | 4 +++- drivers/bus/fslmc/mc/fsl_dpmng.h | 2 +- 8 files changed, 67 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/mc/dpbp.c b/drivers/bus/fslmc/mc/dpbp.c index 0215d22da..d9103409c 100644 --- a/drivers/bus/fslmc/mc/dpbp.c +++ b/drivers/bus/fslmc/mc/dpbp.c @@ -248,6 +248,16 @@ int dpbp_reset(struct fsl_mc_io *mc_io, /* send command to mc*/ return mc_send_command(mc_io, &cmd); } +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ int dpbp_get_attributes(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/bus/fslmc/mc/dpci.c b/drivers/bus/fslmc/mc/dpci.c index ff366bfa9..ab5a123dc 100644 --- a/drivers/bus/fslmc/mc/dpci.c +++ b/drivers/bus/fslmc/mc/dpci.c @@ -265,6 +265,15 @@ int dpci_reset(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +/** + * dpci_get_attributes() - Retrieve DPCI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCI object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ int dpci_get_attributes(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -292,6 +301,19 @@ int dpci_get_attributes(struct fsl_mc_io *mc_io, return 0; } +/** + * dpci_set_rx_queue() - Set Rx queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPCI object + * @priority: Select the queue relative to number of + * priorities configured at DPCI creation; use + * DPCI_ALL_QUEUES to configure all Rx queues + * identically. + * @cfg: Rx queue configuration + * + * Return: '0' on Success; Error code otherwise. + */ int dpci_set_rx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, @@ -314,6 +336,9 @@ int dpci_set_rx_queue(struct fsl_mc_io *mc_io, dpci_set_field(cmd_params->dest_type, DEST_TYPE, cfg->dest_cfg.dest_type); + dpci_set_field(cmd_params->dest_type, + ORDER_PRESERVATION, + cfg->order_preservation_en); /* send command to mc*/ return mc_send_command(mc_io, &cmd); diff --git a/drivers/bus/fslmc/mc/dpio.c b/drivers/bus/fslmc/mc/dpio.c index 966277cc6..a3382ed14 100644 --- a/drivers/bus/fslmc/mc/dpio.c +++ b/drivers/bus/fslmc/mc/dpio.c @@ -268,6 +268,15 @@ int dpio_reset(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } +/** + * dpio_get_attributes() - Retrieve DPIO attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise + */ int dpio_get_attributes(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, diff --git a/drivers/bus/fslmc/mc/fsl_dpbp.h b/drivers/bus/fslmc/mc/fsl_dpbp.h index 111836261..9d405b42c 100644 --- a/drivers/bus/fslmc/mc/fsl_dpbp.h +++ b/drivers/bus/fslmc/mc/fsl_dpbp.h @@ -82,6 +82,7 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, /** * BPSCN write will attempt to allocate into a cache (coherent write) */ +#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001 int dpbp_get_api_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t *major_ver, diff --git a/drivers/bus/fslmc/mc/fsl_dpbp_cmd.h b/drivers/bus/fslmc/mc/fsl_dpbp_cmd.h index 18402cedf..55c9fc9b4 100644 --- a/drivers/bus/fslmc/mc/fsl_dpbp_cmd.h +++ b/drivers/bus/fslmc/mc/fsl_dpbp_cmd.h @@ -9,13 +9,15 @@ /* DPBP Version */ #define DPBP_VER_MAJOR 3 -#define DPBP_VER_MINOR 3 +#define DPBP_VER_MINOR 4 /* Command versioning */ #define DPBP_CMD_BASE_VERSION 1 +#define DPBP_CMD_VERSION_2 2 #define DPBP_CMD_ID_OFFSET 4 #define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION) +#define DPBP_CMD_V2(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_VERSION_2) /* Command IDs */ #define DPBP_CMDID_CLOSE DPBP_CMD(0x800) @@ -37,8 +39,8 @@ #define DPBP_CMDID_GET_IRQ_STATUS DPBP_CMD(0x016) #define DPBP_CMDID_CLEAR_IRQ_STATUS DPBP_CMD(0x017) -#define DPBP_CMDID_SET_NOTIFICATIONS DPBP_CMD(0x1b0) -#define DPBP_CMDID_GET_NOTIFICATIONS DPBP_CMD(0x1b1) +#define DPBP_CMDID_SET_NOTIFICATIONS DPBP_CMD_V2(0x1b0) +#define DPBP_CMDID_GET_NOTIFICATIONS DPBP_CMD_V2(0x1b1) #define DPBP_CMDID_GET_FREE_BUFFERS_NUM DPBP_CMD(0x1b2) @@ -68,8 +70,8 @@ struct dpbp_cmd_set_notifications { uint32_t depletion_exit; uint32_t surplus_entry; uint32_t surplus_exit; - uint16_t options; - uint16_t pad[3]; + uint32_t options; + uint16_t pad[2]; uint64_t message_ctx; uint64_t message_iova; }; @@ -79,8 +81,8 @@ struct dpbp_rsp_get_notifications { uint32_t depletion_exit; uint32_t surplus_entry; uint32_t surplus_exit; - uint16_t options; - uint16_t pad[3]; + uint32_t options; + uint16_t pad[2]; uint64_t message_ctx; uint64_t message_iova; }; diff --git a/drivers/bus/fslmc/mc/fsl_dpci.h b/drivers/bus/fslmc/mc/fsl_dpci.h index f69ed3f33..04ee93e66 100644 --- a/drivers/bus/fslmc/mc/fsl_dpci.h +++ b/drivers/bus/fslmc/mc/fsl_dpci.h @@ -17,7 +17,7 @@ struct fsl_mc_io; /** * Maximum number of Tx/Rx priorities per DPCI object */ -#define DPCI_PRIO_NUM 2 +#define DPCI_PRIO_NUM 4 /** * Indicates an invalid frame queue @@ -153,6 +153,11 @@ struct dpci_dest_cfg { */ #define DPCI_QUEUE_OPT_DEST 0x00000002 +/** + * Set the queue to hold active mode. + */ +#define DPCI_QUEUE_OPT_HOLD_ACTIVE 0x00000004 + /** * struct dpci_rx_queue_cfg - Structure representing RX queue configuration * @options: Flags representing the suggested modifications to the queue; @@ -163,11 +168,14 @@ struct dpci_dest_cfg { * 'options' * @dest_cfg: Queue destination parameters; * valid only if 'DPCI_QUEUE_OPT_DEST' is contained in 'options' + * @order_preservation_en: order preservation configuration for the rx queue + * valid only if 'DPCI_QUEUE_OPT_HOLD_ACTIVE' is contained in 'options' */ struct dpci_rx_queue_cfg { uint32_t options; uint64_t user_ctx; struct dpci_dest_cfg dest_cfg; + int order_preservation_en; }; int dpci_set_rx_queue(struct fsl_mc_io *mc_io, diff --git a/drivers/bus/fslmc/mc/fsl_dpci_cmd.h b/drivers/bus/fslmc/mc/fsl_dpci_cmd.h index 634248ac0..94e253347 100644 --- a/drivers/bus/fslmc/mc/fsl_dpci_cmd.h +++ b/drivers/bus/fslmc/mc/fsl_dpci_cmd.h @@ -8,7 +8,7 @@ /* DPCI Version */ #define DPCI_VER_MAJOR 3 -#define DPCI_VER_MINOR 3 +#define DPCI_VER_MINOR 4 #define DPCI_CMD_BASE_VERSION 1 #define DPCI_CMD_BASE_VERSION_V2 2 @@ -90,6 +90,8 @@ struct dpci_rsp_get_link_state { #define DPCI_DEST_TYPE_SHIFT 0 #define DPCI_DEST_TYPE_SIZE 4 +#define DPCI_ORDER_PRESERVATION_SHIFT 4 +#define DPCI_ORDER_PRESERVATION_SIZE 1 struct dpci_cmd_set_rx_queue { uint32_t dest_id; diff --git a/drivers/bus/fslmc/mc/fsl_dpmng.h b/drivers/bus/fslmc/mc/fsl_dpmng.h index afaf9b711..8559bef87 100644 --- a/drivers/bus/fslmc/mc/fsl_dpmng.h +++ b/drivers/bus/fslmc/mc/fsl_dpmng.h @@ -18,7 +18,7 @@ struct fsl_mc_io; * Management Complex firmware version information */ #define MC_VER_MAJOR 10 -#define MC_VER_MINOR 3 +#define MC_VER_MINOR 10 /** * struct mc_version From patchwork Mon Sep 17 10:36:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146843 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3602705ljw; Mon, 17 Sep 2018 03:38:02 -0700 (PDT) X-Google-Smtp-Source: ANB0Vdan+W9F6Y7wFXBj4VJycZwUhiJAOittY5fUEh76X7Qcd5SllGK08szWlCqFexWWR0oInplM X-Received: by 2002:a1c:700a:: with SMTP id l10-v6mr10861962wmc.90.1537180682736; Mon, 17 Sep 2018 03:38:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180682; cv=none; d=google.com; s=arc-20160816; b=Tf+awIEco+hlkgWBZyt/OVNNDF3MiBCtb6AnkGIq7B6B1nC/+AnmN9fhr/9RGtqVuG n9onPQl1/mg3dIp6f+9EL9bJ+Udc6+gc8jPbNjJvyyqVFN2JHCRs7fRgAVYNbh6diJZN iRmrgeIO0C6H3d47mUUZPw55FqD2KVdk/Y9yHZk6mgzPq8IFhgfnLRtWlxAIFwzn7jH4 xCwejbCIF/7hjcGq7YgfcflJtvMgTjkl5ywcs78q1HCmJ9hWCLYPeVUXiO8WFWdspI8+ k0zx/5jKQfz/wJUx56imeeEcJVb+5JMtYt2tRUjL1OiiFyrrH3luvIW2N/FHOpY91xIk d/LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=5355CFCriD4KFGZD/th/+GxjqwFXTENs7xFaynLry6A=; b=JPabhvoTtnhBSOORJ+BToTRbYFaeRyI0ePgoe6KfQwKuubOTM157VXRCbdmn98/C1L 1fQpJNdgE51F0PWuZBXtj0mnCMCKjGXUIVfOcvoixvh6hIt/EMhKClPLEGJCbJ81oog+ CWOqIMmjv2dopkFNEcoeP/nVAowAgtxpZ4p0oE8II2QAtZiz9nxRHkqAQNlv/DNSj4NM ngxkH0pzKr9sm8vcExckWh0MKX1PmQr4zQDT/22V5zxnZxOxnzQXkcw5BiWXkGIuzRm1 x8A0lzajd/u174uWQwrVPe0udCw4yVB6zSc4NRX9F2uvA6T5io8s6M+O6lawxqBXJuyw Ni7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=SluqrbV4; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id r17-v6si6778630wmg.84.2018.09.17.03.38.02; Mon, 17 Sep 2018 03:38:02 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=SluqrbV4; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9EE845323; Mon, 17 Sep 2018 12:37:53 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40078.outbound.protection.outlook.com [40.107.4.78]) by dpdk.org (Postfix) with ESMTP id C18F13772 for ; Mon, 17 Sep 2018 12:37:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5355CFCriD4KFGZD/th/+GxjqwFXTENs7xFaynLry6A=; b=SluqrbV4dGBEQlnFod040YGRkiooO/vphWNTv6YFb39Q62azVE/73Y41/0lh2jUoD4sQ14TlBLxOZ8Z17P3VM8xQbzcBiCUA/VZdsB6RyQJd8xP+94Tlpstcs6AKUKdVMmOwJHaPulxkuZHEw0tdV6URhufzXaYi4TvgzWC30es= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:48 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Hemant Agrawal Date: Mon, 17 Sep 2018 16:06:22 +0530 Message-Id: <20180917103631.32304-3-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bf9f8b22-c2c9-4af8-fd13-08d61c899ce7 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:ziJFTvk7bHbxyUrnkkZ1RzWEWIJYuHdlDVcSWyFCn7hlJYxYvXsvS5FVmJwN6FKlS+WRur0Gtt74Qvm+O6tmNCFu6Q1fUytJ0aRzCvj4AtToBx6/IMZf81n09LfBZjcl3GsCu2Q1nXqug9pr5PV/GU+VlZ1aN1THtT09SH9X6zKKObrfQNPfxRhOpY9aTJH5/PlvHeP6X+ilIP7/L7PFei+t2TPzePEMmymC9mjHKKWJOCY1V9kNXby9wKVQWhbc; 25:vmT5ZSRHxKQPWMlCPhas3gnKj1VgJ3gkdiCgrxKP8lp+XoFfqm+52+htpH1oanrZzC5McJQru9Os8kYIMUVTVchuexP/X1Yj1p6RByT0iYwJCANuqLwUj2A5fj8d7+thZQeNQQ2w9L/g+mogYFHKcEXEv7sXAZPs0PS0X9M8z/e8ynNiUE2wlzKTKXx+0dddA7FiCFN+KWqniJWpN1S20jof/YIhZ3KEFheQtw3brqmAlmVkSHbGccSkfaSyrsA5wb0Le7kOsesTHRMzk9dly0uMOqyrbSBD4pHRKXMslVtm8X2VdSLoa5AoCrsXR9wHd7lUUxeJezYdHq2iiQi9zg==; 31:tpACQCScQ2qiWRjr1aquDVnF7/othTJ+Ihhd4ZfiaIUjvYP/ziqn7q7tSdAYldoDbSR41Yxligo3T5LpXpKYkmHSnWU9KEsWamI/s3dznmFrxHxZYKDlkp1xTMODBMvWWcE4X3WnZGE/nwgQGp9cerN3Md2VbztfQp1lioh0jE25aTS54UcRT98sGYswOcFz4Kmw/vWdRxc9yxertFafr3zhS/LsOKmPUHOneqnkK8g= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:VCb2kPnSdkxi4DZ3KLkw24iuoLXVuVErmbD4M9Btc3RrbH2q3X9XW2Xd3UW0Ylo2Wx0YTqZOCDa2lRKYrV46efQvk7tMs53sapNLvkKB1n0AlW3EhMDtHFdTwbKINCX8OOHo6buDbxjq/BFUfKpkc34niB4//MshnwBcat0eGi4/idXa50+M8ifNSrk1hel+AEKStAYtIj7F11d4N1Ow8IDaaZrMvuaZmgrlfwEpDm79o976Cce7+PnxPm6jJ26q+c/iyDvW3BPEr4ssk8cxwBs6SznnqOo0b/L4Nclzhl2JfLQfe8t+i8eQf+GSYVhal7hpEt7jEdNxZ4K1XB7y+bD45FA6OIqTZE0IuGR1Z3GRbOGJuztdKj3TxYuBugAYWnQ549xzyJ5yuaBiRBptmBK1SxTvuKzOgfSVIi7uf/bikh+p+qQNz5EzOlv8nPPMHW4vPYyHCVPFtxr5srkF2nNfW9mUGk0spnqmo3fJ39eSG40Cyi4/0JNcHRCwUmio; 4:gPjsaUBZXnYPK8VHEi5pQHWdERHq/641DDk+63jj0lSjQkjO29uWvuQamoZvBRpCRi7VnIjs613gvmijjLarbrSq4Ljx23djuqElQkbY22BbckILoNW94LsdZigUFUXXQRJ2uInMzf6xYCLTIfcM1AEKUxyU2l/Hk5bG6AcTyzyIxXwFROIpTEUYIVYIYGhu+95Wwu1n2sB12LpzWO938wqzid4CSBaT/VXWtAv9FNDjAyvvW1HMyq7zQJ4FRHdPq4UBaoUqe1zF2zW3srGKHGIZ1Z0hcti9hiomBrHBdyqFxhY3Od1EO3mQz6CYezLfjGVm4xJlHdq+eyUx81+hYsJ5bHuxoNods2V/VxytlWY= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(575784001)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:IP2IixaVIHRKAFJMS8uqvSxLBahGKT9y/paq925/W?= 1trTwTWibz2xyehbwlJuRow52wSO2WsSTxSJUr6Yj1ifmF+VJyr5Clo6SPZlKCUswK8lslOta2KWNas3giw1hizLYJMqyVZoniUZc9tXujXuXOg/aACtKneD6CyzMsxgWBeuBa6+qGCwxjQB9dlnNsdWQ8aZTRq5jCilMoIgCPOwU4mGOij4nihrIsD8Qzdc3ThiW8fHq/3Z1qacMagsF/udfaDWAvwD8T1mZ+psf3QJxZbcj8I6B5luCCaX7We8/vHZguzPH8oSaTbnlp1rz7IhNznnI47VQAlv31C1wiVeFWAGsOA3ImWnREZq1PEEIsGHbIySd0QUqgSFcDY/Vt2O4RLkBEu7UltDTBz3FcS4YQcv+nFAff1yIQcepYjcrwa4aeUeEYb9rGC5C1eM5SD9Vi2I8InhgkWDGmAyeS+JbvnzLV4Q++eD34JWj6iVnwaFTABhPHGmRP01xsTclnFTN4l3diGpkOgjvdG8BDYN/TIsEpRaquVtiu9xP8IbZtKng+xDyl3DFiBJ2M1w3mF0J1SOK1Mu8mO62irh/Ag1D0OPjM2ijsAAOmo78i/Zl5pXOQczePBUiaCQBnejeybBrKWFwHYDlEz8sohZjPx7bAYc4ejj9LewBq7ZDVqOCNdWcPbXNh4zx2e81+9xj6l24sA7M96uo8Jjj/P9Pmavzn2AKQ+SgzV/t2t2Fmc7usoVMcxQWdJwiCFMRzttLBovIRzLnuTBiXDCHgJks3ZWdtEo68bW1UwDnN0rLZPc4I9mbt/FRL7K6OgVgA/4maJ7Yi6FyIpCm2p7EIWRcr9n3yLPiTJv5XPK+eE/qCPh+RzHsiJdLWizXyfBTUXbUjFHQMMhLyQ8Q1fLHrpm5ZAr1NFtWTttrzDkwBVu9nizjUglDZSLKGj/+95Phzdpoo0JKqXqfQFvA21C1IevcnQfOVnu58tGetrGcv4ewzu3avusK9vEfqVU7PU7M5coTgxLWJqXY1icDTlMpbQI7TwTgciY2cwFc7wecPhUR52+l+9HG4JJxvJu3D9HHAzgF83l1NnDCCpCxZoUxNmQruN/ykvtA4xQbf9JsEOW1kTd7Qn5XEbr8l7w6AOzKaqdimSriqiBxCWiPUd+54Cxr7F84udDTIXg44++ZralXAHquBIj7x9rNH2S5SAtWmcTlTiyVyELVUv0ICkJruYaM0WWbhSZzG7T91HE5sB4YQLK9KJqmpd8cngCKrvYVrtXScu31TyuqGqnEwmy8lXDiNRRg== X-Microsoft-Antispam-Message-Info: K2GEJxMB8nReQWu+Ub7wdhYLz7GV9TODYneBGZ1T/3vonzToajYzqod9I7DpsR+DUA1joaYH8E+AYRy03wdaaSn0rQSmVyjS9RzTG0q9piSOKlZh/Ip9bdHjQdNaElh9qbunNwoq6lq+PW2HPu5SbUaUYSNtAfNP1iWFCQbnRNn3orZi034r80m3YldFgZH9LlmaA1qC9i1o3zz9KqnXmBxqjGnbIzPqN0FGNyfMKcqROQ5V7VETlNz2uF7/BZeVU8xgdN+4pyLEO10mspBNnL7EITf1A+yhr3RJiTs9Knnshtymk+Fc3wXyU8wvX2Ekm/i9EYshDngEi/YM5J9G+P6BPRaY+rKUb4QhpIB1rfQ= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:0Rws0SWe+8MHTIHG6rxPmy/p24LnZd9V6Ph6FwwwJa1NzJWWtJico/Of73itDlNtv9T3BDSdL4T8qJhzD3o1p85emgjlc0iwkGLyKjkChxCTvmn3jF45yhg2tKzA6Djvrxkj+PJVf3ZcnwdiGn7sIP7Llzio7yGtOOmTki2lrwY9Esg8yvseagG1aXkyHcCfiEnqDiEjV3zFHgLkjktFgmQUQMJQe7QeZgIMERJvE2KgFptqAegKl7V0P8qbrNXngIUs/Prb2UEGB8/YnZBV1TBZuXR9pvHX0sKXzy0HPpaTTnZX2VHZcuQ0bpEK+yFWRyKSgZ2XQRVqgNwbYzH2GNtnNFLXB7dCzB5FH4GNXeb52tHiikwIkgppEbpoLEjdKlzTfEkDfmOGGFe9JDpQqbPDBk+t3jhLaeA+4AfA1reK+py0JgopkcTduwZVhstbnSb8B79d7MCnVJJo/jN7Aw==; 5:IwCoeB58yEDGlM+BLOWIAl6WWWgKegn0cWAvG/7ukrRNdylKJFIbh+30i2gO7bOEUyotXkmf4SE61uKoJ1eFPfG+SSDmd/yPDe1Mhj3wPkcI5Q1GXYN8FlQJnJzn2viDaDRQbKLxzBMFi1QuSxXyEvmIPPtYKiDhp1TvNpU3tkY=; 7:EyJ0mqMEmYin7n5Php8Ubqg7/R3pTzY7f7jDX6lXfJ775sOHkIv4LFHxEUnFKtk+VUmEJf9QaKB8qTlqQfBwlOTY4U4aKoYnBISBtzYow+vF6bcIEyvwWpLy60nDITQhL0ijLg+lmUlBGs/FqQn6O5foxSqmrnpp1+UiDEjCVyAu7l2kF8L5p0Nv1WRU1jtWRJV4Yhbw+inxa8sCU+u9H0+ao4664BQYO0CNIZ71xOYbeRYEm99KV7H5+WfElIIp SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:48.0706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf9f8b22-c2c9-4af8-fd13-08d61c899ce7 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 02/11] bus/fslmc: upgrade qdma mc FW APIs to 10.10.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/mc/dpdmai.c | 14 ++++++++++++++ drivers/bus/fslmc/mc/fsl_dpdmai.h | 5 +++++ drivers/bus/fslmc/mc/fsl_dpdmai_cmd.h | 21 +++++++++++++-------- drivers/raw/dpaa2_qdma/dpaa2_qdma.c | 14 +++++++------- drivers/raw/dpaa2_qdma/dpaa2_qdma.h | 6 ++++-- 5 files changed, 43 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/mc/dpdmai.c b/drivers/bus/fslmc/mc/dpdmai.c index 528889df3..dcb9d516a 100644 --- a/drivers/bus/fslmc/mc/dpdmai.c +++ b/drivers/bus/fslmc/mc/dpdmai.c @@ -113,6 +113,7 @@ int dpdmai_create(struct fsl_mc_io *mc_io, cmd_flags, dprc_token); cmd_params = (struct dpdmai_cmd_create *)cmd.params; + cmd_params->num_queues = cfg->num_queues; cmd_params->priorities[0] = cfg->priorities[0]; cmd_params->priorities[1] = cfg->priorities[1]; @@ -297,6 +298,7 @@ int dpdmai_get_attributes(struct fsl_mc_io *mc_io, rsp_params = (struct dpdmai_rsp_get_attr *)cmd.params; attr->id = le32_to_cpu(rsp_params->id); attr->num_of_priorities = rsp_params->num_of_priorities; + attr->num_of_queues = rsp_params->num_of_queues; return 0; } @@ -306,6 +308,8 @@ int dpdmai_get_attributes(struct fsl_mc_io *mc_io, * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPDMAI object + * @queue_idx: Rx queue index. Accepted values are form 0 to num_queues + * parameter provided in dpdmai_create * @priority: Select the queue relative to number of * priorities configured at DPDMAI creation; use * DPDMAI_ALL_QUEUES to configure all Rx queues @@ -317,6 +321,7 @@ int dpdmai_get_attributes(struct fsl_mc_io *mc_io, int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, const struct dpdmai_rx_queue_cfg *cfg) { @@ -331,6 +336,7 @@ int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id); cmd_params->dest_priority = cfg->dest_cfg.priority; cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx); cmd_params->options = cpu_to_le32(cfg->options); dpdmai_set_field(cmd_params->dest_type, @@ -346,6 +352,8 @@ int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPDMAI object + * @queue_idx: Rx queue index. Accepted values are form 0 to num_queues + * parameter provided in dpdmai_create * @priority: Select the queue relative to number of * priorities configured at DPDMAI creation * @attr: Returned Rx queue attributes @@ -355,6 +363,7 @@ int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, struct dpdmai_rx_queue_attr *attr) { @@ -369,6 +378,7 @@ int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, token); cmd_params = (struct dpdmai_cmd_get_queue *)cmd.params; cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -392,6 +402,8 @@ int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPDMAI object + * @queue_idx: Tx queue index. Accepted values are form 0 to num_queues + * parameter provided in dpdmai_create * @priority: Select the queue relative to number of * priorities configured at DPDMAI creation * @attr: Returned Tx queue attributes @@ -401,6 +413,7 @@ int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, struct dpdmai_tx_queue_attr *attr) { @@ -415,6 +428,7 @@ int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, token); cmd_params = (struct dpdmai_cmd_get_queue *)cmd.params; cmd_params->priority = priority; + cmd_params->queue_idx = queue_idx; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); diff --git a/drivers/bus/fslmc/mc/fsl_dpdmai.h b/drivers/bus/fslmc/mc/fsl_dpdmai.h index 03e46ec14..40469cc13 100644 --- a/drivers/bus/fslmc/mc/fsl_dpdmai.h +++ b/drivers/bus/fslmc/mc/fsl_dpdmai.h @@ -39,6 +39,7 @@ int dpdmai_close(struct fsl_mc_io *mc_io, * should be configured with 0 */ struct dpdmai_cfg { + uint8_t num_queues; uint8_t priorities[DPDMAI_PRIO_NUM]; }; @@ -78,6 +79,7 @@ int dpdmai_reset(struct fsl_mc_io *mc_io, struct dpdmai_attr { int id; uint8_t num_of_priorities; + uint8_t num_of_queues; }; int dpdmai_get_attributes(struct fsl_mc_io *mc_io, @@ -149,6 +151,7 @@ struct dpdmai_rx_queue_cfg { int dpdmai_set_rx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, const struct dpdmai_rx_queue_cfg *cfg); @@ -168,6 +171,7 @@ struct dpdmai_rx_queue_attr { int dpdmai_get_rx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, struct dpdmai_rx_queue_attr *attr); @@ -183,6 +187,7 @@ struct dpdmai_tx_queue_attr { int dpdmai_get_tx_queue(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, + uint8_t queue_idx, uint8_t priority, struct dpdmai_tx_queue_attr *attr); diff --git a/drivers/bus/fslmc/mc/fsl_dpdmai_cmd.h b/drivers/bus/fslmc/mc/fsl_dpdmai_cmd.h index 618e19eae..6c3602c1c 100644 --- a/drivers/bus/fslmc/mc/fsl_dpdmai_cmd.h +++ b/drivers/bus/fslmc/mc/fsl_dpdmai_cmd.h @@ -7,30 +7,33 @@ /* DPDMAI Version */ #define DPDMAI_VER_MAJOR 3 -#define DPDMAI_VER_MINOR 2 +#define DPDMAI_VER_MINOR 3 /* Command versioning */ #define DPDMAI_CMD_BASE_VERSION 1 +#define DPDMAI_CMD_VERSION_2 2 #define DPDMAI_CMD_ID_OFFSET 4 #define DPDMAI_CMD(id) ((id << DPDMAI_CMD_ID_OFFSET) | DPDMAI_CMD_BASE_VERSION) +#define DPDMAI_CMD_V2(id) ((id << DPDMAI_CMD_ID_OFFSET) | \ + DPDMAI_CMD_VERSION_2) /* Command IDs */ #define DPDMAI_CMDID_CLOSE DPDMAI_CMD(0x800) #define DPDMAI_CMDID_OPEN DPDMAI_CMD(0x80E) -#define DPDMAI_CMDID_CREATE DPDMAI_CMD(0x90E) +#define DPDMAI_CMDID_CREATE DPDMAI_CMD_V2(0x90E) #define DPDMAI_CMDID_DESTROY DPDMAI_CMD(0x98E) #define DPDMAI_CMDID_GET_API_VERSION DPDMAI_CMD(0xa0E) #define DPDMAI_CMDID_ENABLE DPDMAI_CMD(0x002) #define DPDMAI_CMDID_DISABLE DPDMAI_CMD(0x003) -#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMD(0x004) +#define DPDMAI_CMDID_GET_ATTR DPDMAI_CMD_V2(0x004) #define DPDMAI_CMDID_RESET DPDMAI_CMD(0x005) #define DPDMAI_CMDID_IS_ENABLED DPDMAI_CMD(0x006) -#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMD(0x1A0) -#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMD(0x1A1) -#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMD(0x1A2) +#define DPDMAI_CMDID_SET_RX_QUEUE DPDMAI_CMD_V2(0x1A0) +#define DPDMAI_CMDID_GET_RX_QUEUE DPDMAI_CMD_V2(0x1A1) +#define DPDMAI_CMDID_GET_TX_QUEUE DPDMAI_CMD_V2(0x1A2) /* Macros for accessing command fields smaller than 1byte */ #define DPDMAI_MASK(field) \ @@ -47,7 +50,7 @@ struct dpdmai_cmd_open { }; struct dpdmai_cmd_create { - uint8_t pad; + uint8_t num_queues; uint8_t priorities[2]; }; @@ -66,6 +69,7 @@ struct dpdmai_rsp_is_enabled { struct dpdmai_rsp_get_attr { uint32_t id; uint8_t num_of_priorities; + uint8_t num_of_queues; }; #define DPDMAI_DEST_TYPE_SHIFT 0 @@ -77,7 +81,7 @@ struct dpdmai_cmd_set_rx_queue { uint8_t priority; /* from LSB: dest_type:4 */ uint8_t dest_type; - uint8_t pad; + uint8_t queue_idx; uint64_t user_ctx; uint32_t options; }; @@ -85,6 +89,7 @@ struct dpdmai_cmd_set_rx_queue { struct dpdmai_cmd_get_queue { uint8_t pad[5]; uint8_t priority; + uint8_t queue_idx; }; struct dpdmai_rsp_get_rx_queue { diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c index 2787d3028..44503331e 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.c +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.c @@ -805,7 +805,7 @@ dpaa2_dpdmai_dev_uninit(struct rte_rawdev *rawdev) DPAA2_QDMA_ERR("dmdmai disable failed"); /* Set up the DQRR storage for Rx */ - for (i = 0; i < DPDMAI_PRIO_NUM; i++) { + for (i = 0; i < dpdmai_dev->num_queues; i++) { struct dpaa2_queue *rxq = &(dpdmai_dev->rx_queue[i]); if (rxq->q_storage) { @@ -856,17 +856,17 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) ret); goto init_err; } - dpdmai_dev->num_queues = attr.num_of_priorities; + dpdmai_dev->num_queues = attr.num_of_queues; /* Set up Rx Queues */ - for (i = 0; i < attr.num_of_priorities; i++) { + for (i = 0; i < dpdmai_dev->num_queues; i++) { struct dpaa2_queue *rxq; memset(&rx_queue_cfg, 0, sizeof(struct dpdmai_rx_queue_cfg)); ret = dpdmai_set_rx_queue(&dpdmai_dev->dpdmai, CMD_PRI_LOW, dpdmai_dev->token, - i, &rx_queue_cfg); + i, 0, &rx_queue_cfg); if (ret) { DPAA2_QDMA_ERR("Setting Rx queue failed with err: %d", ret); @@ -893,9 +893,9 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) } /* Get Rx and Tx queues FQID's */ - for (i = 0; i < DPDMAI_PRIO_NUM; i++) { + for (i = 0; i < dpdmai_dev->num_queues; i++) { ret = dpdmai_get_rx_queue(&dpdmai_dev->dpdmai, CMD_PRI_LOW, - dpdmai_dev->token, i, &rx_attr); + dpdmai_dev->token, i, 0, &rx_attr); if (ret) { DPAA2_QDMA_ERR("Reading device failed with err: %d", ret); @@ -904,7 +904,7 @@ dpaa2_dpdmai_dev_init(struct rte_rawdev *rawdev, int dpdmai_id) dpdmai_dev->rx_queue[i].fqid = rx_attr.fqid; ret = dpdmai_get_tx_queue(&dpdmai_dev->dpdmai, CMD_PRI_LOW, - dpdmai_dev->token, i, &tx_attr); + dpdmai_dev->token, i, 0, &tx_attr); if (ret) { DPAA2_QDMA_ERR("Reading device failed with err: %d", ret); diff --git a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h b/drivers/raw/dpaa2_qdma/dpaa2_qdma.h index c6a057806..0cbe90255 100644 --- a/drivers/raw/dpaa2_qdma/dpaa2_qdma.h +++ b/drivers/raw/dpaa2_qdma/dpaa2_qdma.h @@ -11,6 +11,8 @@ struct qdma_io_meta; #define DPAA2_QDMA_MAX_FLE 3 #define DPAA2_QDMA_MAX_SDD 2 +#define DPAA2_DPDMAI_MAX_QUEUES 8 + /** FLE pool size: 3 Frame list + 2 source/destination descriptor */ #define QDMA_FLE_POOL_SIZE (sizeof(struct qdma_io_meta) + \ sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \ @@ -142,9 +144,9 @@ struct dpaa2_dpdmai_dev { /** Number of queue in this DPDMAI device */ uint8_t num_queues; /** RX queues */ - struct dpaa2_queue rx_queue[DPDMAI_PRIO_NUM]; + struct dpaa2_queue rx_queue[DPAA2_DPDMAI_MAX_QUEUES]; /** TX queues */ - struct dpaa2_queue tx_queue[DPDMAI_PRIO_NUM]; + struct dpaa2_queue tx_queue[DPAA2_DPDMAI_MAX_QUEUES]; }; #endif /* __DPAA2_QDMA_H__ */ From patchwork Mon Sep 17 10:36:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146844 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3602886ljw; Mon, 17 Sep 2018 03:38:15 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbZsY/QjVE2WXaRk+fcRS/cANsbuvt8h6Khsqconl9nrpfo6Xer6r43D2NhNQVdowNBk5qH X-Received: by 2002:a50:9feb:: with SMTP id c98-v6mr41079625edf.130.1537180695821; Mon, 17 Sep 2018 03:38:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180695; cv=none; d=google.com; s=arc-20160816; b=qxhaHBrr5SOMQpL+ly7oNjaSWP4G1VfYr/h0ttA5R2vGW6ALun0+GRBIu9Krk7HFXC Pq0HbbQTupZk3kOEk/WPn6dhniY9/nEjJtKIcUl0+hWA+ElcVUoy4HXggB9MxeETOKnB y3e/WqCNxPf6SHEXefJ6Lh0MGmyynBpUCoix/PhobtAuuPOUGiUqNheXWXA0MyQH3wTj YTftDviUQ/QDfE22WmukxIQgFK6wgMvJC1G1YJyH6ehH724iGo1D9e2ySKPXr14ZnEoi Gy6AQCBP1iQRUmjv6v/aXhJKpyg27r2p384VwOWrgH4Pwa4LG+PZTVzGp6i0MMN7yqFg SR7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=OgfsEgpUDou0TCT/7NURysbm/Wpe+bXIhRmutQ3oqtc=; b=YWhEHlv1dQ3VMv7YiPPxIhvBWMTxLnEkdL38TUsSNKNlpYWhb6hU8+M2q/daMyBqpT tb5SCsRlQQ0vs/x73aYDcV3fGCozPvFNteQmVB4hDQusFG1DztmZPH4KLyKKqTzvlGVY /dW3ou81GW5QuxU9LimChPzhw2NcWHg80sIrVxS7MGjjyLdfM7H8YM4DkJZXue2LKoEr /U9tskH7Uvsnj8dn3T3+wfw6VGn6oGJlFmssYRfEvrfcIC3JdQnVCQa3xqcQFsrgwJxi puRQIi3astAtBTa9U7Y4fD6zj8FB/4L6PEPKtiyUEKmizuS4DWgtL2olKvFL4wgMFNaC x55Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=UXASZQIM; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id a14si1454537edx.401.2018.09.17.03.38.15; Mon, 17 Sep 2018 03:38:15 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=UXASZQIM; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D86E458CB; Mon, 17 Sep 2018 12:37:55 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40067.outbound.protection.outlook.com [40.107.4.67]) by dpdk.org (Postfix) with ESMTP id 599424F93 for ; Mon, 17 Sep 2018 12:37:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OgfsEgpUDou0TCT/7NURysbm/Wpe+bXIhRmutQ3oqtc=; b=UXASZQIMPFCJWG+LtXTNRgt5okGnUPtWH87jDxC/yd1U31R0kNvoGL+rwHH7GMwaPet0zRSfQHP/Qp4hXb7Fx5liljmkE20y5ps/3MuAnxQxQ7o1Jd4bgx17LgNCYiNAjNEBM2DRe9JN0JdNQAVZDluEJz16iQSJ9yyjsPCo+9w= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:49 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Hemant Agrawal Date: Mon, 17 Sep 2018 16:06:23 +0530 Message-Id: <20180917103631.32304-4-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 952cec03-8ee5-4e46-a676-08d61c899d93 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:UQJuwnWlUS3KBV+Xyosy9lSJJfNWyecqOICPPz5NAy6+3d81CEUkQMicaXrBFzjwY3B460KtdA5bU/iQ7J/LHQH51SjqRNKM57SfLZ6DK+wIJbrFAs0Tfu8n+nTRWzAjolm+5ePsz59XVPnNjj5HiUcDydr2D1F9TuqBW1ZIq2aHKX5iwsWvp6q7X3HRBf7xckB8xlbiFoDOqk4CyqCEPwLf+qyZIHMK7lK8H+X+C5xEo1+2/Weo54ZaDl2DV4Kq; 25:3vXpx7Ed/pGyEmkqeV+WYpFsXTf11kUPhZoJLcJNVDiDVV9LM8Em8/hBXllJ99lIq2PAP9rdL8M0wgbjWA9dKOYqNqKBjQIf8aoSrlH4BJfIsmme74zRwE7BUpUhktx/yzZpAkk+pVagaz3Upipm59Ty/d66Af/Kk4UJQSifWpe0N03EO4678EVlhd7yHKI1XlDvltYyVfZta6S+5rrUROOJdVFaREKEm8f++6WKp9jJzihy8YVelLUH2Xm1ARKwOCBTadbNpZk52udm8gtMaCWLArsjp/xJ3hEYpUPN8QfneC3FhWzeGRAlFMznvX2/5uLyM7uerX1c9INQiJSRTg==; 31:Uk+7DuctcQ61epeb90FUPdFrwM9TheW782KmR8PwfQyf4FYNgVPwUZ4ItXdvwIO2yjQ2ozQES3CcQqHPHJKCvU0+igOKlntPt24BaBs9AdBGdEV5N4HWjNyVrL7b5JL/3zD3POhGrnEi29LndH7FCbQPwt0v8uLcsGcRY0Pr+us8A41ef8UtJzBcNtmPCyWDA/3V4UERquXkBvX0uY6DsChwA0AXT/S567/3sy0bpig= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:aZ4Bvs0qh9ji6NNyKT67KPk2V5eC4nZbPFVPsRBwlupoPBol4z/up5s8jB4Q1NuwXFO8QM+iX6TTV0sdnBkpgqKYoNfU9jBKHaPMrnsV0/EcG5DmHiRlETQs+TNDclRP7aU0UFObfvP3ygDlnBg1XbQVignFOcrpjNQdWqyuI6U2/owFp+zuCarv+5FB64Dym2BaRpcdcBoj3AqxGLmFqWlYzHuzgTgG/7JhVBDIYT0iIIDHd1iLD+9p4rGo0ihB8ciWQhqQFnKlMDEVIz84Nk9eukux2W9yTYrPC86VzbiB66vFdHiiup2N9u4Mn+nEgXiOJ3bR5+l7CPLy3eI9Kez/FQuf2Gwe/QAhnrb9YahoGtP3kwST+H8R37Si4Sxx7YhrX8IpyTvHBuMj3//c5Gd+w2jgtIZ6ocI9ir9k2A2bGwla8UgjAh12F5AZJcjaTCYwu/kBiwGJtxZY6dWmA2Ol5gn3rpB3qQ2FLzQW/oIK58GUE2jSG8JLdsxy8zXC; 4:rWWOdgcfqRXPZFUrVDUvEmNwshPtvzSjftCCW81et5HJenF/Bo8dIQSvEAdnTDM/U31Wk7LV+zAJyg2Xr989o8JPrTwlllH2uLOim9WW4WuGZWoHaOLorIKjpAL2UvtAZySoiWpNiiBwRET+BeJitPyggb5LMRt34EjwIFkDkWXswABQtoFUwWR+w4iJUceKBcOkUpzS2nanlHldMDcaVZYvltkdtxrDamnQvZl6dDFMwti8sIUHAGuutosqcH/saHNzz7BJdSyG/MlE4gOXjgGyF6YGGxHRGE276ulhdMXAubzDTzhan/5+xGdPXiBES2YOMdBEcxHh449bt/egFVuiBrPVpeBfAv0zIgE5RmI= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(103651359005742); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(53946003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(575784001)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:XUrOROCXh7CRAiIsw3Guq5a0eNIDzpD1oLB3/ZrkX?= gE97j6mlUrmYvZF1YOGAyxHVfTfbm4wCXkIx4+PRHoL5Rl5GzqLj19JZ8DRxZv35u5Zy0LAcQgD4JPyRHCvT22iKcfmN9i0vaNLtIvpG5U7SHPfRq3DrcZX5/J4YVJuejnKwCgIz/2DVMth/7XXCqiLSUZ8893rBgKmltuMT1+taYYDePDwmOzzq59ki/MRfP0vsjcBugFcPIn0UK93eU4gLs9yTkLwLXV53VZis2dxfVCISllhHHHRh/62EWQK7vk/2J4EOQeoutOBr6C+LROXeJcTooadGw7QoUCIxp4R4jMUfm/sYtfANcSdX0k5nDld5vfOKsRdEfKUaalbIy8BVhyE0XhyD7d1Ec1TG+Ezu2WpIb4Pjh/3oQRRiHZcclVrI4yMQ+DV58Z5TpuVVSa92UzKR7UfTv0q6pdcqV+SZ3mylo0hPODyD88AbdyyOE/5CNilNyKkwpnIK9TmrnqAC0SzUkvat4H+9zlAlTYMk4wFVSmbiqnnOIfXWyuFNKqrta6grObYnOlrgjyBroC1ypmk+oKmNNDfnX7Ud5iGPeFsPZvbwsNbk0ZmxNK2lPlx/eoNFREpeLLONrxXiqB4YLSIbq39OyR7tsxCa1TKXeRCSB/uvX5CfOqdW/k0wcdBc9rklK92bKNlkkSp+KaOOTUNqAGo3SW1+qU2F4w2JkhYv6Zh6C9lbsZpO0pAxYPJENFVj4aXSOJDkc8YYoF+1H82ECk81IqzfpvJLo5e3KONXslGTPFb91K12/ye1PPTqLIkAL5I3FVEq2k4XuO76RLvd5ujmSn2s8UzIi3yqA6fZptMWDwrKEQjuwOYvX84Yuvvec3+bYjDbJNvNrO79wjeWbRHzLmQpejFIbu7n64/jEDf/6qn/ScxpXJ1/p0NgWtMRunc8Ku/+wX9XXUYi6/q6bWHpD8Wgky3mmQdXMFxyhGGJIjU/lmqw9v9JRCE9COzmc3xDDwC6jZa3FWTV/+fYBwicQtkDgdv17usJXSOxh5yiC3krrc1YryTKVLkoQsyj5NQZjpqkC0CZ2IJg9sizU30vdWwQLxzkcnI7jkWqJMFR3KaPZNv4Zw/DXXqbBOYci3/GtRDk0bEBCN9qVzA4iGNb8Ks7LhvsbUDw8GfUkGRrnsPaj7SVHxbmiFXKb9Ox/ypM/wG8aFukfoBRVfuwKnfQrSCKnte7Zovco3BdPqxL9R7ct9Ry3uwy18pF4PHzZ08f68TGwwNzU9QtZHeGxRmcA8CCwZ0G4HRtDcdwKkWPF1GT2aMeZHG6Ww= X-Microsoft-Antispam-Message-Info: xM+GYJPy32BW6G4r9T8jUjeKw+D9RDuJhhssDnPVPCuFyfeTTF0BULrNxH9Khp1KkVtbgEe1JnWibo+1mM6Ey/vKa5TIH3/Cg79pR4ox71iUAoLD/XfAM3WOthitlFPXGiD8xj/iLRE7rCkN68XYC3s2uQsTu3ZiCsG/+pzFLCIk+AF+3ZVlIO8A/Md8wu/bZT6SUdA/yVUZEw+/9uAsRwKDgXa8PN8wTUodxLPcfe42mM3Mq8pD+joGYZDn1Z/UPiSOvhhgn1VNfwOiOMatoC+wIhxA66uwHQ/kpr6N/4RavZlLkV7831HpFtWx4sYR2R1B1/thLd0vHwTpGlKZDoywP/06en2yccUx5fNeWJY= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:BiP3bLMcpEIGeAOLpQNMKIOpa06eMDGbnsi9/vXzti1/bZ4YwnJkXsW9xYRq5h2u5NbiAyf/4F74zEz8VXhlHKolXgqWe4mRR3I5BmdRnGHUoUO5Tnh+B2nxy3xXhsJ3Iv8Zcgwv5jk9X8qbkjlMdM31ig3naq5mzn9HyZCbD14voAbngCgIDbMuABOWna3rrFndxEEjeCaeJ82IasueLeOX1gBKKyjSSUZl+d5+DrWy9RsDs58r9Gi65r5CyK4xQBc0MSQCs2DOj2umRIwGlR5uT2vJK82TmuDtjPNXu2DEXKs8o9SfMthWb2jWVx6E+Zl+M8XVjjr8/tbAmSU+o38bgOzyjQLisT1KsA6a2jQWfGQmiW8k8N5O2f5LHMlSSXn7X5LM0x/jxS/70VbERHSYjjjAeGLkSB1Ke0OZNB3ZHkhY0EOIMzSM/H0FDKXnz7CHicT1NCKdZrirKn3AfQ==; 5:O98eKxEqv+d5phQIaCYfOmlaDDAXmQ/ffkNr6p99rvpG4fly94mY3DUBQq0HLoXy0CqMwzaz90Ynejtv/FoY81cxL3xhp0f8IBgTLwZbSMrZblF+m3uFs9RHXQHbyjTfEC8I2qoPx9y+wjAiQNieNcz3xeAHa46dhH0yVuCeb/0=; 7:ijWxmasPYi8qjCMbrnH9tzOwBCbzOG7sMXSSwT/WSXgAT1cO3If1N+ijbaBEV2PN1dRpu306Z5EXuM6hyVP1g06kOs/h0FtVM6DPakOM8XvU/2D/tMPYgm0Bd6L1VDkhlAg6urMHBprm5veiPEOCIxQ3bGANgrjTV2wIhgaHnEIxPpp1al/TsPzMBPSY3yCwzY1D82Sjjbdzealyn/8bls/yBvrRM2udTZXBj81ZhbUhWpTsqFNZmSPoOVkGJVhE SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:49.1956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 952cec03-8ee5-4e46-a676-08d61c899d93 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 03/11] net/dpaa2: upgrade dpni to mc FW APIs to 10.10.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 21 +- drivers/net/dpaa2/mc/dpni.c | 22 +- drivers/net/dpaa2/mc/fsl_dpni.h | 343 +++++++++++++++------------- drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 17 +- drivers/net/dpaa2/mc/fsl_net.h | 2 +- 5 files changed, 229 insertions(+), 176 deletions(-) -- 2.17.1 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 8d3d54bfe..7ae74c65d 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -219,6 +219,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) struct dpaa2_dev_priv *priv = dev->data->dev_private; uint16_t dist_idx; uint32_t vq_id; + uint8_t num_rxqueue_per_tc; struct dpaa2_queue *mc_q, *mcq; uint32_t tot_queues; int i; @@ -226,6 +227,7 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, RTE_CACHE_LINE_SIZE); @@ -264,8 +266,8 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) vq_id = 0; for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; - mcq->tc_index = DPAA2_DEF_TC; - mcq->flow_id = dist_idx; + mcq->tc_index = dist_idx / num_rxqueue_per_tc; + mcq->flow_id = dist_idx % num_rxqueue_per_tc; vq_id++; } @@ -428,7 +430,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; struct dpaa2_queue *dpaa2_q; struct dpni_queue cfg; - uint8_t options = 0; + uint8_t options = 0, num_rxqueue_per_tc; uint8_t flow_id; uint32_t bpid; int ret; @@ -448,8 +450,10 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ + num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); + /*Get the flow id from given VQ id*/ - flow_id = rx_queue_id % priv->nb_rx_queues; + flow_id = rx_queue_id % num_rxqueue_per_tc; memset(&cfg, 0, sizeof(struct dpni_queue)); options = options | DPNI_QUEUE_OPT_USER_CTX; @@ -1793,7 +1797,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) struct dpni_attr attr; struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; struct dpni_buffer_layout layout; - int ret, hw_id; + int ret, hw_id, i; PMD_INIT_FUNC_TRACE(); @@ -1839,11 +1843,8 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev) priv->num_rx_tc = attr.num_rx_tcs; - /* Resetting the "num_rx_queues" to equal number of queues in first TC - * as only one TC is supported on Rx Side. Once Multiple TCs will be - * in use for Rx processing then this will be changed or removed. - */ - priv->nb_rx_queues = attr.num_queues; + for (i = 0; i < attr.num_rx_tcs; i++) + priv->nb_rx_queues += attr.num_queues; /* Using number of TX queues as number of TX TCs */ priv->nb_tx_queues = attr.num_tx_tcs; diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c index 9f228169a..6f5393f26 100644 --- a/drivers/net/dpaa2/mc/dpni.c +++ b/drivers/net/dpaa2/mc/dpni.c @@ -121,6 +121,7 @@ int dpni_create(struct fsl_mc_io *mc_io, cmd_params->num_queues = cfg->num_queues; cmd_params->num_tcs = cfg->num_tcs; cmd_params->mac_filter_entries = cfg->mac_filter_entries; + cmd_params->num_rx_tcs = cfg->num_rx_tcs; cmd_params->vlan_filter_entries = cfg->vlan_filter_entries; cmd_params->qos_entries = cfg->qos_entries; cmd_params->fs_entries = cpu_to_le16(cfg->fs_entries); @@ -664,9 +665,14 @@ int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, /* retrieve response parameters */ rsp_params = (struct dpni_rsp_get_buffer_layout *)cmd.params; - layout->pass_timestamp = dpni_get_field(rsp_params->flags, PASS_TS); - layout->pass_parser_result = dpni_get_field(rsp_params->flags, PASS_PR); - layout->pass_frame_status = dpni_get_field(rsp_params->flags, PASS_FS); + layout->pass_timestamp = + (int)dpni_get_field(rsp_params->flags, PASS_TS); + layout->pass_parser_result = + (int)dpni_get_field(rsp_params->flags, PASS_PR); + layout->pass_frame_status = + (int)dpni_get_field(rsp_params->flags, PASS_FS); + layout->pass_sw_opaque = + (int)dpni_get_field(rsp_params->flags, PASS_SWO); layout->private_data_size = le16_to_cpu(rsp_params->private_data_size); layout->data_align = le16_to_cpu(rsp_params->data_align); layout->data_head_room = le16_to_cpu(rsp_params->head_room); @@ -702,10 +708,11 @@ int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, token); cmd_params = (struct dpni_cmd_set_buffer_layout *)cmd.params; cmd_params->qtype = qtype; - cmd_params->options = cpu_to_le16(layout->options); + cmd_params->options = cpu_to_le16((uint16_t)layout->options); dpni_set_field(cmd_params->flags, PASS_TS, layout->pass_timestamp); dpni_set_field(cmd_params->flags, PASS_PR, layout->pass_parser_result); dpni_set_field(cmd_params->flags, PASS_FS, layout->pass_frame_status); + dpni_set_field(cmd_params->flags, PASS_SWO, layout->pass_sw_opaque); cmd_params->private_data_size = cpu_to_le16(layout->private_data_size); cmd_params->data_align = cpu_to_le16(layout->data_align); cmd_params->head_room = cpu_to_le16(layout->data_head_room); @@ -1471,6 +1478,9 @@ int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io, dpni_set_field(cmd_params->keep_hash_key, KEEP_HASH_KEY, cfg->fs_cfg.keep_hash_key); + dpni_set_field(cmd_params->keep_hash_key, + KEEP_ENTRIES, + cfg->fs_cfg.keep_entries); /* send command to mc*/ return mc_send_command(mc_io, &cmd); @@ -1764,8 +1774,8 @@ int dpni_get_queue(struct fsl_mc_io *mc_io, * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @page: Selects the statistics page to retrieve, see - * DPNI_GET_STATISTICS output. Pages are numbered 0 to 2. - * @param: Custom parameter for some pages used to select + * DPNI_GET_STATISTICS output. Pages are numbered 0 to 3. + * @param: Custom parameter for some pages used to select * a certain statistic source, for example the TC. * @stat: Structure containing the statistics * diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h index f0edcd270..40f045c9d 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni.h +++ b/drivers/net/dpaa2/mc/fsl_dpni.h @@ -77,6 +77,11 @@ struct fsl_mc_io; */ #define DPNI_OPT_NO_FS 0x000020 +/** + * All Tx traffic classes will use a single sender (ignore num_queueus for tx) + */ +#define DPNI_OPT_SINGLE_SENDER 0x000100 + int dpni_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, int dpni_id, @@ -88,71 +93,74 @@ int dpni_close(struct fsl_mc_io *mc_io, /** * struct dpni_cfg - Structure representing DPNI configuration - * @mac_addr: Primary MAC address - * @adv: Advanced parameters; default is all zeros; - * use this structure to change default settings + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_SINGLE_SENDER + * @fs_entries: Number of entries in the flow steering table. + * This table is used to select the ingress queue for + * ingress traffic, targeting a GPP core or another. + * In addition it can be used to discard traffic that + * matches the set rule. It is either an exact match table + * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING + * bit in OPTIONS field. This field is ignored if + * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise, + * value 0 defaults to 64. Maximum supported value is 1024. + * Note that the total number of entries is limited on the + * SoC to as low as 512 entries if TCAM is used. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. This is an exact match table used to filter + * ingress traffic based on VLAN IDs. Value 0 disables VLAN + * filtering. Maximum supported value is 16. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. This is an exact match table and allows both + * unicast and multicast entries. The primary MAC address + * of the network interface is not part of this table, + * this contains only entries in addition to it. This + * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in + * OPTIONS field. Otherwise, value 0 defaults to 80. + * Maximum supported value is 80. + * @num_queues: Number of Tx and Rx queues used for traffic + * distribution. This is orthogonal to QoS and is only + * used to distribute traffic to multiple GPP cores. + * This configuration affects the number of Tx queues + * (logical FQs, all associated with a single CEETM queue), + * Rx queues and Tx confirmation queues, if applicable. + * Value 0 defaults to one queue. Maximum supported value + * is 8. + * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI. + * TCs can have different priority levels for the purpose + * of Tx scheduling (see DPNI_SET_TX_PRIORITIES), different + * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM + * queues for traffic classes (including class queues on + * Tx). Value 0 defaults to one TC. Maximum supported value + * is 16. There are maximum 16 TCs for Tx and 8 TCs for Rx. + * When num_tcs>8 Tx will use this value but Rx will have + * only 8 traffic classes. + * @num_rx_tcs: if set to other value than zero represents number + * of TCs used for Rx. Maximum value is 8. If set to zero the + * number of Rx TCs will be initialized with the value provided + * in num_tcs parameter. + * @qos_entries: Number of entries in the QoS classification table. This + * table is used to select the TC for ingress traffic. It + * is either an exact match or a TCAM table, depending on + * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This + * field is ignored if the DPNI has a single TC. Otherwise, + * a value of 0 defaults to 64. Maximum supported value + * is 64. */ struct dpni_cfg { - /** - * @options: Any combination of the following options: - * DPNI_OPT_TX_FRM_RELEASE - * DPNI_OPT_NO_MAC_FILTER - * DPNI_OPT_HAS_POLICING - * DPNI_OPT_SHARED_CONGESTION - * DPNI_OPT_HAS_KEY_MASKING - * DPNI_OPT_NO_FS - * @fs_entries: Number of entries in the flow steering table. - * This table is used to select the ingress queue for - * ingress traffic, targeting a GPP core or another. - * In addition it can be used to discard traffic that - * matches the set rule. It is either an exact match table - * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING - * bit in OPTIONS field. This field is ignored if - * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise, - * value 0 defaults to 64. Maximum supported value is 1024. - * Note that the total number of entries is limited on the - * SoC to as low as 512 entries if TCAM is used. - * @vlan_filter_entries: Number of entries in the VLAN address filtering - * table. This is an exact match table used to filter - * ingress traffic based on VLAN IDs. Value 0 disables VLAN - * filtering. Maximum supported value is 16. - * @mac_filter_entries: Number of entries in the MAC address filtering - * table. This is an exact match table and allows both - * unicast and multicast entries. The primary MAC address - * of the network interface is not part of this table, - * this contains only entries in addition to it. This - * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in - * OPTIONS field. Otherwise, value 0 defaults to 80. - * Maximum supported value is 80. - * @num_queues: Number of Tx and Rx queues used for traffic - * distribution. This is orthogonal to QoS and is only - * used to distribute traffic to multiple GPP cores. - * This configuration affects the number of Tx queues - * (logical FQs, all associated with a single CEETM queue), - * Rx queues and Tx confirmation queues, if applicable. - * Value 0 defaults to one queue. Maximum supported value - * is 8. - * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI. - * TCs can have different priority levels for the purpose - * of Tx scheduling (see DPNI_SET_TX_SELECTION), different - * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM - * queues for traffic classes (including class queues on - * Tx). Value 0 defaults to one TC. Maximum supported value - * is 8. - * @qos_entries: Number of entries in the QoS classification table. This - * table is used to select the TC for ingress traffic. It - * is either an exact match or a TCAM table, depending on - * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This - * field is ignored if the DPNI has a single TC. Otherwise, - * a value of 0 defaults to 64. Maximum supported value - * is 64. - */ uint32_t options; uint16_t fs_entries; uint8_t vlan_filter_entries; uint8_t mac_filter_entries; uint8_t num_queues; uint8_t num_tcs; + uint8_t num_rx_tcs; uint8_t qos_entries; }; @@ -172,17 +180,14 @@ int dpni_destroy(struct fsl_mc_io *mc_io, * @num_dpbp: Number of DPBPs * @pools: Array of buffer pools parameters; The number of valid entries * must match 'num_dpbp' value + * @pools.dpbp_id: DPBP object ID + * @pools.priority: Priority mask that indicates TC's used with this buffer. + * I set to 0x00 MC will assume value 0xff. + * @pools.buffer_size: Buffer size + * @pools.backup_pool: Backup pool */ struct dpni_pools_cfg { uint8_t num_dpbp; - /** - * struct pools - Buffer pools parameters - * @dpbp_id: DPBP object ID - * @priority: priority mask that indicates TC's used with this buffer. - * I set to 0x00 MC will assume value 0xff. - * @buffer_size: Buffer size - * @backup_pool: Backup pool - */ struct { int dpbp_id; uint8_t priority_mask; @@ -296,6 +301,8 @@ int dpni_clear_irq_status(struct fsl_mc_io *mc_io, * variants, * - 0x422 - WRIOP version 1.1.2, used on LS1088 and * variants. + * - 0xC00 - WRIOP version 3.0.0, used on LX2160 and + * variants. */ struct dpni_attr { uint32_t options; @@ -320,6 +327,13 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, * DPNI errors */ +/** + * Discard error. When set all discarded frames in wriop will be enqueued to + * error queue. To be used in dpni_set_errors_behavior() only if error_action + * parameter is set to DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE. + */ +#define DPNI_ERROR_DISC 0x80000000 + /** * Extract out of frame header error */ @@ -408,6 +422,10 @@ int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, * Select to modify the data-tail-room setting */ #define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 +/** + * Select to modify the sw-opaque value setting + */ +#define DPNI_BUF_LAYOUT_OPT_SW_OPAQUE 0x00000080 /** * struct dpni_buffer_layout - Structure representing DPNI buffer layout @@ -427,6 +445,7 @@ struct dpni_buffer_layout { int pass_timestamp; int pass_parser_result; int pass_frame_status; + int pass_sw_opaque; uint16_t private_data_size; uint16_t data_align; uint16_t data_head_room; @@ -501,16 +520,48 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, #define DPNI_STATISTICS_CNT 7 +/** + * union dpni_statistics - Union describing the DPNI statistics + * @page_0: Page_0 statistics structure + * @page_0.ingress_all_frames: Ingress frame count + * @page_0.ingress_all_bytes: Ingress byte count + * @page_0.ingress_multicast_frames: Ingress multicast frame count + * @page_0.ingress_multicast_bytes: Ingress multicast byte count + * @page_0.ingress_broadcast_frames: Ingress broadcast frame count + * @page_0.ingress_broadcast_bytes: Ingress broadcast byte count + * @page_1: Page_1 statistics structure + * @page_1.egress_all_frames: Egress frame count + * @page_1.egress_all_bytes: Egress byte count + * @page_1.egress_multicast_frames: Egress multicast frame count + * @page_1.egress_multicast_bytes: Egress multicast byte count + * @page_1.egress_broadcast_frames: Egress broadcast frame count + * @page_1.egress_broadcast_bytes: Egress broadcast byte count + * @page_2: Page_2 statistics structure + * @page_2.ingress_filtered_frames: Ingress filtered frame count + * @page_2.ingress_discarded_frames: Ingress discarded frame count + * @page_2.ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers + * @page_2.egress_discarded_frames: Egress discarded frame count + * @page_2.egress_confirmed_frames: Egress confirmed frame count + * @page_3: Page_3 statistics structure with values for the selected TC + * @page_3.ceetm_dequeue_bytes: Cumulative count of the number of bytes dequeued + * @page_3.ceetm_dequeue_frames: Cumulative count of the number of frames + * dequeued + * @page_3.ceetm_reject_bytes: Cumulative count of the number of bytes in all + * frames whose enqueue was rejected + * @page_3.ceetm_reject_frames: Cumulative count of all frame enqueues rejected + * @page_4: congestion point drops for seleted TC + * @page_4.cgr_reject_frames: number of rejected frames due to congestion point + * @page_4.cgr_reject_bytes: number of rejected bytes due to congestion point + * @page_5: policer statistics per TC + * @page_5.policer_cnt_red: NUmber of red colored frames + * @page_5.policer_cnt_yellow: number of yellow colored frames + * @page_5.policer_cnt_green: number of green colored frames + * @page_5.policer_cnt_re_red: number of recolored red frames + * @page_5.policer_cnt_re_yellow: number of recolored yellow frames + * @raw: raw statistics structure, used to index counters + */ union dpni_statistics { - /** - * struct page_0 - Page_0 statistics structure - * @ingress_all_frames: Ingress frame count - * @ingress_all_bytes: Ingress byte count - * @ingress_multicast_frames: Ingress multicast frame count - * @ingress_multicast_bytes: Ingress multicast byte count - * @ingress_broadcast_frames: Ingress broadcast frame count - * @ingress_broadcast_bytes: Ingress broadcast byte count - */ struct { uint64_t ingress_all_frames; uint64_t ingress_all_bytes; @@ -519,15 +570,6 @@ union dpni_statistics { uint64_t ingress_broadcast_frames; uint64_t ingress_broadcast_bytes; } page_0; - /** - * struct page_1 - Page_1 statistics structure - * @egress_all_frames: Egress frame count - * @egress_all_bytes: Egress byte count - * @egress_multicast_frames: Egress multicast frame count - * @egress_multicast_bytes: Egress multicast byte count - * @egress_broadcast_frames: Egress broadcast frame count - * @egress_broadcast_bytes: Egress broadcast byte count - */ struct { uint64_t egress_all_frames; uint64_t egress_all_bytes; @@ -536,15 +578,6 @@ union dpni_statistics { uint64_t egress_broadcast_frames; uint64_t egress_broadcast_bytes; } page_1; - /** - * struct page_2 - Page_2 statistics structure - * @ingress_filtered_frames: Ingress filtered frame count - * @ingress_discarded_frames: Ingress discarded frame count - * @ingress_nobuffer_discards: Ingress discarded frame count due to - * lack of buffers - * @egress_discarded_frames: Egress discarded frame count - * @egress_confirmed_frames: Egress confirmed frame count - */ struct { uint64_t ingress_filtered_frames; uint64_t ingress_discarded_frames; @@ -552,26 +585,23 @@ union dpni_statistics { uint64_t egress_discarded_frames; uint64_t egress_confirmed_frames; } page_2; - /** - * struct page_3 - Page_3 statistics structure with values for the - * selected TC - * @ceetm_dequeue_bytes: Cumulative count of the number of bytes - * dequeued - * @ceetm_dequeue_frames: Cumulative count of the number of frames - * dequeued - * @ceetm_reject_bytes: Cumulative count of the number of bytes in all - * frames whose enqueue was rejected - * @ceetm_reject_frames: Cumulative count of all frame enqueues rejected - */ struct { uint64_t ceetm_dequeue_bytes; uint64_t ceetm_dequeue_frames; uint64_t ceetm_reject_bytes; uint64_t ceetm_reject_frames; } page_3; - /** - * struct raw - raw statistics structure, used to index counters - */ + struct { + uint64_t cgr_reject_frames; + uint64_t cgr_reject_bytes; + } page_4; + struct { + uint64_t policer_cnt_red; + uint64_t policer_cnt_yellow; + uint64_t policer_cnt_green; + uint64_t policer_cnt_re_red; + uint64_t policer_cnt_re_yellow; + } page_5; struct { uint64_t counter[DPNI_STATISTICS_CNT]; } raw; @@ -750,11 +780,20 @@ enum dpni_fs_miss_action { * struct dpni_fs_tbl_cfg - Flow Steering table configuration * @miss_action: Miss action selection * @default_flow_id: Used when 'miss_action = DPNI_FS_MISS_EXPLICIT_FLOWID' + * @keep_hash_key: used only when miss_action is set to DPNI_FS_MISS_HASH. When + * set to one unclassified frames will be distributed according to previous + * used hash key. If set to zero hash key will be replaced with the key + * provided for flow steering. + * @keep_entries: if set to one command will not delete the entries that already + * exist into FS table. Use this option with caution: if the table + * entries are not compatible with the distribution key the packets + * will not be classified properly. */ struct dpni_fs_tbl_cfg { enum dpni_fs_miss_action miss_action; uint16_t default_flow_id; char keep_hash_key; + uint8_t keep_entries; }; /** @@ -915,34 +954,52 @@ int dpni_get_congestion_notification(struct fsl_mc_io *mc_io, /** * struct dpni_queue - Queue structure - * @user_context: User data, presented to the user along with any frames - * from this queue. Not relevant for Tx queues. + * @destination - Destination structure + * @destination.id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. + * Not relevant for Tx queues. + * @destination.type: May be one of the following: + * 0 - No destination, queue can be manually + * queried, but will not push traffic or + * notifications to a DPIO; + * 1 - The destination is a DPIO. When traffic + * becomes available in the queue a FQDAN + * (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is + * associated with a DPCON object for the + * purpose of scheduling between multiple + * queues. The DPCON may be independently + * configured to generate notifications. + * Not relevant for Tx queues. + * @destination.hold_active: Hold active, maintains a queue scheduled for longer + * in a DPIO during dequeue to reduce spread of traffic. + * Only relevant if queues are + * not affined to a single DPIO. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. + * @flc: FD FLow Context structure + * @flc.value: Default FLC value for traffic dequeued from + * this queue. Please check description of FD + * structure for more information. + * Note that FLC values set using dpni_add_fs_entry, + * if any, take precedence over values per queue. + * @flc.stash_control: Boolean, indicates whether the 6 lowest + * - significant bits are used for stash control. + * significant bits are used for stash control. If set, the 6 + * least significant bits in value are interpreted as follows: + * - bits 0-1: indicates the number of 64 byte units of context + * that are stashed. FLC value is interpreted as a memory address + * in this case, excluding the 6 LS bits. + * - bits 2-3: indicates the number of 64 byte units of frame + * annotation to be stashed. Annotation is placed at FD[ADDR]. + * - bits 4-5: indicates the number of 64 byte units of frame + * data to be stashed. Frame data is placed at FD[ADDR] + + * FD[OFFSET]. + * For more details check the Frame Descriptor section in the + * hardware documentation. */ struct dpni_queue { - /** - * struct destination - Destination structure - * @id: ID of the destination, only relevant if DEST_TYPE is > 0. - * Identifies either a DPIO or a DPCON object. - * Not relevant for Tx queues. - * @type: May be one of the following: - * 0 - No destination, queue can be manually - * queried, but will not push traffic or - * notifications to a DPIO; - * 1 - The destination is a DPIO. When traffic - * becomes available in the queue a FQDAN - * (FQ data available notification) will be - * generated to selected DPIO; - * 2 - The destination is a DPCON. The queue is - * associated with a DPCON object for the - * purpose of scheduling between multiple - * queues. The DPCON may be independently - * configured to generate notifications. - * Not relevant for Tx queues. - * @hold_active: Hold active, maintains a queue scheduled for longer - * in a DPIO during dequeue to reduce spread of traffic. - * Only relevant if queues are - * not affined to a single DPIO. - */ struct { uint16_t id; enum dpni_dest type; @@ -950,28 +1007,6 @@ struct dpni_queue { uint8_t priority; } destination; uint64_t user_context; - /** - * struct flc - FD FLow Context structure - * @value: Default FLC value for traffic dequeued from - * this queue. Please check description of FD - * structure for more information. - * Note that FLC values set using dpni_add_fs_entry, - * if any, take precedence over values per queue. - * @stash_control: Boolean, indicates whether the 6 lowest - * - significant bits are used for stash control. - * significant bits are used for stash control. If set, the 6 - * least significant bits in value are interpreted as follows: - * - bits 0-1: indicates the number of 64 byte units of context - * that are stashed. FLC value is interpreted as a memory address - * in this case, excluding the 6 LS bits. - * - bits 2-3: indicates the number of 64 byte units of frame - * annotation to be stashed. Annotation is placed at FD[ADDR]. - * - bits 4-5: indicates the number of 64 byte units of frame - * data to be stashed. Frame data is placed at FD[ADDR] + - * FD[OFFSET]. - * For more details check the Frame Descriptor section in the - * hardware documentation. - */ struct { uint64_t value; char stash_control; diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h index eb3e99878..fe0915968 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h +++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h @@ -9,19 +9,21 @@ /* DPNI Version */ #define DPNI_VER_MAJOR 7 -#define DPNI_VER_MINOR 3 +#define DPNI_VER_MINOR 7 #define DPNI_CMD_BASE_VERSION 1 #define DPNI_CMD_VERSION_2 2 +#define DPNI_CMD_VERSION_3 3 #define DPNI_CMD_ID_OFFSET 4 #define DPNI_CMD(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION) #define DPNI_CMD_V2(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_2) +#define DPNI_CMD_V3(id) (((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_3) /* Command IDs */ #define DPNI_CMDID_OPEN DPNI_CMD(0x801) #define DPNI_CMDID_CLOSE DPNI_CMD(0x800) -#define DPNI_CMDID_CREATE DPNI_CMD(0x901) +#define DPNI_CMDID_CREATE DPNI_CMD_V2(0x901) #define DPNI_CMDID_DESTROY DPNI_CMD(0x981) #define DPNI_CMDID_GET_API_VERSION DPNI_CMD(0xa01) @@ -65,7 +67,7 @@ #define DPNI_CMDID_REMOVE_VLAN_ID DPNI_CMD(0x232) #define DPNI_CMDID_CLR_VLAN_FILTERS DPNI_CMD(0x233) -#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V2(0x235) +#define DPNI_CMDID_SET_RX_TC_DIST DPNI_CMD_V3(0x235) #define DPNI_CMDID_GET_STATISTICS DPNI_CMD_V2(0x25D) #define DPNI_CMDID_RESET_STATISTICS DPNI_CMD(0x25E) @@ -76,8 +78,8 @@ #define DPNI_CMDID_GET_PORT_MAC_ADDR DPNI_CMD(0x263) -#define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD(0x264) -#define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD(0x265) +#define DPNI_CMDID_GET_BUFFER_LAYOUT DPNI_CMD_V2(0x264) +#define DPNI_CMDID_SET_BUFFER_LAYOUT DPNI_CMD_V2(0x265) #define DPNI_CMDID_SET_CONGESTION_NOTIFICATION DPNI_CMD(0x267) #define DPNI_CMDID_GET_CONGESTION_NOTIFICATION DPNI_CMD(0x268) @@ -113,6 +115,7 @@ struct dpni_cmd_create { uint8_t qos_entries; uint8_t pad3; uint16_t fs_entries; + uint8_t num_rx_tcs; }; struct dpni_cmd_destroy { @@ -228,6 +231,8 @@ struct dpni_cmd_set_errors_behavior { #define DPNI_PASS_PR_SIZE 1 #define DPNI_PASS_FS_SHIFT 2 #define DPNI_PASS_FS_SIZE 1 +#define DPNI_PASS_SWO_SHIFT 3 +#define DPNI_PASS_SWO_SIZE 1 struct dpni_cmd_get_buffer_layout { uint8_t qtype; @@ -415,6 +420,8 @@ struct dpni_cmd_set_tx_priorities { #define DPNI_MISS_ACTION_SIZE 4 #define DPNI_KEEP_HASH_KEY_SHIFT 7 #define DPNI_KEEP_HASH_KEY_SIZE 1 +#define DPNI_KEEP_ENTRIES_SHIFT 6 +#define DPNI_KEEP_ENTRIES_SIZE 1 struct dpni_cmd_set_rx_tc_dist { uint16_t dist_size; diff --git a/drivers/net/dpaa2/mc/fsl_net.h b/drivers/net/dpaa2/mc/fsl_net.h index 964870ba9..0dc0131bb 100644 --- a/drivers/net/dpaa2/mc/fsl_net.h +++ b/drivers/net/dpaa2/mc/fsl_net.h @@ -180,7 +180,7 @@ #define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 5) #define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 6) #define NH_FLD_SCTP_CHUNK_DATA_UNORDERED (NH_FLD_SCTP_CHUNK_DATA_TYPE << 7) -#define NH_FLD_SCTP_CHUNK_DATA_BEGGINNING (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8) +#define NH_FLD_SCTP_CHUNK_DATA_BEGGINING (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8) #define NH_FLD_SCTP_CHUNK_DATA_END (NH_FLD_SCTP_CHUNK_DATA_TYPE << 9) #define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS \ ((NH_FLD_SCTP_CHUNK_DATA_TYPE << 10) - 1) From patchwork Mon Sep 17 10:36:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146845 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3603046ljw; Mon, 17 Sep 2018 03:38:27 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYjaDxBjvODmIsgMfj2SbbK9UgaFg5WPcygvM9L25lmGWEIZYjgIcjdUHqc3GGKhOja1T0x X-Received: by 2002:a50:f419:: with SMTP id r25-v6mr40867271edm.226.1537180706950; Mon, 17 Sep 2018 03:38:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180706; cv=none; d=google.com; s=arc-20160816; b=GJDkJ+4+UNq+jdwT1yNQ6Q3X4zI4pG826795K3YMFd27HY+HvCvDmPrioWMW/C5ne4 tUPaMT7nNmJOEcdJN4vRVR/ODWyRydiAV4tklH5U3M+TGvDOdZOc6xz2fREEkhxBSFbW T7E3IdFvm0UJKWdu63mfJQoB5ioS80DKmS4xTVidhJ6s9Jc/EaRUyvSly1RCD/y3DkHm cY0D2X47lZHZxTwMTvEz43rdJ0qcmwj4y5/8FR4nhnKvKxMpd8boUeOc+rRQLIRTJ1QB LgyHC31QAJ0QtS7ki0BG6RVRvQ/oc08+kdtbPB2qQsZ8niF7Yt4sMOf4Vgnm36Xt8Diy ccew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=znX2fWlSFOiwhQtMTtOsTfL9I+enghH4BX/agzpx/Mo=; b=qwlZZZL64lmuc0qW5etDQ6KOrOMd0uljClRVEPnEckz6oDinPsjl+PhmUySkVNa1YJ om091uMWj9Q1BQZVIuuXg9kDOSHn5O5E4XeJ6GyEFJo07+kygqZcH5K87CY2ffaertif utCnGnIyWte+erHFv1eWiISTQ1jc8n+fqxrXE1kkOjkSLmWm0AtsAuhC57WGYpvdsOZR PEYCc/qbFc0lnwwBfAUC5NU6Ng7vdkjOtG+zL+n+kr3lLkOE61C2+VAs2v8u9u3lNoVi FhvDKGWhcgbv8W63tUduzfjMXxKgrTTtRgbbnjXMf1ozj2g8otIkdfIgMJ+XlXu7lLxU c3nQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=PjpAFN+n; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id f12-v6si4103403edn.275.2018.09.17.03.38.26; Mon, 17 Sep 2018 03:38:26 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=PjpAFN+n; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8168A5920; Mon, 17 Sep 2018 12:37:57 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40071.outbound.protection.outlook.com [40.107.4.71]) by dpdk.org (Postfix) with ESMTP id 0EFA44F93 for ; Mon, 17 Sep 2018 12:37:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=znX2fWlSFOiwhQtMTtOsTfL9I+enghH4BX/agzpx/Mo=; b=PjpAFN+nQZTa3LKQ+yA/IiC3PngScHqHZBRDSA2BzRUv3Y4E8S6j7UznQohIz8dNnRiy3ojwWK4v7yZ5tF4MqzYkLk9WGr2OHNky7+xRPVRHvmb4fPkazcCKDVAXo0QitxZYjex1pkL0xumC2A35x0dFzn8mjlSo0r3Kk2QPcGQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:50 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Hemant Agrawal Date: Mon, 17 Sep 2018 16:06:24 +0530 Message-Id: <20180917103631.32304-5-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 00fa9145-a74e-4a58-9def-08d61c899e4d X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:wM5AABtq9HD9mzoS56ij18rovqh4uW8ViR3v9bQykiNJh09/rSCX4NtUPYikfsikdyP9ue3q4D1YZdvosmX4bbbwI3+9wb7aZDdgddl1L35tUwsUA6ZkanyWCBSdMdSucazlPt8R2nY/6tS8JoKXMWh4UxakN+Ua9GMFBsG2AXqbLTEqXOVcOPTfo/pX1Jejqz4JrwOLZyl+Tvl3GlwRt7hcQYllzzI81dAMDCMMIZwcTu19tIh7OC2Y7JRVaAYn; 25:e+vN1dmrOjMl20KNmQIDu0MxBFUkqKk/C/jy6a+RPiZ6tvwrBB/j0wbwJhPTk08ObTEmHv/cYl/hZ2twvBN8TwpA4NG2h1Mig/6CaAd7rKwUUKhvoXl8c1XxwYEcheVAqzkHLFZLKlDsU3vVPTHQCI+TJJYtz4vN81vQcILQpfMydqqLWqCs25kvBNWHGsSlnANunYzTM3RVYkr6KoMBsWY/04yDNgaSjyNLS1Ll/SrcEXwOP1zW4guKUbldWdWFsjpr4BmqrKtk3GzRvUsG8oYIearkoXz6BiQA1SWr21yTXxykysSj/kbx3A4soqAxWXYNdAbSreX+aflR8Na4qw==; 31:etgyZ7AMc2a76HmjjUOGah9EluggylGMBVHbzLC5rjMgscBZPjUlN79A4gT8kQo0Rijw982nsV1R6/2/++foS9wtKueqRbaRxTEDJECI4FluZjzDdww905cebQ4rPaU3Yhd5wAToWV8QYBsLIR9DMTPoeXKX8RnPNeyYAYw1awVS+dVhdY3jvD4Irunyd9rqJSQbZLawV0/D9OmAg7qqE1IsKvjEa2UljSTapL4M0e4= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:DL5QLBy89AaboXQVblb2H8hpKQMoAfKk2mZ82N4Grr7YTC1TpG2OIE/yOCoYoIubtg2xc0nCzjktTc05X+f9sOdZMLH6lFpKiDIssy0PxtIrAOV5nS6l4gHFBKsEkV5OSV/u543sNQ0jZAQinriF5enLWaVZ59TEA0C+FkWpsm4znwIjqC7RsTus0kqGvv2D71W6eHdXHsL8P+9F6ga53Rsp/+WJhqBMhCX3NxLMrlutORcW7LPRBNZ9iJIIrOajoFlV0bhDphBcMK82pm8j8pW2JZnCilCAINQOb/6+a++ywtLUzQm5t3FfWxzq6ygPhP+xht4myhbfbiaZLyQl61Nqa8ORmnDvpvRpUEM6MKlRhBkHyyEwaVnr1qboC0aaUxX7iwSZtzCM4Qv8aN4rOTxZhkEAOriLVSpgynUZGwclU/sU4H1Swm3DBd8yaEoMvn4JZLx/sB3FTv/dSvnUHqbaGMW1iz6MjoRKA99UOFFKKRWfBfEOBim4xLEuOrwi; 4:dP43Z3AtDmu0xZc8egW6dC9JUc1UWWSwA4XNykrKo+jzOAM+eTPW/BOVJCIfvEUaB/OJi/yP9250q8ckp2/7w5uMe5Eeexh++NgOoT4tWaLi1nZ3Y5VkPGNx7QjAP6DDp24sXSC7kfrLMHOyeK8ClHvJGrfiEw77PkIdT81fp7cY1hIfftulcfSgr3IUTzOzGcON6BJjbojBEno5h0krChJQuPstzM/Twor5vO7lgOfBNBD/fWtNgyaXn3pSg5N275WIhs/7N4r42ZpKVL9yuwkXXRz94mfGSQeIMBt9/lRuGIeulKqnP22C/KDTG9RITJYrq05gtigTwiN34REo+0h9GyxX6FC6gOiv/W7zK64= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(575784001)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:gUAE/4la5ZIwX09UjtfPRubc3CS/TP2Rx4S9H/6Pd?= W/Rjm1zMvsUtjV8+7Iggbueux9StoW7oDkjUGMS7K1JxxZmfuzBZPHK/79n9TxCKaT2WeP7stFerRMKtPmU2Y80RcT4EyAN83sbajeJJwJvCsfWonzd7eVRPL2K7DPti4fkzl6Tok1ah3wCgJ3cMjT6PVl+JfvgB8UiaUF8ooWs7LbP+cK5PGqBGib3M9jnXc2RnhWBKsZQkSePQjOvc/lGJR1ZzqOEIGslsUnBfdJG+cP1QZGz5UWUM+ig2eYI+b91fTGdfUoxXAxGDhrIKvAohHNREd7Wv0XXiOtkeZG67RiRzs8WJcp5Ha47LZwvrCqFvMmkE93HRC2QmUWtQhOq3cEnomRk/UHyxY+pNMlfLMBMDzubaNlxybAVRae8X2RrU1e2sT4oamDIK8e0SUEVW7guiunVBM42hueiUS/VhzzbpGFypdgRwnjrFWmTg9M7q7P/ppTzWxThum2gOAb2OfILoYRAmCp4zAByBOuxjoQajtt+WvMKNXwFNkFvKyU0xHmIQJSk4a9XjzPxWMuMGk3XUT2UylkdMvMiwIATMCTYfwb3v6sQd5uCB0EoNaooLdwpRURjf+ptV2EM0Fod8waXeld7jqSbaDGwyKR5eSeExpyTTI/EfQOuWZ3jPlFP0FkOf7ADv8cTybKdtq5ddZBGcbuc0KsY4fox7FmGCAjSEzDgqXKulwXodgGcqeYb4H3ZxcdEc2vB/2uXM+m1sgkWVWSpgTATnE6uzNJU9brCtCebJj2TeUdNBBtGuRKKsz0thcTmtU9x3+32iD97CwLBwzroQ3NSiHfFaoivyQCcucmczZ0cCGfWR+/e/tu7GgGJC1sDU20ikzZdkJ8FOKrPjQp/potI6zQu30Wtio1J0rZTmdxZC6jkhTKgEboOuc710AxGWax/h50XhAvnvVx9HRqwQc/ZBQOAGrmkRHWuPn8TrjxK0OcF8E5NH88FTpDdw6jCzvU+77bZaU8Epeud5Y7ekwEnUTwNPaeBa908iuCeagNT2AbnHwVxImEfJoDQgQQHbW4ya2qu/BpjO+LOZX10vihRxrtB0CQdz3cPrjOsO/4Lku8fluESWFpVsI569XPZtGizeC9IFZqXw4/uLtSTh1WZg8E7CN38AL22MpslrwXUgBIj8O/kBy2nfFxfWCyZIYlzA+KjFEHG18ACR5eZVEMvHJV8m3EbqIAvv17sGu97Kkql7Bbwb6FLjSUMsGNWwuRoKRWbjEZoezrwjzKQk4YsdmlJFkkazQ== X-Microsoft-Antispam-Message-Info: URIerBrYRKhFy3zlsEb0IAkIsoisIAmUwECJoUYA9dWH9h3VKhACVIOjzPes4V16HA3xFY484sdRE3+zFZHEeQuSoULfCJ1Y5EBgOabzjq3pDbYuFF1RJzjQDujXNdRUiwAI/GqK84JY8l2R1/VExPrIpDCdN1y0du6kUCHWSF6aDC7JGH6uxxtvUF2TtJ7LvqhfqHtTG7X8Cwb15SY0QkbPwdP3bXIE+9pEt9hfcfERyC6R73NNk25zBb7DexXNBEdWvInCCtnHy9PsGEswG+k+AvJe4jhutIv0udgTlC8qDaVWeihSYI3KJxuWi7X0WeUWa1SJClPzLX+QBKmd7kiipXL0B8DW1sLhQK7nV00= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:ZONPkuMLYN9CmH5etkk3uEyzBxNhfUjZFTIKBPF3SFdmbtHuf6l/a4Kd6nQD+iQGsj7JhWGpFic7C+dkdvxRo3Nd6YLOjFnYDEfP6WsVkU1WdV9QdKIA2q4xBsDCoT0Xvpp+sxs2MYss5hsv+uxRCaUP5Q+S8YL792vonPBc4KCYIx+R4MZE70s4lr4Ft5rGlAV2MPQTQOyX2rnBN6mJjGUlu23aWxfLASn4iDw7wWTPehRDjJHZP5i9Pu2+XWk/jvr1QIQfQQ7HSZCHtoHzJXuZXUi+h4PtToC5WGNSBYUJ6yp4lXrFyRgdWdOTBZNaghc1k5k4KXJf7ASmQS30j812TCI7FxJIh2Tg8D+0YmRYy7zbo7S45k08JiGudwF29PqeLnYM7TuqIX8G4ME63QlgDj7Hpnj4GSidkN57ZFqxFqFew6Kq11X6U7CRrLmO6wG0kgSJnO2ehozL3j24Xg==; 5:bloW45B1uWYyd9W9vqxb1He/N3F/s06a3CkjXSZsTQGVJQyOU1dZe45E9R3Lt5qMagAY8XqLA707vESaHzSKnEMFrgRpuSDKcRH8gE3S+/b554qvpcu+q9EJlxSeM5/LOkH2o45ObzNLXu5nB1lhfDNraK7D20yq8p1c8XtL+SI=; 7:NcWnMkhhCknTc+xHfJjIMJNmOmO9MNeY9l8t5AqHtvD96jHgI/X6dc3OT/rklX6W3dc2Iljp3v3VUPeVvOQC8mlRo6JMFQ/5fFxJ0IuopAuakIcQFuqxmTLFYFfASzkEmn+gORAKkECweQdVEoZa3K77EOyvjDaDu2DYU//oNsdevwaut94STYmDxs5QtCyBqNWHid2WDMaYz7Q9P5ONhvIivCw2lbccYYdD5s7nBX8G4tchle+AfUqGYUxKrzIf SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:50.4144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00fa9145-a74e-4a58-9def-08d61c899e4d X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 04/11] crypto/dpaa2_sec: upgarde mc FW APIs to 10.10.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Signed-off-by: Hemant Agrawal --- drivers/crypto/dpaa2_sec/mc/dpseci.c | 30 ++++++++++++++++++-- drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h | 10 +++++-- drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h | 13 +++++++-- 3 files changed, 45 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/mc/dpseci.c b/drivers/crypto/dpaa2_sec/mc/dpseci.c index de8ca970c..778dc37f7 100644 --- a/drivers/crypto/dpaa2_sec/mc/dpseci.c +++ b/drivers/crypto/dpaa2_sec/mc/dpseci.c @@ -116,11 +116,13 @@ int dpseci_create(struct fsl_mc_io *mc_io, cmd_flags, dprc_token); cmd_params = (struct dpseci_cmd_create *)cmd.params; - for (i = 0; i < DPSECI_PRIO_NUM; i++) + for (i = 0; i < 8; i++) cmd_params->priorities[i] = cfg->priorities[i]; + for (i = 0; i < 8; i++) + cmd_params->priorities2[i] = cfg->priorities[8 + i]; cmd_params->num_tx_queues = cfg->num_tx_queues; cmd_params->num_rx_queues = cfg->num_rx_queues; - cmd_params->options = cfg->options; + cmd_params->options = cpu_to_le32(cfg->options); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -302,7 +304,7 @@ int dpseci_get_attributes(struct fsl_mc_io *mc_io, /* retrieve response parameters */ rsp_params = (struct dpseci_rsp_get_attr *)cmd.params; attr->id = le32_to_cpu(rsp_params->id); - attr->options = rsp_params->options; + attr->options = le32_to_cpu(rsp_params->options); attr->num_tx_queues = rsp_params->num_tx_queues; attr->num_rx_queues = rsp_params->num_rx_queues; @@ -490,6 +492,8 @@ int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, attr->arc4_acc_num = rsp_params->arc4_acc_num; attr->des_acc_num = rsp_params->des_acc_num; attr->aes_acc_num = rsp_params->aes_acc_num; + attr->ccha_acc_num = rsp_params->ccha_acc_num; + attr->ptha_acc_num = rsp_params->ptha_acc_num; return 0; } @@ -569,6 +573,16 @@ int dpseci_get_api_version(struct fsl_mc_io *mc_io, return 0; } +/** + * dpseci_set_congestion_notification() - Set congestion group + * notification configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @cfg: congestion notification configuration + * + * Return: '0' on success, error code otherwise + */ int dpseci_set_congestion_notification( struct fsl_mc_io *mc_io, uint32_t cmd_flags, @@ -604,6 +618,16 @@ int dpseci_set_congestion_notification( return mc_send_command(mc_io, &cmd); } +/** + * dpseci_get_congestion_notification() - Get congestion group + * notification configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSECI object + * @cfg: congestion notification configuration + * + * Return: '0' on success, error code otherwise + */ int dpseci_get_congestion_notification( struct fsl_mc_io *mc_io, uint32_t cmd_flags, diff --git a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h index 12ac005ad..f4b6fe8ad 100644 --- a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h +++ b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h @@ -20,7 +20,7 @@ struct fsl_mc_io; /** * Maximum number of Tx/Rx priorities per DPSECI object */ -#define DPSECI_PRIO_NUM 8 +#define DPSECI_MAX_QUEUE_NUM 16 /** * All queues considered; see dpseci_set_rx_queue() @@ -58,7 +58,7 @@ struct dpseci_cfg { uint32_t options; uint8_t num_tx_queues; uint8_t num_rx_queues; - uint8_t priorities[DPSECI_PRIO_NUM]; + uint8_t priorities[DPSECI_MAX_QUEUE_NUM]; }; int dpseci_create(struct fsl_mc_io *mc_io, @@ -259,6 +259,10 @@ int dpseci_get_tx_queue(struct fsl_mc_io *mc_io, * implemented in this version of SEC. * @aes_acc_num: The number of copies of the AES module that are * implemented in this version of SEC. + * @ccha_acc_num: The number of copies of the ChaCha20 module that are + * implemented in this version of SEC. + * @ptha_acc_num: The number of copies of the Poly1305 module that are + * implemented in this version of SEC. **/ struct dpseci_sec_attr { @@ -279,6 +283,8 @@ struct dpseci_sec_attr { uint8_t arc4_acc_num; uint8_t des_acc_num; uint8_t aes_acc_num; + uint8_t ccha_acc_num; + uint8_t ptha_acc_num; }; int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, diff --git a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h index 26cef0f73..2f78c3563 100644 --- a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h +++ b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h @@ -9,22 +9,25 @@ /* DPSECI Version */ #define DPSECI_VER_MAJOR 5 -#define DPSECI_VER_MINOR 1 +#define DPSECI_VER_MINOR 3 /* Command versioning */ #define DPSECI_CMD_BASE_VERSION 1 #define DPSECI_CMD_BASE_VERSION_V2 2 +#define DPSECI_CMD_BASE_VERSION_V3 3 #define DPSECI_CMD_ID_OFFSET 4 #define DPSECI_CMD_V1(id) \ ((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION) #define DPSECI_CMD_V2(id) \ ((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION_V2) +#define DPSECI_CMD_V3(id) \ + ((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION_V3) /* Command IDs */ #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800) #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809) -#define DPSECI_CMDID_CREATE DPSECI_CMD_V2(0x909) +#define DPSECI_CMDID_CREATE DPSECI_CMD_V3(0x909) #define DPSECI_CMDID_DESTROY DPSECI_CMD_V1(0x989) #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09) @@ -37,7 +40,7 @@ #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194) #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196) #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197) -#define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V1(0x198) +#define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198) #define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199) #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170) @@ -63,6 +66,8 @@ struct dpseci_cmd_create { uint8_t num_rx_queues; uint8_t pad[6]; uint32_t options; + uint32_t pad2; + uint8_t priorities2[8]; }; struct dpseci_cmd_destroy { @@ -152,6 +157,8 @@ struct dpseci_rsp_get_sec_attr { uint8_t arc4_acc_num; uint8_t des_acc_num; uint8_t aes_acc_num; + uint8_t ccha_acc_num; + uint8_t ptha_acc_num; }; struct dpseci_rsp_get_sec_counters { From patchwork Mon Sep 17 10:36:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146846 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3603220ljw; Mon, 17 Sep 2018 03:38:39 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZcsae1ryU8OkaUQj2iUgoMjyolIq1F0UiDLqPsTLJJybhJUUh/daOBFEEEMJU7Onl0sG5m X-Received: by 2002:adf:d1c1:: with SMTP id m1-v6mr18980367wri.138.1537180719052; Mon, 17 Sep 2018 03:38:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180719; cv=none; d=google.com; s=arc-20160816; b=FHCcCmLuKMelnRBxeCY4L5KjF7GrQg9GvwltJZM72/eTPiUoCJWcznmMJRnFP2LBJd m5yC4BKfQZVNT9JfX+Ijx7ZrodXUKC+il4l7jetlfAk5EuQ8VmcXszHOs4qQqZKn7HHM CZmIIH8bDD5aAeIFjQX9/2Cx/yETheHXgt9438ud+Gr7ATCSwMsts11VVs5gkUO4noDo XgwOooCRuXuNMr5MkFn122j9dymKyaQtFtXdV1nJNGPKKSURrPunYllMIhX6y2Fnyr3n 7fuIW1wlZIMgjb6pXwe3Q6GLuD+v+8xNJcVYwZjade2di+24C6haEIal0BySwB5/YtRx wyww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=+3XJIrXHjbFWCNoKtw+H+iDZFAU+5+4Kj0aTskqNYvU=; b=TgXxyoC5ovKGRTBaJv8YN61BWWuFurXidu9uyZ6qMQENbGneuGI/gmfdIORw8qKDHv GPBz2DxfKu+h9hVXPgzWFGxTuAvI/LD/HTHZdlflAE0SB7rFVqJaRjs3FJ2CtHMSYqRB Jj7WGpSMPUbbgvfIfZCdfY+8tFeD6h1tpsiBOB/AQNlyIo0fzOthWHCUV3u+SDv4odBN /T50BjgW8PmelZz/uDo5wy1qxbbEG70mU/b5akiZxinuBmf11Jl9LL4BmM2pAqCZDa5r 93FuSmZXaTLCoUsllnrKzph2y1HMsgjI03wlSmIHztlbK7lPYq55IvYrFITAektpD5NC sFnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=S0BiHXUX; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id t6-v6si13602620wrn.195.2018.09.17.03.38.38; Mon, 17 Sep 2018 03:38:39 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=S0BiHXUX; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 476A05B16; Mon, 17 Sep 2018 12:38:00 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40054.outbound.protection.outlook.com [40.107.4.54]) by dpdk.org (Postfix) with ESMTP id 33C1A532C for ; Mon, 17 Sep 2018 12:37:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+3XJIrXHjbFWCNoKtw+H+iDZFAU+5+4Kj0aTskqNYvU=; b=S0BiHXUXhqLzOVDG5T/jkKAeJPA+TaQdLkpEypdsNLTQ/CtjM7PAZwZUJHPBQu51MNM4U2CXrPzIUOaVIRV+CBllb9GpIPX+/4aDXURXhe7Sg99ICRiIQf9jffLsaN4C/VuveWwCWGVAAHTCO+TP3JrW9v5EPnmGaxp6UmQBLRg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:51 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Nipun Gupta , Youri Querry , Roy Pledge Date: Mon, 17 Sep 2018 16:06:25 +0530 Message-Id: <20180917103631.32304-6-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5d80f905-9c24-4b21-9401-08d61c899f26 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:hJ6mUSemgSJOFzSCzJPj/9VwiprdISl4YgX2M1z07Iuu29CDhKYwRj6p8k9IO+RyfipD2ZX2r8Mt950+DTSgNcCKbxZ8BOXvp+ibP4FuDlb1WA30rjd1izTdIK75dih+2qoEZ1YAeK3iev1cbDVO/7Z2PdH3OapRbUEoUKqpLvDsoID4cbqJlxEJVIa4WyitlVBysxjSmP6FAi8x4hS2/tbZYUuOAMhO/Rt2crAGfXXsqHLUQU0PgealKqGXURs9; 25:U6+FVOIJbaabgSU+WatcqdYfvqTxzbOtru3uDWJZfL5BGIwoQy1o6CT6Q0F8eXqoRYf1PhudrdtXFq841pMciDuxPnpBQn+V74XrvK5xiV76k08mCNKUKD9Tv1CbggkmePVRW+6co3UvjXa8WxJrZzvtL+65nXo8p6KzAWAxKy1eatJo+ZoxxgYc3SiwtAq5yGwUhJoxW+FCZjcjS6UInUFIxVWTE/6AjPNWNWzcZfTJLOxFWM5ZebvfM7jlaMGY5/wCp2HpKJGQapbht0mrlyu6tr/5GGPmv4fGNRHKG5Tx7ZAaVD9VwN2v9vTDy7EzCve54jEJPipu1bLq5pCQQw==; 31:sp0xkds7fRn2LAwPKP/agB0Rgfsg7UbEI+Xp5qqolwjHwHhM18VhDdLHBQKinXvmhmXA1X4WdvYAOuaBmY6JQbhf3xpwby7CWxJaL5ck0EMl1j+DFjUHIen4h43cWehiAdnUSbnWlsLwOzqubfAkycU8LKjKs+xV+w9/REexgnbwYQrCjQQH+xsw3un7k2AZUYa3OJAq7rNbjrGrazb1EQvn4PJ/cHS0pasBotw955Y= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:TyqXWIpcLGBFvEKmygVOBZmQ4HMrOu48oKpqzH1Rf/pLvnVKfmiAszpkhbykaNjz9PtwN4lUoOUVBsDugDqH20yvI8XGuDlIt4sZlXyco+2YGAmVbqKlo8H05UK09ZnpOCqr8D78vmqxOo9uUTuuiSxw48NV6p91kqCukMy8b7DO9mPBfmsijtgcAQcQ2mhztLh2HHC1fPTaCJCRXxfvHqNt1XjXz46ZddKzKcdZ4/W/ecApMhVLuk8cj1b9fM4+qGH4FDifc17Yg/RVRaKiw2K90jUOXzNAXfEygxByvpUIBibRCaR6+cE/PUV47vMnqpbKGLpHZDuJNFFoPji15xvlryU4lXIGlX6S5Vl2d+7hXEhmkC/uZMSiFac7Yukd4Z7/KXhdXxs9JzHcAprymdCYL4/MxVdO5wpcFRrcEb8U3q4eRKfixvYjnPgNZ+4MX1O68oqiecMbdd87uHH5qEmjgcpFpjL2jUaSPtAJ22Mne6J3HHapA3kIxPo3i+99; 4:LoZ2ZqHKNyMjqoK05H15D6fAXDJY/xCK6c0lXjGZOOy8E1baKqhLRXF5XK2rCC7O1AY5PTSrBIa9YyvsRxkLbSCM65YsLmDlxIFXVEez7UO30BaQh8X7vC/yTeuoGHESob7vLwfuyH1jWOaTIYfW1hjeMbwT4noQYQfkPFz/VMuoU6cdaTIeUo5OF7K+bgw39yzIbHiKttMcGGH1NqiGzdHbaffQ/riNQMes6UhZJqKk5Mo/WWOipdnnBOUYmB4k/CLaZPztC7Wpx+dLmMO1liN6ZUpD28h84HSIOSt4BpKV/iV9t0lPanmtC6sYmHu5WRL1VJuFjnwIUAUMBFacGHCEMuegCbuyEQ59WwoS7h5vw4EdZ+TN1gDkhgWFVhYW X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(227817650892897)(275809806118684); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(54906003)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(53946003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(575784001)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(16200700003)(110426005)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:rnKk8Uijg6+619P7TxLTJnswB8VQiGqcPXg4u2PNE?= uq+ZDwKy+R6fWev6MpTChlIvTGCS3j6N7WMUM5qrwVs0FBbFhDxhmapNx6diEZouRPokxVCSx/I30MqQGJA/7RPjEQeT59RipmSeOKP08pJA2u0qBz08sOmpCUwuoMrgJqTpWjjG9yOzD8Xm3CHUqxCrdAXsECjOQWJgql0nz38Ru43k2JgZdjBRG0uJjm2k9+q9okTRCmzNm4pW1BscbhrJecPQXdSt7DmI/c/lzbmvEgCgYEUF90pKcM5wWdZeDaQeFz+muewNlK8Rj/o0zqiBK0OJnlRwhsQ+ANcu6pP5ALkMEjx/1pF6Zv0VQ0Dy7IN/xNJ+vDXCxwtZgoGgCD1JH9RSSnOLFj2ZTXEd4CNh0Gui4/ZugMQa0rrXd6SoCcBW3752T+jqj9XHBWldaStGatbbSSK43Srmdg48gOV3GHpR5IVxmp6Q+YRoHv4iOaVge9VaFOVYKowF5a7RC3YPtK+ue2Fnlpybh/wWBf7GUCTJ6J7Oc0ia8pn08FvpFB6zHpv3nIOGtMkG3EZ8UF4VTFtErvcwxQ5Hul4AEc6un/FuodUYNjtt99vOJCYcMnOW3+SUGCRaXuVvM9/fjUpW1LWpJY1YsaZEDjlfL6KxfdQwd/7pXx4xg4FcbZZZi24EOz0rD8HMP1ii/R6Z1kLrcYfSmOmVSGTyFfHN9UpXrSnab18Tpj5Gk3HwignzlxRas39SU/5ECZ7QFakjunnrObZ3xKOE2GlytDnuqPybamD11Kpd5swD3M3Zgs/iMvNPgUbUanx2lBHXQyQ3Rgvs7gpzFRHxLdc0FRrJ4lRDkzylLRH2kdqgWFJkjjs66XeNqEVZjpur124kB4otfJGlH9xTUgZ+PFPFQDhoUZ2TR1Pa/pqsLLz8R8L6nQX2LJ9VdH7A/S6qTROQSL6ZODPLdMeOHTlKbYxW7y+o0cMji6o4mjVR2v9CtiGy1vRYcdp23ADBsgENVH5uYPaRp1CIbHe4QSz7aB+SzNskfvRX6rGZGyCWgR6++VKpGf1Xkg+DLQ329AeJqsK8qBIxx7fxGyrWK9ygS3Y3KfE8pSNm277Y+2slYZeWaqmH42MDO2nstU9uBcYYQAFowVm9tGiKtzkk906phdRQoXInz6s7cGE2Exjk1WV/Iig+tvb1SNMpPtxZb0CxD+7uAeJgjgzDe7Vn86iMYzHDQsFTjjcTUbBnIsZaNf6IfnLDOtJXvqRjYlCZ1jOM15GqVo7UH2JCIr6NOalYhgoX/2faIxKb9ZfWeCfeKFKxKKTIXzaFsmD0c5m8b8l2Uv4WClSFpsaBFJj5FzVmbLTh5Qk/AH96O9GJhH/vHV7sTEOdXCK2qg= X-Microsoft-Antispam-Message-Info: 1ZUr4xHW9F5gZzjfuPBXJaijrvqweT9gWOfEd0e9mcyxWirWjMqiinp+L9MQ6WmRoRawLHyXbkqorUqtoZlVUnYX1PBHDGKyCFj7sZnzQO2SeozNsVgaJJ2ivTqCnbshiJR6c/jDMOHrt46lzrlBA/ySTkj2NfxlvFPGSEUHh21iPpq++s84Fhi1KX9TF61IGpoCzK4SnVoIYBg41ZK7hmhWtyIQ7sjySkEC86s+Zz/4dDGDNYWJRxw29gT9KNlhIZVyC/62Ubv0v5uYQkSp3gWKRPboFh9GfuFi38PO5U50644MH+24nZpoUllwea2Eh2w333DIy4tq0SRfawdNUCvVq5yD3itHiCR5exEVRTY= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:3GqOQO0jgFtD1qRB0zccXi0sz5A+Rx2xo4l+Xv1D0fyCMT9WriYe+k4jgnN+hcWfiL4xb4GEHJw2/wzMVJev3jaiXYz64yNaE588tua2zYRpJ0FKFR1+HBl9VYfaqejY1IqcsLGGV0OgzWVqqluINkNK03enjc8VageVCcWgUrOJVt55B3SWG+61PlYrhYEBaxZ4nq1edNjsL4jCrufcz5PEgwP3pgDkN75C397u8iCduc5HlEJRINHYpWJ0rKDz4z1QYtBdYH0iaCgVx5zji/vbNZi0GvqgdL3DS5NF9A9gfUJ4lpkUpbQ7AHBsPHaf3YB9JvQ6DVIvti7brcXcO+P5bIYuIiU7CqkyuArwzd8K2jDY1ltpZpYph38OvCbySeYdTaMw1yI+2GNeEIRWMl5krKoSsPALXeYvfp7D3lYyzHaGLyF0LY3NvSlj+6SWBDLwM/FBjzbwHyGpNFWYsw==; 5:zEHW+uHUrwAtmUDdinObah6PbL9NJjJQnYD73VqaSWdfYW9wZ5B68uG1ZG2uY1rzdScuHqaTq+bMFDTYGYp6/zU6VTJsWMdivq8IpCPqZ/i11syCj78GbPe6oMUFMZ8iylxTwgralLEl65ppq4PQ+h9Rd5yxLb/XBlAg3Kgk0AU=; 7:vzuoBTuSp5B3kKuoZXaie7405tV4hCgy6sxt0yI9+vZ8YHTWa/M5qaNmD8gPlFW7lkfu+Tu76BBXxoDcVAsXmBvSTfAwAn5qRfq1Z0weNEVcREoY0PTb0VjZhxiU7ihtzQB4ocB/W40zGToB50fiIa/TXSSZ+xpYj4ut7W+N/0eRSJ/b3EpvBK4LWBL6c3MwD9uWcc3NWvnwtd5N6+f385mZCD+VlJTFNbVO5n3crOWjgyFM+td8A1FDhMcMxPGL SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:51.5394 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d80f905-9c24-4b21-9401-08d61c899f26 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 05/11] bus/fslmc: support memory backed portals with QBMAN 5.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta Signed-off-by: Youri Querry Signed-off-by: Roy Pledge Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 180 ++--- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 4 + drivers/bus/fslmc/qbman/include/compat.h | 3 +- .../fslmc/qbman/include/fsl_qbman_portal.h | 31 +- drivers/bus/fslmc/qbman/qbman_portal.c | 764 +++++++++++++++--- drivers/bus/fslmc/qbman/qbman_portal.h | 30 +- drivers/bus/fslmc/qbman/qbman_sys.h | 100 ++- drivers/bus/fslmc/qbman/qbman_sys_decl.h | 4 + 8 files changed, 867 insertions(+), 249 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 99f70be1c..76f80b951 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * */ #include @@ -177,68 +177,6 @@ static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev) } #endif -static int -configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) -{ - struct qbman_swp_desc p_des; - struct dpio_attr attr; - - dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io)); - if (!dpio_dev->dpio) { - DPAA2_BUS_ERR("Memory allocation failure"); - return -1; - } - - dpio_dev->dpio->regs = dpio_dev->mc_portal; - if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id, - &dpio_dev->token)) { - DPAA2_BUS_ERR("Failed to allocate IO space"); - free(dpio_dev->dpio); - return -1; - } - - if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { - DPAA2_BUS_ERR("Failed to reset dpio"); - dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); - free(dpio_dev->dpio); - return -1; - } - - if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { - DPAA2_BUS_ERR("Failed to Enable dpio"); - dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); - free(dpio_dev->dpio); - return -1; - } - - if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW, - dpio_dev->token, &attr)) { - DPAA2_BUS_ERR("DPIO Get attribute failed"); - dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); - dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); - free(dpio_dev->dpio); - return -1; - } - - /* Configure & setup SW portal */ - p_des.block = NULL; - p_des.idx = attr.qbman_portal_id; - p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr); - p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr); - p_des.irq = -1; - p_des.qman_version = attr.qbman_version; - - dpio_dev->sw_portal = qbman_swp_init(&p_des); - if (dpio_dev->sw_portal == NULL) { - DPAA2_BUS_ERR("QBMan SW Portal Init failed"); - dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); - free(dpio_dev->dpio); - return -1; - } - - return 0; -} - static int dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id) { @@ -402,15 +340,17 @@ dpaa2_create_dpio_device(int vdev_fd, struct vfio_device_info *obj_info, int object_id) { - struct dpaa2_dpio_dev *dpio_dev; + struct dpaa2_dpio_dev *dpio_dev = NULL; struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; + struct qbman_swp_desc p_des; + struct dpio_attr attr; if (obj_info->num_regions < NUM_DPIO_REGIONS) { DPAA2_BUS_ERR("Not sufficient number of DPIO regions"); return -1; } - dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev), + dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev), RTE_CACHE_LINE_SIZE); if (!dpio_dev) { DPAA2_BUS_ERR("Memory allocation failed for DPIO Device"); @@ -423,45 +363,33 @@ dpaa2_create_dpio_device(int vdev_fd, /* Using single portal for all devices */ dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX]; - reg_info.index = 0; - if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { - DPAA2_BUS_ERR("vfio: error getting region info"); - rte_free(dpio_dev); - return -1; + dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io)); + if (!dpio_dev->dpio) { + DPAA2_BUS_ERR("Memory allocation failure"); + goto err; } - dpio_dev->ce_size = reg_info.size; - dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size, - PROT_WRITE | PROT_READ, MAP_SHARED, - vdev_fd, reg_info.offset); - - reg_info.index = 1; - if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { - DPAA2_BUS_ERR("vfio: error getting region info"); - rte_free(dpio_dev); - return -1; + dpio_dev->dpio->regs = dpio_dev->mc_portal; + if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id, + &dpio_dev->token)) { + DPAA2_BUS_ERR("Failed to allocate IO space"); + goto err; } - dpio_dev->ci_size = reg_info.size; - dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size, - PROT_WRITE | PROT_READ, MAP_SHARED, - vdev_fd, reg_info.offset); - - if (configure_dpio_qbman_swp(dpio_dev)) { - DPAA2_BUS_ERR( - "Fail to configure the dpio qbman portal for %d", - dpio_dev->hw_id); - rte_free(dpio_dev); - return -1; + if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + DPAA2_BUS_ERR("Failed to reset dpio"); + goto err; } - io_space_count++; - dpio_dev->index = io_space_count; + if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + DPAA2_BUS_ERR("Failed to Enable dpio"); + goto err; + } - if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) { - DPAA2_BUS_ERR("Fail to setup interrupt for %d", - dpio_dev->hw_id); - rte_free(dpio_dev); + if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW, + dpio_dev->token, &attr)) { + DPAA2_BUS_ERR("DPIO Get attribute failed"); + goto err; } /* find the SoC type for the first time */ @@ -483,9 +411,67 @@ dpaa2_create_dpio_device(int vdev_fd, dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000); } + if (dpaa2_svr_family == SVR_LX2160A) + reg_info.index = DPAA2_SWP_CENA_MEM_REGION; + else + reg_info.index = DPAA2_SWP_CENA_REGION; + + if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + DPAA2_BUS_ERR("vfio: error getting region info"); + goto err; + } + + dpio_dev->ce_size = reg_info.size; + dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + vdev_fd, reg_info.offset); + + reg_info.index = DPAA2_SWP_CINH_REGION; + if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + DPAA2_BUS_ERR("vfio: error getting region info"); + goto err; + } + + dpio_dev->ci_size = reg_info.size; + dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + vdev_fd, reg_info.offset); + + /* Configure & setup SW portal */ + p_des.block = NULL; + p_des.idx = attr.qbman_portal_id; + p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr); + p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr); + p_des.irq = -1; + p_des.qman_version = attr.qbman_version; + + dpio_dev->sw_portal = qbman_swp_init(&p_des); + if (dpio_dev->sw_portal == NULL) { + DPAA2_BUS_ERR("QBMan SW Portal Init failed"); + goto err; + } + + io_space_count++; + dpio_dev->index = io_space_count; + + if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) { + DPAA2_BUS_ERR("Fail to setup interrupt for %d", + dpio_dev->hw_id); + goto err; + } + TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next); return 0; + +err: + if (dpio_dev->dpio) { + dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + } + rte_free(dpio_dev); + return -1; } void diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index 820759360..f2eebe65d 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -37,6 +37,10 @@ #define DPAA2_DQRR_RING_SIZE 16 /** > 16) >> 16)) - #define __iomem #define __raw_readb(p) (*(const volatile unsigned char *)(p)) #define __raw_readl(p) (*(const volatile unsigned int *)(p)) #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); } +#define dma_wmb() rte_smp_mb() + #define atomic_t rte_atomic32_t #define atomic_read(v) rte_atomic32_read(v) #define atomic_set(v, i) rte_atomic32_set(v, i) diff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h index 3e63db3ab..7370e53e0 100644 --- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h +++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h @@ -42,6 +42,15 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d); */ void qbman_swp_finish(struct qbman_swp *p); +/** + * qbman_swp_invalidate() - Invalidate the cache enabled area of the QBMan + * portal. This is required to be called if a portal moved to another core + * because the QBMan portal area is non coherent + * @p: the qbman_swp object to be invalidated + * + */ +void qbman_swp_invalidate(struct qbman_swp *p); + /** * qbman_swp_get_desc() - Get the descriptor of the given portal object. * @p: the given portal object. @@ -172,7 +181,7 @@ void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit); /** * struct qbman_result - structure for qbman dequeue response and/or * notification. - * @donot_manipulate_directly: the 16 32bit data to represent the whole + * @dont_manipulate_directly: the 16 32bit data to represent the whole * possible qbman dequeue result. */ struct qbman_result { @@ -262,7 +271,7 @@ void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable); */ struct qbman_pull_desc { union { - uint32_t donot_manipulate_directly[16]; + uint32_t dont_manipulate_directly[16]; struct pull { uint8_t verb; uint8_t numf; @@ -355,6 +364,14 @@ void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid, void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid, enum qbman_pull_type_e dct); +/** + * qbman_pull_desc_set_rad() - Decide whether reschedule the fq after dequeue + * + * @rad: 1 = Reschedule the FQ after dequeue. + * 0 = Allow the FQ to remain active after dequeue. + */ +void qbman_pull_desc_set_rad(struct qbman_pull_desc *d, int rad); + /** * qbman_swp_pull() - Issue the pull dequeue command * @s: the software portal object. @@ -775,7 +792,7 @@ uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn); /* struct qbman_eq_desc - structure of enqueue descriptor */ struct qbman_eq_desc { union { - uint32_t donot_manipulate_directly[8]; + uint32_t dont_manipulate_directly[8]; struct eq { uint8_t verb; uint8_t dca; @@ -796,11 +813,11 @@ struct qbman_eq_desc { /** * struct qbman_eq_response - structure of enqueue response - * @donot_manipulate_directly: the 16 32bit data to represent the whole + * @dont_manipulate_directly: the 16 32bit data to represent the whole * enqueue response. */ struct qbman_eq_response { - uint32_t donot_manipulate_directly[16]; + uint32_t dont_manipulate_directly[16]; }; /** @@ -998,12 +1015,12 @@ int qbman_swp_enqueue_thresh(struct qbman_swp *s, unsigned int thresh); /*******************/ /** * struct qbman_release_desc - The structure for buffer release descriptor - * @donot_manipulate_directly: the 32bit data to represent the whole + * @dont_manipulate_directly: the 32bit data to represent the whole * possible settings of qbman release descriptor. */ struct qbman_release_desc { union { - uint32_t donot_manipulate_directly[16]; + uint32_t dont_manipulate_directly[16]; struct br { uint8_t verb; uint8_t reserved; diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index 071450052..3380e54f5 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -1,39 +1,17 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ +#include "qbman_sys.h" #include "qbman_portal.h" /* QBMan portal management command codes */ #define QBMAN_MC_ACQUIRE 0x30 #define QBMAN_WQCHAN_CONFIGURE 0x46 -/* CINH register offsets */ -#define QBMAN_CINH_SWP_EQCR_PI 0x800 -#define QBMAN_CINH_SWP_EQCR_CI 0x840 -#define QBMAN_CINH_SWP_EQAR 0x8c0 -#define QBMAN_CINH_SWP_DQPI 0xa00 -#define QBMAN_CINH_SWP_DCAP 0xac0 -#define QBMAN_CINH_SWP_SDQCR 0xb00 -#define QBMAN_CINH_SWP_RAR 0xcc0 -#define QBMAN_CINH_SWP_ISR 0xe00 -#define QBMAN_CINH_SWP_IER 0xe40 -#define QBMAN_CINH_SWP_ISDR 0xe80 -#define QBMAN_CINH_SWP_IIR 0xec0 -#define QBMAN_CINH_SWP_DQRR_ITR 0xa80 -#define QBMAN_CINH_SWP_ITPR 0xf40 - -/* CENA register offsets */ -#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) -#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) -#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6)) -#define QBMAN_CENA_SWP_CR 0x600 -#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) -#define QBMAN_CENA_SWP_VDQCR 0x780 -#define QBMAN_CENA_SWP_EQCR_CI 0x840 - /* Reverse mapping of QBMAN_CENA_SWP_DQRR() */ #define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6) @@ -83,6 +61,102 @@ enum qbman_sdqcr_fc { #define MAX_QBMAN_PORTALS 64 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS]; +/* Internal Function declaration */ +static int +qbman_swp_enqueue_array_mode_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd); +static int +qbman_swp_enqueue_array_mode_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd); + +static int +qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd); +static int +qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd); + +static int +qbman_swp_enqueue_multiple_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames); +static int +qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames); + +static int +qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames); +static int +qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames); + +static int +qbman_swp_pull_direct(struct qbman_swp *s, struct qbman_pull_desc *d); +static int +qbman_swp_pull_mem_back(struct qbman_swp *s, struct qbman_pull_desc *d); + +const struct qbman_result *qbman_swp_dqrr_next_direct(struct qbman_swp *s); +const struct qbman_result *qbman_swp_dqrr_next_mem_back(struct qbman_swp *s); + +static int +qbman_swp_release_direct(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, unsigned int num_buffers); +static int +qbman_swp_release_mem_back(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, unsigned int num_buffers); + +/* Function pointers */ +static int (*qbman_swp_enqueue_array_mode_ptr)(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) + = qbman_swp_enqueue_array_mode_direct; + +static int (*qbman_swp_enqueue_ring_mode_ptr)(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) + = qbman_swp_enqueue_ring_mode_direct; + +static int (*qbman_swp_enqueue_multiple_ptr)(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames) + = qbman_swp_enqueue_multiple_direct; + +static int (*qbman_swp_enqueue_multiple_desc_ptr)(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) + = qbman_swp_enqueue_multiple_desc_direct; + +static int (*qbman_swp_pull_ptr)(struct qbman_swp *s, + struct qbman_pull_desc *d) + = qbman_swp_pull_direct; + +const struct qbman_result *(*qbman_swp_dqrr_next_ptr)(struct qbman_swp *s) + = qbman_swp_dqrr_next_direct; + +static int (*qbman_swp_release_ptr)(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, unsigned int num_buffers) + = qbman_swp_release_direct; + /*********************************/ /* Portal constructor/destructor */ /*********************************/ @@ -104,25 +178,30 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) { int ret; uint32_t eqcr_pi; + uint32_t mask_size; struct qbman_swp *p = malloc(sizeof(*p)); if (!p) return NULL; + + memset(p, 0, sizeof(struct qbman_swp)); + p->desc = *d; #ifdef QBMAN_CHECKING p->mc.check = swp_mc_can_start; #endif p->mc.valid_bit = QB_VALID_BIT; - p->sdq = 0; p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT; p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT; p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT; + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000) + p->mr.valid_bit = QB_VALID_BIT; atomic_set(&p->vdq.busy, 1); p->vdq.valid_bit = QB_VALID_BIT; - p->dqrr.next_idx = 0; p->dqrr.valid_bit = QB_VALID_BIT; - if ((p->desc.qman_version & 0xFFFF0000) < QMAN_REV_4100) { + qman_version = p->desc.qman_version; + if ((qman_version & 0xFFFF0000) < QMAN_REV_4100) { p->dqrr.dqrr_size = 4; p->dqrr.reset_bug = 1; } else { @@ -136,18 +215,54 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d) pr_err("qbman_swp_sys_init() failed %d\n", ret); return NULL; } + + /* Verify that the DQRRPI is 0 - if it is not the portal isn't + * in default state which is an error + */ + if (qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQPI) & 0xF) { + pr_err("qbman DQRR PI is not zero, portal is not clean\n"); + free(p); + return NULL; + } + /* SDQCR needs to be initialized to 0 when no channels are * being dequeued from or else the QMan HW will indicate an * error. The values that were calculated above will be * applied when dequeues from a specific channel are enabled. */ qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0); + + p->eqcr.pi_ring_size = 8; + if ((qman_version & 0xFFFF0000) >= QMAN_REV_5000) { + p->eqcr.pi_ring_size = 32; + qbman_swp_enqueue_array_mode_ptr = + qbman_swp_enqueue_array_mode_mem_back; + qbman_swp_enqueue_ring_mode_ptr = + qbman_swp_enqueue_ring_mode_mem_back; + qbman_swp_enqueue_multiple_ptr = + qbman_swp_enqueue_multiple_mem_back; + qbman_swp_enqueue_multiple_desc_ptr = + qbman_swp_enqueue_multiple_desc_mem_back; + qbman_swp_pull_ptr = qbman_swp_pull_mem_back; + qbman_swp_dqrr_next_ptr = qbman_swp_dqrr_next_mem_back; + qbman_swp_release_ptr = qbman_swp_release_mem_back; + } + + for (mask_size = p->eqcr.pi_ring_size; mask_size > 0; mask_size >>= 1) + p->eqcr.pi_mask = (p->eqcr.pi_mask<<1) + 1; eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI); - p->eqcr.pi = eqcr_pi & 0xF; + p->eqcr.pi = eqcr_pi & p->eqcr.pi_mask; p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT; - p->eqcr.ci = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_CI) & 0xF; - p->eqcr.available = QBMAN_EQCR_SIZE - qm_cyc_diff(QBMAN_EQCR_SIZE, - p->eqcr.ci, p->eqcr.pi); + if ((p->desc.qman_version & QMAN_REV_MASK) < QMAN_REV_5000) + p->eqcr.ci = qbman_cinh_read(&p->sys, + QBMAN_CINH_SWP_EQCR_CI) & p->eqcr.pi_mask; + else + p->eqcr.ci = qbman_cinh_read(&p->sys, + QBMAN_CINH_SWP_EQCR_PI) & p->eqcr.pi_mask; + p->eqcr.available = p->eqcr.pi_ring_size - + qm_cyc_diff(p->eqcr.pi_ring_size, + p->eqcr.ci & (p->eqcr.pi_mask<<1), + p->eqcr.pi & (p->eqcr.pi_mask<<1)); portal_idx_map[p->desc.idx] = p; return p; @@ -229,7 +344,8 @@ int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p) void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit) { - qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0); + qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, + inhibit ? 0xffffffff : 0); } /***********************/ @@ -246,7 +362,10 @@ void *qbman_swp_mc_start(struct qbman_swp *p) #ifdef QBMAN_CHECKING QBMAN_BUG_ON(p->mc.check != swp_mc_can_start); #endif - ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); + if ((p->desc.qman_version & QMAN_REV_MASK) < QMAN_REV_5000) + ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR); + else + ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR_MEM); #ifdef QBMAN_CHECKING if (!ret) p->mc.check = swp_mc_can_submit; @@ -266,8 +385,17 @@ void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb) * caller wants to OR but has forgotten to do so. */ QBMAN_BUG_ON((*v & cmd_verb) != *v); - *v = cmd_verb | p->mc.valid_bit; - qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd); + if ((p->desc.qman_version & QMAN_REV_MASK) < QMAN_REV_5000) { + dma_wmb(); + *v = cmd_verb | p->mc.valid_bit; + qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd); + clean(cmd); + } else { + *v = cmd_verb | p->mr.valid_bit; + qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR_MEM, cmd); + dma_wmb(); + qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_CR_RT, QMAN_RT_MODE); + } #ifdef QBMAN_CHECKING p->mc.check = swp_mc_can_poll; #endif @@ -279,17 +407,34 @@ void *qbman_swp_mc_result(struct qbman_swp *p) #ifdef QBMAN_CHECKING QBMAN_BUG_ON(p->mc.check != swp_mc_can_poll); #endif - qbman_cena_invalidate_prefetch(&p->sys, - QBMAN_CENA_SWP_RR(p->mc.valid_bit)); - ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit)); - /* Remove the valid-bit - command completed if the rest is non-zero */ - verb = ret[0] & ~QB_VALID_BIT; - if (!verb) - return NULL; + if ((p->desc.qman_version & QMAN_REV_MASK) < QMAN_REV_5000) { + qbman_cena_invalidate_prefetch(&p->sys, + QBMAN_CENA_SWP_RR(p->mc.valid_bit)); + ret = qbman_cena_read(&p->sys, + QBMAN_CENA_SWP_RR(p->mc.valid_bit)); + /* Remove the valid-bit - + * command completed iff the rest is non-zero + */ + verb = ret[0] & ~QB_VALID_BIT; + if (!verb) + return NULL; + p->mc.valid_bit ^= QB_VALID_BIT; + } else { + ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR_MEM); + /* Command completed if the valid bit is toggled */ + if (p->mr.valid_bit != (ret[0] & QB_VALID_BIT)) + return NULL; + /* Remove the valid-bit - + * command completed iff the rest is non-zero + */ + verb = ret[0] & ~QB_VALID_BIT; + if (!verb) + return NULL; + p->mr.valid_bit ^= QB_VALID_BIT; + } #ifdef QBMAN_CHECKING p->mc.check = swp_mc_can_start; #endif - p->mc.valid_bit ^= QB_VALID_BIT; return ret; } @@ -417,13 +562,26 @@ void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable, } } -#define EQAR_IDX(eqar) ((eqar) & 0x7) +#define EQAR_IDX(eqar) ((eqar) & 0x1f) #define EQAR_VB(eqar) ((eqar) & 0x80) #define EQAR_SUCCESS(eqar) ((eqar) & 0x100) -static int qbman_swp_enqueue_array_mode(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd) +static inline void qbman_write_eqcr_am_rt_register(struct qbman_swp *p, + uint8_t idx) +{ + if (idx < 16) + qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_EQCR_AM_RT + idx * 4, + QMAN_RT_MODE); + else + qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_EQCR_AM_RT2 + + (idx - 16) * 4, + QMAN_RT_MODE); +} + + +static int qbman_swp_enqueue_array_mode_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) { uint32_t *p; const uint32_t *cl = qb_cl(d); @@ -433,39 +591,69 @@ static int qbman_swp_enqueue_array_mode(struct qbman_swp *s, if (!EQAR_SUCCESS(eqar)) return -EBUSY; p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], fd, sizeof(*fd)); + /* Set the verb byte, have to substitute in the valid-bit */ - lwsync(); + dma_wmb(); p[0] = cl[0] | EQAR_VB(eqar); qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); return 0; } +static int qbman_swp_enqueue_array_mode_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR); -static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd) + pr_debug("EQAR=%08x\n", eqar); + if (!EQAR_SUCCESS(eqar)) + return -EBUSY; + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar))); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], fd, sizeof(*fd)); + + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | EQAR_VB(eqar); + dma_wmb(); + qbman_write_eqcr_am_rt_register(s, EQAR_IDX(eqar)); + return 0; +} + +static inline int qbman_swp_enqueue_array_mode(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + return qbman_swp_enqueue_array_mode_ptr(s, d, fd); +} + +static int qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) { uint32_t *p; const uint32_t *cl = qb_cl(d); - uint32_t eqcr_ci; - uint8_t diff; + uint32_t eqcr_ci, full_mask, half_mask; + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; if (!s->eqcr.available) { eqcr_ci = s->eqcr.ci; s->eqcr.ci = qbman_cena_read_reg(&s->sys, - QBMAN_CENA_SWP_EQCR_CI) & 0xF; - diff = qm_cyc_diff(QBMAN_EQCR_SIZE, - eqcr_ci, s->eqcr.ci); - s->eqcr.available += diff; - if (!diff) + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) return -EBUSY; } p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], fd, sizeof(*fd)); lwsync(); @@ -473,16 +661,61 @@ static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, /* Set the verb byte, have to substitute in the valid-bit */ p[0] = cl[0] | s->eqcr.pi_vb; qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7)); + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); s->eqcr.pi++; - s->eqcr.pi &= 0xF; + s->eqcr.pi &= full_mask; s->eqcr.available--; - if (!(s->eqcr.pi & 7)) + if (!(s->eqcr.pi & half_mask)) s->eqcr.pi_vb ^= QB_VALID_BIT; return 0; } +static int qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t eqcr_ci, full_mask, half_mask; + + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return -EBUSY; + } + + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask)); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], fd, sizeof(*fd)); + + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | s->eqcr.pi_vb; + s->eqcr.pi++; + s->eqcr.pi &= full_mask; + s->eqcr.available--; + if (!(s->eqcr.pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + dma_wmb(); + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_EQCR_PI, + (QB_RT_BIT)|(s->eqcr.pi)|s->eqcr.pi_vb); + return 0; +} + +static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd) +{ + return qbman_swp_enqueue_ring_mode_ptr(s, d, fd); +} + int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, const struct qbman_fd *fd) { @@ -492,27 +725,27 @@ int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d, return qbman_swp_enqueue_ring_mode(s, d, fd); } -int qbman_swp_enqueue_multiple(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - uint32_t *flags, - int num_frames) +static int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames) { - uint32_t *p; + uint32_t *p = NULL; const uint32_t *cl = qb_cl(d); - uint32_t eqcr_ci, eqcr_pi; - uint8_t diff; + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; int i, num_enqueued = 0; uint64_t addr_cena; + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; if (!s->eqcr.available) { eqcr_ci = s->eqcr.ci; s->eqcr.ci = qbman_cena_read_reg(&s->sys, - QBMAN_CENA_SWP_EQCR_CI) & 0xF; - diff = qm_cyc_diff(QBMAN_EQCR_SIZE, - eqcr_ci, s->eqcr.ci); - s->eqcr.available += diff; - if (!diff) + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) return 0; } @@ -523,11 +756,10 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, /* Fill in the EQCR ring */ for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], &fd[i], sizeof(*fd)); eqcr_pi++; - eqcr_pi &= 0xF; } lwsync(); @@ -536,7 +768,7 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, eqcr_pi = s->eqcr.pi; for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); p[0] = cl[0] | s->eqcr.pi_vb; if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; @@ -545,8 +777,7 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); } eqcr_pi++; - eqcr_pi &= 0xF; - if (!(eqcr_pi & 7)) + if (!(eqcr_pi & half_mask)) s->eqcr.pi_vb ^= QB_VALID_BIT; } @@ -554,35 +785,104 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, eqcr_pi = s->eqcr.pi; addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((uintptr_t)(addr_cena + + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask))); eqcr_pi++; - eqcr_pi &= 0xF; } - s->eqcr.pi = eqcr_pi; + s->eqcr.pi = eqcr_pi & full_mask; return num_enqueued; } -int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, - const struct qbman_eq_desc *d, - const struct qbman_fd *fd, - int num_frames) +static int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames) +{ + uint32_t *p = NULL; + const uint32_t *cl = qb_cl(d); + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; + int i, num_enqueued = 0; + + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return 0; + } + + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], &fd[i], sizeof(*fd)); + eqcr_pi++; + } + + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + p[0] = cl[0] | s->eqcr.pi_vb; + if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { + struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; + + d->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | + ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); + } + eqcr_pi++; + if (!(eqcr_pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; + } + s->eqcr.pi = eqcr_pi & full_mask; + + dma_wmb(); + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_EQCR_PI, + (QB_RT_BIT)|(s->eqcr.pi)|s->eqcr.pi_vb); + return num_enqueued; +} + +inline int qbman_swp_enqueue_multiple(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + uint32_t *flags, + int num_frames) +{ + return qbman_swp_enqueue_multiple_ptr(s, d, fd, flags, num_frames); +} + +static int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) { uint32_t *p; const uint32_t *cl; - uint32_t eqcr_ci, eqcr_pi; - uint8_t diff; + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; int i, num_enqueued = 0; uint64_t addr_cena; + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; if (!s->eqcr.available) { eqcr_ci = s->eqcr.ci; s->eqcr.ci = qbman_cena_read_reg(&s->sys, - QBMAN_CENA_SWP_EQCR_CI) & 0xF; - diff = qm_cyc_diff(QBMAN_EQCR_SIZE, - eqcr_ci, s->eqcr.ci); - s->eqcr.available += diff; - if (!diff) + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) return 0; } @@ -593,12 +893,11 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, /* Fill in the EQCR ring */ for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); cl = qb_cl(&d[i]); memcpy(&p[1], &cl[1], 28); memcpy(&p[8], &fd[i], sizeof(*fd)); eqcr_pi++; - eqcr_pi &= 0xF; } lwsync(); @@ -607,12 +906,11 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, eqcr_pi = s->eqcr.pi; for (i = 0; i < num_enqueued; i++) { p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)); + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); cl = qb_cl(&d[i]); p[0] = cl[0] | s->eqcr.pi_vb; eqcr_pi++; - eqcr_pi &= 0xF; - if (!(eqcr_pi & 7)) + if (!(eqcr_pi & half_mask)) s->eqcr.pi_vb ^= QB_VALID_BIT; } @@ -620,14 +918,78 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, eqcr_pi = s->eqcr.pi; addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((uintptr_t)(addr_cena + + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask))); + eqcr_pi++; + } + s->eqcr.pi = eqcr_pi & full_mask; + + return num_enqueued; +} + +static int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) +{ + uint32_t *p; + const uint32_t *cl; + uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask; + int i, num_enqueued = 0; + + half_mask = (s->eqcr.pi_mask>>1); + full_mask = s->eqcr.pi_mask; + if (!s->eqcr.available) { + eqcr_ci = s->eqcr.ci; + s->eqcr.ci = qbman_cinh_read(&s->sys, + QBMAN_CENA_SWP_EQCR_CI) & full_mask; + s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size, + eqcr_ci, s->eqcr.ci); + if (!s->eqcr.available) + return 0; + } + + eqcr_pi = s->eqcr.pi; + num_enqueued = (s->eqcr.available < num_frames) ? + s->eqcr.available : num_frames; + s->eqcr.available -= num_enqueued; + /* Fill in the EQCR ring */ + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + cl = qb_cl(&d[i]); + memcpy(&p[1], &cl[1], 28); + memcpy(&p[8], &fd[i], sizeof(*fd)); + eqcr_pi++; + } + + /* Set the verb byte, have to substitute in the valid-bit */ + eqcr_pi = s->eqcr.pi; + for (i = 0; i < num_enqueued; i++) { + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); + cl = qb_cl(&d[i]); + p[0] = cl[0] | s->eqcr.pi_vb; eqcr_pi++; - eqcr_pi &= 0xF; + if (!(eqcr_pi & half_mask)) + s->eqcr.pi_vb ^= QB_VALID_BIT; } - s->eqcr.pi = eqcr_pi; + + s->eqcr.pi = eqcr_pi & full_mask; + + dma_wmb(); + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_EQCR_PI, + (QB_RT_BIT)|(s->eqcr.pi)|s->eqcr.pi_vb); return num_enqueued; } +inline int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, + const struct qbman_eq_desc *d, + const struct qbman_fd *fd, + int num_frames) +{ + return qbman_swp_enqueue_multiple_desc_ptr(s, d, fd, num_frames); +} /*************************/ /* Static (push) dequeue */ @@ -670,6 +1032,7 @@ void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable) #define QB_VDQCR_VERB_DT_SHIFT 2 #define QB_VDQCR_VERB_RLS_SHIFT 4 #define QB_VDQCR_VERB_WAE_SHIFT 5 +#define QB_VDQCR_VERB_RAD_SHIFT 6 enum qb_pull_dt_e { qb_pull_dt_channel, @@ -702,7 +1065,8 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, d->pull.rsp_addr = storage_phys; } -void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes) +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, + uint8_t numframes) { d->pull.numf = numframes - 1; } @@ -735,7 +1099,20 @@ void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid, d->pull.dq_src = chid; } -int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) +void qbman_pull_desc_set_rad(struct qbman_pull_desc *d, int rad) +{ + if (d->pull.verb & (1 << QB_VDQCR_VERB_RLS_SHIFT)) { + if (rad) + d->pull.verb |= 1 << QB_VDQCR_VERB_RAD_SHIFT; + else + d->pull.verb &= ~(1 << QB_VDQCR_VERB_RAD_SHIFT); + } else { + printf("The RAD feature is not valid when RLS = 0\n"); + } +} + +static int qbman_swp_pull_direct(struct qbman_swp *s, + struct qbman_pull_desc *d) { uint32_t *p; uint32_t *cl = qb_cl(d); @@ -759,6 +1136,36 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) return 0; } +static int qbman_swp_pull_mem_back(struct qbman_swp *s, + struct qbman_pull_desc *d) +{ + uint32_t *p; + uint32_t *cl = qb_cl(d); + + if (!atomic_dec_and_test(&s->vdq.busy)) { + atomic_inc(&s->vdq.busy); + return -EBUSY; + } + + d->pull.tok = s->sys.idx + 1; + s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt; + p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR_MEM); + memcpy(&p[1], &cl[1], 12); + + /* Set the verb byte, have to substitute in the valid-bit */ + p[0] = cl[0] | s->vdq.valid_bit; + s->vdq.valid_bit ^= QB_VALID_BIT; + dma_wmb(); + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_VDQCR_RT, QMAN_RT_MODE); + + return 0; +} + +inline int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) +{ + return qbman_swp_pull_ptr(s, d); +} + /****************/ /* Polling DQRR */ /****************/ @@ -791,7 +1198,12 @@ void qbman_swp_prefetch_dqrr_next(struct qbman_swp *s) * only once, so repeated calls can return a sequence of DQRR entries, without * requiring they be consumed immediately or in any particular order. */ -const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) +inline const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) +{ + return qbman_swp_dqrr_next_ptr(s); +} + +const struct qbman_result *qbman_swp_dqrr_next_direct(struct qbman_swp *s) { uint32_t verb; uint32_t response_verb; @@ -801,7 +1213,7 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) /* Before using valid-bit to detect if something is there, we have to * handle the case of the DQRR reset bug... */ - if (unlikely(s->dqrr.reset_bug)) { + if (s->dqrr.reset_bug) { /* We pick up new entries by cache-inhibited producer index, * which means that a non-coherent mapping would require us to * invalidate and read *only* once that PI has indicated that @@ -833,7 +1245,8 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); } p = qbman_cena_read_wo_shadow(&s->sys, - QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)); + verb = p->dq.verb; /* If the valid-bit isn't of the expected polarity, nothing there. Note, @@ -867,11 +1280,54 @@ const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s) return p; } +const struct qbman_result *qbman_swp_dqrr_next_mem_back(struct qbman_swp *s) +{ + uint32_t verb; + uint32_t response_verb; + uint32_t flags; + const struct qbman_result *p; + + p = qbman_cena_read_wo_shadow(&s->sys, + QBMAN_CENA_SWP_DQRR_MEM(s->dqrr.next_idx)); + + verb = p->dq.verb; + + /* If the valid-bit isn't of the expected polarity, nothing there. Note, + * in the DQRR reset bug workaround, we shouldn't need to skip these + * check, because we've already determined that a new entry is available + * and we've invalidated the cacheline before reading it, so the + * valid-bit behaviour is repaired and should tell us what we already + * knew from reading PI. + */ + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) + return NULL; + + /* There's something there. Move "next_idx" attention to the next ring + * entry (and prefetch it) before returning what we found. + */ + s->dqrr.next_idx++; + if (s->dqrr.next_idx == s->dqrr.dqrr_size) { + s->dqrr.next_idx = 0; + s->dqrr.valid_bit ^= QB_VALID_BIT; + } + /* If this is the final response to a volatile dequeue command + * indicate that the vdq is no longer busy + */ + flags = p->dq.stat; + response_verb = verb & QBMAN_RESPONSE_VERB_MASK; + if ((response_verb == QBMAN_RESULT_DQ) && + (flags & QBMAN_DQ_STAT_VOLATILE) && + (flags & QBMAN_DQ_STAT_EXPIRED)) + atomic_inc(&s->vdq.busy); + return p; +} + /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct qbman_result *dq) { - qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq)); + qbman_cinh_write(&s->sys, + QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq)); } /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */ @@ -884,6 +1340,7 @@ void qbman_swp_dqrr_idx_consume(struct qbman_swp *s, /*********************************/ /* Polling user-provided storage */ /*********************************/ + int qbman_result_has_new_result(struct qbman_swp *s, struct qbman_result *dq) { @@ -898,11 +1355,11 @@ int qbman_result_has_new_result(struct qbman_swp *s, ((struct qbman_result *)dq)->dq.tok = 0; /* - * VDQCR "no longer busy" hook - not quite the same as DQRR, because the - * fact "VDQCR" shows busy doesn't mean that we hold the result that - * makes it available. Eg. we may be looking at our 10th dequeue result, - * having released VDQCR after the 1st result and it is now busy due to - * some other command! + * VDQCR "no longer busy" hook - not quite the same as DQRR, because + * the fact "VDQCR" shows busy doesn't mean that we hold the result + * that makes it available. Eg. we may be looking at our 10th dequeue + * result, having released VDQCR after the 1st result and it is now + * busy due to some other command! */ if (s->vdq.storage == dq) { s->vdq.storage = NULL; @@ -936,11 +1393,11 @@ int qbman_check_command_complete(struct qbman_result *dq) s = portal_idx_map[dq->dq.tok - 1]; /* - * VDQCR "no longer busy" hook - not quite the same as DQRR, because the - * fact "VDQCR" shows busy doesn't mean that we hold the result that - * makes it available. Eg. we may be looking at our 10th dequeue result, - * having released VDQCR after the 1st result and it is now busy due to - * some other command! + * VDQCR "no longer busy" hook - not quite the same as DQRR, because + * the fact "VDQCR" shows busy doesn't mean that we hold the result + * that makes it available. Eg. we may be looking at our 10th dequeue + * result, having released VDQCR after the 1st result and it is now + * busy due to some other command! */ if (s->vdq.storage == dq) { s->vdq.storage = NULL; @@ -1142,8 +1599,10 @@ void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable) #define RAR_VB(rar) ((rar) & 0x80) #define RAR_SUCCESS(rar) ((rar) & 0x100) -int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, - const uint64_t *buffers, unsigned int num_buffers) +static int qbman_swp_release_direct(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, + unsigned int num_buffers) { uint32_t *p; const uint32_t *cl = qb_cl(d); @@ -1157,22 +1616,63 @@ int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d, /* Start the release command */ p = qbman_cena_write_start_wo_shadow(&s->sys, - QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); /* Copy the caller's buffer pointers to the command */ u64_to_le32_copy(&p[2], buffers, num_buffers); - /* Set the verb byte, have to substitute in the valid-bit and the number - * of buffers. + /* Set the verb byte, have to substitute in the valid-bit and the + * number of buffers. */ lwsync(); p[0] = cl[0] | RAR_VB(rar) | num_buffers; qbman_cena_write_complete_wo_shadow(&s->sys, - QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); + QBMAN_CENA_SWP_RCR(RAR_IDX(rar))); return 0; } +static int qbman_swp_release_mem_back(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, + unsigned int num_buffers) +{ + uint32_t *p; + const uint32_t *cl = qb_cl(d); + uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR); + + pr_debug("RAR=%08x\n", rar); + if (!RAR_SUCCESS(rar)) + return -EBUSY; + + QBMAN_BUG_ON(!num_buffers || (num_buffers > 7)); + + /* Start the release command */ + p = qbman_cena_write_start_wo_shadow(&s->sys, + QBMAN_CENA_SWP_RCR_MEM(RAR_IDX(rar))); + + /* Copy the caller's buffer pointers to the command */ + u64_to_le32_copy(&p[2], buffers, num_buffers); + + /* Set the verb byte, have to substitute in the valid-bit and the + * number of buffers. + */ + p[0] = cl[0] | RAR_VB(rar) | num_buffers; + lwsync(); + qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_RCR_AM_RT + + RAR_IDX(rar) * 4, QMAN_RT_MODE); + + return 0; +} + +inline int qbman_swp_release(struct qbman_swp *s, + const struct qbman_release_desc *d, + const uint64_t *buffers, + unsigned int num_buffers) +{ + return qbman_swp_release_ptr(s, d, buffers, num_buffers); +} + /*******************/ /* Buffer acquires */ /*******************/ @@ -1214,7 +1714,7 @@ int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, /* Complete the management command */ r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE); - if (unlikely(!r)) { + if (!r) { pr_err("qbman: acquire from BPID %d failed, no response\n", bpid); return -EIO; @@ -1224,7 +1724,7 @@ int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers, QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE); /* Determine success or failure */ - if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { + if (r->rslt != QBMAN_MC_RSLT_OK) { pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n", bpid, r->rslt); return -EIO; @@ -1271,7 +1771,7 @@ static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid, /* Complete the management command */ r = qbman_swp_mc_complete(s, p, alt_fq_verb); - if (unlikely(!r)) { + if (!r) { pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n", alt_fq_verb); return -EIO; @@ -1281,7 +1781,7 @@ static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid, QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != alt_fq_verb); /* Determine success or failure */ - if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { + if (r->rslt != QBMAN_MC_RSLT_OK) { pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n", fqid, alt_fq_verb, r->rslt); return -EIO; @@ -1362,7 +1862,7 @@ static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid, /* Complete the management command */ r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE); - if (unlikely(!r)) { + if (!r) { pr_err("qbman: wqchan config failed, no response\n"); return -EIO; } @@ -1372,7 +1872,7 @@ static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid, != QBMAN_WQCHAN_CONFIGURE); /* Determine success or failure */ - if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) { + if (r->rslt != QBMAN_MC_RSLT_OK) { pr_err("CDAN cQID %d failed: code = 0x%02x\n", channelid, r->rslt); return -EIO; diff --git a/drivers/bus/fslmc/qbman/qbman_portal.h b/drivers/bus/fslmc/qbman/qbman_portal.h index dbea22a1b..3b0fc540b 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.h +++ b/drivers/bus/fslmc/qbman/qbman_portal.h @@ -1,12 +1,17 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ +#ifndef _QBMAN_PORTAL_H_ +#define _QBMAN_PORTAL_H_ + #include "qbman_sys.h" #include +uint32_t qman_version; #define QMAN_REV_4000 0x04000000 #define QMAN_REV_4100 0x04010000 #define QMAN_REV_4101 0x04010001 @@ -14,13 +19,14 @@ /* All QBMan command and result structures use this "valid bit" encoding */ #define QB_VALID_BIT ((uint32_t)0x80) +/* All QBMan command use this "Read trigger bit" encoding */ +#define QB_RT_BIT ((uint32_t)0x100) + /* Management command result codes */ #define QBMAN_MC_RSLT_OK 0xf0 /* QBMan DQRR size is set at runtime in qbman_portal.c */ -#define QBMAN_EQCR_SIZE 8 - static inline uint8_t qm_cyc_diff(uint8_t ringsize, uint8_t first, uint8_t last) { @@ -51,6 +57,10 @@ struct qbman_swp { #endif uint32_t valid_bit; /* 0x00 or 0x80 */ } mc; + /* Management response */ + struct { + uint32_t valid_bit; /* 0x00 or 0x80 */ + } mr; /* Push dequeues */ uint32_t sdq; /* Volatile dequeues */ @@ -87,6 +97,8 @@ struct qbman_swp { struct { uint32_t pi; uint32_t pi_vb; + uint32_t pi_ring_size; + uint32_t pi_mask; uint32_t ci; int available; } eqcr; @@ -141,4 +153,16 @@ static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd, * an inline) is necessary to work with different descriptor types and to work * correctly with const and non-const inputs (and similarly-qualified outputs). */ -#define qb_cl(d) (&(d)->donot_manipulate_directly[0]) +#define qb_cl(d) (&(d)->dont_manipulate_directly[0]) + +#ifdef RTE_ARCH_ARM64 + #define clean(p) \ + { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); } + #define invalidate(p) \ + { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); } +#else + #define clean(p) + #define invalidate(p) +#endif + +#endif diff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h index 2bd33ea56..d41af8358 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys.h +++ b/drivers/bus/fslmc/qbman/qbman_sys.h @@ -18,11 +18,51 @@ * *not* to provide linux compatibility. */ +#ifndef _QBMAN_SYS_H_ +#define _QBMAN_SYS_H_ + #include "qbman_sys_decl.h" #define CENA_WRITE_ENABLE 0 #define CINH_WRITE_ENABLE 1 +/* CINH register offsets */ +#define QBMAN_CINH_SWP_EQCR_PI 0x800 +#define QBMAN_CINH_SWP_EQCR_CI 0x840 +#define QBMAN_CINH_SWP_EQAR 0x8c0 +#define QBMAN_CINH_SWP_CR_RT 0x900 +#define QBMAN_CINH_SWP_VDQCR_RT 0x940 +#define QBMAN_CINH_SWP_EQCR_AM_RT 0x980 +#define QBMAN_CINH_SWP_RCR_AM_RT 0x9c0 +#define QBMAN_CINH_SWP_DQPI 0xa00 +#define QBMAN_CINH_SWP_DQRR_ITR 0xa80 +#define QBMAN_CINH_SWP_DCAP 0xac0 +#define QBMAN_CINH_SWP_SDQCR 0xb00 +#define QBMAN_CINH_SWP_EQCR_AM_RT2 0xb40 +#define QBMAN_CINH_SWP_RCR_PI 0xc00 +#define QBMAN_CINH_SWP_RAR 0xcc0 +#define QBMAN_CINH_SWP_ISR 0xe00 +#define QBMAN_CINH_SWP_IER 0xe40 +#define QBMAN_CINH_SWP_ISDR 0xe80 +#define QBMAN_CINH_SWP_IIR 0xec0 +#define QBMAN_CINH_SWP_ITPR 0xf40 + +/* CENA register offsets */ +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_CR 0x600 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) +#define QBMAN_CENA_SWP_VDQCR 0x780 +#define QBMAN_CENA_SWP_EQCR_CI 0x840 + +/* CENA register offsets in memory-backed mode */ +#define QBMAN_CENA_SWP_DQRR_MEM(n) (0x800 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6)) +#define QBMAN_CENA_SWP_CR_MEM 0x1600 +#define QBMAN_CENA_SWP_RR_MEM 0x1680 +#define QBMAN_CENA_SWP_VDQCR_MEM 0x1780 + /* Debugging assists */ static inline void __hexdump(unsigned long start, unsigned long end, unsigned long p, size_t sz, const unsigned char *c) @@ -125,8 +165,8 @@ struct qbman_swp_sys { * place-holder. */ uint8_t *cena; - uint8_t __iomem *addr_cena; - uint8_t __iomem *addr_cinh; + uint8_t *addr_cena; + uint8_t *addr_cinh; uint32_t idx; enum qbman_eqcr_mode eqcr_mode; }; @@ -292,13 +332,16 @@ static inline void qbman_cena_prefetch(struct qbman_swp_sys *s, * qbman_portal.c. So use of it is declared locally here. */ #define QBMAN_CINH_SWP_CFG 0xd00 -#define QBMAN_CINH_SWP_CFG 0xd00 + #define SWP_CFG_DQRR_MF_SHIFT 20 #define SWP_CFG_EST_SHIFT 16 +#define SWP_CFG_CPBS_SHIFT 15 #define SWP_CFG_WN_SHIFT 14 #define SWP_CFG_RPM_SHIFT 12 #define SWP_CFG_DCM_SHIFT 10 #define SWP_CFG_EPM_SHIFT 8 +#define SWP_CFG_VPM_SHIFT 7 +#define SWP_CFG_CPM_SHIFT 6 #define SWP_CFG_SD_SHIFT 5 #define SWP_CFG_SP_SHIFT 4 #define SWP_CFG_SE_SHIFT 3 @@ -329,11 +372,20 @@ static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn, return reg; } +#define QMAN_RT_MODE 0x00000100 + +#define QMAN_REV_4000 0x04000000 +#define QMAN_REV_4100 0x04010000 +#define QMAN_REV_4101 0x04010001 +#define QMAN_REV_5000 0x05000000 +#define QMAN_REV_MASK 0xffff0000 + static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, const struct qbman_swp_desc *d, uint8_t dqrr_size) { uint32_t reg; + int i; #ifdef RTE_ARCH_64 uint8_t wn = CENA_WRITE_ENABLE; #else @@ -343,7 +395,7 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; s->idx = (uint32_t)d->idx; - s->cena = malloc(4096); + s->cena = malloc(64*1024); if (!s->cena) { pr_err("Could not allocate page for cena shadow\n"); return -1; @@ -358,12 +410,34 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); QBMAN_BUG_ON(reg); #endif + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000) + memset(s->addr_cena, 0, 64*1024); + else { + /* Invalidate the portal memory. + * This ensures no stale cache lines + */ + for (i = 0; i < 0x1000; i += 64) + dccivac(s->addr_cena + i); + } + if (s->eqcr_mode == qman_eqcr_vb_array) - reg = qbman_set_swp_cfg(dqrr_size, wn, 0, 3, 2, 3, 1, 1, 1, 1, - 1, 1); - else - reg = qbman_set_swp_cfg(dqrr_size, wn, 1, 3, 2, 2, 1, 1, 1, 1, - 1, 1); + reg = qbman_set_swp_cfg(dqrr_size, wn, + 0, 3, 2, 3, 1, 1, 1, 1, 1, 1); + else { + if ((d->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) + reg = qbman_set_swp_cfg(dqrr_size, wn, + 1, 3, 2, 2, 1, 1, 1, 1, 1, 1); + else + reg = qbman_set_swp_cfg(dqrr_size, wn, + 1, 3, 2, 0, 1, 1, 1, 1, 1, 1); + } + + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000) { + reg |= 1 << SWP_CFG_CPBS_SHIFT | /* memory-backed mode */ + 1 << SWP_CFG_VPM_SHIFT | /* VDQCR read triggered mode */ + 1 << SWP_CFG_CPM_SHIFT; /* CR read triggered mode */ + } + qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg); reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG); if (!reg) { @@ -371,6 +445,12 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, free(s->cena); return -1; } + + if ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000) { + qbman_cinh_write(s, QBMAN_CINH_SWP_EQCR_PI, QMAN_RT_MODE); + qbman_cinh_write(s, QBMAN_CINH_SWP_RCR_PI, QMAN_RT_MODE); + } + return 0; } @@ -378,3 +458,5 @@ static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s) { free(s->cena); } + +#endif /* _QBMAN_SYS_H_ */ diff --git a/drivers/bus/fslmc/qbman/qbman_sys_decl.h b/drivers/bus/fslmc/qbman/qbman_sys_decl.h index fa6977fee..a29f5b469 100644 --- a/drivers/bus/fslmc/qbman/qbman_sys_decl.h +++ b/drivers/bus/fslmc/qbman/qbman_sys_decl.h @@ -3,6 +3,9 @@ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * */ +#ifndef _QBMAN_SYS_DECL_H_ +#define _QBMAN_SYS_DECL_H_ + #include #include @@ -51,3 +54,4 @@ static inline void prefetch_for_store(void *p) RTE_SET_USED(p); } #endif +#endif /* _QBMAN_SYS_DECL_H_ */ From patchwork Mon Sep 17 10:36:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146847 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3603388ljw; Mon, 17 Sep 2018 03:38:50 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYkEfBmK6ozOmmIVytKwD/YdSkoNVXC+LVxRjjJ9Bjeo4WR9kmsbk45mnglNqDetZEhQK48 X-Received: by 2002:adf:bd10:: with SMTP id j16-v6mr17776800wrh.267.1537180730021; Mon, 17 Sep 2018 03:38:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180730; cv=none; d=google.com; s=arc-20160816; b=kkDUAyPjzZZ858PwRm/8eLDO8AsxCHJAS0m0F875lPCXGRc1YM7Lyfzdr0qVivXqMp cjNqMxq3H77hTW/GoLk47N5IG+JYM+WWdE7TaOxcqEj1JCPaUHe5AxbJff3csitUIgZ8 HhUWlvDtdym75myUX5T25+7/0Hp3mRmfoMYfFP8htzxIWyFPNBqZA6vPFMUfWh7NhNVT PMuufFLSZq8HxdFAir5hM+CYrCBSWY/8YNCfE+wwdtG0aOmYLArr88MFNRgBKMJEviUR WaEvwUeNf/VFQwzrvt8w46oCvma+5XYJop6Yjqfv4ptc6Cgdx63rI4krzoAtn8TG/6TI YZuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=oHjJpuGs4i5osTYIplx6zi5wkA9HfR8xxSu+tUMV6uM=; b=PoVjMLGpVvqLw/AUusUcwp0NDyuQ1at/RycXMDvVdTxSZPVMPqzmHkjPEdKq8UafVU bUKoRNoqiEopvq3jbATyemIbDk3XzWAq2cNY0ZNajWyjhf49O0gLbQwhmt0VJ4Ez1Vhq vP1xwU8g31bYhZcUz20TCYNe6odB65xcEBuENO7+5wZA3G9CEqknjx9Gru4jwvlayJrI Sutq6glhIZOF7qQj4VLpYoKh+nxvFZ+8NNHz9RfZzSjnuRF62t8LRFDV+mxoCTuMKhuT IYwovGni0K5pR+XvndVk2aIGBJADlw1YLrHEGumRDekTkHQrpj/attM2oi363CwAejBw ao/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=xPpndJpE; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id p6-v6si16088348wrf.110.2018.09.17.03.38.49; Mon, 17 Sep 2018 03:38:50 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=xPpndJpE; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B1A725B2C; Mon, 17 Sep 2018 12:38:01 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40089.outbound.protection.outlook.com [40.107.4.89]) by dpdk.org (Postfix) with ESMTP id ACCE4559A for ; Mon, 17 Sep 2018 12:37:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oHjJpuGs4i5osTYIplx6zi5wkA9HfR8xxSu+tUMV6uM=; b=xPpndJpEpF2Iak6ViSLCyNe+kYSYvCvIqtR9CY31vQ2MoeLf+mowrFfGU0V70jLmN8UQp3GO9O31ZA0xQEQzTeeqPqKwnkcCCZviZyCIaItlbbLGHPHmZLNosqfg+87bQGBMojJF5dIyEw0b9sSk0mDV/bxi23qZb1tsMQ1dkcM= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:53 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Nipun Gupta Date: Mon, 17 Sep 2018 16:06:26 +0530 Message-Id: <20180917103631.32304-7-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 31589c30-5fa3-455a-292b-08d61c899fde X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:86Rujm6IdrHTGt/SG2ETdSsgLHWkYIfj226Kpl7IELDTkwMIg46XAZjjftO50eQbxI1FnpmzMkYlY2BUvY8HBq+r2b1pNegdG7M0WJmyzwvViQew1abeZ+ccO6fSC12b1NLJsktr+r1PZuFUgTMtj5FVWPTxUD//9Lg/cmuzvMTd+XNHDWBOT4X3p/6ii2GADLyD5G/kvTgiXBCFNxJizjsZCrh97Bok9K+qTdA0ip68Ca1ll/AIMOxwRLTGxHpD; 25:lWBdjC0421JGyzqGN85TWXLgJpF5SC6XVBMLYCMneMojb6XJpHtAxwgC+PNRidT999WjFMD8QaVBwbNZHhGYMqttvVFojHFx287opRymdf9OdBh6va21Q6cYx0l+mOINfdRCmQXbYaTDxt1WZ9p5buMfZcXkogBEdHf/7HldqKWDDQhef+QIPDHPjNM9Z6OLYxNptrMVaXGzNL7IloPd7w8dsPhcTun20Cp2O2IszPTEXonPOtMCdZAbPLUxSoxqXuA47o0F9oW+WcmKRjhiv0GfNqYDRhR7j8Dnt6+W4maJIpg03hBH7lz8kQSiALD6eKDz5iel5lQi2rYNgY8TVg==; 31:QHiPDwrRtudG73EMeB4tQt92wjbEsRFMqtZQaIV8ghF+5JPoHUBZrgCi86d06abfnc4Cj5Dr9kK7Z2gts3ircVvPjbQA/7EAMd2BRxbFUcgihd0k8ttb6tfA3VHVn1NCeSZROCldYa6odQ11EIwUljJ7lzbNuyYR+ERw5eeEDIymhpRj9OAPdT2gvOWin/qAAHDClVZqhaFsQG0QCvxpLGH5GURMQTgoT/NenValpe8= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:ZEFYyXbXvUJnKqXmRxIc79jA+OZgqplqJqy8vCf3ALeSHRsah8JVML+38IqUr1xPsHJnQuPAqF6YEAtvGMaDZv/R2CXj7ijYvr3YQEPkr9fbdcTaxJ93hAH5eUXWKtDb3KKzNZpW2sFUvqhtyDbEY4YK+PYwwtlrTOWkCF/xONOzNFmbWfhxMg7pekTXUH/WSbvvCnvcCGq1HXgDys+E1tkH5kM3MoaNpCcsBumIM7axHNMatioFEPny3VqJDtT3Pl3mP1qiZIfZu9CyoJOIM3kdIng6XT+Pe58amuOvALN4rI/uoaGiWcJExMrXk71lNSdXkOTt3tZC45FHYGLVPcemfcky6JpdH8KUR99sVKCxA8hE7wz2ym6RVwaU9quQZ4IHidSjCbC9dJA4TV0Sp1eujPT9hZIWJt6heKoVOnHjMRCj4lYKYHhxrSQ8SeiGEdVUNvPsYpYP6az0N9LV2KAo5N+7N57z/+lb9aryJ2TCQzleF5ckinUbxeq/VlpQ; 4:aWl2R3jAlBCqfJYSBCOTOz+b2ynnTy3rn0pG1FmNCN9JvpThyCw69hMdINYbKiYS7c8jqcCpXxqPDmQFMsBB2sX6AzpF3UL7AG7x55DqZEqNauNs2h8pikNMmdEGd6JwC2O8ErQAtzT9AGTAONAVNeSCwIY6SH30aU+Lnh62oIy4plZR4RvWDmP2gbzOnOTBjrQBZePQ9OWGnlO1DhTIhtfGr6jz+1uxIaCR4XgGoDjCFNIVYEbLHiCQ+6R1F7Z1GaNvTVVoiasP7j2VXZDXh3fPulCW64gKYyubBl7jthsjvDBhCo1fzlK1w5YvxwCGATkYtD5nl4g+TYLRxTxXbGHSXo7lw8nTGfEoswqnkGA= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:QjGifEM2OtL4DCQXZNyApBEA/1xoQkZcMSIyoBM5+?= 0H4tLajVmrGRj4mmdfosEOq54PixPAzHt4wEBvP9jTclR3In0t5cojXAn85f7Iyj3q4rii1JblwtEkszRJPeZRGsa82kJjth+LQZEhnt+1Jt7VYgnOcZeoAZ6B+aM7unJCeH9G/3XFt3wsjyF/ERXYzrrUbJXaF3yKCBXtV1/JXS+fAGFF0/9dyeIRg/wZeT+ALwb05l8uuGbMJf0wWEAJL5WXg0HFw09kkLVd0lb7j+DHw3qZecCc95kRqdOtbkK3ShtyRwo0E/P17UnJPtM0LtFzR3ESfpzNQ1jCNNePEqFn4etpOOq/16lqfIkQB118GsYEUl3thQad8QZEmKydJ/pXMN0EUBAQUCbbLvQG6EyRBd6r2Vxm50MnOTX036RYO8EIh8SR7bL1MhE3+UkcfV0/yvvrQFa/z2RN30HmXnWgkYTrJK29RLu+9QtYB4XB6bYtg7loKS46vAckxawWQDB+jYjD8AkPki2TqLf1DDKzYgCskHxxeyEYJFq+jML7IBkEzXLhCXLhjFFBM9SB4w5djrrDyj5SDLPsHMa7lUJJyPXYJMsJl2MYZqGlkZIj8zWOhWPwadYqDfwIwMz1Z2fEPZzHZlNzoPSk6wPrG0fTaDpN7jlg15WOb1n6RMwhXGurjMhEfC6Gpq+Vca0m+1k3NG5wLeBRIgO/ldWjWD7oIWFJdaA4dQ/hPdJ3FW6oP4jPrBRn1ZQr9BPUvqMMDxzEATGGxhVeOlpNG42vc2eTbvMH2KpliniqMtHJ0vuNaeIMc1MRYitrbzjRjoQ3S2fnWb0nWDBxKFwexmAw8zjOMzQfkOztW43uEhgrZin50+r99AEA7d0K4T03dqdFrelKuNBOVzuOKPUFwVmwKv3ruCwK9CB6N3WIyZqsSdHPRSmiLOkIlZBCr7h5G1X+s5vhKeeV5FXqDK7dxjYEnxqFF1cByPEgu2fv0iLsQPThqUEeefAgiEInTP4CB/tJ98fGCmRBYL53yRddP/vWCqtKATeX/ssfDdXTzCAWqkp8PIooGKxEpT42KWkhtgusMjBo7QtE80I1WCPQdPg3Vaii/9AplUedj2OT3jXObjSk04fXIVMoVdFKVfNrx7myJcak+PqPvFSgTa0ZD6QZxxnq8Rukmqx49nDnM48W/x/hP5fAbY4GaGUBdFz/ibwDGtqEI0Wxlnx01c6GAFbM2wzFBaWvLRNBkNmpjXEMOJr9roZj13XwcugN8ccRmZhIf X-Microsoft-Antispam-Message-Info: wic5tLMZJxE20O7xgYUQU8mQC2wCOioBGQOFauG6LZEsEaiFJWkyMdijS8hARDVN+aSMg3pl6bCblSDOs3ECNR+JfIXZlvb369ghku6vlLjGbovLMnz/Yri1ZYOGk2My48Uv7EbOBdsUwclkeiSL/sEC2WQJmks0xsNeiW/Fe/OPCNxh7PO4QcTI9WNYGVtKHQaYxtP/ULHvpO8guM+hpE1eFD4xc28ouW0qT9v3PZvgLpDl0469GlhZ9tJywPUAFer4sG/rjfYaqb0VsswZDli+vxuFBq0tCxpHiZVFD+HYaSdoTQhPbPCyQ4CCzVD/v1diHDNh1CWo4Rt5bIclEVCLNkPFO3qQgqlvTP5F1pY= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:r/N3MPHpxSxr8+So4yM1HfYHzkw0nnGQ2gpfYl2Pnbtpw7p50iCMTvOrZ0mW26Erki0EmGpz9kpy5XyaTaqxyZyF+BfQv64XLzmDnHDZaebnMyQSU5Vxb4QD/NARu2vPA82ZQPjMJMqnJXv5dFQZVgUdP/IapufKdQmEpe+WSGUMT27gtRk7q/i5EphrOwLEskSgCr76tHv4nuvSTeOX6NfH/wUsjZQCqG6ElQi8ihWDtXKO/B/qIIkpB6d9cYXBmyz857NwiJtX1WxGMlhujoNBK7wogMOmdqTibMOCI61JyNtixW/xwUhOug0+EEEu20klYsNgYg9WvB8xLyjFwjT+NdYP+bwPatVgReBehJBcgfZ62s5fnNdwruV4BQKLi5c3rr1zlBRWCjqCox2iFkTkCMok5B+edKK28OC7M3O0Ii3iaM9/GtFixwFjQN49imOGpQzRAPiOOwybeK9Vbw==; 5:uxs2Y9DxoBe3aJMMQ5Xlb9Ds95W99+/Y5d54q0+sPYTBi7ZRHVIYROk927vDs1cL30SVV48WlgrcinjN5iUDKW0iHYCzF3j0abW0sQgJTudqlEvCEVYto9ya8fstF+s7Eud8c8lx8hR1xVWiPeJpeomnBwwLBovpXtkgxwl5PLw=; 7:l1Xh2noqu4xAnwdP270Sf7+PWcIV1/tBguv004I0J4Cdt2xEClFS5xGPxhuUpP4IoqsSsQK9xw7am0J19J34XfAq2Cxx2dAwNvCkiNyFJbFu9aNa9J1aaJ2YJmvDMuD970G/kGm22L94d+zyXCd3Ol96EzpHeMjbOM3D5mcjPBX5JA6De/hTAkzej/6BEMdL7Klba9rwOOblemFXVzvOdqjzdRSfmn/KK3s0mL/hVIznLQbX12tuFqdgEiKSOlJS SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:53.0238 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31589c30-5fa3-455a-292b-08d61c899fde X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 06/11] bus/fslmc: support 32 enq and deq for LX2 platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 17 ++++++++++++++-- drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 4 ++++ drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 22 ++++++++++++++++----- drivers/bus/fslmc/rte_bus_fslmc_version.map | 8 ++++++++ drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 7 ++++--- drivers/event/dpaa2/dpaa2_eventdev.c | 4 ++-- drivers/net/dpaa2/dpaa2_rxtx.c | 8 ++++---- 7 files changed, 54 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index 76f80b951..ce0699842 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -53,6 +53,11 @@ static uint32_t io_space_count; /* Variable to store DPAA2 platform type */ uint32_t dpaa2_svr_family; +/* Variable to store DPAA2 DQRR size */ +uint8_t dpaa2_dqrr_size; +/* Variable to store DPAA2 EQCR size */ +uint8_t dpaa2_eqcr_size; + /*Stashing Macros default for LS208x*/ static int dpaa2_core_cluster_base = 0x04; static int dpaa2_cluster_sz = 2; @@ -125,7 +130,7 @@ static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id) cpu_mask, token); ret = system(command); if (ret < 0) - DPAA2_BUS_WARN( + DPAA2_BUS_DEBUG( "Failed to affine interrupts on respective core"); else DPAA2_BUS_DEBUG(" %s command is executed", command); @@ -409,6 +414,14 @@ dpaa2_create_dpio_device(int vdev_fd, DPAA2_BUS_DEBUG("LX2160 Platform Detected"); } dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000); + + if (dpaa2_svr_family == SVR_LX2160A) { + dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE; + dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE; + } else { + dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE; + dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE; + } } if (dpaa2_svr_family == SVR_LX2160A) @@ -492,7 +505,7 @@ dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage) for (i = 0; i < NUM_DQS_PER_QUEUE; i++) { q_storage->dq_storage[i] = rte_malloc(NULL, - DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result), + dpaa2_dqrr_size * sizeof(struct qbman_result), RTE_CACHE_LINE_SIZE); if (!q_storage->dq_storage[i]) goto fail; diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h index d593eea74..462501a2e 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -30,6 +30,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); /* Variable to store DPAA2 platform type */ extern uint32_t dpaa2_svr_family; +/* Variable to store DPAA2 DQRR size */ +extern uint8_t dpaa2_dqrr_size; +/* Variable to store DPAA2 EQCR size */ +extern uint8_t dpaa2_eqcr_size; extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index f2eebe65d..ec8f42806 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * */ @@ -31,11 +31,23 @@ #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */ #endif -#define MAX_TX_RING_SLOTS 8 - /** > 3) = 8 for LS2/LS2 */ +#define DPAA2_EQCR_SHIFT 3 +/* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */ +#define DPAA2_LX2_EQCR_SHIFT 5 #define DPAA2_SWP_CENA_REGION 0 #define DPAA2_SWP_CINH_REGION 1 diff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map index b4a881704..a9cd80ad0 100644 --- a/drivers/bus/fslmc/rte_bus_fslmc_version.map +++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map @@ -117,3 +117,11 @@ DPDK_18.05 { rte_dpaa2_memsegs; } DPDK_18.02; + +DPDK_18.11 { + global: + + dpaa2_dqrr_size; + dpaa2_eqcr_size; + +} DPDK_18.05; diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 2a3c61c66..2bfe2514f 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -1172,7 +1172,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, swp = DPAA2_PER_LCORE_PORTAL; while (nb_ops) { - frames_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops; + frames_to_send = (nb_ops > dpaa2_eqcr_size) ? + dpaa2_eqcr_size : nb_ops; for (loop = 0; loop < frames_to_send; loop++) { /*Clear the unused FD fields before sending*/ @@ -1321,8 +1322,8 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops, qbman_pull_desc_clear(&pulldesc); qbman_pull_desc_set_numframes(&pulldesc, - (nb_ops > DPAA2_DQRR_RING_SIZE) ? - DPAA2_DQRR_RING_SIZE : nb_ops); + (nb_ops > dpaa2_dqrr_size) ? + dpaa2_dqrr_size : nb_ops); qbman_pull_desc_set_fq(&pulldesc, fqid); qbman_pull_desc_set_storage(&pulldesc, dq_storage, (dma_addr_t)DPAA2_VADDR_TO_IOVA(dq_storage), diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index ea1e5cc67..2831e141e 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -80,8 +80,8 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], swp = DPAA2_PER_LCORE_PORTAL; while (nb_events) { - frames_to_send = (nb_events >> 3) ? - MAX_TX_RING_SLOTS : nb_events; + frames_to_send = (nb_events > dpaa2_eqcr_size) ? + dpaa2_eqcr_size : nb_events; for (loop = 0; loop < frames_to_send; loop++) { const struct rte_event *event = &ev[num_tx + loop]; diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index ef109a621..89cfd2929 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016 NXP + * Copyright 2016-2018 NXP * */ @@ -476,8 +476,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } } swp = DPAA2_PER_LCORE_ETHRX_PORTAL; - pull_size = (nb_pkts > DPAA2_DQRR_RING_SIZE) ? - DPAA2_DQRR_RING_SIZE : nb_pkts; + pull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts; if (unlikely(!q_storage->active_dqs)) { q_storage->toggle = 0; dq_storage = q_storage->dq_storage[q_storage->toggle]; @@ -699,7 +698,8 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) goto skip_tx; } - frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts; + frames_to_send = (nb_pkts > dpaa2_eqcr_size) ? + dpaa2_eqcr_size : nb_pkts; for (loop = 0; loop < frames_to_send; loop++) { if ((*bufs)->seqn) { From patchwork Mon Sep 17 10:36:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146848 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3603519ljw; Mon, 17 Sep 2018 03:38:59 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYX/aPogLfXiIS3c7DY6sLAy7s+5sQ3bNWFZU07GyMChtOBz299cZKCVke4MTvQDPd1WRQe X-Received: by 2002:a5d:4849:: with SMTP id n9-v6mr392160wrs.234.1537180739554; Mon, 17 Sep 2018 03:38:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180739; cv=none; d=google.com; s=arc-20160816; b=jLmk4Dn6y8nZ5udVp6pG2WF6w9+UdUJtkj9gVrZl/aiaH/HEz3ceJuQtK1Vjh9z7IM wu329ADoO+zYWk4aawC8IIJ/+ot1yIHRVR9P3cGmo1Xs6oi7RjSUDcyhzuSsoJF46zWB JHJqpEdCbkjtTFJtHTimjuIjFrnJkY7OTeI2/UaTNDJ5/1WikRxfrhr55b9YQ/Ugvlqp FlPlj62kAgRVrRCFhxLjOs96m8ocw7EFJi6SBjVjmhFzooltN9n2GBbU2tKVCpyFhk+v b9tOiSjsGCTxj5GlgTzuG+DvgHU2NLiFeqrTCHYYEVB/Hyfju/Jp/llt5vA7cdZp9+Ym bDmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=i2XLLH25vX1LUaTX5x2caNA17GnP09DEWtiXjn6UsGY=; b=LSh6PjC5h4YwBmtiSRCAwzPtC1SmblQepj5Cx4Kc+M6Diaw3p9Vd4n0sS464aZWl5v mLMz6v8mC955Jl2TptkoaTWIlGcnm9E+A+y9RC7aomlgsJ1wxg6GH5SUwPUN14Z/j9+s 7b5j4TN7cNgFHRNxJCba2DtXgzZzwBtSxVIUZCMXjUm2U5h2hEaI39D57zPZOF09PYvb qQcEbORyDP5/gyKbAZ1RoHQ1xAVDNFt17+L7q1nYt5RNlkUg7dw+cqT0EjULTzBwh1uz bXBwuCaeCWXgWijivHlQKEhDyr/g72V8KRj5MBni3U3oIWsp31FD0tWgbXQaTD34A/+3 db3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=uGxCHQsb; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id h4-v6si14136310wrm.44.2018.09.17.03.38.59; Mon, 17 Sep 2018 03:38:59 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=uGxCHQsb; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 13F9B5B30; Mon, 17 Sep 2018 12:38:04 +0200 (CEST) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40068.outbound.protection.outlook.com [40.107.4.68]) by dpdk.org (Postfix) with ESMTP id 248CB5911 for ; Mon, 17 Sep 2018 12:37:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=i2XLLH25vX1LUaTX5x2caNA17GnP09DEWtiXjn6UsGY=; b=uGxCHQsbja7Tx3G7dzM/IQnQ3weUvNGaOX384up7BZCuZFytlzAZ0LaUj3bkyXUfu0W4TPB1xDz6rq0uM+7ypWu7KxHAX6eC6k2W307t8L6n0M9mA0Q6AD/Aer3JSa9yNQnkA0G1QCvyZj77IsF6pSjpn+WqfiEBxSbV6e+vWmQ= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:54 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Nipun Gupta Date: Mon, 17 Sep 2018 16:06:27 +0530 Message-Id: <20180917103631.32304-8-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7b805077-f791-4e42-34e2-08d61c89a08c X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:wXdfNuMorKYV4HgdX5IqLCeeikO/8Pbbg9KpgZ7QufnMYsMapnQshg7w1iBVRPSmAqXi+vwsPa1Eh6q0UYWy675AAeGMGpA7hgCOswGXbRRo2Y7fTV13jxMnFRToDEtEl7ka/uLshpvBVw4E4MniOCChZ/Iz+rZSGFhaCM7dWAK9Vrn2V1dbzGFHQsiEkxK0aeIps245s5ab/vcGjNqByPwK2x515ElMRS7/iDmcN3ktCiGCqwZ5xlRVm1Uxhvig; 25:9EGeaLWotZaze1FH5BRYM7kMM0gnD7HEEaWc1PxBgpByr83Efjm9rh+RMESEaI1W8M+CzygRqLeUBzT9G5wz16BRSJVekS58bk8AFwRZcy77vh1YvD19l8qSfULPRiCa6ZM4B0Sjh91SUma79hc1zzbdnpVNlOW0gyfZq5js67Paer1oyUC5wIDR2MkFFZGYrlX+JwjghG6wU/pdbZMfr5zCFVRtcS3OWww0IGyfp60c6l8TR8buqX9Gwy+dkeM/cXXNAsL47KX/nz1FUMgeps56cxn02J/pY4fL8CDEbW44DjJ6y9SRt9NWWMPFmiY+UW8aaJl4BK4suo+M9R8ZtQ==; 31:9206hhCLpBMbWZeEGwfunGlzzl8uOK0lXGN3BuEyhncvfIGCW1tbkuYLKfIkdIQ9FrmqbEBm7jUH35k0Rd9eb4+v3MiG2cUY9Ov9XI99YZNddRs2Yyu+s+PaG3RkE/wKmv6P1qM19JapmvSwOnCb6wlcfIICskmEHkn46cRE4Rnsb8QYphyJeqMlXf6vCgqLMerFU1/71x0l7dYD9yNjtYiGbhrU4oVRxdf/0kSfSzw= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:yNI3trStv+Ll64/yXDI18LEklYNvoAPyp15CK0X5/sb4zelPwy9xq8JlH3uZxMoM/iq27Jxy8cx4+7WHKuuQi4MkQjdWKiGg115SK+xd6LNUjpwQ4sZQqJm8NDQ+XN53CrCUyafWIfKIgoshcK2PSVGPAuWQT7j+aY72567VKMGF0iKk+HkN2Z9VYOOUcK2Kvi41Mjgn25l9fc0mOTGb5ezlDJa6jEnAa5hK+U7Gy1nCb69/ggmW/oqUO7ErdSwOn6ZInFQtreljt6QLyw64rO7HVku28/l6g7K/b0/c4MbKIKFpMA8Z8JD2y4ejGGBPEpJ2LsPOn/g/Q1YJNhWgLi/pnIKzF4XogCrhXsKY+pMQ+fJMWkirpx1BwYMOIH/o5ayHHoMESKBVdR7C3tWf31Aa3r/C3V0CoYsBzdM0iqj8GHf3iivrbPWluj29FZvuhw/xmRQ9D43hwAGPjGg4oIhv//ER6e/NQvLrdZQLFHDSRPlS4QmFQ7Rffok2WD6e; 4:D8A2BAs75NZaN85xTQZ71sV6gUgZ2nrdsBPzWyP9ZegTZ7HpmCbzNgnI9x7Xd3Mqtbmdzz/SoC5fD4yj8mIoVFgWZm3TuOBSNk1Rk1tMDneucbyiIuZ1aRhzlf3fGCEO4Y8w8C30XoM8ASUPSthVMzEkGLOosqrqN4yDeegvUFrFk1tNrEoUj5QfRm6mx9Kjh1t5hxonwjKPcVEU5L8NpK1zTSQIkqHzxABF+zKuK+TK7r4qy1kt2/6Bey0NugFC55EY7tYZBmCQaR4NbuawyKOpBqeG71QDfXqtdCU3zqJFjTxD+YkME3yp4ZPfNOB+ X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:+BIWIA/bfyVZYJkHPZMNWJmpxBg1wFMXlq2algaxC?= bCILCNbSa6+XzYYFacPDI6Knj7QvbufJxZd1HLAzhir0+wodFfZRj2jzmCTkxcqTbELFVziMI9hBPcCRtEDsZ12SR5l4dwVphKcyfAfraINsleXM5vvVCoNj/uUOjfcft6os9T4g5Q0y8DqcaWU0b3fCtyqG1NKJrhDmn1TPhUJ/9/O2Lpc4X8cvs4i8pBpO0M9metYcSQNl+sjPDvpuaYVNtiUCxEpdPa16W09kIcOR56p4O6juYpgcosaguNE0PczuVaxQj8WxRr72tExX18xyb6UUXaumevzhRxoPcniYwsGrsiEcxf5fqkz+IMahV5Zkjycak2IzRm7O2OuS72+K1eBHEKTrwSiLNPAQSWPPcozrAWxu87Vxhv1x/t045Jz866WRneUd0lPqlNSm8wBsYFeSLUuWbcHujbLSRDxWEs+2zvD972IYQq+oOnpOYEpOQfODc87ORJQiZawdQKGZyhrCgUCanfSvtfhmTuvQGizuVvevGzof87pXnsxOWUtu0gos6fWj96diMwa+jax0T52YaOH2TfbwtBKfU1xV0LVYifFYVL8Bh7j/xLrKci1/KROb7UObc9NVY+HyZXy2+IM1siERblfNTav8Uz4P3nYWH6xL3GAuq0eqfafjYQLLTYHY2feLxUWZAe/NeR7dWPrf3am1HlXgmDLT33KkNy+ItcSa/j/8PzKrtZ1lb5grkLptzU0Rj46CzjBBWSeaaWJATdVfkYbsNb1EPWLh1P752hkKl8dn5xxjhZF/qsjHMX/6eIaLHyXntJ927/queDehOmPjNO7X4Ds3huCjnWryX7lY0g1dgTIVVKgMvPDOzhUMnG5Pij5eRZzyMjtcoFm5uA9TBD1wIKDtYIcOR5joN3MazzAO+b3uNkeYV545EHDSc4fkd3/Zms5h1T3oH1ZOBugItOsOQFHpz8vNBoB36sW6ux/aYbxk74Dx4alfEc1G7KjBL/o/8ZdOwiuo9m3U+Kp16sbDCCjeFeIgAEhSCyS2EIPRURDxzbVgjmhdZXSIa/RGXzavjzK9o8KCPt4NQ0hlyq7pT/fPqBvJpz81oThw8DHgRxfICWN0RlhNXDR49t6b0q+DbS/57+l8RZMRGdKaeBXzbfRHAvtOE8S0bmyctNME1edvJpbtR+Vb8WxD55lm0xi//LcunmKTsdRDFaDewQSfWK9bNxEQVF8MdHC4QqfNKfvS/0SdwdPJYKPPedK9L0QkDqQxfxx X-Microsoft-Antispam-Message-Info: eriK4uqAmmct4PoZHYdHalMQ4POIcsc0Yet5GlogKMrSjGViFrqX4Hz/bpFe8sIG7PP6j4Y33/ONzRnK04NP3tA+SceRxnRzYxBxfnnHP4RhJO3Ldok7nSrf+ntOyvjDkpEsQg6q31xYLLpO8xNGlf/Igi1aNxcRgTAMVxw5FQEjFdwxtlsJqIp1Em1Z17m7aUvyPzdk/Rt7zouz7JAKSdHSZR2lpxZ38rXR4PSFO37im3TxrZJoc2XbIAlFBh6g0JX4rYhxAnU11XUTlELEFIZMuea8CWptVDrWtvjhFCxpySQhukHKdvgl4GA3Ex1BQq7NXu9NyjvFnfPspLZrMtXNwLERMs+C3yB3n4j86QI= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:EOQ1b7VY1zmLwOlYWBFc/N1k8rqcmf7VS+mnbNrgY2f0nFTb+ECt5RyhBfxctf5vlog/bUxLsdEAiQ2cvT2izKKJdAjGoDP7Q94ZnKfPciQy5kvyePxKweFqEwxrHBgTWrFvpnJr7rYpdkDdPQR2D/Qd3aRN2g9F96wMxVWPIzBuSQw4eKceVyhz2ghD2VXKg6obYSKneLVWjBkPBSMFdZ22GuIf77za4U026WhqMAorylYZwlYy7BVYKPfCL650QIh5X+YsOIEWkuqY7Tkg3xXKThHKmzE9sgBfmBmzIs7R8D+VEoynatWjrXlczLX9IeqrG8cJM0RBuLrWU7tpu9xxg5iFN3yYa42B1JFaUgwyQ9dFdZ05GVcBZApgpFBTUC3Q1lVtQyb4f+1mpmbL5vUMPNbijX/3S7ESLhYqabd93H4G3o5MTconbTqUkVW/j1Q6SCJXpJ2oD3e+hy/foA==; 5:sOKYxstaOS0Tmnuf89fao/nlGmm6GKXC7pcLazGDc4zGL2dOVxic9orZ/nOPtgat09rnwc1ixXCfhIhYCWRItvrMmahr2lNZCOnMmpYcHgxRh6ENnY624ohwHAnMeziKprBrzyMJ0G21a1TzHyJVap15Z9s2Vij4tX5JDEBEADk=; 7:lAQF7Tz948LnR+uTi96KsEeDK6q7NvsbPrdIEBSXwzq6KxPKnJAvdxiRZGn2FplZdXBEK39lJ+oG4jWst5hDZOoSsy59DqUCeWlVPM0lC7puzyF9SCbXD54Pz0IJfJIzsxGaRR+OnbKYfrMIa+ZLqPSSHOFYhIyMxzZve/6Q3dCDRYjMotECrSZ6Vpfb5g4+Y4Nn8AlhBv0+qQZgKYwi0RnwuhwqN2Rgdi4A4Hpgkvt9tyLRPcuHaqQKWGPZit6/ SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:54.1488 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b805077-f791-4e42-34e2-08d61c89a08c X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 07/11] bus/fslmc: disable annotation prefetch for LX2 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta In case of LX2 we get parse result summary in FD. We do not need to prefetch and read the annotation to fetch the parse results. Signed-off-by: Nipun Gupta DPDK-1404 --- drivers/net/dpaa2/dpaa2_rxtx.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 89cfd2929..953fed2ad 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -554,10 +554,12 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } fd = qbman_result_DQ_fd(dq_storage); - next_fd = qbman_result_DQ_fd(dq_storage + 1); - /* Prefetch Annotation address for the parse results */ - rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd) - + DPAA2_FD_PTA_SIZE + 16)); + if (dpaa2_svr_family != SVR_LX2160A) { + next_fd = qbman_result_DQ_fd(dq_storage + 1); + /* Prefetch Annotation address for the parse results */ + rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR( + next_fd) + DPAA2_FD_PTA_SIZE + 16)); + } if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)) bufs[num_rx] = eth_sg_fd_to_mbuf(fd); From patchwork Mon Sep 17 10:36:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146849 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3603696ljw; Mon, 17 Sep 2018 03:39:10 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ4t5RkWNVm9i9WuKuOXlj2A6fmafdRdZdLYzcxD3httSY/BKsKuCehXhd8DEziHaKKXZhI X-Received: by 2002:a1c:7412:: with SMTP id p18-v6mr10855104wmc.49.1537180750423; Mon, 17 Sep 2018 03:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180750; cv=none; d=google.com; s=arc-20160816; b=JwR0W3JYvv/0qjKIQkgc+OWwO2MwCCWBeYgE+AJePRyo1dMDNCVpg2c57ynMQM4zka cIT75Dk/cuKFY/IL0DpWmVlH6NH626xOYxj4yx2/gt6hK4sighytjYyKcAJoov0tSzgA 64pFCJVWWBKJg+Aj+ky/lFnvb+1/EMozgR3aTKprzKZwJjxI/tR0EDD5FaYqqQKVe1zv a3Sp1cU2iWR4X7vgmNBntM4YilG6woAAAsfJC4FZfwjQTHDTiswBm+LRSBqYj09/1Uyx BCZng+XZ4sF6jgn0Yl0gdtqSJR2QkDwPu5rcEZXAiYXf5fxEqWJQVoj/9IiZV2UBdJCS 66Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=AsUF3kKS/V2vItF3tZ0r0dl+HT5RsBCCbCROwmpu0mw=; b=FE5Qro6kNfJJuo+wXfkIcLuckQPNKEbYaLQ8mEhPcltdRM2R5HbuyFIm08kBomvmD8 WikyvTaSy0Tujq4v5DdAr4E7roU9C4uMSM08xIUZ1vkQdNNLoG2eqcXStj5SDBX0DkHO 2k/N6YBkk3pqbWN8biBJBNe0xGgUbVufCXWO8KAisa4ny+Yp3WPC2XEoWKRGZaKSOTsO 61ybt+P0XyJmY2NoXD2WdwDIi/C57nD0eUZ2Njew31llXVIpQiK0c4rLvBaYy4Rbtrfg g7oozy8xCTwmvwUAW8ueR7bcWlE0qiPm4beiEfNw1Iop+qJGRVQroVL3ViHSDdtztP3e boOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=CznKhVNi; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id t8-v6si6564452wmc.124.2018.09.17.03.39.10; Mon, 17 Sep 2018 03:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=CznKhVNi; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 366305F14; Mon, 17 Sep 2018 12:38:06 +0200 (CEST) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0075.outbound.protection.outlook.com [104.47.1.75]) by dpdk.org (Postfix) with ESMTP id 96C8D5A44; Mon, 17 Sep 2018 12:37:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AsUF3kKS/V2vItF3tZ0r0dl+HT5RsBCCbCROwmpu0mw=; b=CznKhVNi1oJ9pkRYjy/CPYGmrVlhJT/tQokEGUyp5X1mvWphDrWq+d8iVmG1PzoLOmW5pRV3Gm+o0v9zUUFDNd7udpQ7FnolrmcbRL0JmsLaAAc4DePLo1eajqbqiAz6K0bDo3XGv9F0h0Pkbc+JgBOktbIuQdLLnJzhBzbAM7k= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:55 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Nipun Gupta , stable@dpdk.org Date: Mon, 17 Sep 2018 16:06:28 +0530 Message-Id: <20180917103631.32304-9-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 19b6550d-36e9-4336-b2ee-08d61c89a18d X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:audxDR14DOhuq6a1Bok70paVrDIrDTz4KPkHv3aVwrYQmzdeaEnlnEgFUBO5Fp681FQtxI/kSxaG5VbAjFNgAshJkTgEod7YIEJpw0RrRUnCuavZUugpF435zuLRp/eq/b5USlxhWVAwdoQe1lBU8bWVhApFiwa6VNmBI8rRJnL8/VbcVVStj566LzM02QdVnz/fvx46oUSaVUPfdVep1vu7/RlRIon1dO6gWzQVdlTGG5EmkrLuNipPT2HFjpeT; 25:GlAOF+AzrQel5IIq2lbrvmmPwylEp7xSbwl1lxNmT54FcJw1H27qi5PxGr/boTiHYoke0A9lh8JQF85nvgr6aS5bfK5uvLPockyG4tlwRoG3ibgpE7vpgTsJ+23eYESGEC3dsFrskaOnAu6mET5izQRuxDZ9ridzLqP0hEZ/4bnNgQ/LQ62Pt5qQ97/f0wsXxcoF2o6xToz0FD6jOyjSC7H0Jc9m96zf0I/YgU0HQZXTMxngzdpEcedqNUqBbjWXUZiziClboQWVPTQVhkHBkPLFSuiMkX0khmRHiU720w4dxbjl6i9fQGRuxIJGtq6YrpA+XeH+PtEbaFTeAAkzeQ==; 31:UJyh2Czx/F65X0xOJXi6LCJH19Qz8a56NSWsPClUc1g+HmFQZ7OtkpwTVizVM00jRiPBv04y6ZkBYZNKObVjan8cPPBFL1S5Dvq9JtR6LeRtEOuK2w3NWzSVJ4wAbGfFDRAyxueYBW+Od5gXt/DR6b8rkVgrq/Y2anAWUsw6KARi6C5l1sKwBrCuJlzMpC1dpAH1Ee/uti5K+fZdN5HLf3XwBJzItaSf8I47Sli6r4o= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:JjO3ByqRsUEyEggn02p4jVmquDX183XK+zJAJn2rjO7jcH55zQ3nc9739iBatkx2BfKGSK4F3HvzJ0vrGZPQWQjsoKD8g2OPPV/KwC5b77oJZsR2j8LB4KquQjG1V7wddTWQDJQUJ9fRzb+/ZD9wyaorm/UJ8GdylImLeN5U3DRYMJt5E7xk75N2BOM02a0G2TeylHERJ5sixNzxY1hEsQ8PrHaBeKdjG/oCwzHUvc7Kv+M11yZ8biPPj+gpvGYQ1arrA2sKey5+hTiFxu0G/zVS/iclADhRnwFP+uYzS65DPAQU9eRDYsc/kBrn27NWcZlMVne3D1X0I1PnV/akV+UDj7Az62xzNuZgtmSONA6Rjz3AAqoSWC8AEWFYI2f3VoFEQjuzuhyvH2o0Bqu6m8tU7/85xOSv5hpKSAI4kEizrYuuzQR/ayNH3wrV6NKxtYgGw95VcUDkDcLT8traEQKtw8tUy86+Tw6REPVkLrqpfhc2sK4D5gGW+gaBO/x8; 4:BsZRO3oLTykXVjrLQgqgl+GQpPQeJt6ED2BRxG7YQXOMjLCUCzmtzF3rpHppL9hjkI8kuGr99C+BaKrVZFAQg5f67z52Man1UMvlD3Kxd5Y8rndodHdFhbLUqbLRC/2B6sFWp3rsc3jNfIrl/TGyySfBASCdQaOjv2nQQVVGkDj12esv9soo+ZOukWbNOXWlx9VZi2K/K4nubDMJCIElwj52nnktGDd1EGxfHURAuWBqAAm6cf+5qNICYuX11ccp2HpFArFuxkWfGTlIyTwl/FG3PKRis53LtapYIqZS5DaqhgieE2I32qTOcffa3cwS X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(136003)(396003)(346002)(366004)(376002)(39860400002)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(575784001)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:ttneBdFx6VzLo+jfyhnGJT4Ui+lxRD6zDTwi2e9CD?= kRoxWs7Ub/dGG23mXMQb9dSwTp0q9bTjebYxMIhhGIQh1u7kpiVUQyMPWZ/beX6WTYMdX78LFjBdfiOjYnOf6qvpkWDu2O5cmwKWHZw5ZMVrJIueEiE0dy6rH6/9sp2UCdWyh5wRu8HqNUSocnqsFhL1I5JRxIK7HOBPfp+O7Q0wgfQ+Vlo2MU1BswbUZ1O0rV+mCYOBK5jAhsh669Pc+RrCAQAZMffKEUQhlXzxd8EvGJWSCCu37pPLADPYRciRj8jSsCWcQ2w652fVE9jDzEPzIxIbaaHf7E/PyB6HpMQCuc5nEW6P/JTAhOH+RkRt2wttTF9SOUpp7ICT2XW9eZ3J1pKjmw7O84dWkosGRR+sRi9LD2sq8z26nToJ3b6dCWnVWKzF7pl0YrVVXMu09sHO7TBA/WiI2gsvevidATwrEx6J3mSqYWzIU/XHlSXueOE6ACy3vldp70JmXYja3xQ4j5Z5kHoljOCq3Qjr1VAbMhFf8H4+Hd6RHJRlIujNf9Dvfe//55mda4HNsMVtqqaif8kZxKAFZeFRrEeNWIsXxKrEf65e1vrQ1b4melBoSzdpMjKS4sxytO8BNnN/L4HMeb9J2E54Z1v+zq4lW4TXgsW08RgMy7zwGuhrd5DZL9lGGpm4aTic8lYfanrnb4m7ACVd6dKPzeXI0abkRBEomwaBG5Ngvtvbz1yXGBVx6nc3pQqTO/btwvgDNMJkvMiI/H+D2RVTMz1S4b8edQO8dkVG1AQ5nMZZWu/CKAqLXRygJsLIjudDtQgKEceJmls/475Qy1ZwkU5xteDTZ0pJfn39Kuo2H8rR3pdmqe772/T0iq2TL69aErvMGjETHtimL2mMqxuWpBlTMSTUgYNN5MNhzNfNtOFZVTGm79wcyFUXW086KIdH8g3Y3Dmh06ELcmhnJkD3lxBAM6ggjWIVFUeCvhuoqu9KVFmv9Z2ismlPurraL9asOu+t3PGzRUh+ndg5Utd+yv2JpOx31YSW7TwzDKSRCB7bVsV6fc4LidGfkCZWKL5EzK/q9Q13YHK4gXDpfRAPswnc7ggw8VvCDqk0D2M78geWkr0/YWrlGk2aS2oAq4Gj9QwuxJfijvoEQmSztp46r0VVtKYC4RetEv/+MIdw0geoCO237FfJIF+Rc680yifU4ki4qap4KDk9TdBp4VfEXryyrPbQ+Y/0FvkvXE99GQ/HfvV5isZGsfhavIFE/OAVamC+f0O1Ztd6DOe/3/uhc+uIsEUr/LlCA== X-Microsoft-Antispam-Message-Info: bbcMmnEkq3e2QisheZ2t7Shw76LCRp+Y5wJjFfGuJCsA4mAvkVR1D4qQU4YYMmeyWGgKA3ot7ewLEng+xBmO8cRlL9kO2SEfgAe0+qCBspbEenoQsWyKjAsHzxH+HFp7sMSF6K1GGF9BIqbUdYJgULh9BPfckDqSrMlZmbki6PGjGEyFOouC5EBSOMfZvMkzeOtXrAb4Z5ucnDHwpFl9wfZjq9K8xg+t303OxVvnWHKCUOCOBucWwwTbzNUA5MGPomA6V3ixG/0zobvla06ZmhubP8cwnkBcn98O+VKL5pZxzKDvwnr/7Qkp52Q3mmJ5Sfp8O9tUjcIzKNRtNCUjiOUKjXhqDFZMKYPE0C3u7Xo= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:1C+m8UM1lF18QbgExO5PTHshUsKUNNYa3C/QWAw+bzFpEjoX/jXaV9GVU/gxsv2Q5rSDv4RfM8QjIOR7cx920Qb4tcliRgolv3TX/pGaOmbVNTIc1XnNuKjXil63QCvnX+oljYTTemU9hIaPn6YWWKrbap3lHW5NZkhmWee4foX96dk3Lym4chfpCzWECzMRZvdS3+/JIktj6NKyZCKuSvtM1YFdxlEyKA2Ti4u9Qy0VBUc7U5DtWbw0IVzWcPhA48u+0rSwJBRWrD2VWJCbyorxnpsV3c+qVQ5zUKDtZoQY7WJnFvCvkcKoVVFRgrFNuOUgNCcSHa/2DOUGe6OqDfpcgLeKwJi4zoaYg+asK+l6Ulu0cpQ95ywPM2h78kpYaGEkpDClkEtSQ1ScEs+k7yZRx+8xEqqIMNzA8SBWvHN/O0zqVJAxPxvWSlbUv6NWgQs7pfztq5haRFj+r1vSaQ==; 5:DkjLQ7+0OSJO/uPQOP9W4JAEcpvQsmuCcJ3iyEr5APHmOM6+3dFcRgGoEOzDmVaKmagHgZJnezQ8KGOBRjuwuaJ1k5JWVHmVUj2n+s1RnRdcwLfEno/JNFQ2tBrvpqXtQOWFO3TcoJgnP0Qlrvus7aHGJWAwPxaK/E4ZyILBB7M=; 7:BcJzG9h5bY2PglgnjHLZWNbPO8B2xNE5wnNRWlkkjKCHycCnbSbx8fihW8kTKU26y0NAzqKdLvt8Mf66FkIf9pzH5Eu/5z3LLt6RMs4c102Aod39s0uhN3pk9Xsuyis8jFiaS5EQVRSb9px9Uyf5sUr5M/pVARjtpCc45JPDhOhaVRZ0YUnmcyxQEnUxuFdTRoUAm7r4pphaXdeRVMeDyu5Yxj7Lo6FwUpW1QyuJVLjbkZoSmAP2gT3ZlFOgvYcA SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:55.7113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19b6550d-36e9-4336-b2ee-08d61c89a18d X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 08/11] net/dpaa2: fix IOVA conversion for congestion memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta Fixes: 5ae1edff6895 ("dpaa2: prepare for 32-bit build") Cc: stable@dpdk.org Signed-off-by: Nipun Gupta --- drivers/net/dpaa2/dpaa2_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 7ae74c65d..02cea0cd1 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -572,7 +572,8 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, */ cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; cong_notif_cfg.message_ctx = 0; - cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn; + cong_notif_cfg.message_iova = + (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; cong_notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | From patchwork Mon Sep 17 10:36:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shreyansh Jain X-Patchwork-Id: 146850 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp3604118ljw; Mon, 17 Sep 2018 03:39:41 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYn3iOuLY71vQesLKKQyCxj26WTHt9UKCGl9+22yYwGpNdMSSa40X/DH1D4L9RELhsLaOlY X-Received: by 2002:adf:c64e:: with SMTP id u14-v6mr17440817wrg.177.1537180781721; Mon, 17 Sep 2018 03:39:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537180781; cv=none; d=google.com; s=arc-20160816; b=zxiF1yA+mUPSyqoya3/r84keDdDGLhakR9aFnCAtcD08xgi/iLp09gZVDqd/xP/8pU aWwsgFNaUV7g2m4Z2+1DrM8bScJsNDCi3CxEjLQRZ5OPuQi5SifIMt59tQkWE4NDmU/z ZQyCYWkfR8wZiP6TIyD5AWG6cISoCnRU+hJps/rPsoAMzcEd4UNHtxzpt1X5SifJ2R2t QxfTfnnulE+MvI8l06NMGrBlUmNPoj0tnF8G2IbcfvlqEfVPcrEb7I/yUyXmvayvdT7o 4Zzz/C47oQ1cK551h6C3bdspB3+4etZTouKu8LBX3L3ngfEFPCEHzVUZN54Nx3JKJ360 un9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature; bh=eGpMe1l4vwI37m031h1WSmPNIzg/JwbMel44pD7T+yM=; b=X2+LsdXEEJiymhOETfA332RjV4vWP3fozmOlvxvKEpiUjd9om7pZyxr+2X1xSp1omC BeR36gQI2Kn85i/+UUdjwjxd07uFDX5F3pQNWIt4kN6r5nEh1BVIEXJ/i5CpBsZTcz+t OJyFNCzisRoZJBGDV4ZvR3JmJofKKHvNMklibDMatcsrgHzBNk+XIB87QsRH616LRSaA hTn17sSd2B3ABN7citLyI9LrqR4yiaDDBPv7yfjy2U9p9rIyXHERdbYIuQMM3vRmWVkv ks33QZLGsYIWX+Uyq8JwE410s/L8/gZCUemu0/fQDzdSq7F3Oz/WqhbsSrmMF5idKi4o bZbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b="OpTfJ/sK"; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id w15-v6si12963343wro.101.2018.09.17.03.39.41; Mon, 17 Sep 2018 03:39:41 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b="OpTfJ/sK"; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 009685F27; Mon, 17 Sep 2018 12:38:13 +0200 (CEST) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on0047.outbound.protection.outlook.com [104.47.1.47]) by dpdk.org (Postfix) with ESMTP id 33F555B26; Mon, 17 Sep 2018 12:38:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eGpMe1l4vwI37m031h1WSmPNIzg/JwbMel44pD7T+yM=; b=OpTfJ/sK5G6/vvLNGMneb0BqH7gpSToUR/2/8tQMPLMVE1yQEdxnw9KmldwSSKCArjj5eXf6XQDemibvlPxr5SvC+s9nsYhJuLGKS95igNTLjlzuezvTUs9Tet24qeLxd4zhXdpuOUq23kdZ5Ui7t0hxHm3arJvq3sPZ2Z5rdjE= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; Received: from Tophie.ap.freescale.net (14.142.187.166) by AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Mon, 17 Sep 2018 10:37:59 +0000 From: Shreyansh Jain To: dev@dpdk.org, ferruh.yigit@intel.com Cc: Hemant Agrawal , stable@dpdk.org Date: Mon, 17 Sep 2018 16:06:31 +0530 Message-Id: <20180917103631.32304-12-shreyansh.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917103631.32304-1-shreyansh.jain@nxp.com> References: <20180917103631.32304-1-shreyansh.jain@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR01CA0092.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::32) To AM0PR04MB4673.eurprd04.prod.outlook.com (2603:10a6:208:75::15) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b480560e-295f-44be-9966-08d61c89a3bb X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4673; X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 3:w7WsPAyy3fAG5Gh2PIr1f6p5N9/SALYojz3b0UR063jD9vWL/dJ37VMR9bG/mEgwhZcUjnvzsRS9t1O/ufO758IkCjPaq8DqhW5U01gkpzz4cPGoMDAzBl1w47TJT8s/yt2NgOlhMu78lYrRzNwAN+JnZYIENuPv6EjGkdrjKCiXGyg0a3vgsgsDBfb+gVSdYH+YRH87rHdckbZskStWdNyDk3iZAFxSxHoeue4UC6pR3vsrO+BPLcsWBfXVjyqh; 25:V4qmAScst765UVj2HBoak4/gjUF7+fU93RJaEXdGIQkfqFQAdh+khA5owa2oQXlpBCy0yxCdI1b8l/PXerAZ95h3iAEKlhND/ysn7UEDkVOUjuCxjVFDw08jXOk+Lh3799moQCBtTr1a9fl7J7ff+GY0+Sn6sd4oM4H62fuvDLQi9YC9GsrEETtcRc0J720eiCO6M0N4/ZfQjEOfbIFIqXVy8oKxBa+c+v54sAmmEWWFtK5JKXgDn39FerJj+IcIrt8oQaGki09Oe5Lay2CYwTdRgCVXnuX3PQDJ3puXQdPdUvF9Q0zSp1MFJQlQjcp8wm6CuWvGRoezU4H+Mc8OyQ==; 31:hFvPL9U+Kb0FKv7ZTAHhFoVsHNGgJ8Vp70UZQpzo60UVFgbi4hP04Dw7gcFM9iXscwrf+3htqAiWPjp0zC0lMMzEgLtPPVVVayyoe5JEj6W7DKWnh7SVR+Z89W8LRFqjrURDKa0th4jqqo4BGInpQTVd35KZp6vno5fc/INhcYLuYR2NE9XL7LAk1wJm9NmFkPBXL4VPNBNSlPlhfaZfcnHTc5U2CkW/nTT5pfETlEQ= X-MS-TrafficTypeDiagnostic: AM0PR04MB4673: X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 20:CYB8AfjuqZ0fHHk1yNCfgcVAYV1eSMB8xABVJwxVbcWmIMG698503UtmvYCQ/lOTi5fJUSKpGTot6RF+iTRPzrzCZQ99oScVI4kNE8coM/zvRtDBGVcNDkZiIaskc+dTU7JFrFJMF4PINuAiP+3JVDzWHnqveiEmYe62DUExxqTfr1+QsuE1ZPDIFPZuw6f7Ri4ZthZlSHB7llKY+va5WAKZ2s4pNukA90NOiWY2CUlSBEsnh8R67eHP86GgJYgnaSnkZrZvkltUehl6vRL/gbiIv1kqKJmd2McRatItfD+FyowexZhpaKXbhgCgR7HwM8gkV2AwpLCrLf+oxWTecwu5oV/VyolGkneh27In3GCMNDH4F1JQ4cMSSNo2F7XFzanRnzQHAdcVsEQxzKXw0AmeDHu7q8VYzCeolfb+iKsOQ2v/eUBu5eXb+RS8ngZdkNgfQ3Hm9+Ng/BSlv1Auv67BsZh1QeDogcHyG3lHx/qJ69/aj/2lm7JJDsFo0JXN; 4:DR+HajqfyrUPc6wsqfZnhi0clX3U1zkXnLzA2AIb22I+1tOSlWq/uljBrf5oCLS6vdY47Eu130D1v5eRofigNGINNHMKt904F6nsNzEOTlwskh2jbYGMHnCXuIEN98JfZkG9zDB6syq1oOn8JsWBzQPLD8A/yGifV+dxB54B5LGwuBRphBJjnC1LjW2MQiAf7KUORh4p+av8zzkE9iK1HNquBmM9egC9lbySmlEHAx4O0LBPv1kfPzrz264lg0VYKr4a/Grg0Ty0SiPvjcmxG98VMa/0sSgndprzoXgoPqflMKrxtFGbvPL0hSbmCePv X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231355)(944501410)(52105095)(10201501046)(3002001)(93006095)(93001095)(6055026)(149027)(150027)(6041310)(20161123564045)(20161123558120)(20161123560045)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(201708071742011)(7699050); SRVR:AM0PR04MB4673; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4673; X-Forefront-PRVS: 0798146F16 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(979002)(136003)(396003)(346002)(366004)(376002)(39860400002)(45074003)(199004)(189003)(16526019)(48376002)(186003)(1076002)(3846002)(5660300001)(486006)(6506007)(386003)(16586007)(316002)(36756003)(14444005)(44832011)(5009440100003)(52116002)(6116002)(2616005)(76176011)(446003)(51416003)(11346002)(956004)(476003)(6512007)(47776003)(106356001)(25786009)(50226002)(2906002)(68736007)(105586002)(81156014)(81166006)(7736002)(6666003)(305945005)(8676002)(8936002)(4326008)(86362001)(97736004)(6486002)(478600001)(50466002)(66066001)(26005)(53936002)(110426005)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4673; H:Tophie.ap.freescale.net; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM0PR04MB4673; 23:2LRR6xbUVbTBaWco/HKKmaggI6xa5lPRWyFJOZIPc?= wVLAtTAHgRvXzQLR36hwyKz3oWA6mJ1ux7AJ4DI7lt/czhtbUPcc9wKyfgsSrwFVPPQrZkpYDvnxdccbU1mff0DztiP+NoagizhjNEUcRZgWVCbRzyVjekE4gpSk+KahKsOFeNb0F0Bb1LG36I/7fAhJcVl6G0Cl0rFOtTxzIGj2S4CiSnPAKdmS4mMiNk3+BcCEIZu86Pg+BJq90Vdfl952z6lKjCmyfC+tvyGvkoyfnUCGVRSCS2oys7Ddf7++xUFQnq8qBkIiwPZOISCb38/dXMrngKAyHMb2IRvBqUCUFLPu5VG5wM8/ms37hglneyWA16Vq7Z1zr1zB3NzQk3ddonFE4L6CScRhMSXsFgAq/lj3DnwJs3I600pkTpK2AxT0Kpo7CjGT2bnFAivJVNhBzY+gX0LudXCVk80P1PKV7j+qE1KKRhiCmVrOoU4u5+AYa7MFg5nP833G2A6o+Cgy7OALUcvKjOpW6GzFH7md8UwQ4dB1JfyoJRYGQMApYHy/H44MYKay8kgxncD0DNKFGdR2Goxq78EvayqFc6q2+eryq266uerGCOjqCUeleMM1hYvLVZYt/CpJl5BEvs+N1yu3mZhAZun2qm9kKDIjk/AUvvXbtK/m8G2QgnD4QaJCMJX3pZ5iG9m1V5MpPIAhqr02qY3f7CzAXJnv12qjgBvUMdYiP/D238qM9iZZ2NFMu/cmH+MwwninwMCGRQWeN3KboIJhT0Sq9lrRNgQlVqFTXknqgSNCmDn5aEuD6gjmub5kUsY/6d5gX3W9D0O9Zm82xCv4jDuF/6EScTKs19wVcDo1GjPOD0BohPojOwVDzNQsndjqa9VWURKDh5MsCbXCInNbOxAU1x8hfyK01T4kHnF+4agrfIQUVkzjPFndtdKvZ/4Nupimg+20F3tZFJ2NmvsEDOi9w0Nffecc3/mpPJ1/YwKvHciKU2DhdxG+SxoysswBok2+/TF0vNTwTYIOXFmalsg1jq2XQv57UcLuijeLJG4mXzgnjry+dQa7kvKGquREOq65AVqFCGKwEM7/ovnHbs50dI0Imm7yn8skZdb/0XgiIRMccPhpdPjYTa1SBUCGj2Dhn3DvPXnwom/U2sLJ9XGTs8Se5zo6EtQ0C53kDrV15a5BlXMm0cuPJFNjGjaUm/UR9eZ+MwEf4uj6w1Ick7FUDxyYQjVP4VVdrJTLHYpY6Tpct0b9iV+lk4HqxdLbtaY+h/5kf5OvphTp0iBGgCgtXT1drecHrBX8iq+GcKSfSgX76sTMtSMLHoomJGUbZkvE6LQUbQNpGXW4IiUF6E0objTDSPD7jH0LU0DbXv4ntKISGjEJTU= X-Microsoft-Antispam-Message-Info: bR3lH4UBKMZhMVrnS0NKZdyc6feXSYhtc8jJCoSXp6fY2qW8hHrXVZIoFavLqoirPfN9lEfmgoMcksCs3SFH9Atzc7dMSDbXs9zi9efRg1Dw5eLuRtAJXjp03CX7KlGQM2CZCG3yzsXGqaSNhOSau1q/Ham++YFq6Hvd4WcKpkzNExGhnyA4plw/5np0m7znl5cgVTYpl8wg8HbPgYh2VpphWskcKukbj+Xq/rDrDTIup0BWKrYz4rZkX4KCUK56HkER8x2EwmDS8QwQrVuOh+yxD1MnEWsSOj57uO4RdUrBLbzMY17KoXpvzJUGdtaKpb7punVdr0eHJJQ0anADrSmue0gumc0Jyv042VYkGwc= X-Microsoft-Exchange-Diagnostics: 1; AM0PR04MB4673; 6:oE+rph/0JOMbO4+4rHHuaKML9EvyGcLG6TsidIGIErCGbXJR7gNJi25eW6RftvnOtUnFBo4pmVeHYDa62K8petzr3P6tnqNnsFKWJs7XidwGt0P/Ea9Adv6iuh5G5/y8tZa2bBhKEZoBJq2eN5+A/3tXc5++xlbZ56yHHXz6t/mHSSuLEPx+GgkCzgz++qnDPIiwpOvMF39D27nUi53x6bfPB9G4e69esa5BDISO29YrLhUl697rd7gJsmEt6ASNMM5GAGacEdThWy48mfKSaa6oKTd2TI+qhsDDz2BZIh+23++4KovQBgp57KVUcEuFQmyvEWAS7oAdid9YRM3UKcJjDFOaxT88vAtKYLIyEuy9fGlbxzax5zsIls1QZYPV9tbM+MlmiFv0aUU95igZg18NTuNhFTbmEFxyTEX41ov0Nb48bGBQe0dd0QBVgNKD5iQ/EaaFl7Vnnmfr1N96iA==; 5:iJDWbM4QBb4aRqjzbHp5S7Au3RSQ2Zb0p6O3o51lgnKatP9a9jIkgrIsmxhNW9B66z0iScKFBe0Ouegp5jzzbDxkimrY122dWGZ0vnkxL/cheC+1upCE+PCnier434JMtFIhe823+ixYxgEuW3OQWDO+ErHL6xgMTYfoiQXK6p0=; 7:eXwM7DGNwUvjYZgGPKL46TLlXRF/x12t2Nzcbp2th1t9vzrfLSG8htUJMRtqv807IaTW1LgyP4yWptWH4FZRA8S+98XCWtsqNQ8wBEyqWrKZSJmiWjTJb5dn5XNCFqWeuZ5Jrhaf/lPVfOG0TUjR5K9NCFwKGUNjk1z3cPrUlIFm1EKc1T9/SkW1/LmT8dE/SDv15R0lVZO72fWuRy+qVGNOxr9KGCpeQfm+o9rnYpC6Y9PiI41CogNQp8lONwuG SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2018 10:37:59.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b480560e-295f-44be-9966-08d61c89a3bb X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4673 Subject: [dpdk-dev] [PATCH 11/11] net/dpaa2: fix VLAN filter enablement X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Fixes: 0ebce6129bc6 ("net/dpaa2: support new ethdev offload APIs") Cc: stable@dpdk.org Signed-off-by: Hemant Agrawal --- drivers/net/dpaa2/dpaa2_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 1715e9f33..d9be3377b 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -407,7 +407,8 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev) } } - dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); + if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) + dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); /* update the current status */ dpaa2_dev_link_update(dev, 0);