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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id x93-v6si3654924qtd.54.2018.10.04.10.57.23 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 04 Oct 2018 10:57:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DUQrFhX3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58100 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87sJ-00069b-3s for patch@linaro.org; Thu, 04 Oct 2018 13:57:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60992) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87s7-00069U-Vs for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g87s3-0005hG-JT for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:11 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]:43881) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g87s3-0005g0-CO for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:07 -0400 Received: by mail-ot1-x333.google.com with SMTP id e21-v6so10059508otk.10 for ; Thu, 04 Oct 2018 10:57:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eoQfmeIbqQYNxqFOPaK1rddW7v/35ufvgMSTkPh3uTI=; b=DUQrFhX3vA8iB5oP8MZ5MWYhqtMWPbny+UoK0JAAxd1qAbrLaZTC4DNxytvxRg8nXn mof7MKArrvm1oUsnp71XP5OIHRWQykDEaxaWph5jjZg6EEjCCsTS45FWNBJI43/UX2Cp p36XlSsJu6fgtUDgdzVioKlyO/i94Qr2iiugI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eoQfmeIbqQYNxqFOPaK1rddW7v/35ufvgMSTkPh3uTI=; b=knlLzn802FA603qIHX8eK6B7aLW5sfGVvalQuoQzQ4P8jF9rGwZYZc5XEy/dFdDJru 0ZHaI7cgu3DnJ7OjtPf/8k8fQZ7U47/bVhGlqFJ0FhT5EHP38hHZEVgo0FEHYjw3AEcP a0eualiZPE8Go/5lPLnJXn08mllYtYLK+kR85nRSiY3pf764qrSImgQkVuaZjmBac73x /ZbBahCE/t0qsxUzdHlnvJg9bGVbVEPRJjz0K4+IL6ZKyK92qcEXb/YCqvNKgl/QNRRi 3zm/vA8Wsr2ITy+APi3i2+xzLqhrHMy/pWm+X6nzcc7uH7BzQfM6ZQdsgUG9D1iCLktu zKaQ== X-Gm-Message-State: ABuFfohw30OwGMZNMNpCsX6GvT8v2HNZDAzv4A9N6O2Xy51HDmrqqBF4 +j8TwmOfuzz01SW9QxXFCkIIDb3asoE3iQ== X-Received: by 2002:a9d:76d:: with SMTP id 100mr4486917ote.153.1538675825753; Thu, 04 Oct 2018 10:57:05 -0700 (PDT) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id f84-v6sm1830649oia.44.2018.10.04.10.57.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Oct 2018 10:57:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Oct 2018 12:56:57 -0500 Message-Id: <20181004175700.20847-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181004175700.20847-1-richard.henderson@linaro.org> References: <20181004175700.20847-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::333 Subject: [Qemu-devel] [PATCH v3 1/4] softfloat: Fix division X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The __udiv_qrnnd primitive that we nicked from gmp requires its inputs to be normalized. We were not doing that. Because the inputs are nearly normalized already, finishing that is trivial. Replace div128to64 with a "proper" udiv_qrnnd, so that this remains a reusable primitive. Fixes: cf07323d494 Fixes: https://bugs.launchpad.net/qemu/+bug/1793119 Tested-by: Emilio G. Cota Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 34 ++++++++++++++++++++++++--------- fpu/softfloat.c | 35 ++++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index edc682139e..a1d99c730d 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -329,15 +329,30 @@ static inline void | pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. *----------------------------------------------------------------------------*/ -static inline void - shortShift128Left( - uint64_t a0, uint64_t a1, int count, uint64_t *z0Ptr, uint64_t *z1Ptr) +static inline void shortShift128Left(uint64_t a0, uint64_t a1, int count, + uint64_t *z0Ptr, uint64_t *z1Ptr) { + *z1Ptr = a1 << count; + *z0Ptr = count == 0 ? a0 : (a0 << count) | (a1 >> (-count & 63)); +} - *z1Ptr = a1<>( ( - count ) & 63 ) ); +/*---------------------------------------------------------------------------- +| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the +| number of bits given in `count'. Any bits shifted off are lost. The value +| of `count' may be greater than 64. The result is broken into two 64-bit +| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. +*----------------------------------------------------------------------------*/ +static inline void shift128Left(uint64_t a0, uint64_t a1, int count, + uint64_t *z0Ptr, uint64_t *z1Ptr) +{ + if (count < 64) { + *z1Ptr = a1 << count; + *z0Ptr = count == 0 ? a0 : (a0 << count) | (a1 >> (-count & 63)); + } else { + *z1Ptr = 0; + *z0Ptr = a1 << (count - 64); + } } /*---------------------------------------------------------------------------- @@ -619,7 +634,8 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b) * * Licensed under the GPLv2/LGPLv3 */ -static inline uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d) +static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, + uint64_t n0, uint64_t d) { uint64_t d0, d1, q0, q1, r1, r0, m; @@ -658,8 +674,8 @@ static inline uint64_t div128To64(uint64_t n0, uint64_t n1, uint64_t d) } r0 -= m; - /* Return remainder in LSB */ - return (q1 << 32) | q0 | (r0 != 0); + *r = r0; + return (q1 << 32) | q0; } /*---------------------------------------------------------------------------- diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 71da0f68bb..46ae206172 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1112,19 +1112,38 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) bool sign = a.sign ^ b.sign; if (a.cls == float_class_normal && b.cls == float_class_normal) { - uint64_t temp_lo, temp_hi; + uint64_t n0, n1, q, r; int exp = a.exp - b.exp; + + /* + * We want a 2*N / N-bit division to produce exactly an N-bit + * result, so that we do not lose any precision and so that we + * do not have to renormalize afterward. If A.frac < B.frac, + * then division would produce an (N-1)-bit result; shift A left + * by one to produce the an N-bit result, and decrement the + * exponent to match. + * + * The udiv_qrnnd algorithm that we're using requires normalization, + * i.e. the msb of the denominator must be set. Since we know that + * DECOMPOSED_BINARY_POINT is msb-1, the inputs must be shifted left + * by one (more), and the remainder must be shifted right by one. + */ if (a.frac < b.frac) { exp -= 1; - shortShift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, - &temp_hi, &temp_lo); + shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 2, &n1, &n0); } else { - shortShift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, - &temp_hi, &temp_lo); + shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0); } - /* LSB of quot is set if inexact which roundandpack will use - * to set flags. Yet again we re-use a for the result */ - a.frac = div128To64(temp_lo, temp_hi, b.frac); + q = udiv_qrnnd(&r, n1, n0, b.frac << 1); + + /* + * Set lsb if there is a remainder, to set inexact. + * As mentioned above, to find the actual value of the remainder we + * would need to shift right, but (1) we are only concerned about + * non-zero-ness, and (2) the remainder will always be even because + * both inputs to the division primitive are even. + */ + a.frac = q | (r != 0); a.sign = sign; a.exp = exp; return a; From patchwork Thu Oct 4 17:56:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148121 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1285381lji; Thu, 4 Oct 2018 10:59:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV62zZb5OaOzlEzvmkTtvmxq0kBPwjZP5X9NIQ22Lq1fV5a1xUDr8ZyjDlAGyjl3ozrvV4fEp X-Received: by 2002:ae9:e507:: with SMTP id w7-v6mr5854494qkf.246.1538675988252; Thu, 04 Oct 2018 10:59:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538675988; cv=none; d=google.com; s=arc-20160816; b=GU0qumCxy0cEtQAy0kI+euTFpwX7WlJ3jHJuywNHhRTLRCQ+edie0jDVhvAXP7LNHV b/R8MF7VYcJcoT/zg/JrtGqHcn4Anse+XUxdm80cVDeiP693sO2MJnBb328GC7eeHx7s EZSjZBK+Xtou2G/XjOQGN98bPV8YSZ8SLRJRrZEPJ7J5x2U6g4gYJmLV5D7kTV433Mni wEea8nZOvC+odPQIrKNevbe8PU729jMjVBxiOo7kgJYiwklYJutbm0NiEOazcoFv6119 0MHnuymGylO+SL95aK4Rozuedq5YwWXAIAX4R+sCo+pNyPE+RVKHebTAI7vQO0OmxIyl kNLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cRmMqmBeH6CVVhBpy5pb3rhG/pnTWg+KHZ8CbvTFIJs=; b=RnJPE/P3PxNee+kEwr9HUeDBo8aRT1vanT9XItv2mGImmDVR/kaZVY7ZKUT0N+Kx3G Ln3Q5XmHMdns+NQIY66mhwBt6x4b6rYQTPilz7EMSxJwcXmCmuQsB0meOxugB80VwJC3 2hp5Fhutom2go1Gi9+HcSbcUsjABqOTD5C39t2nfPzS4hTBnOfYuVdBy1+Mwxlp5BudB 6sSL0vLeGxYH2htvpgq2uro7XUko162Nv3lhb/+dnJQeiw+OrhgRjM+KebUQG7W+ajzS pMNy6KEZi+FpLbj/OhjGbP3i49caDuwJdrs4G4yA2cgx3QJmraWawvijDOjAMr16R8fF KpfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Usei+u1k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v3 2/4] softfloat: Specialize udiv_qrnnd for x86_64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ISA has a 128/64-bit division instruction. Tested-by: Emilio G. Cota Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index a1d99c730d..39eb08b4f1 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -637,6 +637,11 @@ static inline uint64_t estimateDiv128To64(uint64_t a0, uint64_t a1, uint64_t b) static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, uint64_t n0, uint64_t d) { +#if defined(__x86_64__) + uint64_t q; + asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); + return q; +#else uint64_t d0, d1, q0, q1, r1, r0, m; d0 = (uint32_t)d; @@ -676,6 +681,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, *r = r0; return (q1 << 32) | q0; +#endif } /*---------------------------------------------------------------------------- From patchwork Thu Oct 4 17:56:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148123 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1287910lji; Thu, 4 Oct 2018 11:01:53 -0700 (PDT) X-Google-Smtp-Source: ACcGV608FYMtaI0tbJeb6qh7+g4ZiLelsU9IgcNVhP0qFjOnfEN++I5EL6VX3bJXn72woNoENF7e X-Received: by 2002:a37:a49:: with SMTP id 70-v6mr5980271qkk.63.1538676112910; Thu, 04 Oct 2018 11:01:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538676112; cv=none; d=google.com; s=arc-20160816; b=NdHzGpK7fCMOj/6rHgVE3OXF1epuWxFPUTtFYpZpau8v8oDPQqKa0jgliSrAe9GyPF gM1XVqx/XGdY5Qd/wGKFITTfqHLxEjjlABF+dGFnN8haxQqqYkkZvH87zrSeqgAPA/9i 47i9xQ4Uk3w4Ay5wpxcmYVCS92lrBp8fis/QPJlf7X2sP9stdH+6s2GmKoReUZuPL3+8 kNFw0t2bJ6vwFHyppOD+GOM+JG627bWmHAK86SBdgc/KodiUbMKrkJtOZU8oW7tJkyhU ydjn5qqx0efU7cLHkYot5VLC4nbvH555W9EcQ4bh1hEqQ1S5aoQfBtnfhY09Sq13V5ZF h8Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=xKPvW5IjWZu4Fj5tr9JMUkuXW0J49HylPrXBi7VJgeY=; b=tzuVUr9ew66A3Wz8wedPuownfyhOXB5rPoaPrchuJTfn5EmB+Pjo9GEPZCca9D8/Tx STtviyY6v+OvmkiCFnDPKDisbeQV17REJqKe0GA04g+mrj/UTvrrSTleRM3rBzcW1l18 vWFBbWKMmwJN5gKgGWW/M1mmtsPIGMaqof4T/oFs6FceXXB3OHysGvnw309naGV4itTI 4S382yEkJ9iDgeUrzwMkflWtIYmcOriWZ7ZGBj21mj2kLHQL9tRO+9pAMIQ0pwIXL0pA jR2aHtLpAJsxLzbAock7AwI1Ik/P4phakCZLHmh4EyJtBCQiDxWUjRLWyFOQJgQozZIv xS1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IbfK+tzH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 34-v6si3317426qtp.70.2018.10.04.11.01.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 04 Oct 2018 11:01:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IbfK+tzH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58126 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87we-0001E5-6q for patch@linaro.org; Thu, 04 Oct 2018 14:01:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87sH-0006Du-BT for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g87s7-0005le-9d for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:17 -0400 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:36017) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g87s6-0005kf-P0 for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:10 -0400 Received: by mail-ot1-x342.google.com with SMTP id c18-v6so10085890otm.3 for ; Thu, 04 Oct 2018 10:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xKPvW5IjWZu4Fj5tr9JMUkuXW0J49HylPrXBi7VJgeY=; b=IbfK+tzHzKB8j1kIu/vo26T8zGw1fVMwsDBbSsLTwsEYQstb5PWXxEeaRszc/E4ioo 0LWZgVY3o2mZiZBCj853aKMhZdL4ThwWZv9AJyAJT1p+zuWhODAylvSJENL3GZ1CzYpM Pwl6mJvxgfmdXaT44oa3nPqq0S7LqP/Vm8JS8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xKPvW5IjWZu4Fj5tr9JMUkuXW0J49HylPrXBi7VJgeY=; b=mTo4dRsvM9TB9wFebhC5DktTTFP7BrSnBLo5bVggRctCV2wDx5SRmVgl6BxaQ5KjeY BX2dWzUYEKlS2SM4M0kVtNqSN+aiu/GfOM2cfwEEaRpSwej7x9Vwk/k4uSRxa1p1ftTA 6iZVy/IkFLo6laTpLoVSbFWncOWE32IzB7+BgHToLsPrS1SJO5ZRwAcApNAE+gUDIxz+ cdGXmDinOHEpvBUZ79sLcAab+p2id+c6qC2ALpzHW46QnMUh8BsHelsPz1M5QHkyzvKy VIU+/IDKvQqmyheBvpAPqCibEzO5szI7gOsQqbYz8D4p49ZldYzugQZh9viDYNA+Rd3v bgKA== X-Gm-Message-State: ABuFfohPtaJ9WLEoqZwH766BVaauYPPxb6fj5xtT4cSi/nH7HigLwKyB PVHkpeIgh3zLSHsx9q5B15JGYYEME/iTLA== X-Received: by 2002:a9d:5148:: with SMTP id u8mr4103456oti.5.1538675829712; Thu, 04 Oct 2018 10:57:09 -0700 (PDT) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id f84-v6sm1830649oia.44.2018.10.04.10.57.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Oct 2018 10:57:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Oct 2018 12:56:59 -0500 Message-Id: <20181004175700.20847-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181004175700.20847-1-richard.henderson@linaro.org> References: <20181004175700.20847-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v3 3/4] softfloat: Specialize udiv_qrnnd for s390x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ISA has a 128/64-bit division instruction. Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 39eb08b4f1..eafc68932b 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -641,6 +641,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, uint64_t q; asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); return q; +#elif defined(__s390x__) + /* Need to use a TImode type to get an even register pair for DLGR. */ + unsigned __int128 n = (unsigned __int128)n1 << 64 | n0; + asm("dlgr %0, %1" : "+r"(n) : "r"(d)); + *r = n >> 64; + return n; #else uint64_t d0, d1, q0, q1, r1, r0, m; From patchwork Thu Oct 4 17:57:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148120 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1283683lji; Thu, 4 Oct 2018 10:57:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV63Tgfp/WBmWFdo2DXRMTqCnJYWWCnHbZk+vFZua/Ze6s3m55Xc4amkdfGmLSHjdYNWjcmQi X-Received: by 2002:a0c:f4d1:: with SMTP id o17-v6mr6361936qvm.33.1538675871318; Thu, 04 Oct 2018 10:57:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538675871; cv=none; d=google.com; s=arc-20160816; b=rf2RrIFjbHq6a+Z3p0mJjGase4aWfk3afN28fWCUVU0dMwNjzkeOMUOGqUgcf8mz4Z QMdhdnFAtPDMZTDjavOoI4uDVq+/t6cKyzfA6EK3hmLI5XR3wpNFaGOmsCW4VtqBDSCb /UkficitPh3cbTlM5UqWdTbS1JfKqCSm+vOOLEogyGFeIUC1CB5ZLyommT1Rgcmstggv 0x1Rlw9rr5qhLDL7WFMsiFasqiYmBU3h52nEhDFVkdMGTY24yjrNN7sVOeFidjqWkY3G mCqd51wl0FNnID/y7hUqqm6dgS8CEWa4d5Vv+cfWIVNBQ8es7Cj0/8Y12dw8mOd6jfEy 4Njg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=X5a/KvnsV8gRrymCZvMRPaAHMUoAfW8yBsI+pfK7k9k=; b=NNwNtaVHmy3ZU+fogLyXT5PDkzDrgLkcGbYjBNdRK0QgHphkDobnWMfBrMctTWdxg6 g6AXGqcYbMjNPwpAFH2UtF9zKTrT58uBobKcjshQSddw5ImjzcBrNUmBuLymeLpSXHJj HrUTHGTQI/HCj3aFHYLk/N5hjpEDYdMZbH7SRo1hTB3EzMv7blWhDrgu5gUXEQxkqJSb skJUyU0a0ULDeANLGloHaJaZ5skUGTHUF7Ox73Xo1wjkuTGUgs2c5OFuFmEX1y5n74dN WiAfYtjVpsS9KTkDBrwnc/rpDbPotR9WVRTF94IXqlxYt1VitMbqbSKYmeJsa4NzM0n6 6CIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AftpCVuL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n12-v6si3707975qta.256.2018.10.04.10.57.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 04 Oct 2018 10:57:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AftpCVuL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87sk-0006Gz-Ra for patch@linaro.org; Thu, 04 Oct 2018 13:57:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32814) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g87sM-0006Fu-JT for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g87sK-0005vW-ME for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:26 -0400 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:35170) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g87sK-0005mq-4h for qemu-devel@nongnu.org; Thu, 04 Oct 2018 13:57:24 -0400 Received: by mail-oi1-x243.google.com with SMTP id 22-v6so7235216oiz.2 for ; Thu, 04 Oct 2018 10:57:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X5a/KvnsV8gRrymCZvMRPaAHMUoAfW8yBsI+pfK7k9k=; b=AftpCVuLuCR6waok4+StaLcsUa1LkEegQzSliCJW8cvAhx9uGc+ABVd7vMV0z2Vo0t QMyuyZ1jFnenT8/IK602xwtntQxTue+LywO8U0b7AxUkUHlNFdOmNRaIdO8YCIfC23Sq rSqXq0IV8yVhCTiDLTue0stWFWir5ep5Ssekg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X5a/KvnsV8gRrymCZvMRPaAHMUoAfW8yBsI+pfK7k9k=; b=OdTGQUC9/s0RXT5+iZE4VCV7sJOxqkdRbRgnmy98KlE8+VSrowyD0tTnoT0uGd2nA5 rG4gKTztMmMetQaPxUshqZ+XarJl2V8ezGLoKPlrVbfh3rkf5DryJoFB3D+8CiS023mM ccQRIqfxMfMJ/Z596i3i6D9PQfLZ4KKdmIKMe0mxzWb8j21zVVp69egaAdihQB/njBIM 0Su8EIZSKRNj0L1zDE1tIjhRaTA81us+DLPzfdhsvLNPt8mA0fs8+ON+OmKo2QxDfSUV +RKJgBgmQis8v4PB4JdkjBDMSk70+r7SFu5b2lw3nwJ1ug0lfJqYu1T2PUaaW2WFxbTW 1SEQ== X-Gm-Message-State: ABuFfojEReF1eUlcP6ybqupodwFgtLSIBHXGvAUm9QMz9B0aCzZgw+pR dfzubJzp5e0M3Zi6YaiSh2G0Qiz8bQGhMw== X-Received: by 2002:aca:ce4c:: with SMTP id e73-v6mr3373560oig.225.1538675831284; Thu, 04 Oct 2018 10:57:11 -0700 (PDT) Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id f84-v6sm1830649oia.44.2018.10.04.10.57.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 Oct 2018 10:57:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 4 Oct 2018 12:57:00 -0500 Message-Id: <20181004175700.20847-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181004175700.20847-1-richard.henderson@linaro.org> References: <20181004175700.20847-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v3 4/4] softfloat: Specialize udiv_qrnnd for ppc64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index eafc68932b..c86687fa5e 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -647,6 +647,22 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r = n >> 64; return n; +#elif defined(_ARCH_PPC64) + /* From Power ISA 3.0B, programming note for divdeu. */ + uint64_t q1, q2, Q, r1, r2, R; + asm("divdeu %0,%2,%4; divdu %1,%3,%4" + : "=&r"(q1), "=r"(q2) + : "r"(n1), "r"(n0), "r"(d)); + r1 = -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ + r2 = n0 - (q2 * d); + Q = q1 + q2; + R = r1 + r2; + if (R >= d || R < r2) { /* overflow implies R > d */ + Q += 1; + R -= d; + } + *r = R; + return Q; #else uint64_t d0, d1, q0, q1, r1, r0, m;