From patchwork Fri Oct 5 16:58:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148229 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688773lji; Fri, 5 Oct 2018 09:58:56 -0700 (PDT) X-Google-Smtp-Source: ACcGV620zgQdV48FTMmho9liJng8nf4fCtxC+DdlrswfmhGHhmKevtXasap2L/GF48gBFLLY9Dss X-Received: by 2002:a63:100c:: with SMTP id f12-v6mr2144605pgl.38.1538758736379; Fri, 05 Oct 2018 09:58:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758736; cv=none; d=google.com; s=arc-20160816; b=kmuCW70YlVrV7gLuk1IXrOOCy0s3aXuAsg6pl226H2f/8cb4A+tRBoJPEkdswA/Lkn UfXz7H+70ZfZEIvp9+mMYrA7NbviSe5GjdWUqKNcGEojFp4cgN8JWQ7wRgcQx18QLTZt GY86e8SR2RJj5/vQxa3tzE8FAPXZAqsxTPuhyE5OMXlmrQfnY3jc8oL/H8Bu357mWjWI ITTlgBE+J2C+8/h27yvTZ/e/COqVS0FpA9fHREZkCb5/s4gp4AIzM2bK2Y3ToS+Dy37G TBRK2tHjEY4PppyKG9rRBcLYWutVnVvqUeSMpmu5oGBgV3TOlO/Xi/xpeAW92dusQ+wi LHgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=71oY5HWjvjta+vASdeqnC6CknPvTEuU3/FDPawmJ7HI=; b=ERTXHLaF8FsCqwOkFGcpOSRDaAOW2JCsm8fhdhNueCZB5SGYFGoHz+OhT5qei8W7A2 RkLQbxQasffSC+kGeOM5FV4SMi4J0x3y2+UTvJx+wx6AmWniOzoulhEb1pjK0w5+Tv31 cIRyJrlXveIE6Uxr+9OqPA+fsVdJ6hbqjc2Hov9ouGHQo/VewoAjsp/QzRk11aHOUCBu o7eXv3iX1PcE5NKk+UPEn1WcsqVlQhXGEUTbKcI/URUQLI2f74swcjIvEjWLckDCAklF 2MpW+TN7tinwfhAR0wmaY9Dmh4GT2Y1t753ymiuSN24+WwGdf8D3x7FSa+fhFmdlXarm zM8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q185-v6si9792546pfb.277.2018.10.05.09.58.56; Fri, 05 Oct 2018 09:58:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728766AbeJEX61 (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:27 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:39916 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728160AbeJEX60 (ORCPT ); Fri, 5 Oct 2018 19:58:26 -0400 Received: by mail-ot1-f67.google.com with SMTP id c20-v6so13345479otl.6; Fri, 05 Oct 2018 09:58:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=71oY5HWjvjta+vASdeqnC6CknPvTEuU3/FDPawmJ7HI=; b=tUaLnFrZb5US74nXKpOrVjuq/Jy0brkhvUVAP5J5ZUi4HUzLd/G7coRUAPbDZzXMRk Zri7Infk6u2Bbg3tCO+CS3eXRP0/SfjROF4eEctE5S8aD6HVfc9j5XaJisV/dA2DdB1d Gr8lc674xUbUum6ib9IeOmGW+SGyyYjjHbf3vxeOhvifWteujCeDUgxHYfm2xEHZDoi9 T6xvPDnevS7IFAXv08gPTkcoEgd0RAk5KVaqCAj56aYPEUjc8PdtMCzmvt8NSXYrc0va IItC57j2s653tIyUbsg5sRcwACcbD0JwC2AK7JBXV1mVtnWO+sXMnGNdptxW5C5TbAO3 youA== X-Gm-Message-State: ABuFfohCcm+II5l/qXCjMgGRNS93A42ymOa8jBNqBlvKX7WlchDnEcpx N7RriHaJhWqgOlxD9XnZTU5VDMpSbQ== X-Received: by 2002:a9d:2992:: with SMTP id n18mr661801otb.54.1538758731588; Fri, 05 Oct 2018 09:58:51 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:51 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Tsahee Zidenberg , Antoine Tenart Subject: [PATCH 01/36] dt-bindings: arm: alpine: Move CPU control related binding to cpu-enable-method/al, alpine-smp Date: Fri, 5 Oct 2018 11:58:13 -0500 Message-Id: <20181005165848.3474-2-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It is best practice to have 1 binding per file, so board level bindings should be separate for various misc SoC bindings. Move the Alpine CPU control to al,alpine-smp and we can also remove a cross reference. Cc: Tsahee Zidenberg Cc: Antoine Tenart Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/al,alpine.txt | 72 ------------------- .../arm/cpu-enable-method/al,alpine-smp | 34 ++++++++- 2 files changed, 31 insertions(+), 75 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt index f404a4f9b165..d00debe2e86f 100644 --- a/Documentation/devicetree/bindings/arm/al,alpine.txt +++ b/Documentation/devicetree/bindings/arm/al,alpine.txt @@ -14,75 +14,3 @@ compatible: must contain "al,alpine" ... } - -* CPU node: - -The Alpine platform includes cortex-a15 cores. -enable-method: must be "al,alpine-smp" to allow smp [1] - -Example: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "al,alpine-smp"; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; -}; - - -* Alpine CPU resume registers - -The CPU resume register are used to define required resume address after -reset. - -Properties: -- compatible : Should contain "al,alpine-cpu-resume". -- reg : Offset and length of the register set for the device - -Example: - -cpu_resume { - compatible = "al,alpine-cpu-resume"; - reg = <0xfbff5ed0 0x30>; -}; - -* Alpine System-Fabric Service Registers - -The System-Fabric Service Registers allow various operation on CPU and -system fabric, like powering CPUs off. - -Properties: -- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". -- reg : Offset and length of the register set for the device - -Example: - -nb_service { - compatible = "al,alpine-sysfabric-service", "syscon"; - reg = <0xfb070000 0x10000>; -}; - -[1] arm/cpu-enable-method/al,alpine-smp diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp index c2e0cc5e4cfd..35e5afb6d9ad 100644 --- a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp @@ -14,7 +14,28 @@ Related properties: (none) Note: This enable method requires valid nodes compatible with -"al,alpine-cpu-resume" and "al,alpine-nb-service"[1]. +"al,alpine-cpu-resume" and "al,alpine-nb-service". + + +* Alpine CPU resume registers + +The CPU resume register are used to define required resume address after +reset. + +Properties: +- compatible : Should contain "al,alpine-cpu-resume". +- reg : Offset and length of the register set for the device + + +* Alpine System-Fabric Service Registers + +The System-Fabric Service Registers allow various operation on CPU and +system fabric, like powering CPUs off. + +Properties: +- compatible : Should contain "al,alpine-sysfabric-service" and "syscon". +- reg : Offset and length of the register set for the device + Example: @@ -48,5 +69,12 @@ cpus { }; }; --- -[1] arm/al,alpine.txt +cpu_resume { + compatible = "al,alpine-cpu-resume"; + reg = <0xfbff5ed0 0x30>; +}; + +nb_service { + compatible = "al,alpine-sysfabric-service", "syscon"; + reg = <0xfb070000 0x10000>; +}; From patchwork Fri Oct 5 16:58:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148230 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688782lji; Fri, 5 Oct 2018 09:58:57 -0700 (PDT) X-Google-Smtp-Source: ACcGV606fyFzpDs87tSp1g2bSN3zi+Fa+5Rlb7gECHD8okHSyNByK8xoPY9MiiU7lv1L2WnS/+Pu X-Received: by 2002:a63:fe13:: with SMTP id p19-v6mr10976847pgh.265.1538758737032; Fri, 05 Oct 2018 09:58:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758737; cv=none; d=google.com; s=arc-20160816; b=VKvfEj3RgWXg4NVQLC0TNWD/HzQ24cKrisnSlr8Py2ZPw73AI/AEpHo6jeILfnw7De 6IMi3orYUURB3W3Pv3PsrkLLZHPPwdF6sxXoWvt4oMjpM8dSdotxRCDHUNKinuune5B3 Uv77JEYkMFun3czCksMJ6B68FqIqEATsmfwQLTxnMXzPqs80nxu0jSY74/HQF9cVi1gx th1iyuUGHwhQneLkffEiPVTGQ4dVZPdiqleuIlrgdeWfSl/8erBInZXDZfCyQ+CLfgiQ 9yXxXOauB9vV17F00vhqhWOTLYmk9RyJC/6NQToCl64nfwb6/SfOdo6SLOWinZQ46Phe h7uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=nWJ/W+jar+UdXjg1HaxmR9q3z8+XxFV2Te6InmR2rr4=; b=Pr2kuR/KFV4zZJ4JcXi3qpuWh9qh0wl89qUB+YwMEzOxMaT4tOJb4PkS6eVp1eFrSL 4rdsVL1B+YhO/sDrszDAnHRySAhedLGHMDtAtXux5TBuboPdS142Cgv9bN3RTOCE4FzC F+Xn9d9OJmEJowUXXwh4nTHq0uaBivu14zOp0Y+TjAYsk+dgXBsimB25AeNFbDfmL2l5 FsmCLfzGaEg6sTGNFishdCF1J6hvZEPHfWXI9lFZ53rtguoqyv2TLIkaRWM//3pWMFHH 5dQ+EL6wU7lp3dVXIjEAY8SNdPrLF3p0ZuOjB6c1v4x5sx/RI0LQEIWOSGp2OdpdRm0z 7A2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q185-v6si9792546pfb.277.2018.10.05.09.58.56; Fri, 05 Oct 2018 09:58:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728819AbeJEX62 (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:28 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:42893 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbeJEX62 (ORCPT ); Fri, 5 Oct 2018 19:58:28 -0400 Received: by mail-ot1-f68.google.com with SMTP id h26-v6so13359764otl.9; Fri, 05 Oct 2018 09:58:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nWJ/W+jar+UdXjg1HaxmR9q3z8+XxFV2Te6InmR2rr4=; b=d44uhtnv3WJRolJCk5WkGnfLR8+RItiUlq62aVLgCGODzfkyKooPQrKqLl4kxYjr/S yeULEgxfdULuSp8yz4WFmOal5cWzSeKZaiKTpLzZYxOPtBhH5cx+qe7CSzzsnZlVfrwn ku3F0VxOemJdvHutIDVZJXPUs0723HPp5mwdY1qnJLxVVS1gXsyEv+IffR2YFWNcT1Kd haOObEyAuibc/8F407eE3DM8Xq8D8t4+Kw8sKpoPIi899xjygm9rtqcDubiDDKQp4FE5 GzYN/vBhfE+OvIIDoF14b+BtLIp6DzcrnOP5OAfqnMq9CvaREtXKR8aMDv7OfpquijVo J5aA== X-Gm-Message-State: ABuFfogyJW4Xg6i56ud6nra5uoo06M/jyWgbWtor/cb7z41Of4DfjyM3 yvhkEatXzDqrIj+vGtoClngYerK2JQ== X-Received: by 2002:a9d:76d:: with SMTP id 100mr7220736ote.153.1538758733044; Fri, 05 Oct 2018 09:58:53 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:52 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Carlo Caione , Kevin Hilman , linux-amlogic@lists.infradead.org Subject: [PATCH 02/36] dt-bindings: arm: amlogic: Move 'amlogic, meson-gx-ao-secure' binding to its own file Date: Fri, 5 Oct 2018 11:58:14 -0500 Message-Id: <20181005165848.3474-3-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It is best practice to have 1 binding per file, so board level bindings should be separate for various misc SoC bindings. Cc: Mark Rutland Cc: Carlo Caione Cc: Kevin Hilman Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/amlogic.txt | 29 ------------------- .../amlogic/amlogic,meson-gx-ao-secure.txt | 28 ++++++++++++++++++ 2 files changed, 28 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index b5c2b5c35766..2f2d01a00c54 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -100,32 +100,3 @@ Board compatible values (alphabetically, grouped by SoC): - "tronsmart,vega-s96" (Meson gxm s912) - "amlogic,s400" (Meson axg a113d) - -Amlogic Meson Firmware registers Interface ------------------------------------------- - -The Meson SoCs have a register bank with status and data shared with the -secure firmware. - -Required properties: - - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon" - -Properties should indentify components of this register interface : - -Meson GX SoC Information ------------------------- -A firmware register encodes the SoC type, package and revision information on -the Meson GX SoCs. -If present, the following property should be added : - -Optional properties: - - amlogic,has-chip-id: If present, the interface gives the current SoC version. - -Example -------- - -ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; -}; diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt new file mode 100644 index 000000000000..c67d9f48fb91 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt @@ -0,0 +1,28 @@ +Amlogic Meson Firmware registers Interface +------------------------------------------ + +The Meson SoCs have a register bank with status and data shared with the +secure firmware. + +Required properties: + - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon" + +Properties should indentify components of this register interface : + +Meson GX SoC Information +------------------------ +A firmware register encodes the SoC type, package and revision information on +the Meson GX SoCs. +If present, the following property should be added : + +Optional properties: + - amlogic,has-chip-id: If present, the interface gives the current SoC version. + +Example +------- + +ao-secure@140 { + compatible = "amlogic,meson-gx-ao-secure", "syscon"; + reg = <0x0 0x140 0x0 0x140>; + amlogic,has-chip-id; +}; From patchwork Fri Oct 5 16:58:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148231 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688823lji; Fri, 5 Oct 2018 09:58:59 -0700 (PDT) X-Google-Smtp-Source: ACcGV63GV3nx4DghuW5rCJhqatWsVcZ3uWGE7nvrnigQ+DY9OkaDvQdYTTCrSqz6ACa83WmvV+v6 X-Received: by 2002:a17:902:6907:: with SMTP id j7-v6mr12533653plk.232.1538758739587; Fri, 05 Oct 2018 09:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758739; cv=none; d=google.com; s=arc-20160816; b=D6dT4XSlGq0nGhA3I3L8X80Tv3IZ8xDDi2sv2eNYA3PzFB/thSiJMl1+v55zcQGVOs EfSbQyXv025Rpc0dS4yZmfe9nGnpdPjG2hs9C8A509BVsfIM4m4btGUK3So4TC755b79 i9k0EVaYZc4Hyr+Mne1FuADWKlsdU81IUG51D1HZGcOS8wfJHJLJMfCGjj2xqszvTgxa WJeAMORWXOgNiCXcyYYFIsLoRWER3wH+CaZ2rKMKz9h2xo4Bt4brpM9mCuPPWhfRBOII 2h6Lzfj1P6nGzGEn+O35dCwnzwP0FD7iZ7CiKZd2DUBNuduAcxm/ayUKDl/9i1t3a03G qvbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=VtoR2oRqKzf2lI1MPPT0c7kPsIXdB0xyaajjOkNkhmQ=; b=Yd9+z7XVrpij22Dy1jLzA+lMSPlUo1eHEr98ufTnGX6mCQQGOdr3M8uri/9uHNEYFr cRQb5aCFjK3nh5Y+upMvkGvdGdabC6XCsaJ4T+dTvVuPAiy7ERW+cX0RYAKPYIJ2Sfqu 7NVYwxPMEbouwLly63xqYlzXguLxk5yZJ2JkLfwPZ53MAK0q73tkgok28Boh/2YZF8Ol luA8z6LyUHQYbxppkrstkDJEJcf8JpbgQVTwtzoYS+46E5E50QTTHLTDalV5DXRjlkHf EO8LlStH+Rw6FkcnQS4QLEQWnso+PBileMG2CPS5KHjg3t+UIH1bBYOqAx6WF6FKMjTX RafA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 202-v6si9304166pfz.227.2018.10.05.09.58.59; Fri, 05 Oct 2018 09:58:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728890AbeJEX6a (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:30 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:36847 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbeJEX63 (ORCPT ); Fri, 5 Oct 2018 19:58:29 -0400 Received: by mail-ot1-f65.google.com with SMTP id k5so558039ote.3; Fri, 05 Oct 2018 09:58:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VtoR2oRqKzf2lI1MPPT0c7kPsIXdB0xyaajjOkNkhmQ=; b=jRs98tRqLO6smI1TbaqI3Nh2kdXThI0kyTYin9Jms7m2WbIVlSUiw1ttYYDJIeFO70 hD18Urhc2Kbt6CoiyIHV5Gk0Zu5r4TAt0lHqM9iNQWRioGzLp/wYVncrq04Ua/3SMGtj /LLXcUZpVcN9F0TgNNttUwVqixeglkOslrS7sF3tjIXJk/4wxoYEpNr4gomb9udJeeRA qHA8aPGp5uvrpcNws7lMYryfSeN267FeJel4MjSG7OZPsudSE1+E55wWYZr4HUTSID1+ l3I30CU0FVeBVbeF3e+QAncWhL+hrVUwOqjGaYRJwo13/fG2OosrJL4NGxXi4pX9Ws8V WF4g== X-Gm-Message-State: ABuFfojF16Tpl2sxWp/f6cb4hUUAigtpbrnLEV7N/5MlzKZQ+wzx/PN0 JMbYlnV7ecs2eN2FoS9UT/ng4IY9kQ== X-Received: by 2002:a9d:2186:: with SMTP id s6-v6mr6588825otb.67.1538758734571; Fri, 05 Oct 2018 09:58:54 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:54 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Nicolas Ferre , Alexandre Belloni Subject: [PATCH 03/36] dt-bindings: arm: atmel: Move various sys registers out of SoC binding doc Date: Fri, 5 Oct 2018 11:58:15 -0500 Message-Id: <20181005165848.3474-4-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Cc: Mark Rutland Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/atmel-at91.txt | 170 ----------------- .../devicetree/bindings/arm/atmel-sysregs.txt | 171 ++++++++++++++++++ 2 files changed, 171 insertions(+), 170 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel-sysregs.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 31220b54d85d..4bf1b4da7659 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -70,173 +70,3 @@ compatible: must be one of: - "atmel,samv71q19" - "atmel,samv71q20" - "atmel,samv71q21" - -Chipid required properties: -- compatible: Should be "atmel,sama5d2-chipid" -- reg : Should contain registers location and length - -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - -RSTC Reset Controller required properties: -- compatible: Should be "atmel,-rstc". - can be "at91sam9260" or "at91sam9g45" or "sama5d3" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - -RAMC SDRAM/DDR Controller required properties: -- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" - "atmel,at91sam9260-sdramc", - "atmel,at91sam9g45-ddramc", - "atmel,sama5d3-ddramc", -- reg: Should contain registers location and length - -Examples: - - ramc0: ramc@ffffe800 { - compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe800 0x200>; - }; - -SHDWC Shutdown Controller - -required properties: -- compatible: Should be "atmel,-shdwc". - can be "at91sam9260", "at91sam9rl" or "at91sam9x5". -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -optional properties: -- atmel,wakeup-mode: String, operation mode of the wakeup mode. - Supported values are: "none", "high", "low", "any". -- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). - -optional at91sam9260 properties: -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9rl properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. -- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. - -optional at91sam9x5 properties: -- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. - -Example: - - shdwc@fffffd10 { - compatible = "atmel,at91sam9260-shdwc"; - reg = <0xfffffd10 0x10>; - clocks = <&clk32k>; - }; - -SHDWC SAMA5D2-Compatible Shutdown Controller - -1) shdwc node - -required properties: -- compatible: should be "atmel,sama5d2-shdwc". -- reg: should contain registers location and length -- clocks: phandle to input clock. -- #address-cells: should be one. The cell is the wake-up input index. -- #size-cells: should be zero. - -optional properties: - -- debounce-delay-us: minimum wake-up inputs debouncer period in - microseconds. It's usually a board-related property. -- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. - -The node contains child nodes for each wake-up input that the platform uses. - -2) input nodes - -Wake-up input nodes are usually described in the "board" part of the Device -Tree. Note also that input 0 is linked to the wake-up pin and is frequently -used. - -Required properties: -- reg: should contain the wake-up input index [0 - 15]. - -Optional properties: -- atmel,wakeup-active-high: boolean, the corresponding wake-up input described - by the child, forces the wake-up of the core power supply on a high level. - The default is to be active low. - -Example: - -On the SoC side: - shdwc@f8048010 { - compatible = "atmel,sama5d2-shdwc"; - reg = <0xf8048010 0x10>; - clocks = <&clk32k>; - #address-cells = <1>; - #size-cells = <0>; - atmel,wakeup-rtc-timer; - }; - -On the board side: - shdwc@f8048010 { - debounce-delay-us = <976>; - - input@0 { - reg = <0>; - }; - - input@1 { - reg = <1>; - atmel,wakeup-active-high; - }; - }; - -Special Function Registers (SFR) - -Special Function Registers (SFR) manage specific aspects of the integrated -memory, bridge implementations, processor and other functionality not controlled -elsewhere. - -required properties: -- compatible: Should be "atmel,-sfr", "syscon" or - "atmel,-sfrbu", "syscon" - can be "sama5d3", "sama5d4" or "sama5d2". -- reg: Should contain registers location and length - - sfr@f0038000 { - compatible = "atmel,sama5d3-sfr", "syscon"; - reg = <0xf0038000 0x60>; - }; - -Security Module (SECUMOD) - -The Security Module macrocell provides all necessary secure functions to avoid -voltage, temperature, frequency and mechanical attacks on the chip. It also -embeds secure memories that can be scrambled - -required properties: -- compatible: Should be "atmel,-secumod", "syscon". - can be "sama5d2". -- reg: Should contain registers location and length - - secumod@fc040000 { - compatible = "atmel,sama5d2-secumod", "syscon"; - reg = <0xfc040000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt new file mode 100644 index 000000000000..4b96608ad692 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -0,0 +1,171 @@ +Atmel system registers + +Chipid required properties: +- compatible: Should be "atmel,sama5d2-chipid" +- reg : Should contain registers location and length + +PIT Timer required properties: +- compatible: Should be "atmel,at91sam9260-pit" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for the PIT which is the IRQ line + shared across all System Controller members. + +System Timer (ST) required properties: +- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for the ST which is the IRQ line + shared across all System Controller members. +- clocks: phandle to input clock. +Its subnodes can be: +- watchdog: compatible should be "atmel,at91rm9200-wdt" + +RSTC Reset Controller required properties: +- compatible: Should be "atmel,-rstc". + can be "at91sam9260" or "at91sam9g45" or "sama5d3" +- reg: Should contain registers location and length +- clocks: phandle to input clock. + +Example: + + rstc@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&clk32k>; + }; + +RAMC SDRAM/DDR Controller required properties: +- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" + "atmel,at91sam9260-sdramc", + "atmel,at91sam9g45-ddramc", + "atmel,sama5d3-ddramc", +- reg: Should contain registers location and length + +Examples: + + ramc0: ramc@ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + +SHDWC Shutdown Controller + +required properties: +- compatible: Should be "atmel,-shdwc". + can be "at91sam9260", "at91sam9rl" or "at91sam9x5". +- reg: Should contain registers location and length +- clocks: phandle to input clock. + +optional properties: +- atmel,wakeup-mode: String, operation mode of the wakeup mode. + Supported values are: "none", "high", "low", "any". +- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). + +optional at91sam9260 properties: +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9rl properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9x5 properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. + +Example: + + shdwc@fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + clocks = <&clk32k>; + }; + +SHDWC SAMA5D2-Compatible Shutdown Controller + +1) shdwc node + +required properties: +- compatible: should be "atmel,sama5d2-shdwc". +- reg: should contain registers location and length +- clocks: phandle to input clock. +- #address-cells: should be one. The cell is the wake-up input index. +- #size-cells: should be zero. + +optional properties: + +- debounce-delay-us: minimum wake-up inputs debouncer period in + microseconds. It's usually a board-related property. +- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. + +The node contains child nodes for each wake-up input that the platform uses. + +2) input nodes + +Wake-up input nodes are usually described in the "board" part of the Device +Tree. Note also that input 0 is linked to the wake-up pin and is frequently +used. + +Required properties: +- reg: should contain the wake-up input index [0 - 15]. + +Optional properties: +- atmel,wakeup-active-high: boolean, the corresponding wake-up input described + by the child, forces the wake-up of the core power supply on a high level. + The default is to be active low. + +Example: + +On the SoC side: + shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + +On the board side: + shdwc@f8048010 { + debounce-delay-us = <976>; + + input@0 { + reg = <0>; + }; + + input@1 { + reg = <1>; + atmel,wakeup-active-high; + }; + }; + +Special Function Registers (SFR) + +Special Function Registers (SFR) manage specific aspects of the integrated +memory, bridge implementations, processor and other functionality not controlled +elsewhere. + +required properties: +- compatible: Should be "atmel,-sfr", "syscon" or + "atmel,-sfrbu", "syscon" + can be "sama5d3", "sama5d4" or "sama5d2". +- reg: Should contain registers location and length + + sfr@f0038000 { + compatible = "atmel,sama5d3-sfr", "syscon"; + reg = <0xf0038000 0x60>; + }; + +Security Module (SECUMOD) + +The Security Module macrocell provides all necessary secure functions to avoid +voltage, temperature, frequency and mechanical attacks on the chip. It also +embeds secure memories that can be scrambled + +required properties: +- compatible: Should be "atmel,-secumod", "syscon". + can be "sama5d2". +- reg: Should contain registers location and length + + secumod@fc040000 { + compatible = "atmel,sama5d2-secumod", "syscon"; + reg = <0xfc040000 0x100>; + }; From patchwork Fri Oct 5 16:58:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148232 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688847lji; Fri, 5 Oct 2018 09:59:01 -0700 (PDT) X-Google-Smtp-Source: ACcGV63sQ0y9J483Mmwb6svMdHkfm8GSnodgWKfdMDuPvbOYApgmMwoY4LjkFjlXG0qAk49HzgUD X-Received: by 2002:a63:1752:: with SMTP id 18-v6mr11162218pgx.131.1538758741465; Fri, 05 Oct 2018 09:59:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758741; cv=none; d=google.com; s=arc-20160816; b=R64cHVKrRFpxEJlH6NT0k+GqpyWOkVNv4BnU/JIVdbBox6OYVdqtru8sGhFxHH5Q8w XcAzBfyg9vHxHJrgWjWu/5lxOZMLqsvHN7pwdn04ypJUeq5g8Nxdvr2wJDIoNC/gQIxa ovgGmaTMBcUD9pYEXItqhKRbbMQ1Jma3SGlOEdycQMh9YMDtR9jeWH7TiNwJ7kSF9S50 LYNvfnVPeoeBd5uXmkRAhnsoAzEA0B7Oj95BPlQYBKJ44OkrFmXFKF24bPgY2xCIIFp1 DOKgr326UoJl9EzHjLiW6VP69eP5nJANEZQZ1AwHVld1RqDTBBO46SxOg+idJ5fFgo77 zuug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=l099Y6jzpfQyO/xPjIXxsAls6PjdHyNSgIgLlrCYeSY=; b=yRRCe1UbUZq2N+Pe8cHNf/tvdIib8bN81PqALzJ/1nCE0+k8Pda4tZp0hKl9KQI1NQ drsXziLpvAY3I2J8me5vO9mxE2sQ6gtzGgSC4+vIAtzMYjqSGTUm2yliCsPasXnAFHRK EsTuIUY/03QAY5pYifEd1ef1DLVyZTEJp91Jf0dGXn+4f5gDRhjUkAmDLeINFEImLXqf ONf6yQEje/9YU7Ru8xcIo3bgWNZWPkBZNaBIstlfTPxMjmmokQhxrMGozj8/zFEFM+ND y2laCnRd4+bcWlD8kiJXuG9bezkoBvQFrazwBKjrLcudaS83b5Ewz4ZmIjk3Sn+OHxhO 7PyA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d12-v6si8451114pga.81.2018.10.05.09.59.01; Fri, 05 Oct 2018 09:59:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728967AbeJEX6c (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:32 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:38546 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728826AbeJEX6a (ORCPT ); Fri, 5 Oct 2018 19:58:30 -0400 Received: by mail-ot1-f65.google.com with SMTP id l1so28775otj.5; Fri, 05 Oct 2018 09:58:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l099Y6jzpfQyO/xPjIXxsAls6PjdHyNSgIgLlrCYeSY=; b=M7z/0A5OGzgRhjudBQ2NtcDDDwA1uH3sIRcpNGIYJVrzmnDxnr45QShIkFH4U1meBG IHDPvChb+HRfDdZ+2KMOkHk413lQTjXBA/OuVnDYOaobpBlXjUhA5oL9Pw1D2CgSYLrr ldKr73SRH+KjD4TCdN88r+2+7Sdewg0rA9W57o3aWSmlXWenULCbn6Xjyxo+p0BmxatE eK/FGAdxBXQKvbSWK297WPRLDhPeiJkqPp+y8EDtAxLwv0iKXThBzyWB5Ny0sLe1hRu7 kWVWvW5iNHUf6obJngLwXeULnTNvAmxX8eMWlv7qx+ZaaZOE+3hd8r2VGkfWzm3xMuZ7 92Ag== X-Gm-Message-State: ABuFfohQrVYtnFpNfk/1a88Y6tJ6t/hW38Nn5pwYwjUiZmaZdNJAdh9t saowdjg9MTGhb9B+4S2PqD0UM9lqxw== X-Received: by 2002:a9d:654a:: with SMTP id q10-v6mr3358223otl.256.1538758735840; Fri, 05 Oct 2018 09:58:55 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:55 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Shawn Guo Subject: [PATCH 04/36] dt-bindings: arm: fsl: Move DCFG and SCFG bindings to their own docs Date: Fri, 5 Oct 2018 11:58:16 -0500 Message-Id: <20181005165848.3474-5-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Cc: Shawn Guo Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../arm/freescale/fsl,layerscape-dcfg.txt | 19 +++++++++ .../arm/freescale/fsl,layerscape-scfg.txt | 19 +++++++++ Documentation/devicetree/bindings/arm/fsl.txt | 39 ------------------- 3 files changed, 38 insertions(+), 39 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt new file mode 100644 index 000000000000..b5cb374dc47d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt @@ -0,0 +1,19 @@ +Freescale DCFG + +DCFG is the device configuration unit, that provides general purpose +configuration and status for the device. Such as setting the secondary +core start address and release the secondary core from holdoff and startup. + +Required properties: + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-dcfg", + The following s are known to be supported: + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + + - reg : should contain base address and length of DCFG memory-mapped registers + +Example: + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt new file mode 100644 index 000000000000..0ab67b0b216d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt @@ -0,0 +1,19 @@ +Freescale SCFG + +SCFG is the supplemental configuration unit, that provides SoC specific +configuration and status registers for the chip. Such as getting PEX port +status. + +Required properties: + - compatible: Should contain a chip-specific compatible string, + Chip-specific strings are of the form "fsl,-scfg", + The following s are known to be supported: + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + + - reg: should contain base address and length of SCFG memory-mapped registers + +Example: + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg"; + reg = <0x0 0x1570000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index 8a1baa2b9723..1e775aaa5c5b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -101,45 +101,6 @@ Freescale LS1021A Platform Device Tree Bindings Required root node compatible properties: - compatible = "fsl,ls1021a"; -Freescale SoC-specific Device Tree Bindings -------------------------------------------- - -Freescale SCFG - SCFG is the supplemental configuration unit, that provides SoC specific -configuration and status registers for the chip. Such as getting PEX port -status. - Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,-scfg", - The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg: should contain base address and length of SCFG memory-mapped registers - -Example: - scfg: scfg@1570000 { - compatible = "fsl,ls1021a-scfg"; - reg = <0x0 0x1570000 0x0 0x10000>; - }; - -Freescale DCFG - DCFG is the device configuration unit, that provides general purpose -configuration and status for the device. Such as setting the secondary -core start address and release the secondary core from holdoff and startup. - Required properties: - - compatible: Should contain a chip-specific compatible string, - Chip-specific strings are of the form "fsl,-dcfg", - The following s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - - - reg : should contain base address and length of DCFG memory-mapped registers - -Example: - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - }; - Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ---------------------------------------------------------------- From patchwork Fri Oct 5 16:58:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148233 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688849lji; Fri, 5 Oct 2018 09:59:02 -0700 (PDT) X-Google-Smtp-Source: ACcGV60PYn4AnkLWPXG30DoowQ/vu+b/pH8DugzkH2fQGy99GPcJh6eArAtJ2iMUX6SX8SIM5x+A X-Received: by 2002:a62:cac4:: with SMTP id y65-v6mr12811043pfk.27.1538758741858; Fri, 05 Oct 2018 09:59:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758741; cv=none; d=google.com; s=arc-20160816; b=N/nh7PskVPspwHdcZYImbA+4eSJC5k+zNaY7326d2pH4YnEbmAECVzDaxU/Ngt7gkN rAr0pSLxSRBKm21sGEGi5gBI9pSbpFtUehqmInUW4x0kP0KTBVrkB4KPgjRtBp2kqYCn fVqw3KrjL9MPBYlTfQiF9UNs4jT7n/CxbppL6UNmChYcqz2h5ZYq9IrzilB/Sw9SFaPe cvAJ4HD2cz7UJiEYjEULYx7UzJxtxgJThVgaH9keaThnCOHkvQlfbrkvaK+OCnjCqHPg UEdiOD3VsaCDTjM2j9Y4oIE1rrVSxPrvowBAaVQNA9SQHtp7rTBOpctBAmGtjyZ19hxd e/zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=KNhjzAmt9eL8NLGjn9GDrypvo+dbuTO/DTaZ2Q51w5I=; b=Cn35P7QupbIy4BX751gXA5zxJcVifiDoS7Bp3KVg9rgbIKgN4Matz16insietA9yBX NOkdwrnlHxTsukqTVEfM2T2hta7JEMzU3v0Q+3UcDuNuJPEpProZAvXTJub4yXEn2muX mzDILQ5AG8xchBWzxFFHFfF/uRkWXZ7lWpLnvfb4gjx66Gd8RiYJ9bm2wcEYUhslBwv4 OKqucvRzMks6DIDrmoRnfuURIuvG+12RWR9A1FiJrYrI60BRpY9b7PmA8h/RMYuQLUlt HC/1+lDcBvl4xJ5sgSSESuWhnHNDKU5K84gY54MdTZzHeO1VOEF1P7nbIIYvj7pUjXJV R8DQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d12-v6si8451114pga.81.2018.10.05.09.59.01; Fri, 05 Oct 2018 09:59:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729024AbeJEX6d (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:33 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:41301 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbeJEX6c (ORCPT ); Fri, 5 Oct 2018 19:58:32 -0400 Received: by mail-ot1-f65.google.com with SMTP id e18-v6so13356103oti.8; Fri, 05 Oct 2018 09:58:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNhjzAmt9eL8NLGjn9GDrypvo+dbuTO/DTaZ2Q51w5I=; b=iJfJ4ZtP8GeDH9u/oPdR14vg65S00dkd1zF9jnvesFMAghlCKmSdOv8zKfu+iivPBt b9jwWwPj/EnQJYaSIDn/9vqPVXJCjtMvY16KveK6MneqB+q5ccxhpM19cDWyIRT63phl 0Qw2YqD9OtBx8Sb/Ll384loPV9/iMoCXOqpLQrq1d5korFYNwZZYrThUGOVcZe34g+mU suoTlGtN1pvHV34LXOudys8IBS8bRtpHxdiLhY4cdQkxCyuSWqrsZDCFbaQHeZAL/Trf bnvs2W11GbONNsEdPyqZnc14lsNk0xhH3eJpWsx5rJ/FytMpubCOVaGx7E6KA2ynU8ky ROuA== X-Gm-Message-State: ABuFfog3UvzLRKVT8PbGo4RHyR6FPi/HazB9kYWnXPsWoIQyMgmQSoHH ftC9XM6fcsppywDSocn0j+92vfV9mA== X-Received: by 2002:a9d:2372:: with SMTP id k47mr6624858otd.98.1538758737220; Fri, 05 Oct 2018 09:58:57 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:56 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org Subject: [PATCH 05/36] dt-bindings: arm: renesas: Move 'renesas, prr' binding to its own doc Date: Fri, 5 Oct 2018 11:58:17 -0500 Message-Id: <20181005165848.3474-6-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Cc: Mark Rutland Cc: Simon Horman Cc: Magnus Damm Cc: devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/renesas,prr.txt | 18 ++++++++++++++++++ .../devicetree/bindings/arm/shmobile.txt | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt new file mode 100644 index 000000000000..5000bf492f70 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt @@ -0,0 +1,18 @@ +Renesas Product Register + +Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC +product and revision information. If present, a device node for this register +should be added. + +Required properties: + - compatible: Must be "renesas,prr". + - reg: Base address and length of the register block. + + +Examples +-------- + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 89b4a389fbc7..619b765e5bee 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -141,21 +141,3 @@ Boards: compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" - - -Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC -product and revision information. If present, a device node for this register -should be added. - -Required properties: - - compatible: Must be "renesas,prr". - - reg: Base address and length of the register block. - - -Examples --------- - - prr: chipid@ff000044 { - compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; - }; From patchwork Fri Oct 5 16:58:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148234 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688895lji; Fri, 5 Oct 2018 09:59:04 -0700 (PDT) X-Google-Smtp-Source: ACcGV61q32WwbscVAoEhKHwCVoZcNsa7UkOzOi5QMztvAOeD0QkX/TO9VoEZcIQDRv9vAjYMC5Ln X-Received: by 2002:a62:4e09:: with SMTP id c9-v6mr12819977pfb.105.1538758744291; Fri, 05 Oct 2018 09:59:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758744; cv=none; d=google.com; s=arc-20160816; b=WSVNWsyzW2S8+le4OmeM00sCMUHs7rEIrwb0rqemAMaaCQybLWSDOns3cnWN4YCiw8 fl3s4ImvrtYAY3CUv/DzKshCBCV1oXTXLkQWzOhihXwGqLNBz8QiSFjda11elfQQp/CU T28IjUTedcnNhYtjBiW91jjmb3Nxt06cZxTSmnAxurYG5iM8Qz1Lqp9GPHCp3rxsnjdU CIwkATVk0GYO/z2/LbiKD+ezQSy+U8+4PwRJlSif6AX0DxfZhfqfmSsM1hcXzV0d8xxh e5Gf7ShlCpO3oQ8ZQilVjilGf3UE0UedaczpQZjq8PPdKYjTJQXJ5VfvxbSa0teo+Mu3 hjvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=OlNXSrgQVk4KWBLGVdUP3P75RriHc27c3ag6VlOGG+E=; b=fZ0REUP0EntbYU3S/50vb6xvXC997FdsmKgO20MVkmLLrFZROPHKHgEpr8feAkJQUg hBDn2aMuuSxHwjCrUDTh62FTKeSOSCaDwteRch/EZUXcIRXGSd64O3H7jTh5zDsDibXl MZtaT33RggtT66gPdupVnUPP/kLbEkbWtA2pK5oI9VS9j/PMElY5jjjz0AHtHsuwHHGQ GL3zpGOuKNrReKkj+XpvI5mOcGmZTJQohNt4BC1s9va4fZ1UNtQ3HOqq2CyV83vhEHRi Dj6jww0su0TmBnz0nir1Yvfq/BRsXp7vtjG2JrPeuvbfI4VaXao54Iuul/mvvwKScgJ8 y6wg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h7-v6si8874507plt.21.2018.10.05.09.59.03; Fri, 05 Oct 2018 09:59:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729103AbeJEX6g (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:36 -0400 Received: from mail-ot1-f66.google.com ([209.85.210.66]:38551 "EHLO mail-ot1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728770AbeJEX6e (ORCPT ); Fri, 5 Oct 2018 19:58:34 -0400 Received: by mail-ot1-f66.google.com with SMTP id l1so28926otj.5; Fri, 05 Oct 2018 09:58:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OlNXSrgQVk4KWBLGVdUP3P75RriHc27c3ag6VlOGG+E=; b=S5rly4akOTXqpBWpHmibVaS2OeZiE/8BZJo1YTkhm6wwePplmNaKTMijNMur5ZyKPb 4GSLP0DQBaHsLCDoxH3lqu9j0UEuYQ3SAMMQW4Bd7ClhLOgZM4nBo51z+qkDDsR6OzEX +4DT3ZCybNj+v2/us5jAay/Mb3pnOziM0LV3rAJv6FwoDtxXB7dE57SokC1LZRo+zY/d hbtwhvM5BlR8DPtSQ33XDQq51hlJvZsbUQZMDBFxcLA/cSAg71OVpIxPzvsni9bWf8/A L5N39I/dhojFs/fyauMRl3ObzMhh3c2NcffrekDxFy2I+xfRZzpeS3VCK+Ylo1waTSAI LyWg== X-Gm-Message-State: ABuFfoi82ukE6qKMuUPWUNSNXXVpdFZ+LNTTnx0N+YPDQpEBAPvj5fPZ juk769qCHtMFl94ZoV23WTO+suNMhA== X-Received: by 2002:a9d:48b9:: with SMTP id d54mr6766139otf.144.1538758738565; Fri, 05 Oct 2018 09:58:58 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.58.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:58:58 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Jun Nie , Baoyou Xie , Shawn Guo Subject: [PATCH 06/36] dt-bindings: arm: zte: Move sysctrl bindings to their own doc Date: Fri, 5 Oct 2018 11:58:18 -0500 Message-Id: <20181005165848.3474-7-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation to convert board-level bindings to json-schema, move various misc SoC bindings out to their own file. Cc: Mark Rutland Cc: Jun Nie Cc: Baoyou Xie Cc: Shawn Guo Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/zte-sysctrl.txt | 30 +++++++++++++++++++ Documentation/devicetree/bindings/arm/zte.txt | 27 +---------------- 2 files changed, 31 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/zte-sysctrl.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/zte-sysctrl.txt b/Documentation/devicetree/bindings/arm/zte-sysctrl.txt new file mode 100644 index 000000000000..7e66b7f7ba96 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte-sysctrl.txt @@ -0,0 +1,30 @@ +ZTE sysctrl Registers + +Registers for 'zte,zx296702' SoC: + +System management required properties: + - compatible = "zte,sysctrl" + +Low power management required properties: + - compatible = "zte,zx296702-pcu" + +Bus matrix required properties: + - compatible = "zte,zx-bus-matrix" + + +Registers for 'zte,zx296718' SoC: + +System management required properties: + - compatible = "zte,zx296718-aon-sysctrl" + - compatible = "zte,zx296718-sysctrl" + +Example: +aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; +}; + +sysctrl: sysctrl@1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt index 83369785d29c..340612794a37 100644 --- a/Documentation/devicetree/bindings/arm/zte.txt +++ b/Documentation/devicetree/bindings/arm/zte.txt @@ -1,20 +1,10 @@ ZTE platforms device tree bindings ---------------------------------------- +--------------------------------------- - ZX296702 board: Required root node properties: - compatible = "zte,zx296702-ad1", "zte,zx296702" -System management required properties: - - compatible = "zte,sysctrl" - -Low power management required properties: - - compatible = "zte,zx296702-pcu" - -Bus matrix required properties: - - compatible = "zte,zx-bus-matrix" - - --------------------------------------- - ZX296718 SoC: Required root node properties: @@ -22,18 +12,3 @@ Bus matrix required properties: ZX296718 EVB board: - "zte,zx296718-evb" - -System management required properties: - - compatible = "zte,zx296718-aon-sysctrl" - - compatible = "zte,zx296718-sysctrl" - -Example: -aon_sysctrl: aon-sysctrl@116000 { - compatible = "zte,zx296718-aon-sysctrl", "syscon"; - reg = <0x116000 0x1000>; -}; - -sysctrl: sysctrl@1463000 { - compatible = "zte,zx296718-sysctrl", "syscon"; - reg = <0x1463000 0x1000>; -}; From patchwork Fri Oct 5 16:58:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148235 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688946lji; Fri, 5 Oct 2018 09:59:07 -0700 (PDT) X-Google-Smtp-Source: ACcGV63PdIMyPTH6Oeg0vGoRTxQZZYRswcpYsGYJjwpFFnP9ICXzJg7yFesDHwtBXrfgwtEXAyE+ X-Received: by 2002:a62:3001:: with SMTP id w1-v6mr12793345pfw.19.1538758747296; Fri, 05 Oct 2018 09:59:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758747; cv=none; d=google.com; s=arc-20160816; b=X/dF2dbld7TaRuZNE1AQALD2Op0uV4VOz+yVKAK90t+sEg0RyaLUj3HM5g8mrjfxYL rb79PKf8covA09dmWmasKboEoh3OKgvy63QvVXnaAc7DUHcEkQc3OeH/0Ft7ThUbTzYA YPwu1XJz6JvRVUSRnJVZaIP8wOt8Qv5ndyNfQ3aTWZly889pl+E6v1NyacRYCD9As0QT tPPcJ5sHjIeLgwpu1tIhcgQ5LcBsKxHD2U/cqwIoHVwNLgPSl3y4q1cQH/57kBvd+qF/ AqUvnXxx1+Uzvy0yFsl5NdJVVHiHb9cn6i3RPF5ytWDV35EEdFnE+e9OYUClowOGpkI+ 9V/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=x2mzVRPujteGexchx9lGyCag4aIXbmkmqEcveyWYS/I=; b=moOmhSmmNshLO0EUYw3+X8v4bQZ2Cr2VVD7+KN2mHVVqIFojPRR99u2fRAk6TzgaOB 4lB6weeQhzTIFCCHpDWDqHnjEJostQmK3r4pdnCA0FINPy9tLeAJRgESlZOeYQtswq7o /Kuc18L69O9IFm7Vej2wsAFB6DsUodv2HcWabO0xbdwM6ruaRRAwoXWHNFal8G7GfTsH rFbVREiQjiU417/Wq5xxpiB2KYeeSafpk/LqWGjgBTfZCooHmKd8UJ93a6bACENmn/rm H4vHt8D5Xz0fy34JgrF6Rkd6uMATaJxqn1AsuRE1hksmz4/uH6b9ZtsBtacHAz1zmA6k KS6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o4-v6si9293588pll.431.2018.10.05.09.59.06; Fri, 05 Oct 2018 09:59:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729136AbeJEX6i (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:38 -0400 Received: from mail-oi1-f195.google.com ([209.85.167.195]:45354 "EHLO mail-oi1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729025AbeJEX6h (ORCPT ); Fri, 5 Oct 2018 19:58:37 -0400 Received: by mail-oi1-f195.google.com with SMTP id e17-v6so10927196oig.12; Fri, 05 Oct 2018 09:59:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x2mzVRPujteGexchx9lGyCag4aIXbmkmqEcveyWYS/I=; b=i0qLHyY3oZNzPIiE/vTK5vskJoCU5N68XXqbQcDsw+X/v+arSRiwOLxT6MqP4aTbe8 Ov9s83EY7nxGowHWHy3/HYendCLdMHpJVS3g4xkA7YCSl9CySDOyqua20QIy8U0ZRluK EWjzI7EStBUlPQ11sRPMjzuc3nXhwS9NBIOghFremJJYVKwIB5Qo2DJR7hKulf2hwoj7 mpRdwXExw4+agXcwLoeekCCdHA/h+bKNqWgqzoSGNqIKHDM/wbHzS78DMBre3fFliIzb QH0TH8128+zTMebf5iTtRyzRAJKhG0P2mUIFzrkZeYU6nNuvGj5OY3MuetAkN2zCisS9 GkwQ== X-Gm-Message-State: ABuFfoj0eXAFOurAspaMslqRCldyYjo1MBQ3O/YCNYMJtAPTkj1rl1lB RyFBZ53Qt8yMAQC5J2AlZDsAPEeSsA== X-Received: by 2002:aca:ce07:: with SMTP id e7-v6mr6050227oig.54.1538758741325; Fri, 05 Oct 2018 09:59:01 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:00 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson Subject: [PATCH 08/36] dt-bindings: Add a writing DT schemas how-to and annotated example Date: Fri, 5 Oct 2018 11:58:20 -0500 Message-Id: <20181005165848.3474-9-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a how-to doc on writing DT schema documentation. This gives a description of each section and details on how to validate the DT schema file. The DT schema are written using json-schema vocabulary in a YAML encoded document. Using jsonschema gives us access to existing tooling. A YAML encoding gives us something easy to edit. The example is annotated to help explain what each section does. This example is just the tip of the iceberg, but is it the part most developers writing bindings will interact with. Backing all this up are meta-schema (to validate the binding schemas), some DT core schema, YAML encoded DT output with dtc, and a small number of python scripts to run validation. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/example-schema.yaml | 155 ++++++++++++++++++ Documentation/devicetree/writing-schema.md | 111 +++++++++++++ 2 files changed, 266 insertions(+) create mode 100644 Documentation/devicetree/bindings/example-schema.yaml create mode 100644 Documentation/devicetree/writing-schema.md -- 2.17.1 diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml new file mode 100644 index 000000000000..4cbdbf59695f --- /dev/null +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: BSD-2-Clause +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +# All the top-level keys are standard json-schema keywords except for +# 'maintainers' and 'select' + +# $id is a unique idenifier based on the filename +$id: "http://devicetree.org/schemas/example-schema.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: An example schema annotated with jsonschema details + +maintainers: + - Rob Herring + +description: | + A more detailed multi-line description of the binding. + + Details about the hardware device and any links to datasheets can go here. + + Literal blocks are marked with the '|' at the beginning. The end is marked by + indentation less than the first line of the literal block. + +select: false + # 'select' is a schema applied to a DT node to determine if this binding + # schema should be applied to the node. It is optional and by default the + # possible compatible strings are extracted and used to match. + +properties: + # A dictionary of DT properties for this binding schema + compatible: + # More complicated schema can use oneOf (XOR), anyOf (OR), or allOf (AND) + # to handle different conditions. + # In this case, it's needed to handle a variable number of values as there + # isn't another way to express a constraint of the last string value. + # The boolean schema must be a list of schemas. + oneOf: + - items: + # items is a list of possible values for the property. The number of + # values is determined by the number of elements in the list. + # Order in lists is significant, order in dicts is not + # Must be one of the 1st enums followed by the 2nd enum + # + # Each element in items should be 'enum' or 'const' + - enum: + - vendor,soc4-ip + - vendor,soc3-ip + - vendor,soc2-ip + - enum: + - vendor,soc1-ip + # additionalItems being false is implied + # minItems/maxItems equal to 2 is implied + - items: + # 'const' is just a special case of an enum with a single possible value + - const: vendor,soc1-ip + + reg: + # The description of each element defines the order and implicitly defines + # the number of reg entries + items: + - description: core registers + - description: aux registers + # minItems/maxItems equal to 2 is implied + + reg-names: + # The core schema enforces this is a string array + items: + - const: core + - const: aux + + clocks: + maxItems: 1 + # Only a single entry, so just need to set the max number of items. + description: hello + + clock-names: + items: + - const: bus + + interrupts: + # Either 1 or 2 interrupts can be present + minItems: 1 + maxItems: 2 + items: + - description: tx or combined interrupt + - description: rx interrupt + + description: + A variable number of interrupts warrants a description of what conditions + affect the number of interrupts. Otherwise, descriptions on standard + properties are not necessary. + + interrupt-names: + # minItems must be specified here because the default would be 2 + minItems: 1 + maxItems: 2 + items: + - const: "tx irq" + - const: "rx irq" + + # Property names starting with '#' must be quoted + '#interrupt-cells': + # A simple case where the value must always be '2'. + # The core schema handles that this must be a single integer. + const: 2 + + interrupt-controller: true + # The core checks this is a boolean, so just have to list it here to be + # valid for this binding. + + clock-frequency: + # The type is set in the core schema. Per device schema only need to set + # constraints on the possible values. + minimum: 100 + maximum: 400000 + # The value that should be used if the property is not present + default: 200 + + foo-gpios: + maxItems: 1 + description: A connection of the 'foo' gpio line. + + vendor,int-property: + description: Vendor specific properties must have a description + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - enum: [2, 4, 6, 8, 10] + + vendor,bool-property: + description: Vendor specific properties must have a description + type: boolean + + vendor,string-array-property: + description: Vendor specific properties may refer to core schema + allOf: + - $ref: '/schemas/types.yaml#/definitions/stringarray' + - maxItems: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + +examples: + - | + node@1000 { + compatible = "vendor,soc4-ip", "vendor,soc1-ip"; + reg = <0x1000 0x80>, + <0x3000 0x80>; + reg-names = "core", "aux"; + interrupts = <10>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/writing-schema.md b/Documentation/devicetree/writing-schema.md new file mode 100644 index 000000000000..b1d9798ca3e4 --- /dev/null +++ b/Documentation/devicetree/writing-schema.md @@ -0,0 +1,111 @@ +# Writing DeviceTree Bindings in json-schema + +Devicetree bindings are written using json-schema vocabulary. Schema files are +written in a JSON compatible subset of YAML. YAML is used instead of JSON as it +considered more human readable and has some advantages such as allowing +comments (Prefixed with '#'). + +## Schema Contents + +Each schema doc is a structured json-schema which is defined by a set of +top-level properties: + +- __$id__ - A json-schema unique identifier string. The string must be a valid +URI typically containing the binding's filename and path. DT schema it must +begin with "http://devicetree.org/schema/". The URL is used for non file local +"$ref" lookups. A URL is used even for local files, and there may not actually +be files present at those locations. + +- __$schema__ - Indicates the meta-schema the schema file adheres to. + +- __title__ - A one line description on the contents of the binding schema. + +- __maintainers__ - A DT specific property. Contains a list of email address(es) +for maintainers of this binding. + +- __description__ - Optional. A multi-line text block containing any detailed +information about this binding. It should contain things such as what the block +or device does, standards the device conforms to, and links to datasheets for +more information. + +- __select__ - Optional. A json-schema to match nodes for applying the schema. +By default, nodes are matched against their possible compatible string values +or node name and select is not necessary. + +- __properties__ - A set of sub-schema defining all the DT properties for the +binding. The exact schema depends on the type of property. A property can also +define a child DT node with child properties defined under it. + +- __patternProperties__ - Optional. Similar to 'properties', but names are regex. + +- __required__ - A list of DT properties from the 'properties' section that +must always be present. + +- __examples__ - Optional. A list of one or more DTS hunks implementing the +binding. + +Unless noted otherwise, all properties are required. + +## Property Schema + +The 'properties' section of the schema contains all the DT properties for a +binding. Each property contains a set of constraints using json-schema +vocabulary for that property. The properties schemas are what is used for +validation of DT files. + +For common properties, only additional constraints not covered by the common +binding schema need to be defined such as how many values are valid or what +possible values are valid. + +Vendor specific properties will typically need more detailed schema. With the +exception of boolean properties, they should have a reference to a type in +schemas/types.yaml. A "description" property is always required. + +The Devicetree schemas don't exactly match the YAML encoded DT data produced by +dtc. They are simplified to make them more compact and avoid a bunch of +boilerplate. The tools process the schema files to produce the final schema for +validation. There are currently 2 transformations the tools perform. + +The default for arrays in json-schema is they are variable sized and allow more +entries than explicitly defined. This can be restricted by defining 'minItems', +'maxItems', and 'additionalItems'. However, for DeviceTree Schemas, a fixed +size is desired in most cases, so these properties are added based on the +number of entries in an 'items' list. + +The YAML Devicetree format also makes all string values an array and scalar +values a matrix (in order to define groupings) even when only a single value +is present. Single entries in schemas are fixed up to match this encoding. + +## Testing + +### Dependencies + +The DT schema project must be installed in order to validate the DT schema +binding documents and validate DTS files using the DT schema. The DT schema +project can be installed with pip: + +`pip3 install git+https://github.com/robherring/yaml-bindings.git@master --process-dependency-links` + +dtc must also be built with YAML output support enabled. This requires that +libyaml and its headers be installed on the host system. + +### Running checks + +The DT schema binding documents must be validated using the meta-schema (the +schema for the schema) to ensure they are both valid json-schema and valid +binding schema. All of the DT binding documents can be validated using the +`dt_binding_check` target: + +`make dt_binding_check` + +In order to perform validation of DT source files, use the `dtbs_check` target: + +`make dtbs_check` + +This will first run the `dt_binding_check` which generates the processed schema. + +## json-schema Resources + +[JSON-Schema Specifications](http://json-schema.org/) + +[Using JSON Schema Book](http://usingjsonschema.com/) From patchwork Fri Oct 5 16:58:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148236 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp688979lji; Fri, 5 Oct 2018 09:59:09 -0700 (PDT) X-Google-Smtp-Source: ACcGV61uyLwYn94ofb/5eXDOl6iC8v4CAAY480Qmop3Dsu6bdHO5SGNnRdNz2OHjndrrMqh52e0H X-Received: by 2002:a62:2bc2:: with SMTP id r185-v6mr12867870pfr.21.1538758749728; Fri, 05 Oct 2018 09:59:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758749; cv=none; d=google.com; s=arc-20160816; b=YqQhWinA/dhCpD3sFFOwjKWeE5H0T//0QtEhH2Ag8jq0Q9/ITJB74A4RXUyHsNxTxE hmB9Yw24Pi8adWWFxmxGFg0soiufiHw1+1gA20axRK0e7PhENIKHQ5Q5iLMXPqd0wked DrD7xq7RORCHUOWRafDPBKj6wul1AzK7p8TFWf5724JeMQEGmzxvR8AwwAdyWzgjt8Ub jJpzsCkZbw84YP+r7iDRidd1UYFXISKOz1aH+L+cKn8bSF3py3ViWSFM7SJBMCnvh8W0 7G9VXjV+kJZbaHEoHHjv08UwBU8rrZIh9oz1qTJeQW4Gtzig9mFmqbh8+guWFPJthhOI 6+9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZC8t4Idln4S7ORmFnf/SrAK5cNn1ZboPvxmN3CleSFM=; b=RjsTffHtrYQx5VZoUqAELU7yRpljpHx8AgZh5epn3gWdApmx3BtYs+USCJ5tBsxn6k XCDrzd85cXvL0zNIY3DJonW34b6h4zRIPi43fOkqE8DsWOgXXS5g5z7hGcqSEEMsg4dK q7d2Gs9LV15SkmNUzQIHkQyUAbfGtWmnH5QsMwhIDZzPPeXHS4bHfhLsqAe57P6RrbU4 RBwSIcjOttxqOr4LOr647cOK5yY48YO6QRUtoEQOpX1C6xCmZPFdKBNiMiO0HOYPfoNo nRrqAlzMD1O1kypveje/XqReA7G/VQ202ccALM8bBpBjojacXN6vygKwmIUyjXfySs1Z xV5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w31-v6si9104076pla.133.2018.10.05.09.59.09; Fri, 05 Oct 2018 09:59:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729161AbeJEX6k (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:40 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:38909 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729108AbeJEX6j (ORCPT ); Fri, 5 Oct 2018 19:58:39 -0400 Received: by mail-oi1-f193.google.com with SMTP id u197-v6so10958781oif.5; Fri, 05 Oct 2018 09:59:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZC8t4Idln4S7ORmFnf/SrAK5cNn1ZboPvxmN3CleSFM=; b=rCnvtB//zHL6iyIAh70mnURLnKIT5XgTpUsOEHSXBzP89jSIhj0+RIOnLoU1ch4tYA 2vy9bCI6vBQzg1Gwnw8v/fZN+4ycDJ7dtw82RYYfO9ZI3IOfJDeQ27nd+U9rmm/txS/c 46S1lX8D4Ni9rqAxSvgLVdmKuQ1TAJpMiGoKEgMxWfnXvLgHTahTqOClFJfA2JHB/6dW cN68P3lW4rOJGgDaZ8KZg9pkMeyIesWaPhEpiEE7MuNQeGjEgy4s9P/zv+bEZKn8af5x S7pn5zqtiBCmncHRnRCRqqHrxDoL2pETUcGVVE8kBAD3IHZzC5vxufA3x2aZWZ7vivZS g7+w== X-Gm-Message-State: ABuFfohllbe9lqzWVKGwx83Q1a1+NVs4jsH6UgctVQiOE/Z76/DjJ6QV NBrtPPl/YLEOqBGLjNn0zobPFRbjZg== X-Received: by 2002:aca:f341:: with SMTP id r62-v6mr5554485oih.230.1538758742731; Fri, 05 Oct 2018 09:59:02 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:02 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson Subject: [PATCH 09/36] dt-bindings: Convert trivial-devices.txt to json-schema Date: Fri, 5 Oct 2018 11:58:21 -0500 Message-Id: <20181005165848.3474-10-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert trivial-devices.txt to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/trivial-devices.txt | 201 --------- .../devicetree/bindings/trivial-devices.yaml | 414 ++++++++++++++++++ 2 files changed, 414 insertions(+), 201 deletions(-) delete mode 100644 Documentation/devicetree/bindings/trivial-devices.txt create mode 100644 Documentation/devicetree/bindings/trivial-devices.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt deleted file mode 100644 index 763a2808a95c..000000000000 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ /dev/null @@ -1,201 +0,0 @@ -This is a list of trivial i2c devices that have simple device tree -bindings, consisting only of a compatible field, an address and -possibly an interrupt line. - -If a device needs more specific bindings, such as properties to -describe some aspect of it, there needs to be a specific binding -document for it just like any other devices. - - -Compatible Vendor / Chip -========== ============= -abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface -ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin -ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems -adi,adt7461 +/-1C TDM Extended Temp Range I.C -adt7461 +/-1C TDM Extended Temp Range I.C -adi,adt7473 +/-1C TDM Extended Temp Range I.C -adi,adt7475 +/-1C TDM Extended Temp Range I.C -adi,adt7476 +/-1C TDM Extended Temp Range I.C -adi,adt7490 +/-1C TDM Extended Temp Range I.C -adi,adxl345 Three-Axis Digital Accelerometer -adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) -ams,iaq-core AMS iAQ-Core VOC Sensor -amstaos,tsl2571 AMS/TAOS ALS and proximity sensor -amstaos,tsl2671 AMS/TAOS ALS and proximity sensor -amstaos,tmd2671 AMS/TAOS ALS and proximity sensor -amstaos,tsl2771 AMS/TAOS ALS and proximity sensor -amstaos,tmd2771 AMS/TAOS ALS and proximity sensor -amstaos,tsl2572 AMS/TAOS ALS and proximity sensor -amstaos,tsl2672 AMS/TAOS ALS and proximity sensor -amstaos,tmd2672 AMS/TAOS ALS and proximity sensor -amstaos,tsl2772 AMS/TAOS ALS and proximity sensor -amstaos,tmd2772 AMS/TAOS ALS and proximity sensor -at,24c08 i2c serial eeprom (24cxx) -atmel,at97sc3204t i2c trusted platform module (TPM) -capella,cm32181 CM32181: Ambient Light Sensor -capella,cm3232 CM3232: Ambient Light Sensor -cirrus,cs42l51 Cirrus Logic CS42L51 audio codec -dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output -dallas,ds1631 High-Precision Digital Thermometer -dallas,ds1672 Dallas DS1672 Real-time Clock -dallas,ds1682 Total-Elapsed-Time Recorder with Alarm -dallas,ds1775 Tiny Digital Thermometer and Thermostat -dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM -dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O -dallas,ds75 Digital Thermometer and Thermostat -devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode -devantech,srf08 Devantech SRF08 ultrasonic ranger -devantech,srf10 Devantech SRF10 ultrasonic ranger -dlg,da9053 DA9053: flexible system level PMIC with multicore support -dlg,da9063 DA9063: system PMIC for quad-core application processors -domintech,dmard09 DMARD09: 3-axis Accelerometer -domintech,dmard10 DMARD10: 3-axis Accelerometer -epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE -emmicro,em3027 EM Microelectronic EM3027 Real-time Clock -fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer -fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor -fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer -fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor -fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller -fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec -gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface -infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) -infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) -infineon,tlv493d-a1b6 Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor -isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM -isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM -isil,isl12022 Intersil ISL12022 Real-time Clock -isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor -isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor -maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator -maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs -maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion -maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface -mcube,mc3230 mCube 3-axis 8-bit digital accelerometer -memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer -microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k) -microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k) -microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k) -microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k) -microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k) -microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k) -microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k) -microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k) -microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k) -microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k) -microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k) -microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k) -microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) -microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) -microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) -microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) -microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection -microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection -microcrystal,rv3029 Real Time Clock Module with I2C-Bus -miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer -miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer -miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer -national,lm63 Temperature sensor with integrated fan control -national,lm75 I2C TEMP SENSOR -national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor -national,lm85 Temperature sensor with integrated fan control -national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface -nuvoton,npct501 i2c trusted platform module (TPM) -nuvoton,npct601 i2c trusted platform module (TPM2) -nuvoton,w83773g Nuvoton Temperature Sensor -nxp,pca9556 Octal SMBus and I2C registered interface -nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset -nxp,pcf2127 Real-time clock -nxp,pcf2129 Real-time clock -nxp,pcf8523 Real-time Clock -nxp,pcf8563 Real-time clock/calendar -nxp,pcf85063 Tiny Real-Time Clock -oki,ml86v7667 OKI ML86V7667 video decoder -ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus -pericom,pt7c4338 Real-time Clock Module -plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch -pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor -ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC -samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) -sgx,vz89x SGX Sensortech VZ89X Sensors -sii,s35390a 2-wire CMOS real-time clock -silabs,si7020 Relative Humidity and Temperature Sensors -skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply -st,24c256 i2c serial eeprom (24cxx) -taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface -ti,ads7828 8-Channels, 12-bit ADC -ti,ads7830 8-Channels, 8-bit ADC -ti,amc6821 Temperature Monitoring and Fan Control -ti,tsc2003 I2C Touch-Screen Controller -ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface -ti,tmp275 Digital Temperature Sensor -winbond,w83793 Winbond/Nuvoton H/W Monitor -winbond,wpct301 i2c trusted platform module (TPM) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml new file mode 100644 index 000000000000..a17278a44699 --- /dev/null +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -0,0 +1,414 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/trivial-devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trivial I2C and SPI devices that have simple device tree bindings + +maintainers: + - Rob Herring + +description: | + This is a list of trivial I2C and SPI devices that have simple device tree + bindings, consisting only of a compatible field, an address and possibly an + interrupt line. + + If a device needs more specific bindings, such as properties to + describe some aspect of it, there needs to be a specific binding + document for it just like any other devices. + +properties: + reg: + maxItems: 1 + interrupts: + maxItems: 1 + compatible: + items: + - enum: + # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface + - abracon,abb5zes3 + # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin + - ad,ad7414 + # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems + - ad,adm9240 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7461 + # +/-1C TDM Extended Temp Range I.C + - adt7461 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7473 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7475 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7476 + # +/-1C TDM Extended Temp Range I.C + - adi,adt7490 + # Three-Axis Digital Accelerometer + - adi,adxl345 + # Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too) + - adi,adxl346 + # AMS iAQ-Core VOC Sensor + - ams,iaq-core + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2571 + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2671 + # AMS/TAOS ALS and proximity sensor + - amstaos,tmd2671 + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2771 + # AMS/TAOS ALS and proximity sensor + - amstaos,tmd2771 + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2572 + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2672 + # AMS/TAOS ALS and proximity sensor + - amstaos,tmd2672 + # AMS/TAOS ALS and proximity sensor + - amstaos,tsl2772 + # AMS/TAOS ALS and proximity sensor + - amstaos,tmd2772 + # i2c serial eeprom (24cxx) + - at,24c08 + # i2c trusted platform module (TPM) + - atmel,at97sc3204t + # CM32181: Ambient Light Sensor + - capella,cm32181 + # CM3232: Ambient Light Sensor + - capella,cm3232 + # Cirrus Logic CS42L51 audio codec + - cirrus,cs42l51 + # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output + - dallas,ds1374 + # High-Precision Digital Thermometer + - dallas,ds1631 + # Dallas DS1672 Real-time Clock + - dallas,ds1672 + # Total-Elapsed-Time Recorder with Alarm + - dallas,ds1682 + # Tiny Digital Thermometer and Thermostat + - dallas,ds1775 + # Extremely Accurate I²C RTC with Integrated Crystal and SRAM + - dallas,ds3232 + # CPU Supervisor with Nonvolatile Memory and Programmable I/O + - dallas,ds4510 + # Digital Thermometer and Thermostat + - dallas,ds75 + # Devantech SRF02 ultrasonic ranger in I2C mode + - devantech,srf02 + # Devantech SRF08 ultrasonic ranger + - devantech,srf08 + # Devantech SRF10 ultrasonic ranger + - devantech,srf10 + # DA9053: flexible system level PMIC with multicore support + - dlg,da9053 + # DA9063: system PMIC for quad-core application processors + - dlg,da9063 + # DMARD09: 3-axis Accelerometer + - domintech,dmard09 + # DMARD10: 3-axis Accelerometer + - domintech,dmard10 + # I2C-BUS INTERFACE REAL TIME CLOCK MODULE + - epson,rx8010 + # I2C-BUS INTERFACE REAL TIME CLOCK MODULE + - epson,rx8581 + # EM Microelectronic EM3027 Real-time Clock + - emmicro,em3027 + # MAG3110: Xtrinsic High Accuracy, 3D Magnetometer + - fsl,mag3110 + # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor + - fsl,mma7660 + # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer + - fsl,mma8450 + # MPL3115: Absolute Digital Pressure Sensor + - fsl,mpl3115 + # MPR121: Proximity Capacitive Touch Sensor Controller + - fsl,mpr121 + # SGTL5000: Ultra Low-Power Audio Codec + - fsl,sgtl5000 + # G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface + - gmt,g751 + # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) + - infineon,slb9635tt + # Infineon SLB9645 I2C TPM (new protocol, max 400khz) + - infineon,slb9645tt + # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor + - infineon,tlv493d-a1b6 + # Intersil ISL1208 Low Power RTC with Battery Backed SRAM + - isil,isl1208 + # Intersil ISL1218 Low Power RTC with Battery Backed SRAM + - isil,isl1218 + # Intersil ISL12022 Real-time Clock + - isil,isl12022 + # Intersil ISL29028 Ambient Light and Proximity Sensor + - isil,isl29028 + # Intersil ISL29030 Ambient Light and Proximity Sensor + - isil,isl29030 + # 5 Bit Programmable, Pulse-Width Modulator + - maxim,ds1050 + # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs + - maxim,max1237 + # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion + - maxim,max6621 + # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface + - maxim,max6625 + # mCube 3-axis 8-bit digital accelerometer + - mcube,mc3230 + # MEMSIC 2-axis 8-bit digital accelerometer + - memsic,mxc6225 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4017-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4017-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4017-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4017-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4018-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4018-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4018-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4018-104 + # Microchip 7-bit Single I2C Digital POT (5k) + - microchip,mcp4019-502 + # Microchip 7-bit Single I2C Digital POT (10k) + - microchip,mcp4019-103 + # Microchip 7-bit Single I2C Digital POT (50k) + - microchip,mcp4019-503 + # Microchip 7-bit Single I2C Digital POT (100k) + - microchip,mcp4019-104 + # Microchip 7-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4531-502 + # Microchip 7-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4531-103 + # Microchip 7-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4531-503 + # Microchip 7-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4531-104 + # Microchip 7-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4532-502 + # Microchip 7-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4532-103 + # Microchip 7-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4532-503 + # Microchip 7-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4532-104 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4541-502 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4541-103 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4541-503 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4541-104 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4542-502 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4542-103 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4542-503 + # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4542-104 + # Microchip 8-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4551-502 + # Microchip 8-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4551-103 + # Microchip 8-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4551-503 + # Microchip 8-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4551-104 + # Microchip 8-bit Single I2C Digital Potentiometer (5k) + - microchip,mcp4552-502 + # Microchip 8-bit Single I2C Digital Potentiometer (10k) + - microchip,mcp4552-103 + # Microchip 8-bit Single I2C Digital Potentiometer (50k) + - microchip,mcp4552-503 + # Microchip 8-bit Single I2C Digital Potentiometer (100k) + - microchip,mcp4552-104 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4561-502 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4561-103 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4561-503 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4561-104 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4562-502 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4562-103 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4562-503 + # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4562-104 + # Microchip 7-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4631-502 + # Microchip 7-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4631-103 + # Microchip 7-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4631-503 + # Microchip 7-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4631-104 + # Microchip 7-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4632-502 + # Microchip 7-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4632-103 + # Microchip 7-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4632-503 + # Microchip 7-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4632-104 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4641-502 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4641-103 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4641-503 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4641-104 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4642-502 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4642-103 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4642-503 + # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4642-104 + # Microchip 8-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4651-502 + # Microchip 8-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4651-103 + # Microchip 8-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4651-503 + # Microchip 8-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4651-104 + # Microchip 8-bit Dual I2C Digital Potentiometer (5k) + - microchip,mcp4652-502 + # Microchip 8-bit Dual I2C Digital Potentiometer (10k) + - microchip,mcp4652-103 + # Microchip 8-bit Dual I2C Digital Potentiometer (50k) + - microchip,mcp4652-503 + # Microchip 8-bit Dual I2C Digital Potentiometer (100k) + - microchip,mcp4652-104 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4661-502 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4661-103 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4661-503 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4661-104 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k) + - microchip,mcp4662-502 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k) + - microchip,mcp4662-103 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k) + - microchip,mcp4662-503 + # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k) + - microchip,mcp4662-104 + # PWM Fan Speed Controller With Fan Fault Detection + - microchip,tc654 + # PWM Fan Speed Controller With Fan Fault Detection + - microchip,tc655 + # Real Time Clock Module with I2C-Bus + - microcrystal,rv3029 + # MiraMEMS DA226 2-axis 14-bit digital accelerometer + - miramems,da226 + # MiraMEMS DA280 3-axis 14-bit digital accelerometer + - miramems,da280 + # MiraMEMS DA311 3-axis 12-bit digital accelerometer + - miramems,da311 + # Temperature sensor with integrated fan control + - national,lm63 + # I2C TEMP SENSOR + - national,lm75 + # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor + - national,lm80 + # Temperature sensor with integrated fan control + - national,lm85 + # ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface + - national,lm92 + # i2c trusted platform module (TPM) + - nuvoton,npct501 + # i2c trusted platform module (TPM2) + - nuvoton,npct601 + # Nuvoton Temperature Sensor + - nuvoton,w83773g + # Octal SMBus and I2C registered interface + - nxp,pca9556 + # 8-bit I2C-bus and SMBus I/O port with reset + - nxp,pca9557 + # Real-time clock + - nxp,pcf2127 + # Real-time clock + - nxp,pcf2129 + # Real-time Clock + - nxp,pcf8523 + # Real-time clock/calendar + - nxp,pcf8563 + # Tiny Real-Time Clock + - nxp,pcf85063 + # OKI ML86V7667 video decoder + - oki,ml86v7667 + # OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus + - ovti,ov5642 + # Real-time Clock Module + - pericom,pt7c4338 + # 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch + - plx,pex8648 + # Pulsedlight LIDAR range-finding sensor + - pulsedlight,lidar-lite-v2 + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,r2025sd + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,r2221tl + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rs5c372a + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rs5c372b + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rv5c386 + # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC + - ricoh,rv5c387a + # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) + - samsung,24ad0xd1 + # SGX Sensortech VZ89X Sensors + - sgx,vz89x + # 2-wire CMOS real-time clock + - sii,s35390a + # Relative Humidity and Temperature Sensors + - silabs,si7020 + # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply + - skyworks,sky81452 + # i2c serial eeprom (24cxx) + - st,24c256 + # Ambient Light Sensor with SMBUS/Two Wire Serial Interface + - taos,tsl2550 + # 8-Channels, 12-bit ADC + - ti,ads7828 + # 8-Channels, 8-bit ADC + - ti,ads7830 + # Temperature Monitoring and Fan Control + - ti,amc6821 + # I2C Touch-Screen Controller + - ti,tsc2003 + # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface + - ti,tmp102 + # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface + - ti,tmp103 + # Digital Temperature Sensor + - ti,tmp275 + # Winbond/Nuvoton H/W Monitor + - winbond,w83793 + # i2c trusted platform module (TPM) + - winbond,wpct301 + +required: + - compatible + - reg + +... From patchwork Fri Oct 5 16:58:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148263 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp692370lji; Fri, 5 Oct 2018 10:02:04 -0700 (PDT) X-Google-Smtp-Source: ACcGV62rora/Q2q/HojFL2isR/KfeAI3IcXflLmgTDYhlRHpcVhOuquXWpiliYTujrUb6up/1mNA X-Received: by 2002:a17:902:9893:: with SMTP id s19-v6mr12491157plp.130.1538758924448; Fri, 05 Oct 2018 10:02:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758924; cv=none; d=google.com; s=arc-20160816; b=VxgnQGF24ZGjjkSIrMg8lfj/Z0WyfqZwohHmalxReQVf9hy2o8AWxHpTsHXNgficzq zMTx5YiWzn8mki106KWCE0wCqDyRK0gKid/s7rlYMbK+I4MM436thgZenN0h8XEhGiQX mESR2HroqAsHI1qE3XIACGuqg80eQyeR+1u+A6TB31LaNH6gM1l1nWsyXUkpjeCh87Jl bDhjR1DFi5KQM/BLyJU4BP+10GH0aFA3/Y5VKeJlU/kL4oLiqHgsC7PI/UJPdyOgSFj8 MPuMfEHJH0TpvL6WPsVva+9gZfV2J8BHSDeNDMv1t8UelMsen28dwAGbM70w/m5cl/YQ lmBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=zoNxd1sQf4bhVATt8RklSISv1vp3Ut2WaEzmkh9zdXo=; b=iJnL8yzOkUhmchupY59c/iaN79Xq+D3mZIJz3JKGev4uB857JRBMJv1QtWDVLxYbif 5f2y4TzTS0x7KSYbsPVUXcjNGOdrw7ripZ0TDz4kRkIj2z6K0ukeQky2HhGmtO3SPJMF +dtkfm4mqtrDx9Lfz2Hy2plZfOrRSz102hTk1IejX/zxis2UbW3wWS0f37mtj8grFV1E VTQ47cWh06J1mnB6bF6PzQoYBmBctsHdp5BquKIi2StjgslZUE03RPkzIbVW3K7I3AVY mmu7/YOoaM9qcIgEG0W8Pz3tr6qD3LxY5LIzid1vGFzMI2wi6S6EHX8+/mSdYtn3awah 5COg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h25-v6si9146627pgn.567.2018.10.05.10.02.03; Fri, 05 Oct 2018 10:02:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729629AbeJFABg (ORCPT + 32 others); Fri, 5 Oct 2018 20:01:36 -0400 Received: from mail-oi1-f196.google.com ([209.85.167.196]:43276 "EHLO mail-oi1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729025AbeJEX6j (ORCPT ); Fri, 5 Oct 2018 19:58:39 -0400 Received: by mail-oi1-f196.google.com with SMTP id s69-v6so10935170oie.10; Fri, 05 Oct 2018 09:59:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zoNxd1sQf4bhVATt8RklSISv1vp3Ut2WaEzmkh9zdXo=; b=K9NvKJKJnYlPB+/XEOcbDYU3wuADZTRAM2P+mjDRthw/iPWhSEkLDRQaq8HyKYNlT3 i7d3T9ypU4GI/mwF3syhZHkKNvhXEjreNSoyFjNiDAm9j5BE/0CvXY44X6/jMXh0BQdB fNlUX5Y/OOWNaK2v4veQ/sc5KMvb0+1pB8IDoJ7gqcy8ACqDU9YjvQSYbmjgc2fu0xkM 9/g412RvIzNnEfUiGJG0KhPlrG2EGQ06b026CYvRdY0K6eyD6TloszFOsUefZlT379Pg gZ6VH9Q225eP1ZZFnT3g3x5JO+vJy8fAWYoP/ClfP3DJlh29NZaDVDsxUlDBo5AFkQza gnRQ== X-Gm-Message-State: ABuFfoj0qvbB1wZQTT55gThFoM7cAy/XdSxj0GHF9qK0vOBjLV7uI8vF h6GK/VhoxkApcqE4Z0TP4Jf7BghVTg== X-Received: by 2002:aca:754b:: with SMTP id q72-v6mr6275729oic.13.1538758744745; Fri, 05 Oct 2018 09:59:04 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:03 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Dinh Nguyen Subject: [PATCH 10/36] dt-bindings: altera: Convert clkmgr binding to json-schema Date: Fri, 5 Oct 2018 11:58:22 -0500 Message-Id: <20181005165848.3474-11-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Altera clkmgr to DT schema format using json-schema. Cc: Mark Rutland Cc: Dinh Nguyen Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../arm/altera/socfpga-clk-manager.txt | 11 ------- .../arm/altera/socfpga-clk-manager.yaml | 30 +++++++++++++++++++ 2 files changed, 30 insertions(+), 11 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt deleted file mode 100644 index 2c28f1d12f45..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt +++ /dev/null @@ -1,11 +0,0 @@ -Altera SOCFPGA Clock Manager - -Required properties: -- compatible : "altr,clk-mgr" -- reg : Should contain base address and length for Clock Manager - -Example: - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml new file mode 100644 index 000000000000..37c2cf08fae0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/altera/socfpga-clk-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA Clock Manager + +maintainers: + - Dinh Nguyen +description: test + +properties: + compatible: + items: + - const: altr,clk-mgr + reg: + maxItems: 1 + +required: + - compatible + +examples: + - | + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + }; + +... From patchwork Fri Oct 5 16:58:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148237 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689017lji; Fri, 5 Oct 2018 09:59:11 -0700 (PDT) X-Google-Smtp-Source: ACcGV60qiSg8jUNletOzzdcA8eLUHmx2DxCNivcaRALTRtekxQ6XAkf2PP0diFNP7k7LKCMJe6QA X-Received: by 2002:a62:f58a:: with SMTP id b10-v6mr13002877pfm.253.1538758751537; Fri, 05 Oct 2018 09:59:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758751; cv=none; d=google.com; s=arc-20160816; b=f8UkKZfQ0uKu/Icn9z/B5W2j5WEzEiYY7mnCC3LNvTrtkGDKYQ/lUUENA5Tpx417OC q7JCrKqq8kS3x48A1IEYrpuqvjjjL68qlXyUKz52ksZfJS9ljkURA04GTeZwzdYe+elh yyvhiHRN9BP8GMqaAGtR4mZoSvKsMkrfcKyk6dZbqz8L4uo9FOX0oGFynVfu1RJ3qpNV RI/JGA5E6zEki4YxHsNsYvG1jG4fsxdK0w3gngln/2pbJhgdfULWSyz1wLShe9M3HMgG uUwQdAqJPmY250rB4ln1uGCZ41vm+qjH21mZmh+Qfrf7VFe19gUvYLGHAZtgkVUYbla1 zwJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=mtTL2n+za36SdkRTg7E72YsIYoFfcWaRYH/h28h8iuc=; b=X9fL2LH4qcpfVEfNkCddLruJDFpPOlmdsx3B7fD/QQ5VY2wk1WDN7z1RThsjxjvCSj n+EC2bUJ8f/Fa4sMV95PGdmptZPMH9CrGOw8gxW0YK7GL8TgzZVCEemR9Bv2GJTmX5Oz lgZbkC5+7b7gRo9dNS+fbtg0mZnCWjPQO3U8lhTOe42NJc71Abu6wVAZ1kLqSBClwcTQ cTyBLe5s67doKhZBtSXH3dm2lI7BgPWjUxrHHsDR34uBEaG2+MACcolZarI52TEPp7CI 8/8Y7GXYHmYiwp+M929ZNfey9NKoMXWIal0c3u0g+gzD/BE2VmzC5x+VhZlNwhT9Qboj uJ+g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w31-v6si9104076pla.133.2018.10.05.09.59.11; Fri, 05 Oct 2018 09:59:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729190AbeJEX6n (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:43 -0400 Received: from mail-oi1-f195.google.com ([209.85.167.195]:42331 "EHLO mail-oi1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729108AbeJEX6m (ORCPT ); Fri, 5 Oct 2018 19:58:42 -0400 Received: by mail-oi1-f195.google.com with SMTP id w81-v6so10931016oiw.9; Fri, 05 Oct 2018 09:59:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mtTL2n+za36SdkRTg7E72YsIYoFfcWaRYH/h28h8iuc=; b=nYi/oVfpKAqZQz6MWYyukJYkJY7u4F5tfnHEMC2JQe+XJdCZM6R6ztsi88S6U3Yk1y AN+WOOi6tKrCpEMQiPVrz36dF89dXHS6EawNu11LYAFdukBHBlLv8BWyVXbXGjPyYD2d FL1WDK/41g3/BViKsN293MTFatE3YeqUy8ddFbJ6gCadsa5VZKM92/kZDz6etGZIOnPr pibCLxHZT+7nyl2EwMfn29URo3mDjVoVR5qx4BMplKYWLyFsdkhqQAIc6WaoSlBpCnPu OE+t25h1YMYrbVkTvhZif+Ale6fre7te5ZJG+OZn24gd3Y1lAA+KKWPyE8gZ2hZfQuA7 QsXQ== X-Gm-Message-State: ABuFfojagQR37ILbtoLwi37swXZHTBt9rs7xlyv5FsOSfwwsAUja3NSP 0b1+L28ISW5wMvw0nUkWJuczhcQWHA== X-Received: by 2002:aca:f342:: with SMTP id r63-v6mr6246368oih.6.1538758746338; Fri, 05 Oct 2018 09:59:06 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:05 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Daniel Lezcano , Thomas Gleixner Subject: [PATCH 11/36] dt-bindings: timer: Convert ARM timer bindings to json-schema Date: Fri, 5 Oct 2018 11:58:23 -0500 Message-Id: <20181005165848.3474-12-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ARM timers to DT schema format using json-schema. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../bindings/timer/arm,arch_timer.txt | 112 ---------------- .../bindings/timer/arm,arch_timer.yaml | 103 +++++++++++++++ .../bindings/timer/arm,arch_timer_mmio.yaml | 120 ++++++++++++++++++ .../bindings/timer/arm,global_timer.txt | 27 ---- .../bindings/timer/arm,global_timer.yaml | 46 +++++++ 5 files changed, 269 insertions(+), 139 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.txt create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.yaml create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml delete mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.txt create mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt deleted file mode 100644 index 68301b77e854..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt +++ /dev/null @@ -1,112 +0,0 @@ -* ARM architected timer - -ARM cores may have a per-core architected timer, which provides per-cpu timers, -or a memory mapped architected timer, which provides up to 8 frames with a -physical and optional virtual timer per frame. - -The per-core architected timer is attached to a GIC to deliver its -per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC -to deliver its interrupts via SPIs. - -** CP15 Timer node properties: - -- compatible : Should at least contain one of - "arm,armv7-timer" - "arm,armv8-timer" - -- interrupts : Interrupt list for secure, non-secure, virtual and - hypervisor timers, in that order. - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only where necessary to work around broken firmware which does not configure - CNTFRQ on all CPUs to a uniform correct value. Use of this property is - strongly discouraged; fix your firmware unless absolutely impossible. - -- always-on : a boolean property. If present, the timer is powered through an - always-on power domain, therefore it never loses context. - -- fsl,erratum-a008585 : A boolean property. Indicates the presence of - QorIQ erratum A-008585, which says that reading the counter is - unreliable unless the same value is returned by back-to-back reads. - This also affects writes to the tval register, due to the implicit - counter read. - -- hisilicon,erratum-161010101 : A boolean property. Indicates the - presence of Hisilicon erratum 161010101, which says that reading the - counters is unreliable in some cases, and reads may return a value 32 - beyond the correct value. This also affects writes to the tval - registers, due to the implicit counter read. - -** Optional properties: - -- arm,cpu-registers-not-fw-configured : Firmware does not initialize - any of the generic timer CPU registers, which contain their - architecturally-defined reset values. Only supported for 32-bit - systems which follow the ARMv7 architected reset values. - -- arm,no-tick-in-suspend : The main counter does not tick when the system is in - low-power system suspend on some SoCs. This behavior does not match the - Architecture Reference Manual's specification that the system counter "must - be implemented in an always-on power domain." - - -Example: - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - clock-frequency = <100000000>; - }; - -** Memory mapped timer node properties: - -- compatible : Should at least contain "arm,armv7-timer-mem". - -- clock-frequency : The frequency of the main counter, in Hz. Should be present - only when firmware has not configured the MMIO CNTFRQ registers. - -- reg : The control frame base address. - -Note that #address-cells, #size-cells, and ranges shall be present to ensure -the CPU can address a frame's registers. - -A timer node has up to 8 frame sub-nodes, each with the following properties: - -- frame-number: 0 to 7. - -- interrupts : Interrupt list for physical and virtual timers in that order. - The virtual timer interrupt is optional. - -- reg : The first and second view base addresses in that order. The second view - base address is optional. - -- status : "disabled" indicates the frame is not available for use. Optional. - -Example: - - timer@f0000000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0xf0000000 0x1000>; - clock-frequency = <50000000>; - - frame@f0001000 { - frame-number = <0> - interrupts = <0 13 0x8>, - <0 14 0x8>; - reg = <0xf0001000 0x1000>, - <0xf0002000 0x1000>; - }; - - frame@f0003000 { - frame-number = <1> - interrupts = <0 15 0x8>; - reg = <0xf0003000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml new file mode 100644 index 000000000000..733ae2254c65 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm,arch_timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM architected timer + +maintainers: + - Marc Zyngier + - Mark Rutland +description: |+ + ARM cores may have a per-core architected timer, which provides per-cpu timers, + or a memory mapped architected timer, which provides up to 8 frames with a + physical and optional virtual timer per frame. + + The per-core architected timer is attached to a GIC to deliver its + per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC + to deliver its interrupts via SPIs. + +properties: + compatible: + oneOf: + - items: + - enum: + - arm,cortex-a15-timer + - enum: + - arm,armv7-timer + - items: + - enum: + - arm,armv7-timer + - items: + - enum: + - arm,armv8-timer + + interrupts: + items: + - description: secure timer irq + - description: non-secure timer irq + - description: virtual timer irq + - description: hypervisor timer irq + + clock-frequency: + description: The frequency of the main counter, in Hz. Should be present + only where necessary to work around broken firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + strongly discouraged; fix your firmware unless absolutely impossible. + + always-on: + type: boolean + description: If present, the timer is powered through an always-on power + domain, therefore it never loses context. + + fsl,erratum-a008585: + type: boolean + description: Indicates the presence of QorIQ erratum A-008585, which says + that reading the counter is unreliable unless the same value is returned + by back-to-back reads. This also affects writes to the tval register, due + to the implicit counter read. + + hisilicon,erratum-161010101: + type: boolean + description: Indicates the presence of Hisilicon erratum 161010101, which + says that reading the counters is unreliable in some cases, and reads may + return a value 32 beyond the correct value. This also affects writes to + the tval registers, due to the implicit counter read. + + arm,cpu-registers-not-fw-configured: + type: boolean + description: Firmware does not initialize any of the generic timer CPU + registers, which contain their architecturally-defined reset values. Only + supported for 32-bit systems which follow the ARMv7 architected reset + values. + + arm,no-tick-in-suspend: + type: boolean + description: The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + +required: + - compatible + +oneOf: + - required: + - interrupts + - required: + - interrupts-extended + +examples: + - | + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + clock-frequency = <100000000>; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml new file mode 100644 index 000000000000..34c8ecfea2a5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm,arch_timer_mmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM memory mapped architected timer + +maintainers: + - Marc Zyngier + - Mark Rutland + +description: |+ + ARM cores may have a memory mapped architected timer, which provides up to 8 + frames with a physical and optional virtual timer per frame. + + The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs. + +properties: + compatible: + items: + - enum: + - arm,armv7-timer-mem + + reg: + maxItems: 1 + description: The control frame base address + + '#address-cells': + enum: [1, 2] + + '#size-cells': + const: 1 + + clock-frequency: + description: The frequency of the main counter, in Hz. Should be present + only where necessary to work around broken firmware which does not configure + CNTFRQ on all CPUs to a uniform correct value. Use of this property is + strongly discouraged; fix your firmware unless absolutely impossible. + + always-on: + type: boolean + description: If present, the timer is powered through an always-on power + domain, therefore it never loses context. + + arm,cpu-registers-not-fw-configured: + type: boolean + description: Firmware does not initialize any of the generic timer CPU + registers, which contain their architecturally-defined reset values. Only + supported for 32-bit systems which follow the ARMv7 architected reset + values. + + arm,no-tick-in-suspend: + type: boolean + description: The main counter does not tick when the system is in + low-power system suspend on some SoCs. This behavior does not match the + Architecture Reference Manual's specification that the system counter "must + be implemented in an always-on power domain." + +patternProperties: + '^frame@[0-9a-z]*$': + description: A timer node has up to 8 frame sub-nodes, each with the following properties. + properties: + frame-number: + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + maximum: 7 + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: physical timer irq + - description: virtual timer irq + + reg : + minItems: 1 + maxItems: 2 + items: + - description: 1st view base address + - description: 2nd optional view base address + + required: + - frame-number + - interrupts + - reg + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +examples: + - | + timer@f0000000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xf0000000 0x1000>; + clock-frequency = <50000000>; + + frame@f0001000 { + frame-number = <0>; + interrupts = <0 13 0x8>, + <0 14 0x8>; + reg = <0xf0001000 0x1000>, + <0xf0002000 0x1000>; + }; + + frame@f0003000 { + frame-number = <1>; + interrupts = <0 15 0x8>; + reg = <0xf0003000 0x1000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt deleted file mode 100644 index bdae3a818793..000000000000 --- a/Documentation/devicetree/bindings/timer/arm,global_timer.txt +++ /dev/null @@ -1,27 +0,0 @@ - -* ARM Global Timer - Cortex-A9 are often associated with a per-core Global timer. - -** Timer node required properties: - -- compatible : should contain - * "arm,cortex-a5-global-timer" for Cortex-A5 global timers. - * "arm,cortex-a9-global-timer" for Cortex-A9 global - timers or any compatible implementation. Note: driver - supports versions r2p0 and above. - -- interrupts : One interrupt to each core - -- reg : Specify the base address and the size of the GT timer - register window. - -- clocks : Should be phandle to a clock. - -Example: - - timer@2c000600 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x2c000600 0x20>; - interrupts = <1 13 0xf01>; - clocks = <&arm_periph_clk>; - }; diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml new file mode 100644 index 000000000000..09090f677387 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm,global_timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Global Timer + +maintainers: + - Stuart Menefy + +description: + Cortex-A9 are often associated with a per-core Global timer. + +properties: + compatible: + items: + - enum: + - arm,cortex-a5-global-timer + - arm,cortex-a9-global-timer + + description: driver supports versions r2p0 and above. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + timer@2c000600 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x2c000600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&arm_periph_clk>; + }; +... From patchwork Fri Oct 5 16:58:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148238 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689063lji; Fri, 5 Oct 2018 09:59:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV63fDH+zJbsh2qozbx1as5KvKnyLBseJT5XSY5+0nyjJkT07E0O4dfXoakURN/QatatvPnHO X-Received: by 2002:a62:2982:: with SMTP id p124-v6mr12702474pfp.128.1538758754027; Fri, 05 Oct 2018 09:59:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758754; cv=none; d=google.com; s=arc-20160816; b=sKJF62E5mv5lXkWQ4dg/tmgin2+VueYo6BDSkladl1I/FR6FZPCBpWToFGRA3xAn7B DLErVvj+4ddL8zWWqIuZjE9ZTJ4udw5yupmdbzYzfJvyI45okfbSV3kBHtWVAUljtZD+ 5/id4nuXbspJKiINeGMLRbshiWWcyuNjUp3iZciRwHhGMWLxe0DVcTRrnyFOwJbuvLKB +/m9XB321JJKxwAUw1gYPcAcCPEYegzEID/2IXUBwuN7gCElYgFNHwYZqoAHh+1i06MB pxWrJMs18CzwB5al+ct2HE8u6xVTB+luzUdxmleHZB/pQwSG/x8YSkNMxuGgj5kBsZM9 ZNNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=WLcoBwwBfOERKzo9rW58qzDysAW/KcU3knA0lIoHGhc=; b=pqe51vuIC07bmu930xpnTAUC5QCpqwc6Sa/DmZAUEoqcwIVRfG0iV3tx0DoP7Y8HeS p2bQcc2PmmvzMRnNCegKkpxSsNZAJzhlW/dPNiseJu8cFXJ2c4Y+FAml8ebH5jyeWJb2 w28XLVFiTVi7JkDwCTWbEtMYC/XxDz/M/DchX13aSwbPkpL1cftsqfP1XWEobYcsYDY+ rD58cFsfvTLgN4FUzbJWhB6Wf5QpoLqy4Xo54/dymD0yAWj6/FMzjYrNQ0GdHmxnALcp Jk2of1BGnlV1KjwX+K6HlHyy3SscXAfono5B4MYaJBtxDg0+g+Wg/4qgI4zKQX3N86FJ WoLQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y1-v6si7700793pgf.78.2018.10.05.09.59.13; Fri, 05 Oct 2018 09:59:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729218AbeJEX6o (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:44 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:43279 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729164AbeJEX6o (ORCPT ); Fri, 5 Oct 2018 19:58:44 -0400 Received: by mail-oi1-f193.google.com with SMTP id s69-v6so10935325oie.10; Fri, 05 Oct 2018 09:59:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WLcoBwwBfOERKzo9rW58qzDysAW/KcU3knA0lIoHGhc=; b=AyczDEBX8NVFXNprv4XlsI/sScmMVwVzp/kyXhAeNjQAWmjhjxj/oDOcb2ivG9+enX xz8LdnkJ+Qr3S4ho0OkeH2Uu9FGGLFAmABZdpbmo7wk89b96yObvHS4hDvIUBkzXfK/T NzVpXqIxrAfT77U8OjLnrg0INMqLrdIblgkla5KHBVPu+KpiWlECJp+LbZh5YOdQ/c03 SWvMH4NCW1yOX3ahbvF4CKxQDoCK+wOt6UF4q1NeHaDfONT/AaRi+FfCWnwAwMJaHX2G y6zQ+FCvv1ir+F916oFlex9U+CQZYtk4/Ks6LEAZd5PV3yKZjtE9Bq7VQXc5n1N+eRG4 +bZA== X-Gm-Message-State: ABuFfojKvxZGpBnvqb2vUKWlG4GahMmIzXgwPFWAuw6S9gUKdJP7E+mu j4qDgKLs2+kxZJgzZ3LsZzz0/32QSA== X-Received: by 2002:aca:c392:: with SMTP id t140-v6mr6048578oif.325.1538758747750; Fri, 05 Oct 2018 09:59:07 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:07 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Matthias Brugger , linux-mediatek@lists.infradead.org Subject: [PATCH 12/36] dt-bindings: arm: Convert cpu binding to json-schema Date: Fri, 5 Oct 2018 11:58:24 -0500 Message-Id: <20181005165848.3474-13-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ARM CPU binding to DT schema format using json-schema. Cc: Mark Rutland Cc: Matthias Brugger Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/cpus.txt | 490 ----------------- .../devicetree/bindings/arm/cpus.yaml | 503 ++++++++++++++++++ 2 files changed, 503 insertions(+), 490 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/cpus.txt create mode 100644 Documentation/devicetree/bindings/arm/cpus.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt deleted file mode 100644 index b0198a1cf403..000000000000 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ /dev/null @@ -1,490 +0,0 @@ -================= -ARM CPUs bindings -================= - -The device tree allows to describe the layout of CPUs in a system through -the "cpus" node, which in turn contains a number of subnodes (ie "cpu") -defining properties for every cpu. - -Bindings for CPU nodes follow the Devicetree Specification, available from: - -https://www.devicetree.org/specifications/ - -with updates for 32-bit and 64-bit ARM systems provided in this document. - -================================ -Convention used in this document -================================ - -This document follows the conventions described in the Devicetree -Specification, with the addition: - -- square brackets define bitfields, eg reg[7:0] value of the bitfield in - the reg property contained in bits 7 down to 0 - -===================================== -cpus and cpu node bindings definition -===================================== - -The ARM architecture, in accordance with the Devicetree Specification, -requires the cpus and cpu nodes to be present and contain the properties -described below. - -- cpus node - - Description: Container of cpu nodes - - The node name must be "cpus". - - A cpus node must define the following properties: - - - #address-cells - Usage: required - Value type: - - Definition depends on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - value must be 1, to enable a simple enumeration - scheme for processors that do not have a HW CPU - identification register. - # On 32-bit ARM 11 MPcore, ARM v7 or later systems - value must be 1, that corresponds to CPUID/MPIDR - registers sizes. - # On ARM v8 64-bit systems value should be set to 2, - that corresponds to the MPIDR_EL1 register size. - If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - in the system, #address-cells can be set to 1, since - MPIDR_EL1[63:32] bits are not used for CPUs - identification. - - #size-cells - Usage: required - Value type: - Definition: must be set to 0 - -- cpu node - - Description: Describes a CPU in an ARM based system - - PROPERTIES - - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg - Usage and definition depend on ARM architecture version and - configuration: - - # On uniprocessor ARM architectures previous to v7 - this property is required and must be set to 0. - - # On ARM 11 MPcore based systems this property is - required and matches the CPUID[11:0] register bits. - - Bits [11:0] in the reg cell must be set to - bits [11:0] in CPU ID register. - - All other bits in the reg cell must be set to 0. - - # On 32-bit ARM v7 or later systems this property is - required and matches the CPU MPIDR[23:0] register - bits. - - Bits [23:0] in the reg cell must be set to - bits [23:0] in MPIDR. - - All other bits in the reg cell must be set to 0. - - # On ARM v8 64-bit systems this property is required - and matches the MPIDR_EL1 register affinity bits. - - * If cpus node's #address-cells property is set to 2 - - The first reg cell bits [7:0] must be set to - bits [39:32] of MPIDR_EL1. - - The second reg cell bits [23:0] must be set to - bits [23:0] of MPIDR_EL1. - - * If cpus node's #address-cells property is set to 1 - - The reg cell bits [23:0] must be set to bits [23:0] - of MPIDR_EL1. - - All other bits in the reg cells must be set to 0. - - - compatible: - Usage: required - Value type: - Definition: should be one of: - "arm,arm710t" - "arm,arm720t" - "arm,arm740t" - "arm,arm7ej-s" - "arm,arm7tdmi" - "arm,arm7tdmi-s" - "arm,arm9es" - "arm,arm9ej-s" - "arm,arm920t" - "arm,arm922t" - "arm,arm925" - "arm,arm926e-s" - "arm,arm926ej-s" - "arm,arm940t" - "arm,arm946e-s" - "arm,arm966e-s" - "arm,arm968e-s" - "arm,arm9tdmi" - "arm,arm1020e" - "arm,arm1020t" - "arm,arm1022e" - "arm,arm1026ej-s" - "arm,arm1136j-s" - "arm,arm1136jf-s" - "arm,arm1156t2-s" - "arm,arm1156t2f-s" - "arm,arm1176jzf" - "arm,arm1176jz-s" - "arm,arm1176jzf-s" - "arm,arm11mpcore" - "arm,cortex-a5" - "arm,cortex-a7" - "arm,cortex-a8" - "arm,cortex-a9" - "arm,cortex-a12" - "arm,cortex-a15" - "arm,cortex-a17" - "arm,cortex-a53" - "arm,cortex-a57" - "arm,cortex-a72" - "arm,cortex-a73" - "arm,cortex-m0" - "arm,cortex-m0+" - "arm,cortex-m1" - "arm,cortex-m3" - "arm,cortex-m4" - "arm,cortex-r4" - "arm,cortex-r5" - "arm,cortex-r7" - "brcm,brahma-b15" - "brcm,brahma-b53" - "brcm,vulcan" - "cavium,thunder" - "cavium,thunder2" - "faraday,fa526" - "intel,sa110" - "intel,sa1100" - "marvell,feroceon" - "marvell,mohawk" - "marvell,pj4a" - "marvell,pj4b" - "marvell,sheeva-v5" - "nvidia,tegra132-denver" - "nvidia,tegra186-denver" - "nvidia,tegra194-carmel" - "qcom,krait" - "qcom,kryo" - "qcom,kryo385" - "qcom,scorpion" - - enable-method - Value type: - Usage and definition depend on ARM architecture version. - # On ARM v8 64-bit this property is required and must - be one of: - "psci" - "spin-table" - # On ARM 32-bit systems this property is optional and - can be one of: - "actions,s500-smp" - "allwinner,sun6i-a31" - "allwinner,sun8i-a23" - "allwinner,sun9i-a80-smp" - "amlogic,meson8-smp" - "amlogic,meson8b-smp" - "arm,realview-smp" - "brcm,bcm11351-cpu-method" - "brcm,bcm23550" - "brcm,bcm2836-smp" - "brcm,bcm-nsp-smp" - "brcm,brahma-b15" - "marvell,armada-375-smp" - "marvell,armada-380-smp" - "marvell,armada-390-smp" - "marvell,armada-xp-smp" - "marvell,98dx3236-smp" - "mediatek,mt6589-smp" - "mediatek,mt81xx-tz-smp" - "qcom,gcc-msm8660" - "qcom,kpss-acc-v1" - "qcom,kpss-acc-v2" - "renesas,apmu" - "renesas,r9a06g032-smp" - "rockchip,rk3036-smp" - "rockchip,rk3066-smp" - "ste,dbx500-smp" - - - cpu-release-addr - Usage: required for systems that have an "enable-method" - property value of "spin-table". - Value type: - Definition: - # On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. - - - qcom,saw - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the SAW[1] node associated with this CPU. - - - qcom,acc - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the ACC[2] node associated with this CPU. - - - cpu-idle-states - Usage: Optional - Value type: - Definition: - # List of phandles to idle state nodes supported - by this cpu [3]. - - - capacity-dmips-mhz - Usage: Optional - Value type: - Definition: - # u32 value representing CPU capacity [4] in - DMIPS/MHz, relative to highest capacity-dmips-mhz - in the system. - - - rockchip,pmu - Usage: optional for systems that have an "enable-method" - property value of "rockchip,rk3066-smp" - While optional, it is the preferred way to get access to - the cpu-core power-domains. - Value type: - Definition: Specifies the syscon node controlling the cpu core - power domains. - - - dynamic-power-coefficient - Usage: optional - Value type: - Definition: A u32 value that represents the running time dynamic - power coefficient in units of uW/MHz/V^2. The - coefficient can either be calculated from power - measurements or derived by analysis. - - The dynamic power consumption of the CPU is - proportional to the square of the Voltage (V) and - the clock frequency (f). The coefficient is used to - calculate the dynamic power as below - - - Pdyn = dynamic-power-coefficient * V^2 * f - - where voltage is in V, frequency is in MHz. - -Example 1 (dual-cluster big.LITTLE system 32-bit): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x101>; - }; - }; - -Example 2 (Cortex-A8 uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a8"; - reg = <0x0>; - }; - }; - -Example 3 (ARM 926EJ-S uniprocessor 32-bit system): - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - -Example 4 (ARM Cortex-A57 64-bit system): - -cpus { - #size-cells = <0>; - #address-cells = <2>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100000101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; - - cpu@100010101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x20000000>; - }; -}; - --- -[1] arm/msm/qcom,saw2.txt -[2] arm/msm/qcom,kpss-acc.txt -[3] ARM Linux kernel documentation - idle states bindings - Documentation/devicetree/bindings/arm/idle-states.txt -[4] ARM Linux kernel documentation - cpu capacity bindings - Documentation/devicetree/bindings/arm/cpu-capacity.txt diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml new file mode 100644 index 000000000000..bb75914324a3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -0,0 +1,503 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CPUs bindings + +maintainers: + - Lorenzo Pieralisi + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + + with updates for 32-bit and 64-bit ARM systems provided in this document. + + ================================ + Convention used in this document + ================================ + + This document follows the conventions described in the Devicetree + Specification, with the addition: + + - square brackets define bitfields, eg reg[7:0] value of the bitfield in + the reg property contained in bits 7 down to 0 + + ===================================== + cpus and cpu node bindings definition + ===================================== + + The ARM architecture, in accordance with the Devicetree Specification, + requires the cpus and cpu nodes to be present and contain the properties + described below. + +properties: + $nodename: + const: cpus + description: Container of cpu nodes + + '#address-cells': + enum: [1, 2] + description: | + Definition depends on ARM architecture version and configuration: + + On uniprocessor ARM architectures previous to v7 + value must be 1, to enable a simple enumeration + scheme for processors that do not have a HW CPU + identification register. + On 32-bit ARM 11 MPcore, ARM v7 or later systems + value must be 1, that corresponds to CPUID/MPIDR + registers sizes. + On ARM v8 64-bit systems value should be set to 2, + that corresponds to the MPIDR_EL1 register size. + If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + in the system, #address-cells can be set to 1, since + MPIDR_EL1[63:32] bits are not used for CPUs + identification. + + '#size-cells': + const: 0 + +patternProperties: + '^cpu@[0-9a-f]+$': + properties: + device_type: + const: cpu + + reg: + maxItems: 1 + description: | + Usage and definition depend on ARM architecture version and + configuration: + + On uniprocessor ARM architectures previous to v7 + this property is required and must be set to 0. + + On ARM 11 MPcore based systems this property is + required and matches the CPUID[11:0] register bits. + + Bits [11:0] in the reg cell must be set to + bits [11:0] in CPU ID register. + + All other bits in the reg cell must be set to 0. + + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. + + On ARM v8 64-bit systems this property is required + and matches the MPIDR_EL1 register affinity bits. + + * If cpus node's #address-cells property is set to 2 + + The first reg cell bits [7:0] must be set to + bits [39:32] of MPIDR_EL1. + + The second reg cell bits [23:0] must be set to + bits [23:0] of MPIDR_EL1. + + * If cpus node's #address-cells property is set to 1 + + The reg cell bits [23:0] must be set to bits [23:0] + of MPIDR_EL1. + + All other bits in the reg cells must be set to 0. + + compatible: + items: + - enum: + - arm,arm710t + - arm,arm720t + - arm,arm740t + - arm,arm7ej-s + - arm,arm7tdmi + - arm,arm7tdmi-s + - arm,arm9es + - arm,arm9ej-s + - arm,arm920t + - arm,arm922t + - arm,arm925 + - arm,arm926e-s + - arm,arm926ej-s + - arm,arm940t + - arm,arm946e-s + - arm,arm966e-s + - arm,arm968e-s + - arm,arm9tdmi + - arm,arm1020e + - arm,arm1020t + - arm,arm1022e + - arm,arm1026ej-s + - arm,arm1136j-s + - arm,arm1136jf-s + - arm,arm1156t2-s + - arm,arm1156t2f-s + - arm,arm1176jzf + - arm,arm1176jz-s + - arm,arm1176jzf-s + - arm,arm11mpcore + - arm,cortex-a5 + - arm,cortex-a7 + - arm,cortex-a8 + - arm,cortex-a9 + - arm,cortex-a12 + - arm,cortex-a15 + - arm,cortex-a17 + - arm,cortex-a53 + - arm,cortex-a57 + - arm,cortex-a72 + - arm,cortex-a73 + - arm,cortex-m0 + - arm,cortex-m0+ + - arm,cortex-m1 + - arm,cortex-m3 + - arm,cortex-m4 + - arm,cortex-r4 + - arm,cortex-r5 + - arm,cortex-r7 + - brcm,brahma-b15 + - brcm,brahma-b53 + - brcm,vulcan + - cavium,thunder + - cavium,thunder2 + - faraday,fa526 + - intel,sa110 + - intel,sa1100 + - marvell,feroceon + - marvell,mohawk + - marvell,pj4a + - marvell,pj4b + - marvell,sheeva-v5 + - nvidia,tegra132-denver + - nvidia,tegra186-denver + - nvidia,tegra194-carmel + - qcom,krait + - qcom,kryo + - qcom,kryo385 + - qcom,scorpion + + enable-method: + allOf: + - $ref: '/schemas/types.yaml#/definitions/string' + - oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - ste,dbx500-smp + + cpu-release-addr: + $ref: '/schemas/types.yaml#/definitions/uint64' + + description: + Required for systems that have an "enable-method" + property value of "spin-table". + On ARM v8 64-bit systems must be a two cell + property identifying a 64-bit zero-initialised + memory location. + + qcom,saw: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Usage: required for systems that have an "enable-method" + property value of "qcom,kpss-acc-v1" or + "qcom,kpss-acc-v2" + Definition: Specifies the SAW[1] node associated with this CPU. + + qcom,acc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Usage: required for systems that have an "enable-method" + property value of "qcom,kpss-acc-v1" or + "qcom,kpss-acc-v2" + Definition: Specifies the ACC[2] node associated with this CPU. + + cpu-idle-states: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: | + Usage: Optional + Value type: + description: List of phandles to idle state nodes supported + by this cpu [3]. + + capacity-dmips-mhz: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + u32 value representing CPU capacity [4] in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + + rockchip,pmu: + description: | + Optional for systems that have an "enable-method" + property value of "rockchip,rk3066-smp" + While optional, it is the preferred way to get access to + the cpu-core power-domains. + Value type: + Definition: Specifies the syscon node controlling the cpu core + power domains. + + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the CPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + + required: + - device_type + - reg + - compatible + + dependencies: + cpu-release-addr: [enable-method] + rockchip,pmu: [enable-method] + +required: + - '#address-cells' + - '#size-cells' + +examples: + - | + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + }; + }; + + - | + // Example 2 (Cortex-A8 uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0x0>; + }; + }; + + - | + // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + - | + // Example 4 (ARM Cortex-A57 64-bit system): + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100000101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010000 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010001 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@100010101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x1 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + }; +... From patchwork Fri Oct 5 16:58:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148262 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp692053lji; Fri, 5 Oct 2018 10:01:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV63dJKNQ2sT/7URuPPtcIxR2cfAFRqUjAGpDHsD3dqD4Swn7EFXTN1nqNLc7DPxX0rbr5Wno X-Received: by 2002:a63:8e43:: with SMTP id k64-v6mr10738712pge.75.1538758908698; Fri, 05 Oct 2018 10:01:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758908; cv=none; d=google.com; s=arc-20160816; b=Doyh43yUAzuomxgSRXOkfJM1Rm2fRJQRnC+Xppys3zEJ/YoN7wOvjmq76jeB/uag1S b/i3kQUMrHWAPg/dKabjDUrikrJBfDXuP4ObHROmSJJZqbD45uW45GOmBY0Ihf25gHuX GfrTRrdMpY7l+IVwHP2Dj1ziAO55ZT/LsuKaQPlY8mWZxHyY2oFOsPx10gpNyKAKXVMB WfTQsIRtPgIvLKlBLwhbnP/p1qYGvqqMKP0Nab3LYQlGURDiyhJ+mp7zCkaJMD8UoK6r hARQl7rY2zA7VSelymfx0EQlPnnTx6zlmFcaZQ/bIeTcDTkakltMCavJZZzXZ3OOhscF G61Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=PPgzQVjusYgNqChRktE3KOIpcteqC2FE8uYi4ggIVGg=; b=yCduzfNgquJ3OhNLdRci+8dOPJ+4emm81fUYty11b2Ypcul70DQBMOhLxmv4J9iI8w qbjzHcb6o1BRM2UKR1lhEeOLR7VkXoj5PfeGC7nWx49ZG3jNlhOYP+2q6MweyIFyhK8j l1du475qMmzFK5L/iQP2A7e7KQ45MOP323Fqk4QUw8N+g32pXjq5XJ06WySsZDGMNjqy 7fnOuGhipHSKSldseqs7ST2cWbC48rzVU76Pkb3U4Cl14WVuIj7lMdeAU4DFRTp12/TZ 8c5ojsj6Ctgdx2QYCHUUyRaO+FiN3Q0309wHm2gpuMvbCxhpkM5mCRsSUz1tBe9Ty58W H9Kw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c24-v6si8887417pls.211.2018.10.05.10.01.47; Fri, 05 Oct 2018 10:01:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729615AbeJFABU (ORCPT + 32 others); Fri, 5 Oct 2018 20:01:20 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:41316 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729189AbeJEX6o (ORCPT ); Fri, 5 Oct 2018 19:58:44 -0400 Received: by mail-ot1-f65.google.com with SMTP id e18-v6so13356691oti.8; Fri, 05 Oct 2018 09:59:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PPgzQVjusYgNqChRktE3KOIpcteqC2FE8uYi4ggIVGg=; b=Inbw1RD1tKoTvxe0H0mgW9lbv1BrscJ0IacNTwSoxABAegM86T2DJbaBRqxo0QGcWF GnK8EyQho/6v1crGjHQjxF7pJ0zyHB5/B8n6ZaZfiurRz5phjn8HEAOfgB0PLSiWNyh4 J/EJs3Xx4y1Ha5agpxejSwq6LPI6MVlIeRpBvo38ycKP1DUAHGJbVbYqneX90EdjMJoX 0GFfT+PlYhKjbNYKDKkDi2u2gT4jZB6fPJyAYpC+TtgxiV3XWu+c1aGLOzrM3Aq0Rh68 C2dfs3z+XuybL1gkJ4AzU0MpXnxYUCLEWygbhb38lWUBzUrleiNb7uxHCUYpWBGIeYcC PBSQ== X-Gm-Message-State: ABuFfohlSlsCnD35gVwqQbfYwgfalgqDYeaQeMcrH75N507zUH9V96F7 Fdt85LfZBU4l8SUb3omESsTdeXrbfA== X-Received: by 2002:a9d:1723:: with SMTP id i35mr7447888ota.223.1538758749111; Fri, 05 Oct 2018 09:59:09 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:08 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Will Deacon Subject: [PATCH 13/36] dt-bindings: arm: Convert PMU binding to json-schema Date: Fri, 5 Oct 2018 11:58:25 -0500 Message-Id: <20181005165848.3474-14-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ARM PMU binding to DT schema format using json-schema. Cc: Will Deacon Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/pmu.txt | 70 -------------- .../devicetree/bindings/arm/pmu.yaml | 96 +++++++++++++++++++ 2 files changed, 96 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt deleted file mode 100644 index 13611a8199bb..000000000000 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ /dev/null @@ -1,70 +0,0 @@ -* ARM Performance Monitor Units - -ARM cores often have a PMU for counting cpu and cache events like cache misses -and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU -representation in the device tree should be done as under:- - -Required properties: - -- compatible : should be one of - "apm,potenza-pmu" - "arm,armv8-pmuv3" - "arm,cortex-a73-pmu" - "arm,cortex-a72-pmu" - "arm,cortex-a57-pmu" - "arm,cortex-a53-pmu" - "arm,cortex-a35-pmu" - "arm,cortex-a17-pmu" - "arm,cortex-a15-pmu" - "arm,cortex-a12-pmu" - "arm,cortex-a9-pmu" - "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" - "arm,arm1176-pmu" - "arm,arm1136-pmu" - "brcm,vulcan-pmu" - "cavium,thunder-pmu" - "qcom,scorpion-pmu" - "qcom,scorpion-mp-pmu" - "qcom,krait-pmu" -- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu - interrupt (PPI) then 1 interrupt should be specified. - -Optional properties: - -- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU - nodes corresponding directly to the affinity of - the SPIs listed in the interrupts property. - - When using a PPI, specifies a list of phandles to CPU - nodes corresponding to the set of CPUs which have - a PMU of this type signalling the PPI listed in the - interrupts property, unless this is already specified - by the PPI interrupt specifier itself (in which case - the interrupt-affinity property shouldn't be present). - - This property should be present when there is more than - a single SPI. - - -- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd - events. - -- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register - (SDER) is accessible. This will cause the driver to do - any setup required that is only possible in ARMv7 secure - state. If not present the ARMv7 SDER will not be touched, - which means the PMU may fail to operate unless external - code (bootloader or security monitor) has performed the - appropriate initialisation. Note that this property is - not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux - in Non-secure state. - -Example: - -pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <100 101>; -}; diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml new file mode 100644 index 000000000000..0dbb9e0566af --- /dev/null +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Performance Monitor Units + +maintainers: + - Mark Rutland + - Will Deacon +description: |+ + ARM cores often have a PMU for counting cpu and cache events like cache misses + and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU + representation in the device tree should be done as under:- + +properties: + compatible: + items: + - enum: + - apm,potenza-pmu + - arm,armv8-pmuv3 + - arm,cortex-a73-pmu + - arm,cortex-a72-pmu + - arm,cortex-a57-pmu + - arm,cortex-a53-pmu + - arm,cortex-a35-pmu + - arm,cortex-a17-pmu + - arm,cortex-a15-pmu + - arm,cortex-a12-pmu + - arm,cortex-a9-pmu + - arm,cortex-a8-pmu + - arm,cortex-a7-pmu + - arm,cortex-a5-pmu + - arm,arm11mpcore-pmu + - arm,arm1176-pmu + - arm,arm1136-pmu + - brcm,vulcan-pmu + - cavium,thunder-pmu + - qcom,scorpion-pmu + - qcom,scorpion-mp-pmu + - qcom,krait-pmu + interrupts: + oneOf: + - maxItems: 1 + - minItems: 2 + maxItems: 8 + description: 1 interrupt per core. + + interrupts-extended: + $ref: '#/properties/interrupts' + + interrupt-affinity: + description: + When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of + the SPIs listed in the interrupts property. + + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property, unless this is already specified + by the PPI interrupt specifier itself (in which case + the interrupt-affinity property shouldn't be present). + + This property should be present when there is more than + a single SPI. + + qcom,no-pc-write: + type: boolean + description: + Indicates that this PMU doesn't support the 0xc and 0xd events. + + secure-reg-access: + type: boolean + description: + Indicates that the ARMv7 Secure Debug Enable Register + (SDER) is accessible. This will cause the driver to do + any setup required that is only possible in ARMv7 secure + state. If not present the ARMv7 SDER will not be touched, + which means the PMU may fail to operate unless external + code (bootloader or security monitor) has performed the + appropriate initialisation. Note that this property is + not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux + in Non-secure state. + +required: + - compatible + +oneOf: + - required: + - interrupts + - required: + - interrupts-extended + +... From patchwork Fri Oct 5 16:58:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148239 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689085lji; Fri, 5 Oct 2018 09:59:15 -0700 (PDT) X-Google-Smtp-Source: ACcGV63VSa91KYpeQCUmt/0fGh2zAEiYH5Gm2oNFJz7Gi2g8oOC2rNSTO7HpkN5v66hcCV8TT96s X-Received: by 2002:a62:e110:: with SMTP id q16-v6mr12669426pfh.75.1538758755697; Fri, 05 Oct 2018 09:59:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758755; cv=none; d=google.com; s=arc-20160816; b=H2F/wc8xqgaWxTkrgT9+leuAbSINngYrzLTXAU6QrS06tI548N3lAg6vovFoNldVXK 2Bw5FDol8VAZvXtALlOyX7YJnbS57K8qehA/N94hQWgC2lAKujAo5UaDYfkiJfxMYPoQ qfGNncYWW2NNl7b/zNZiHlVZoM2q9jdJ73J0AAs9MxcV1clIGafG6wbRqwFFoWAxiw+A EdXT5khwaGC8yd5jMovc1mSuXu7MwYqIlrkkTGKu7ZtYvJmZBM/7ACbGdhMBAB/QZ0nD UIbqf5jy1Ft9NTnSA38GeFp9ZgNYFrD5E4m2KDmPBKMskGpS08Pg7TCVqSCAh7+0cmJ8 f/Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=7IXpfPQDP0ZoNfR+xycIt5dHNa3FBYx05kaWJs5b62w=; b=VNHNWkrmngKg3pVbRz8BVijF7w0xd0tZCeL1WHi45AGQIu6DYItMD6TlCJd1a3etU/ qMIgXr9N89FFQgljB63+GU9PHApk9DE1JP45e5sj2hlcd1VtLeWrkcoKmUW2SRglMI0o L2aWeOsK2JYL1zX34CapwYLMkoPzmlnN6RJsDILaJtfOVxKv6LlFfkhh3qn+dRVGherN YO8wCpQEx+jKOwiYlYkvPK5KihbzaZN1+bUx1uyKludfJok354ugBC4Gt1LMehMipTzr nBeN6VyaQT473dR0jfK3ilkogKozl52j1iY+yL4q7i2EMPPzGZjB7UlQT5/SZRkgSuwW GT2A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i4-v6si7781833pgk.564.2018.10.05.09.59.15; Fri, 05 Oct 2018 09:59:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729244AbeJEX6q (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:46 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:42923 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729164AbeJEX6p (ORCPT ); Fri, 5 Oct 2018 19:58:45 -0400 Received: by mail-ot1-f68.google.com with SMTP id h26-v6so13360529otl.9; Fri, 05 Oct 2018 09:59:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7IXpfPQDP0ZoNfR+xycIt5dHNa3FBYx05kaWJs5b62w=; b=CQmyMBgR/AnycuQ+d4PhJYXqLoeKOzfPNA/D9QKpzj4ZTEKoNN/KB/5nW7TjLDvHs5 0mzlQETuEETbUcqqVY3aUKBuj2nDMJAL0eDqJFkmA+B/cEIq0LSxoj+XsBrbAJ8I4xJo zIuSoFhWH8DeYVwxPnZYfsHH2cuRma7HYVmU0SNLod7E6LD+nL5FWb77kvCacOxZl8lz EAaYhRFql3s8ENeczaaQoPGVlNv+v64yS5FCUjq/Hg9DauMVSELIsm8LG4wK86vRiOqp lxZGWSG2YmmZguCSSaa04ReVlsWacH3kRkxGhfvJsjpC9l9dwuVWnsjLE/DPM3I7CUNz 6vzg== X-Gm-Message-State: ABuFfogMSr62zz6I8Z2za8P5rP6T4R/LA31nnHwX/6Gep3TmPV7sGDt1 9T50+zZDsaBjX4gEb3MoY/e41z0dBw== X-Received: by 2002:a9d:538c:: with SMTP id w12mr1623009otg.139.1538758750406; Fri, 05 Oct 2018 09:59:10 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:09 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson Subject: [PATCH 14/36] dt-bindings: arm: Convert primecell binding to json-schema Date: Fri, 5 Oct 2018 11:58:26 -0500 Message-Id: <20181005165848.3474-15-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ARM Primecell binding to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/primecell.txt | 46 ------------------- .../devicetree/bindings/arm/primecell.yaml | 35 ++++++++++++++ 2 files changed, 35 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/primecell.txt create mode 100644 Documentation/devicetree/bindings/arm/primecell.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt deleted file mode 100644 index 0df6acacfaea..000000000000 --- a/Documentation/devicetree/bindings/arm/primecell.txt +++ /dev/null @@ -1,46 +0,0 @@ -* ARM Primecell Peripherals - -ARM, Ltd. Primecell peripherals have a standard id register that can be used to -identify the peripheral type, vendor, and revision. This value can be used for -driver matching. - -Required properties: - -- compatible : should be a specific name for the peripheral and - "arm,primecell". The specific name will match the ARM - engineering name for the logic block in the form: "arm,pl???" - -Optional properties: - -- arm,primecell-periphid : Value to override the h/w value with -- clocks : From common clock binding. First clock is phandle to clock for apb - pclk. Additional clocks are optional and specific to those peripherals. -- clock-names : From common clock binding. Shall be "apb_pclk" for first clock. -- dmas : From common DMA binding. If present, refers to one or more dma channels. -- dma-names : From common DMA binding, needs to match the 'dmas' property. - Devices with exactly one receive and transmit channel shall name - these "rx" and "tx", respectively. -- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- interrupts : one or more interrupt specifiers -- interrupt-names : names corresponding to the interrupts properties - -Example: - -serial@fff36000 { - compatible = "arm,pl011", "arm,primecell"; - arm,primecell-periphid = <0x00341011>; - - clocks = <&pclk>; - clock-names = "apb_pclk"; - - dmas = <&dma-controller 4>, <&dma-controller 5>; - dma-names = "rx", "tx"; - - pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; - pinctrl-1 = <&uart0_sleep_mode>; - pinctrl-names = "default","sleep"; - - interrupts = <0 11 0x4>; -}; - diff --git a/Documentation/devicetree/bindings/arm/primecell.yaml b/Documentation/devicetree/bindings/arm/primecell.yaml new file mode 100644 index 000000000000..d8097521dc7d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/primecell.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/primecell.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Primecell Peripherals + +maintainers: + - Grant Likely +description: |+ + ARM, Ltd. Primecell peripherals have a standard id register that can be used to + identify the peripheral type, vendor, and revision. This value can be used for + driver matching. + +properties: + compatible: + contains: + const: arm,primecell + description: + Should be a specific name for the peripheral followed by "arm,primecell". + The specific name will match the ARM engineering name for the logic block + in the form "arm,pl???" + + arm,primecell-periphid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Value to override the h/w ID value + clocks: + minItems: 1 + maxItems: 32 + clock-names: + contains: + const: apb_pclk + additionalItems: true +... From patchwork Fri Oct 5 16:58:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148242 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689133lji; Fri, 5 Oct 2018 09:59:18 -0700 (PDT) X-Google-Smtp-Source: ACcGV6195DYPwLKlRWqwuCPZOAKE9jLDHG1hLGlyG9whUMr37neCXsYdksZOM46NWtX4QeucDJMZ X-Received: by 2002:a63:1566:: with SMTP id 38-v6mr10856579pgv.383.1538758758782; Fri, 05 Oct 2018 09:59:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758758; cv=none; d=google.com; s=arc-20160816; b=HhGm2BXUWycsPDmavm+XrlOBG+PiZxLcJJ+Gia+LkNxUGvc4l/hpuOJq2WubyXnf8L 19baRfkyHEPUVSq2mWfSSGEGcug7rG88GF4SrBKS4yOVaEOwuqMOvp5BGU41WyJ4fGVt oGQ68dI39lMDUYiYX4o2RcgmpD09IRuKjImpwbTM6wB/awMNK8rdAktcf2ZontpQUEx7 pLKC9h/Zb9guzFRtQhPntgH62Qq8YYBP1HpF4SoqGqzMEZstNLc550BfBye6DwI3ZR2N L8xukKJk8YNV35bV8fjSPGlxbXux75UMTjXfxenpQC6K6aGZrfe27F3dWsiMWCMOhPG6 K51Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=O3XM1RBhY4v1WmTiSPBtIk0ka+l440+ODBKqqXu90pw=; b=fDePIumybFTuy4z28v+UKmN04CDhwuGt9QXIsSVqUvMyGQ+5RN5iILEQOouj+9IQaf 6llncxj3piL1KzjlVJ8e+KZA17/j/4buX0DyHpu/qLIcPyLRcShPKfjXrq6ucWWNYp02 zeISJub/fCrFD94EHXQqZj8xS6Yodx6J9/dkD1cIt2LUU90bXg7Xk+4JOk8IloZ6w622 4aXdMx77AOi7ZStw7AHiRiktvJoPOLsjxh2OQR8wnseOmvoXZ6wQfOWBMU0FzbCQ1Q+h Wylz+7wDMvP6psNdnhNmNQpwRGMVk9iq1NbfU6o8zY7uxLu4U4j63p4T/QqbAUlgy71I fCRg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d128-v6si10146471pfc.211.2018.10.05.09.59.18; Fri, 05 Oct 2018 09:59:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729337AbeJEX6u (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:50 -0400 Received: from mail-oi1-f194.google.com ([209.85.167.194]:42343 "EHLO mail-oi1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728042AbeJEX6t (ORCPT ); Fri, 5 Oct 2018 19:58:49 -0400 Received: by mail-oi1-f194.google.com with SMTP id w81-v6so10931405oiw.9; Fri, 05 Oct 2018 09:59:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O3XM1RBhY4v1WmTiSPBtIk0ka+l440+ODBKqqXu90pw=; b=othPUBM2bK4dCM4/9X3WqfXoKFSqMo0rr706Rl0XvrKEXTb3WNVwystvGb8EuBA+fs 3qINTlxdjhpAI9fZ32bJiGGI+NAIQOOo4xFVhFg4JtqzV68iOa98HJX0xqrDuCfLo93c cRT4m9QtS7NBIKopRwIGZ+D2BdPRCDJ79Tcs++J8S26AXspWKmJw4bSJ46W7cN4irOYD UTG5UeIOm9s0noXg3+o4O/L9hvPbu0pQ4K5k6qX3mGPgOtI/PIyWxgW0IXx93bODzXaf TNM4OHKtNaDAHCYelgyCHpioZ077RMl0lwqome82EMFYMtiJ6n5ds/jPw7x3IVroakHb QBZw== X-Gm-Message-State: ABuFfoj8uuZSKh3jkIt2VXPqbPSG1EwNkhkKABxh6Ml5lgq0+LlAbIwp 5U1qf9tXxKpYjYUk4eVVs8R4APXpiA== X-Received: by 2002:aca:490b:: with SMTP id w11-v6mr5885174oia.126.1538758754465; Fri, 05 Oct 2018 09:59:14 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:13 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Dinh Nguyen Subject: [PATCH 17/36] dt-bindings: arm: Convert Altera board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:29 -0500 Message-Id: <20181005165848.3474-18-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Altera SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Dinh Nguyen Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/altera.txt | 14 ------------- .../devicetree/bindings/arm/altera.yaml | 20 +++++++++++++++++++ 2 files changed, 20 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/altera.txt create mode 100644 Documentation/devicetree/bindings/arm/altera.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/altera.txt b/Documentation/devicetree/bindings/arm/altera.txt deleted file mode 100644 index 558735aacca8..000000000000 --- a/Documentation/devicetree/bindings/arm/altera.txt +++ /dev/null @@ -1,14 +0,0 @@ -Altera's SoCFPGA platform device tree bindings ---------------------------------------------- - -Boards with Cyclone 5 SoC: -Required root node properties: -compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - -Boards with Arria 5 SoC: -Required root node properties: -compatible = "altr,socfpga-arria5", "altr,socfpga"; - -Boards with Arria 10 SoC: -Required root node properties: -compatible = "altr,socfpga-arria10", "altr,socfpga"; diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml new file mode 100644 index 000000000000..0fc6564badc3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/altera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera's SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + compatible: + items: + - enum: + - altr,socfpga-cyclone5 + - altr,socfpga-arria5 + - altr,socfpga-arria10 + - const: altr,socfpga +... From patchwork Fri Oct 5 16:58:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148243 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689172lji; Fri, 5 Oct 2018 09:59:20 -0700 (PDT) X-Google-Smtp-Source: ACcGV60tg3TRk0RP6c+V/Z5NLaqRcKaUBoedEDDIrmadPX1PCpV57GSvBh9vBa4jasFkvdc717Jh X-Received: by 2002:a17:902:32c3:: with SMTP id z61-v6mr12401978plb.324.1538758760712; Fri, 05 Oct 2018 09:59:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758760; cv=none; d=google.com; s=arc-20160816; b=L+FIM/37XU2VQ4xdRQ/TUq56GmyXxEN7znY+DqSxXjLNX7PbDrpv5TkSNY7e+vGGIf OI9+DC2t6iztnf4H3QJHhnjakkbpebKsbKZnwHuOAaHY5zwgQymP4Mf/0J6sc50868vP hOYNwrz9gaWfXJbcBTqzBcu+5I131CKURQiejMf/e//vHleWEAMODONp/uxk41ygJ0Rc ioOvmjnG647SZnvjbeTvGLEUP6Y3uYtJDldTT1sVhofpK0pmuSf6ZeZk1WaxdKAy8wRu ARbMzutkU4agFiD20+ZxprC6KKCRJQrXOQP0sjrZP+R8Y6X+IWiRxE+Kzl2gqLno2t4d 3Yjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=KhWs5kZyc05uwI7M/owtHgSgDDP1Qej9jGMU/kV417k=; b=EgV74eCGNe8Gq5aVRgF9ENKu7NQB1lLHt2gljCj7aDYYj+TwPyJElb6eGxxTzQpbXo 7O/9vFsBHSuDUHBUtfcXAyRiaf0iGPSM2QtNkhM9AmpwDW4BWenakZiUOcm5KKqNYBzQ 2iT+FN8IjAgKA11FbWETGo6lgb1flO7+DJK/C8kCkHKv4z4n4dy6prpakZG3A6219Cmn YAXSxsKSvLyhOSamjnUCs57tfNOG3lpiPiDosaA4Hy/O2SQQRzdqnNmqCWXb1AhSgekr 5YiW2vPiDLxPBCEX9gyR8C1197seqGY3AqeNyVEqnfb+Yc80j5OVJxDMw4Ar2nBAsbyJ 6rcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d128-v6si10146471pfc.211.2018.10.05.09.59.20; Fri, 05 Oct 2018 09:59:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729371AbeJEX6w (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:52 -0400 Received: from mail-oi1-f195.google.com ([209.85.167.195]:40831 "EHLO mail-oi1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728042AbeJEX6v (ORCPT ); Fri, 5 Oct 2018 19:58:51 -0400 Received: by mail-oi1-f195.google.com with SMTP id j68-v6so10952584oib.7; Fri, 05 Oct 2018 09:59:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KhWs5kZyc05uwI7M/owtHgSgDDP1Qej9jGMU/kV417k=; b=lJtydVJ4gTMUJG7udVuaiHY0OQC8Qhyl+039xLKdg6yTyHaiwCbla51X2INX4PfXnf nfNerNLhlM5AxxGtDHliNnAgex3yL3z410XZGAiUi1T0d1GUv7Z1eshUZa2vqj88VehW DtllL5bvvUrJ3hKlHd4jqel07wrl7wzBzfc/5ML59nvWZub+ZRKSHOSxWAEpxqoWWkKF lhJ8abseARlc4FLmbZeSD9aITQYN5sQmYabO4kassQS0ceX2tB9SqVav1COtdqxHcoSo N5Abln4MbC5WOHSkAuN3mqy1hFqjfD6vFCVbuX/O2YcQ0JN/BuZ/vGtBjOXZiS2v3iwK hJTA== X-Gm-Message-State: ABuFfohNmSJRoPzKkT7AEEzbD1nsC7LVIUhqZbB13T7Sr83fZ73IeJ7m Bny/zO1XXD2U5k1SSInK/uPJUGodAg== X-Received: by 2002:aca:e24f:: with SMTP id z76-v6mr5892487oig.95.1538758755910; Fri, 05 Oct 2018 09:59:15 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:15 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Carlo Caione , Kevin Hilman Subject: [PATCH 18/36] dt-bindings: arm: Convert Amlogic board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:30 -0500 Message-Id: <20181005165848.3474-19-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Amlogic SoC bindings to DT schema format using json-schema. Cc: Carlo Caione Cc: Kevin Hilman Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/amlogic.txt | 102 ----------------- .../devicetree/bindings/arm/amlogic.yaml | 104 ++++++++++++++++++ 2 files changed, 104 insertions(+), 102 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/amlogic.txt create mode 100644 Documentation/devicetree/bindings/arm/amlogic.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt deleted file mode 100644 index 2f2d01a00c54..000000000000 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ /dev/null @@ -1,102 +0,0 @@ -Amlogic MesonX device tree bindings -------------------------------------------- - -Work in progress statement: - -Device tree files and bindings applying to Amlogic SoCs and boards are -considered "unstable". Any Amlogic device tree binding may change at -any time. Be sure to use a device tree binary and a kernel image -generated from the same source tree. - -Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a -stable binding/ABI. - ---------------------------------------------------------------- - -Boards with the Amlogic Meson6 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson6" - -Boards with the Amlogic Meson8 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8"; - -Boards with the Amlogic Meson8b SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8b"; - -Boards with the Amlogic Meson8m2 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson8m2"; - -Boards with the Amlogic Meson GXBaby SoC shall have the following properties: - Required root node property: - compatible: "amlogic,meson-gxbb"; - -Boards with the Amlogic Meson GXL S905X SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905x", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S905D SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905d", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S805X SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s805x", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXL S905W SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s905w", "amlogic,meson-gxl"; - -Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: - Required root node property: - compatible: "amlogic,s912", "amlogic,meson-gxm"; - -Boards with the Amlogic Meson AXG A113D SoC shall have the following properties: - Required root node property: - compatible: "amlogic,a113d", "amlogic,meson-axg"; - -Board compatible values (alphabetically, grouped by SoC): - - - "geniatech,atv1200" (Meson6) - - - "minix,neo-x8" (Meson8) - - - "hardkernel,odroid-c1" (Meson8b) - - "tronfy,mxq" (Meson8b) - - - "tronsmart,mxiii-plus" (Meson8m2) - - - "amlogic,p200" (Meson gxbb) - - "amlogic,p201" (Meson gxbb) - - "friendlyarm,nanopi-k2" (Meson gxbb) - - "hardkernel,odroid-c2" (Meson gxbb) - - "nexbox,a95x" (Meson gxbb or Meson gxl s905x) - - "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb) - - "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb) - - "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb) - - "wetek,hub" (Meson gxbb) - - "wetek,play2" (Meson gxbb) - - - "amlogic,p212" (Meson gxl s905x) - - "hwacom,amazetv" (Meson gxl s905x) - - "khadas,vim" (Meson gxl s905x) - - "libretech,cc" (Meson gxl s905x) - - - "amlogic,p230" (Meson gxl s905d) - - "amlogic,p231" (Meson gxl s905d) - - - "amlogic,p241" (Meson gxl s805x) - - - "amlogic,p281" (Meson gxl s905w) - - "oranth,tx3-mini" (Meson gxl s905w) - - - "amlogic,q200" (Meson gxm s912) - - "amlogic,q201" (Meson gxm s912) - - "khadas,vim2" (Meson gxm s912) - - "kingnovel,r-box-pro" (Meson gxm S912) - - "nexbox,a1" (Meson gxm s912) - - "tronsmart,vega-s96" (Meson gxm s912) - - - "amlogic,s400" (Meson axg a113d) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml new file mode 100644 index 000000000000..6168fef53aa1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/amlogic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic MesonX device tree bindings + +maintainers: + - Neil Armstrong + - Carlo Caione +description: |+ + Work in progress statement: + + Device tree files and bindings applying to Amlogic SoCs and boards are + considered "unstable". Any Amlogic device tree binding may change at + any time. Be sure to use a device tree binary and a kernel image + generated from the same source tree. + + Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a + stable binding/ABI. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - geniatech,atv1200 + - const: amlogic,meson6 + - items: + - enum: + - minix,neo-x8 + - const: amlogic,meson8 + - items: + - enum: + - tronsmart,mxiii-plus + - const: amlogic,meson8m2 + - items: + - enum: + - hardkernel,odroid-c1 + - tronfy,mxq + - const: amlogic,meson8b + - items: + - enum: + - amlogic,p200 + - amlogic,p201 + - friendlyarm,nanopi-k2 + - hardkernel,odroid-c2 + - nexbox,a95x + - wetek,hub + - wetek,play2 + - const: amlogic,meson-gxbb + - items: + - enum: + - tronsmart,vega-s95-pro + - tronsmart,vega-s95-meta + - tronsmart,vega-s95-telos + - const: tronsmart,vega-s95 + - const: amlogic,meson-gxbb + - items: + - enum: + - amlogic,p241 + - const: amlogic,s805x + - const: amlogic,meson-gxl + - items: + - enum: + - amlogic,p281 + - oranth,tx3-mini + - const: amlogic,s905w + - const: amlogic,meson-gxl + - items: + - enum: + - amlogic,p212 + - hwacom,amazetv + - khadas,vim + - libretech,cc + - nexbox,a95x + - const: amlogic,s905x + - const: amlogic,meson-gxl + - items: + - enum: + - amlogic,p230 + - amlogic,p231 + - const: amlogic,s905d + - const: amlogic,meson-gxl + - items: + - enum: + - amlogic,q200 + - amlogic,q201 + - khadas,vim2 + - kingnovel,r-box-pro + - nexbox,a1 + - tronsmart,vega-s96 + - const: amlogic,s912 + - const: amlogic,meson-gxm + - items: + - enum: + - amlogic,s400 + - const: amlogic,a113d + - const: amlogic,meson-axg + +... From patchwork Fri Oct 5 16:58:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148244 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689205lji; Fri, 5 Oct 2018 09:59:22 -0700 (PDT) X-Google-Smtp-Source: ACcGV62vJNmlQyw5IfvRP9hJlW3Qva37fNI3yIB4JJAcl4s6FDXCsnQ032QWzqXNhdTT07jXezPZ X-Received: by 2002:a62:1e83:: with SMTP id e125-v6mr12766844pfe.231.1538758762783; Fri, 05 Oct 2018 09:59:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758762; cv=none; d=google.com; s=arc-20160816; b=gSODVb16RuBWit7cM9ZR2htemrC0hKiWb31Wc2YBlf1t5FmXVjMS9D7E0vCVojuy8m J6J70BBjpYbcJN1354KfTqdVAxTPsK1sIOtMeLKGt0yLber9Kwlx182XK+UEnnoOsUnZ ibHM5SVoRKPD+ih4KWQ2rzEU9R7qvZizMxFlBC5HAp6Q47LdJfdKzlHeX/5K+fR7fX/Q Yt3zlHJOt8CUQmBd5he18NUFvvA/HXXhdo652zSeWHcOeXtKpZHTilvEir2xxXHFDBlz 27NdcLOs0Yj5M7LT5xpgcrlSRLnsATfxptGiHHwb6JkmJGT7a4DBYhJhI5PRXeJjBtzx WOpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=j25dCtrBKVBugAGpQt2CYXbqKQPtlxQHNDkhsveznr8=; b=Xc05tcTUe3GX6dpcl0smpbizzLNKjwYpIPxO43jXiZSIa3347eQE4k6XDntCYgNyNf B0jLi8bU9uZKg1dCk9lgognEEOnAgbnhtF6HLVSMsgBgY6j9x3X5LoQ7Y+1P0lbFImUG KoiTBsmb05P5Gu4sJ8vqxi1EdiBMhaUXzqJQZnkdHnTXV4rCy05Qpy/KvhNTbHtTsdYH 7RLNzVQA8IpsIGW0DIAIF9W9dMJsNmYUdx+M2ITcqULB4qQt/1gpLM4KS7qoVjntE3Of Pzanbdz23+qr9Fimlfu611m0jHqjEbO6+iEkGxUhrjqvSUGhgRhwxBOoCItBIjZ30p68 51qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e7-v6si8961967pls.366.2018.10.05.09.59.22; Fri, 05 Oct 2018 09:59:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729394AbeJEX6x (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:53 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:45377 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729340AbeJEX6w (ORCPT ); Fri, 5 Oct 2018 19:58:52 -0400 Received: by mail-oi1-f193.google.com with SMTP id e17-v6so10927883oig.12; Fri, 05 Oct 2018 09:59:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j25dCtrBKVBugAGpQt2CYXbqKQPtlxQHNDkhsveznr8=; b=UE81BCjiZjEbqGhtOZ9QSJgknGTDrIz02A81k9nSTL4kDRc3g6vIFjAIptj/adfdPO 9CLarV8qjXxF0Vvx8kUQ2Y6+zFT9jkJmK6jAbwclx7H72bo0r3M7C64f7UHC2/uLuGXa 1+H9Opl/YRur6mTZb9Sf91WS5Qyz9wiihVv4lk+ai3gMS9SPq9/UIeKET+pqWMNIMTf6 kvB+P8hI9/RByJExRxqYwxFMLsvuOwVo9UNY4Dd4mw9FO2IhQJ4Cz0vK1rqyCn9tHtuG kN7DjB+cFdT3H4MQ9qG1OndTOQ8VXqagNrlsGWj7ShwSDDrdM1nPiC4bMkjUkg4AB6Jn z9Hg== X-Gm-Message-State: ABuFfojRAoNFSzz++qymj7rQbcLm7CvDJeeG2V35DRhu7BHIT70+fTVr SocPmp31ej5oRv3Ir+2781paUAoGkw== X-Received: by 2002:aca:c6d5:: with SMTP id w204-v6mr5424577oif.319.1538758757190; Fri, 05 Oct 2018 09:59:17 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:16 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Nicolas Ferre , Alexandre Belloni Subject: [PATCH 19/36] dt-bindings: arm: Convert Atmel board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:31 -0500 Message-Id: <20181005165848.3474-20-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Atmel SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/atmel-at91.txt | 72 ---------- .../devicetree/bindings/arm/atmel-at91.yaml | 132 ++++++++++++++++++ 2 files changed, 132 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt deleted file mode 100644 index 4bf1b4da7659..000000000000 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ /dev/null @@ -1,72 +0,0 @@ -Atmel AT91 device tree bindings. -================================ - -Boards with a SoC of the Atmel AT91 or SMART family shall have the following -properties: - -Required root node properties: -compatible: must be one of: - * "atmel,at91rm9200" - - * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with - the specific SoC family or compatible: - o "atmel,at91sam9260" - o "atmel,at91sam9261" - o "atmel,at91sam9263" - o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific - SoC compatible: - - "atmel,at91sam9g15" - - "atmel,at91sam9g25" - - "atmel,at91sam9g35" - - "atmel,at91sam9x25" - - "atmel,at91sam9x35" - o "atmel,at91sam9g20" - o "atmel,at91sam9g45" - o "atmel,at91sam9n12" - o "atmel,at91sam9rl" - o "atmel,at91sam9xe" - * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific - SoC family: - o "atmel,sama5d2" shall be extended with the specific SoC compatible: - - "atmel,sama5d27" - o "atmel,sama5d3" shall be extended with the specific SoC compatible: - - "atmel,sama5d31" - - "atmel,sama5d33" - - "atmel,sama5d34" - - "atmel,sama5d35" - - "atmel,sama5d36" - o "atmel,sama5d4" shall be extended with the specific SoC compatible: - - "atmel,sama5d41" - - "atmel,sama5d42" - - "atmel,sama5d43" - - "atmel,sama5d44" - - * "atmel,samv7" for MCUs using a Cortex-M7, shall be extended with the specific - SoC family: - o "atmel,sams70" shall be extended with the specific MCU compatible: - - "atmel,sams70j19" - - "atmel,sams70j20" - - "atmel,sams70j21" - - "atmel,sams70n19" - - "atmel,sams70n20" - - "atmel,sams70n21" - - "atmel,sams70q19" - - "atmel,sams70q20" - - "atmel,sams70q21" - o "atmel,samv70" shall be extended with the specific MCU compatible: - - "atmel,samv70j19" - - "atmel,samv70j20" - - "atmel,samv70n19" - - "atmel,samv70n20" - - "atmel,samv70q19" - - "atmel,samv70q20" - o "atmel,samv71" shall be extended with the specific MCU compatible: - - "atmel,samv71j19" - - "atmel,samv71j20" - - "atmel,samv71j21" - - "atmel,samv71n19" - - "atmel,samv71n20" - - "atmel,samv71n21" - - "atmel,samv71q19" - - "atmel,samv71q20" - - "atmel,samv71q21" diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml new file mode 100644 index 000000000000..f788315b94fa --- /dev/null +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/atmel-at91.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91 device tree bindings. + +maintainers: + - Alexandre Belloni + - Jean-Christophe PLAGNIOL-VILLARD +description: | + Boards with a SoC of the Atmel AT91 or SMART family shall have the following + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: atmel,at91rm9200 + - items: + - enum: + - olimex,sam9-l9260 + - enum: + - atmel,at91sam9260 + - atmel,at91sam9261 + - atmel,at91sam9263 + - atmel,at91sam9g20 + - atmel,at91sam9g45 + - atmel,at91sam9n12 + - atmel,at91sam9rl + - atmel,at91sam9xe + - const: atmel,at91sam9 + + - items: + - enum: + - atmel,at91sam9g15 + - atmel,at91sam9g25 + - atmel,at91sam9g35 + - atmel,at91sam9x25 + - atmel,at91sam9x35 + - const: atmel,at91sam9x5 + - const: atmel,at91sam9 + + - items: + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + + - description: Nattis v2 board with Natte v2 power board + items: + - const: axentia,nattis-2 + - const: axentia,natte-2 + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - description: TSE-850 v3 board + items: + - const: axentia,tse850v3 + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - const: axentia,linea + - const: atmel,sama5d31 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sama5d31 + - atmel,sama5d33 + - atmel,sama5d34 + - atmel,sama5d35 + - atmel,sama5d36 + - const: atmel,sama5d3 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sama5d41 + - atmel,sama5d42 + - atmel,sama5d43 + - atmel,sama5d44 + - const: atmel,sama5d4 + - const: atmel,sama5 + + - items: + - enum: + - atmel,sams70j19 + - atmel,sams70j20 + - atmel,sams70j21 + - atmel,sams70n19 + - atmel,sams70n20 + - atmel,sams70n21 + - atmel,sams70q19 + - atmel,sams70q20 + - atmel,sams70q21 + - const: atmel,sams70 + - const: atmel,samv7 + + - items: + - enum: + - atmel,samv70j19 + - atmel,samv70j20 + - atmel,samv70n19 + - atmel,samv70n20 + - atmel,samv70q19 + - atmel,samv70q20 + - const: atmel,samv70 + - const: atmel,samv7 + + - items: + - enum: + - atmel,samv71j19 + - atmel,samv71j20 + - atmel,samv71j21 + - atmel,samv71n19 + - atmel,samv71n20 + - atmel,samv71n21 + - atmel,samv71q19 + - atmel,samv71q20 + - atmel,samv71q21 + - const: atmel,samv71 + - const: atmel,samv7 + +... From patchwork Fri Oct 5 16:58:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148245 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689231lji; Fri, 5 Oct 2018 09:59:24 -0700 (PDT) X-Google-Smtp-Source: ACcGV603UeSmxPvU3p52XD2sCjtArkuq9dNLt1A1GnrfUxYxjtWtdOrfw67bM2TQGl9udffIwYQu X-Received: by 2002:a62:99cd:: with SMTP id t74-v6mr12627210pfk.179.1538758764163; Fri, 05 Oct 2018 09:59:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758764; cv=none; d=google.com; s=arc-20160816; b=pG07NCLXnNZCT7cFzSg9Z8yL/jVoidjC15gyzujwnM+yZQC25op+eA1qlG5yenQ4iX 6HymSVGtWCrr5Bs6w99XUrvtrGTJnciPPiULD2+DPVzJW26Cqwx98w/Q7/gYzCuCisKz /SIzvtL3EJTFIoZ6s5QK+LxO8D1CsRhL8bf6bQ/bda3aWoeePkqZ2Zl48yVPiMT6fLfn efaeY2oH0QXLl9/BOLSPicekKLBIqwG5q9xgjPBjYVX8UO0lxw9nxn+E+eActhTKnRDm ihQkA3cOZaaXtAntfZlUIXcruNRHTRdSxCmGjdIAqiiI7agy+1UexZIrR1cf9/ASNH8X EFsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=5MLkB6QDD+qMQPlNXzKBuD+GOXCxeFHPrO581g6RS5g=; b=dBriUW+NEYmUz28sK3dtl7mkLHP2y0CDSGGIMZsKAuIHiurock9Ggwbpw1EiyTK7x+ +8z6zxaltSEGkITmD5eT8ZCYV18WiY2VyeXnRqlnB3Z+2S9zro5ypa1Q5r6FEpMW8lqg 7xABMSPZGH4fOjVyg/WOqRPmHyyUB5ACkkAYGDXjdFTn3AqpJ9ZSTKZWuEd8FFk9U9Uh 6BG1NCoL1QXnWLug+mbFbO2uKhqL4xAmo66xNrpjcRnSon/mA+IEFuhq+/J/wgUhM9By lOLm7RUCGxqsVKvTYL0hsgDJqkW9tAU67uwNBoDCG1A5/t/gUb08yQmfhaSzwV6jkvff y5Og== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e7-v6si8961967pls.366.2018.10.05.09.59.23; Fri, 05 Oct 2018 09:59:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729422AbeJEX64 (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:56 -0400 Received: from mail-oi1-f195.google.com ([209.85.167.195]:36877 "EHLO mail-oi1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729395AbeJEX6y (ORCPT ); Fri, 5 Oct 2018 19:58:54 -0400 Received: by mail-oi1-f195.google.com with SMTP id e17-v6so10956810oib.4; Fri, 05 Oct 2018 09:59:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5MLkB6QDD+qMQPlNXzKBuD+GOXCxeFHPrO581g6RS5g=; b=hg/8RSNTUjptVBqLxEYZSeGTQguZtWJXIaIV5sfzsDsthZjXwie73Cyrp0hKw7LgWq 6uzatBm55Hvx00NRX7h11q/8M9LZtnNhvZGlRzAXWisxhuSRMfYEljPEkHZTbreT+KV7 L3cU+PGh09BUkAs0joKSOhDaZDrmjt6Fu8jhEEJJoyQKJ5Zy9FjwmzTlDX9ycRhAG+mn 68x2RN35pcR48UHnoAi91zp5gBKrjUXPYr4r3nPxU2g6OuGzSEJvTS5FMtcFQfPpqbU4 TymVbAicoko2kmgd+zQg2IQy2VcP+37cU0cRREp8ijPagByfPx6esMHuFBpclHmWCtgX r5gA== X-Gm-Message-State: ABuFfoglJq5j5/NBcu9GQi4N8gv0FmwCFbJA9JpX64wF24s5GgqksX/z zGZRoZpbk7nS0GrTNjHpDWbAz0b35Q== X-Received: by 2002:aca:f4c2:: with SMTP id s185-v6mr5857040oih.245.1538758759126; Fri, 05 Oct 2018 09:59:19 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:18 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson Subject: [PATCH 20/36] dt-bindings: arm: Convert Calxeda board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:32 -0500 Message-Id: <20181005165848.3474-21-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Calxeda SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/calxeda.txt | 15 ------------- .../devicetree/bindings/arm/calxeda.yaml | 22 +++++++++++++++++++ 2 files changed, 22 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt create mode 100644 Documentation/devicetree/bindings/arm/calxeda.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt deleted file mode 100644 index 25fcf96795ca..000000000000 --- a/Documentation/devicetree/bindings/arm/calxeda.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the -following properties. - -Required root node properties: - - compatible = "calxeda,highbank"; - - -Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following -properties. - -Required root node properties: - - compatible = "calxeda,ecx-2000"; diff --git a/Documentation/devicetree/bindings/arm/calxeda.yaml b/Documentation/devicetree/bindings/arm/calxeda.yaml new file mode 100644 index 000000000000..bc5c69926c6e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Platforms Device Tree Bindings + +maintainers: + - Rob Herring +description: |+ + Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC + or Cortex-A15 based ECX-2000 SOCs + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - calxeda,highbank + - calxeda,ecx-2000 From patchwork Fri Oct 5 16:58:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148246 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689277lji; Fri, 5 Oct 2018 09:59:26 -0700 (PDT) X-Google-Smtp-Source: ACcGV60YcS99b/3TLtG71QrHrUteKN7bCrTxEk2ydCeWXgbJxmrAD9ABFWSbGctmhxL6rbu7nAqe X-Received: by 2002:a62:ca4d:: with SMTP id n74-v6mr8301957pfg.10.1538758766672; Fri, 05 Oct 2018 09:59:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758766; cv=none; d=google.com; s=arc-20160816; b=mVxXbkOSlk+WHC/EJrS2ZoG9hV5dslmV8hasZz912L2FvoIjXTRf0FFkp/r3roVu1Q 7K4GVBqTGLRygXswPeTb17x2F1Qn7I3fPWydM5Hg3p16Z2YXNI1xso8DsEPQgEKMU1fm O00aRIsIEn5jisH3Ni8uLXLCJ8uQqVFw5SBfqq28n4Qutpi0I4fJFcb0nvxc21ftkRbl zPVOU1kKkbyyVWmXScjFqA+KiWP51MB4sVG/pyUPDh9bxE+2UpJZiTJqaq8Ht0aD321I nmOUsON+Iix39/MtNzyf5ngQIkmiCg1rAa3pQLNJzrv2pk9dQJoN7vfDaChvLNBz53Ii G6nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=oAFZaqX+8vbPo3z2NAIlPqO9Xe1omxZyYJn0IxY6DLE=; b=s4I1zYpCkA987lcr5RyUCBw446G05SThmAnUYTz3MmYsCjdgGYMkDgM4/Eb0ALlIIL oBEhXA6VaN7Egkd6460U9NBqPgiIElinjnhiZS+5uFved/tPU1FGUyDObvgu4CDn1shU cGHGiEcfl1uLiCTA1z5SgE0RPg3BQ35U+LNBw0UDsuaQ3AanwyOJBifVtP12omENBLDY ZESulsWUhVb29Ipqwj5TEKFDptBW4OBHVEyxHu6/2Q8Peh6MUMW2RvAlNyS1hyE6NUq9 ZerNNt+kiOxVk4IvR1g1lIeWZ9H0rFwSefOnISF5rRVHFJNX+rOLjrj+aNznTVe1gh7W t/tw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m15-v6si8882706pga.114.2018.10.05.09.59.26; Fri, 05 Oct 2018 09:59:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729449AbeJEX66 (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:58 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:40838 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729395AbeJEX65 (ORCPT ); Fri, 5 Oct 2018 19:58:57 -0400 Received: by mail-oi1-f193.google.com with SMTP id j68-v6so10952842oib.7; Fri, 05 Oct 2018 09:59:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oAFZaqX+8vbPo3z2NAIlPqO9Xe1omxZyYJn0IxY6DLE=; b=sx15/SXvTUe1uGiCH6bcAUxErp74Wgp/BrUjpxnkcezlU0ur00lRc2njkMR7gOckOt oowWmn090pWFSqrDqxYYG2Ris/Eeo/E8c9UNIUGzzkNaOK8vE8QB41zJOJRi8FyyIftQ opJLAEQMowSZtA5hRmrTduATYt59s7m0adsAgRy+JbOCXiiQPyzEM4qNtHELNz4eo8oY fEs0xYR9Qqlb+C5VhbSEpzEQqJEqYutyYcvtHDD5eiUusq3dBQEkAYSzUb6Ff8yzyjSn 0JSkKGhTkmlkKXfmetCwnY1Jh1H/iBag537PiTUFWRAGorCXAwzGEOLQErnJ8zt5eU/3 U4hA== X-Gm-Message-State: ABuFfohagFr2Qxlsc0nnKIpqIHfdYtsvMHTiLBNYS01jzPe2QPvWxPp9 +ZSp4tZm614NqruYfcbeocguv6SzBA== X-Received: by 2002:aca:d785:: with SMTP id o127-v6mr5659408oig.33.1538758761826; Fri, 05 Oct 2018 09:59:21 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:21 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Shawn Guo Subject: [PATCH 22/36] dt-bindings: arm: Convert FSL board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:34 -0500 Message-Id: <20181005165848.3474-23-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Freescale SoC bindings to DT schema format using json-schema. Cc: Shawn Guo Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/armadeus.txt | 6 - Documentation/devicetree/bindings/arm/bhf.txt | 6 - .../bindings/arm/compulab-boards.txt | 25 --- Documentation/devicetree/bindings/arm/fsl.txt | 185 ------------------ .../devicetree/bindings/arm/fsl.yaml | 166 ++++++++++++++++ .../devicetree/bindings/arm/i2se.txt | 22 --- .../devicetree/bindings/arm/olimex.txt | 10 - .../devicetree/bindings/arm/technologic.txt | 23 --- 8 files changed, 166 insertions(+), 277 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/armadeus.txt delete mode 100644 Documentation/devicetree/bindings/arm/bhf.txt delete mode 100644 Documentation/devicetree/bindings/arm/compulab-boards.txt delete mode 100644 Documentation/devicetree/bindings/arm/fsl.txt create mode 100644 Documentation/devicetree/bindings/arm/fsl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/i2se.txt delete mode 100644 Documentation/devicetree/bindings/arm/olimex.txt delete mode 100644 Documentation/devicetree/bindings/arm/technologic.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt deleted file mode 100644 index 9821283ff516..000000000000 --- a/Documentation/devicetree/bindings/arm/armadeus.txt +++ /dev/null @@ -1,6 +0,0 @@ -Armadeus i.MX Platforms Device Tree Bindings ------------------------------------------------ - -APF51: i.MX51 based module. -Required root node properties: - - compatible = "armadeus,imx51-apf51", "fsl,imx51"; diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt deleted file mode 100644 index 886b503caf9c..000000000000 --- a/Documentation/devicetree/bindings/arm/bhf.txt +++ /dev/null @@ -1,6 +0,0 @@ -Beckhoff Automation Platforms Device Tree Bindings --------------------------------------------------- - -CX9020 Embedded PC -Required root node properties: - - compatible = "bhf,cx9020", "fsl,imx53"; diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt deleted file mode 100644 index 42a10285af9c..000000000000 --- a/Documentation/devicetree/bindings/arm/compulab-boards.txt +++ /dev/null @@ -1,25 +0,0 @@ -CompuLab SB-SOM is a multi-module baseboard capable of carrying: - - CM-T43 - - CM-T54 - - CM-QS600 - - CL-SOM-AM57x - - CL-SOM-iMX7 -modules with minor modifications to the SB-SOM assembly. - -Required root node properties: - - compatible = should be "compulab,sb-som" - -Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on -Freescale i.MX7 ARM Cortex-A7 System-on-Chip. - -Required root node properties: - - compatible = "compulab,cl-som-imx7", "fsl,imx7d"; - -Compulab SBC-iMX7 is a single board computer based on the -Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with -the CL-SOM-iMX7 System-on-Module providing most of the functions, -and SB-SOM-iMX7 carrier board providing additional peripheral -functions and connectors. - -Required root node properties: - - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d"; diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt deleted file mode 100644 index 1e775aaa5c5b..000000000000 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ /dev/null @@ -1,185 +0,0 @@ -Freescale i.MX Platforms Device Tree Bindings ------------------------------------------------ - -i.MX23 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx23-evk", "fsl,imx23"; - -i.MX25 Product Development Kit -Required root node properties: - - compatible = "fsl,imx25-pdk", "fsl,imx25"; - -i.MX27 Product Development Kit -Required root node properties: - - compatible = "fsl,imx27-pdk", "fsl,imx27"; - -i.MX28 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx28-evk", "fsl,imx28"; - -i.MX51 Babbage Board -Required root node properties: - - compatible = "fsl,imx51-babbage", "fsl,imx51"; - -i.MX53 Automotive Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-ard", "fsl,imx53"; - -i.MX53 Evaluation Kit -Required root node properties: - - compatible = "fsl,imx53-evk", "fsl,imx53"; - -i.MX53 Quick Start Board -Required root node properties: - - compatible = "fsl,imx53-qsb", "fsl,imx53"; - -i.MX53 Smart Mobile Reference Design Board -Required root node properties: - - compatible = "fsl,imx53-smd", "fsl,imx53"; - -i.MX6 Quad Armadillo2 Board -Required root node properties: - - compatible = "fsl,imx6q-arm2", "fsl,imx6q"; - -i.MX6 Quad SABRE Lite Board -Required root node properties: - - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; - -i.MX6 Quad SABRE Smart Device Board -Required root node properties: - - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; - -i.MX6 Quad SABRE Automotive Board -Required root node properties: - - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; - -i.MX6SLL EVK board -Required root node properties: - - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; - -Generic i.MX boards -------------------- - -No iomux setup is done for these boards, so this must have been configured -by the bootloader for boards to work with the generic bindings. - -i.MX27 generic board -Required root node properties: - - compatible = "fsl,imx27"; - -i.MX51 generic board -Required root node properties: - - compatible = "fsl,imx51"; - -i.MX53 generic board -Required root node properties: - - compatible = "fsl,imx53"; - -i.MX6q generic board -Required root node properties: - - compatible = "fsl,imx6q"; - -Freescale Vybrid Platform Device Tree Bindings ----------------------------------------------- - -For the Vybrid SoC familiy all variants with DDR controller are supported, -which is the VF5xx and VF6xx series. Out of historical reasons, in most -places the kernel uses vf610 to refer to the whole familiy. -The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 -core support. - -Required root node compatible property (one of them): - - compatible = "fsl,vf500"; - - compatible = "fsl,vf510"; - - compatible = "fsl,vf600"; - - compatible = "fsl,vf610"; - - compatible = "fsl,vf610m4"; - -Freescale LS1021A Platform Device Tree Bindings ------------------------------------------------- - -Required root node compatible properties: - - compatible = "fsl,ls1021a"; - -Freescale ARMv8 based Layerscape SoC family Device Tree Bindings ----------------------------------------------------------------- - -LS1012A SoC -Required root node properties: - - compatible = "fsl,ls1012a"; - -LS1012A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; - -LS1012A ARMv8 based FRDM Board -Required root node properties: - - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -LS1012A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -LS1043A SoC -Required root node properties: - - compatible = "fsl,ls1043a"; - -LS1043A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; - -LS1043A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - -LS1046A SoC -Required root node properties: - - compatible = "fsl,ls1046a"; - -LS1046A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - -LS1046A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - -LS1088A SoC -Required root node properties: - - compatible = "fsl,ls1088a"; - -LS1088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - -LS1088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; - -LS2080A SoC -Required root node properties: - - compatible = "fsl,ls2080a"; - -LS2080A ARMv8 based Simulator model -Required root node properties: - - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - -LS2080A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - -LS2080A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - -LS2088A SoC -Required root node properties: - - compatible = "fsl,ls2088a"; - -LS2088A ARMv8 based QDS Board -Required root node properties: - - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - -LS2088A ARMv8 based RDB Board -Required root node properties: - - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml new file mode 100644 index 000000000000..5241fa92e3d1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Platforms Device Tree Bindings + +maintainers: + - Shawn Guo + - Shaohui Xie + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: i.MX23 based Boards + items: + - enum: + - fsl,imx23-evk + - olimex,imx23-olinuxino + - const: fsl,imx23 + + - description: i.MX25 Product Development Kit + items: + - enum: + - fsl,imx25-pdk + - const: fsl,imx25 + + - description: i.MX27 Product Development Kit + items: + - enum: + - fsl,imx27-pdk + - const: fsl,imx27 + + - description: i.MX28 based Boards + items: + - enum: + - fsl,imx28-evk + - i2se,duckbill + - i2se,duckbill-2 + - technologic,imx28-ts4600 + - const: fsl,imx28 + - items: + - enum: + - i2se,duckbill-2-485 + - i2se,duckbill-2-enocean + - i2se,duckbill-2-spi + - const: i2se,duckbill-2 + - const: fsl,imx28 + + - description: i.MX51 Babbage Board + items: + - enum: + - armadeus,imx51-apf51 + - fsl,imx51-babbage + - technologic,imx51-ts4800 + - const: fsl,imx51 + + - description: i.MX53 Boards + items: + - enum: + - bhf,cx9020 + - fsl,imx53-ard + - fsl,imx53-evk + - fsl,imx53-qsb + - fsl,imx53-smd + - const: fsl,imx53 + + - description: i.MX6Q based Boards + items: + - enum: + - fsl,imx6q-arm2 + - fsl,imx6q-sabrelite + - fsl,imx6q-sabresd + - fsl,imx6q-sabreauto + - technologic,imx6q-ts4900 + - technologic,imx6q-ts7970 + - const: fsl,imx6q + + - description: i.MX6DL based Boards + items: + - enum: + - technologic,imx6dl-ts4900 + - technologic,imx6dl-ts7970 + - const: fsl,imx6dl + + - description: i.MX6SLL based Boards + items: + - enum: + - fsl,imx6sll-evk + - const: fsl,imx6sll + + - description: + Compulab SBC-iMX7 is a single board computer based on the + Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with + the CL-SOM-iMX7 System-on-Module providing most of the functions, + and SB-SOM-iMX7 carrier board providing additional peripheral + functions and connectors. + items: + - const: compulab,sbc-imx7 + - const: compulab,cl-som-imx7 + - const: fsl,imx7d + + - description: + Freescale Vybrid Platform Device Tree Bindings + + For the Vybrid SoC familiy all variants with DDR controller are supported, + which is the VF5xx and VF6xx series. Out of historical reasons, in most + places the kernel uses vf610 to refer to the whole familiy. + The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 + core support. + items: + - enum: + - fsl,vf500 + - fsl,vf510 + - fsl,vf600 + - fsl,vf610 + - fsl,vf610m4 + + - description: LS1021A based Boards + items: + - enum: + - fsl,ls1012a-rdb + - fsl,ls1012a-frdm + - fsl,ls1012a-qds + - const: fsl,ls1021a + + - description: LS1043A based Boards + items: + - enum: + - fsl,ls1043a-rdb + - fsl,ls1043a-qds + - const: fsl,ls1043a + + - description: LS1046A based Boards + items: + - enum: + - fsl,ls1046a-qds + - fsl,ls1046a-rdb + - const: fsl,ls1046a + + - description: LS1088A based Boards + items: + - enum: + - fsl,ls1088a-qds + - fsl,ls1088a-rdb + - const: fsl,ls1088a + + - description: LS2080A based Boards + items: + - enum: + - fsl,ls2080a-simu + - fsl,ls2080a-qds + - fsl,ls2080a-rdb + - const: fsl,ls2080a + + - description: LS2088A based Boards + items: + - enum: + - fsl,ls2088a-qds + - fsl,ls2088a-rdb + - const: fsl,ls2088a + +... diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt deleted file mode 100644 index dbd54a3aa07d..000000000000 --- a/Documentation/devicetree/bindings/arm/i2se.txt +++ /dev/null @@ -1,22 +0,0 @@ -I2SE Device Tree Bindings -------------------------- - -Duckbill Board -Required root node properties: - - compatible = "i2se,duckbill", "fsl,imx28"; - -Duckbill 2 Board -Required root node properties: - - compatible = "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 485 Board -Required root node properties: - - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 EnOcean Board -Required root node properties: - - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - -Duckbill 2 SPI Board -Required root node properties: - - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28"; diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt deleted file mode 100644 index d726aeca56be..000000000000 --- a/Documentation/devicetree/bindings/arm/olimex.txt +++ /dev/null @@ -1,10 +0,0 @@ -Olimex Device Tree Bindings ---------------------------- - -SAM9-L9260 Board -Required root node properties: - - compatible = "olimex,sam9-l9260", "atmel,at91sam9260"; - -i.MX23 Olinuxino Low Cost Board -Required root node properties: - - compatible = "olimex,imx23-olinuxino", "fsl,imx23"; diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt deleted file mode 100644 index f1cedc00dcab..000000000000 --- a/Documentation/devicetree/bindings/arm/technologic.txt +++ /dev/null @@ -1,23 +0,0 @@ -Technologic Systems Platforms Device Tree Bindings --------------------------------------------------- - -TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx28-ts4600", "fsl,imx28" - -TS-4800 board -Required root node properties: - - compatible = "technologic,imx51-ts4800", "fsl,imx51"; - -TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts4900", "fsl,imx6q" - -TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. -It can be mounted on a carrier board providing additional peripheral connectors. -Required root node properties: - - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl" - - compatible = "technologic,imx6q-ts7970", "fsl,imx6q" From patchwork Fri Oct 5 16:58:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148247 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689322lji; Fri, 5 Oct 2018 09:59:28 -0700 (PDT) X-Google-Smtp-Source: ACcGV62X+CRMoo9FKMMFlXC+ASskwHzvToxNGksTI1JT/dWqYYIR6xwSQRRgFaUAlPXWa6yrUNEV X-Received: by 2002:a17:902:9b89:: with SMTP id y9-v6mr12518072plp.239.1538758768722; Fri, 05 Oct 2018 09:59:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758768; cv=none; d=google.com; s=arc-20160816; b=WC9tSbRp6/sZBJ25WwB2mmf6kmA1qgg0CP4/EtWfgujBjOkjX95lEzVW0NQR4t7fzO sZjbkDsDp7TxommtltJTyYRGqvRRV/rMx0wuHhsFVCcrQENvObCkGW6I/7aE1Z6MEC70 19qzf4LuCSy+koLWhB0VFE5DSldCuaris8eYowFYbMNyTw2SCiJM9PUHu7drxs90JdJV fcqOxeJ8kwZzb/mhzINQuLZ5m+trgPQxqcYeL5QEMmzsbPzbx7vw3CEEyC/Zb1u9HV8C w6rYPzRagIgT15FtXjUfgifIUks5ec9yX9i5yfQ34AWNyuDMUVSg03pQntpksfqKia/q 474Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=wn48U+ico/dYcmpUsy+6xSiWO0JyQssECtz/dnTzc3k=; b=D0S8IC9KZ0EG3WwmwkBeBJem0AKQmwWNShkyEzeEo9ehDE5196F7TpEIASFaDXBHx+ GEehKZ5ik/tqH4xMURuK0foW3OqhG41s/nuc5Ge3ns33nWmdMxXfOnqTpSmk1pm2+LHa 3txa3+WfqY+c8rcR8ZRW2p+8HJCl3gAj5qgqsxF0CqCdZY94S8kc3GFktELgSgpR21KG N2ayqclHSAr6A0uVhzn4NV9AYlMa0ik7ySMJ4HbYFCR26R527TZpB34/0Djhmm7SwP7U MJOzQ1FJAs6WlZzQVKboba5AE+PfTPdPzhauBTHBupLhr1Tqr7HIzCWsHtbZInovyP9y Og2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bc11-v6si8865655plb.120.2018.10.05.09.59.28; Fri, 05 Oct 2018 09:59:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729471AbeJEX67 (ORCPT + 32 others); Fri, 5 Oct 2018 19:58:59 -0400 Received: from mail-oi1-f194.google.com ([209.85.167.194]:37919 "EHLO mail-oi1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729391AbeJEX66 (ORCPT ); Fri, 5 Oct 2018 19:58:58 -0400 Received: by mail-oi1-f194.google.com with SMTP id u197-v6so10959708oif.5; Fri, 05 Oct 2018 09:59:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wn48U+ico/dYcmpUsy+6xSiWO0JyQssECtz/dnTzc3k=; b=AtkIUxUfva1o2fEPzSa/yr2E1gxzlbdh+DAwf2gXUkWiTIqgF5ZZZyEt1sPRg/U0UV q+IwvrFddQfhXed6ouR8ZHiXYDInPzT8JW9RmsIwloZzkBhgGo0pFIn9oW7dyj5saP+/ uvDylWYFa/Hm2FP/TPZnJ1EYwWCP7gCUgTH6W+ELDLBtL2T+qrsaHXGCwCelGuyYg7i/ Gu4GfnDMdYPDEKCAJKCP9U5f5HiJW0F3EE1Mby3WUf5r1oKgCYDLh1vygtJdgn5OAKoU /N0efJmUgbGd84DhDIoy0v8LqHnNqDNRN3fBUZ36nq/Her3Qjk0yQtvpeRzAiI5sVbrp fWFw== X-Gm-Message-State: ABuFfoj+UrOoOJcBZibUcQQ/cPl5NEQQ3Qv/NDmL2L2TDMy+MX0UGrJt NG0dzc4OfNJgJjy+wD9woONqO2w/Fw== X-Received: by 2002:a54:4085:: with SMTP id i5-v6mr6046550oii.302.1538758763169; Fri, 05 Oct 2018 09:59:23 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:22 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Matthias Brugger , linux-mediatek@lists.infradead.org Subject: [PATCH 23/36] dt-bindings: arm: Convert MediaTek board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:35 -0500 Message-Id: <20181005165848.3474-24-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert MediaTek SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Matthias Brugger Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/mediatek.txt | 79 ----------------- .../devicetree/bindings/arm/mediatek.yaml | 85 +++++++++++++++++++ 2 files changed, 85 insertions(+), 79 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt deleted file mode 100644 index 8f260e5cfd16..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ /dev/null @@ -1,79 +0,0 @@ -MediaTek SoC based Platforms Device Tree Bindings - -Boards with a MediaTek SoC shall have the following property: - -Required root node property: - -compatible: Must contain one of - "mediatek,mt2701" - "mediatek,mt2712" - "mediatek,mt6580" - "mediatek,mt6589" - "mediatek,mt6592" - "mediatek,mt6755" - "mediatek,mt6765" - "mediatek,mt6795" - "mediatek,mt6797" - "mediatek,mt7622" - "mediatek,mt7623" which is referred to MT7623N SoC - "mediatek,mt7623a" - "mediatek,mt8127" - "mediatek,mt8135" - "mediatek,mt8173" - - -Supported boards: - -- Evaluation board for MT2701: - Required root node properties: - - compatible = "mediatek,mt2701-evb", "mediatek,mt2701"; -- Evaluation board for MT2712: - Required root node properties: - - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; -- Evaluation board for MT6580: - Required root node properties: - - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580"; -- bq Aquaris5 smart phone: - Required root node properties: - - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; -- Evaluation board for MT6592: - Required root node properties: - - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; -- Evaluation phone for MT6755(Helio P10): - Required root node properties: - - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; -- Evaluation board for MT6765(Helio P22): - Required root node properties: - - compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; -- Evaluation board for MT6795(Helio X10): - Required root node properties: - - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; -- Evaluation board for MT6797(Helio X20): - Required root node properties: - - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; -- Mediatek X20 Development Board: - Required root node properties: - - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; -- Reference board variant 1 for MT7622: - Required root node properties: - - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; -- Reference board for MT7623a with eMMC: - Required root node properties: - - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; -- Reference board for MT7623a with NAND: - Required root node properties: - - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; -- Reference board for MT7623n with eMMC: - Required root node properties: - - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; -- Bananapi BPI-R2 board: - - compatible = "bananapi,bpi-r2", "mediatek,mt7623"; -- MTK mt8127 tablet moose EVB: - Required root node properties: - - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; -- MTK mt8135 tablet EVB: - Required root node properties: - - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; -- MTK mt8173 tablet EVB: - Required root node properties: - - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml new file mode 100644 index 000000000000..861af7c66ac5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/mediatek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC based Platforms Device Tree Bindings + +maintainers: + - Sean Wang + - Matthias Brugger +description: | + Boards with a MediaTek SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-evb + - const: mediatek,mt2701 + + - items: + - enum: + - mediatek,mt2712-evb + - const: mediatek,mt2712 + - items: + - enum: + - mediatek,mt6580-evbp1 + - const: mediatek,mt6580 + - items: + - enum: + - mundoreader,bq-aquaris5 + - const: mediatek,mt6589 + - items: + - enum: + - mediatek,mt6592-evb + - const: mediatek,mt6592 + - items: + - enum: + - mediatek,mt6755-evb + - const: mediatek,mt6755 + - items: + - enum: + - mediatek,mt6765-evb + - const: mediatek,mt6765 + - items: + - enum: + - mediatek,mt6795-evb + - const: mediatek,mt6795 + - items: + - enum: + - archermind,mt6797-x20-dev + - mediatek,mt6797-evb + - const: mediatek,mt6797 + - items: + - enum: + - mediatek,mt7622-rfb1 + - const: mediatek,mt7622 + - items: + - enum: + - mediatek,mt7623a-rfb-emmc + - mediatek,mt7623a-rfb-nand + - mediatek,mt7623n-rfb-emmc + - bananapi,bpi-r2 + - const: mediatek,mt7623 + description: Also referred to as MT7623N SoC + + - items: + - const: mediatek,mt7623a + - items: + - enum: + - mediatek,mt8127-moose + - const: mediatek,mt8127 + - items: + - enum: + - mediatek,mt8135-evbp1 + - const: mediatek,mt8135 + - items: + - enum: + - mediatek,mt8173-evb + - const: mediatek,mt8173 +... From patchwork Fri Oct 5 16:58:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148248 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689352lji; Fri, 5 Oct 2018 09:59:30 -0700 (PDT) X-Google-Smtp-Source: ACcGV628hOC0Zdb5SFHqpai0aKPI0sORDAmm5OxtmK6BGhmhkxLiJ/Q71jAvz9g8FeYJFKTkSSaJ X-Received: by 2002:a62:1b45:: with SMTP id b66-v6mr12827098pfb.94.1538758769858; Fri, 05 Oct 2018 09:59:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758769; cv=none; d=google.com; s=arc-20160816; b=xel8KvgNY9HWaw9EPtVMUOs8jF7iBE+oozqTwO7cP+G94iBfuUDzyjXjRO4WB5Km1l ThdoNRtFGAYy4T3vq4G0LktwkVdbzYyS/kQRT++NGiZPO2uP/D52k08Z6AXJ7DoQsJ80 pcQIXq3MmIeVjr0wuYTkBeKrqVcJlQHAt5KpGqUVPZGs895s3lVoBXTyTuty7gMsW8wK WFrNC7XeDd2THoqGho/UhrJ2kWjH79VdRONTAvJ6aSieyHV39Zb9Qa0ai0y0KV2MM6Kv UJPZfX+dpxI9ndUoBMwiMcJTUke7VWASnI1Y+lF9NsT0ICqNUorX4nS0OhQ+anHc6+Vg rbzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=y7aoVKyFfwtD/XX+mmuwaVWhSjIowWCZ6eMMY+0377c=; b=OObOsSERWnOtE+r8NtSxlBXzImy1nY7Wz5MRdYK/2Gfcow6zJXIRNBxjQXfrSIRhQQ 3UT41FBD9GbU5SoZmMxLkQbIhMLSDde5PGlVBXoj2NgS3atJvtJ8xRn0mLRShns/nnYN NeJeVS5BwUyNkapuVi7K5mr0RlEFV0xKFS/ndqLPD7GlePJ2nYqajWPbbOsZ0kwwfx9p 3iVmKBZHcy4zuHc3Bs/oeX6dpqdlLgb0zzjJ4qcSBVCg4t/hBitW2oXiIeMmWvcfYwMa KsgWwmPRan8mM37sIcgVCdOzv1RdsIesVBwtMx8Fen0qMcRoCOX/LQgfCtRCRrdnQemx JqnA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r29-v6si501185pff.262.2018.10.05.09.59.29; Fri, 05 Oct 2018 09:59:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729488AbeJEX7A (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:00 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:40339 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729453AbeJEX67 (ORCPT ); Fri, 5 Oct 2018 19:58:59 -0400 Received: by mail-ot1-f68.google.com with SMTP id w67so13338959ota.7; Fri, 05 Oct 2018 09:59:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y7aoVKyFfwtD/XX+mmuwaVWhSjIowWCZ6eMMY+0377c=; b=lXkVmhfrqA3PgNHSu+mW4aiHJYtURzAI0T5KqajLQJt7+ZhuVTwP3DmtE8kKAH9q+m QJwJPg2qfyY1FnhcFmICtKRlabkdUKoyymbiveJ81+oo4Imo+NHVpAZNFIedew05+xNE bMVQLRb1iHZdJBij1HphZCVQ+QbFQCR/e4KcEQ7T53w5sjf0fbz4jYvJP3MHcLPPZtpF ddB64CvV2LrpPkHrNy2WMRgchfw85XKKCNuwCQbOWx6DtS9Nu4/8S6Zkmcbua2Za1rjb Ivl2CeuFR/RHR2kGf+cjYA+XZcYZ+eLx9kAR76mOBmP2k3aJY3vF/wNFh8Vt82rCpb/i hVJg== X-Gm-Message-State: ABuFfoh8DB/vc+CjIYh0G6D0k8sNAXbN/xt0NMZCdyghfmQXOjH5MBiz x6g32lZRe23TcqX8MDVYLX93TLlVJw== X-Received: by 2002:a9d:2af:: with SMTP id 44-v6mr6580039otl.244.1538758764568; Fri, 05 Oct 2018 09:59:24 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:23 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson Subject: [PATCH 24/36] dt-bindings: arm: Convert TI nspire board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:36 -0500 Message-Id: <20181005165848.3474-25-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert TI NSpire SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/nspire.txt | 14 ----------- .../devicetree/bindings/arm/ti/nspire.yaml | 24 +++++++++++++++++++ 2 files changed, 24 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/nspire.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/nspire.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt deleted file mode 100644 index 4d08518bd176..000000000000 --- a/Documentation/devicetree/bindings/arm/nspire.txt +++ /dev/null @@ -1,14 +0,0 @@ -TI-NSPIRE calculators - -Required properties: -- compatible: Compatible property value should contain "ti,nspire". - CX models should have "ti,nspire-cx" - Touchpad models should have "ti,nspire-tp" - Clickpad models should have "ti,nspire-clp" - -Example: - -/ { - model = "TI-NSPIRE CX"; - compatible = "ti,nspire-cx"; - ... diff --git a/Documentation/devicetree/bindings/arm/ti/nspire.yaml b/Documentation/devicetree/bindings/arm/ti/nspire.yaml new file mode 100644 index 000000000000..882f79f95942 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/nspire.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/nspire.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI-NSPIRE calculators + +maintainers: + - Daniel Tang + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + # CX models + - ti,nspire-cx + # Touchpad models + - ti,nspire-tp + # Clickpad models + - ti,nspire-clp +... From patchwork Fri Oct 5 16:58:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148249 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689375lji; Fri, 5 Oct 2018 09:59:31 -0700 (PDT) X-Google-Smtp-Source: ACcGV63pJ24N80dvQEY39spfnUKGdMRGrVzKugFaE2z6IhebxZE8GXr2YHGXh0ngN0JcHp1krWzZ X-Received: by 2002:a63:2f81:: with SMTP id v123-v6mr10575396pgv.223.1538758771576; Fri, 05 Oct 2018 09:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758771; cv=none; d=google.com; s=arc-20160816; b=QM/8UmH0WXIOwBUI4K8cprn8n+5w8VaeOkZffF2zwgOmsst8eCTFrUomkPkhQi+3tT Iwx8k2s2soHsOA5CB5Xe8xBnTpwfFgY7MIDFOcOI7FvAIkNxJUsa8WSOTdJRWt/7BRwB VkRgzxN/pSj8wAMck3pkU/drSXhSgrUuDPygTjVFQmZNJrKYJRibwHcAC6yCBPOMODV9 xXx7yp3yWfz8/HQPYUUfSPAxykY8FnkNhfMc8wOs1lkcqQm2QgPLqVKRstBvkaUVUlLB 64WODsWiuxy8jT8kWNg83JC5aZr3IPumqXByez80Zol+qhQ89reeSGvJt/YO8m9z2Yyq bA7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=LOcP7SKttVPj8DIgwnpgktISVP3hKyMV9PP4Ts7Q0SY=; b=JVN5N+u0Qr8p2tVZXOB6AJ5ZfwTIm2Maq5mqx22JqWJV7CtIatpm7mLdlDgP/nRBHM czdX5hiBCm2SwqcFLcxNCNDjIc/czgxINPxOlSxGW+r+ah808CavZMxEpRavOlKxdoox uEIYJn7ZXRy8GM9g03YAj5YaOjvbUhx4KkBOOA0fV8NK3fnALy6qIy91/LwrXxN1SR14 PYnzuA+/nqV/jnsKaVZJUCugz20nblwXsxauPzK6OqANM4Q9/RTNgWvGvDPtZDAes7mx GHLnvcatqP6QTS28cqET6wuQj0F2jx9X2q0gBKi6NinaMDyEFb2spZFJ1KtN6pTktQ+F 1ztw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v9-v6si10861318pfj.167.2018.10.05.09.59.31; Fri, 05 Oct 2018 09:59:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729508AbeJEX7C (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:02 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:36975 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729278AbeJEX7A (ORCPT ); Fri, 5 Oct 2018 19:59:00 -0400 Received: by mail-ot1-f67.google.com with SMTP id o13-v6so13350876otl.4; Fri, 05 Oct 2018 09:59:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LOcP7SKttVPj8DIgwnpgktISVP3hKyMV9PP4Ts7Q0SY=; b=H89WgkuaO1ALxX8QjhfVHsa9vFy3A/YTlVQlloqvH8WnTmdoc+tfmPEfaUtcvNBFq0 Sgs+/Ix0UwGn0N3lU+ss1Ue6va3dm/VIPH2Z3byYzMKLbxjKvPvNOC6D5RSeiZvsdZAS GWXNjdx0fQy7y3ZaooQEIEd00M2UJRcMlN6eU8hsirShw1dy2julTBGEUpwadIo1UaK5 jG0DIieIMgMiKrJuVTGsbbmlnri31gFdWlhMTTvKSr13SSgkE7lBPupmqx1/v0C4ThkM +LdvCYXwNI/rUzhd3mPSFD7NeGFqrX5ODWYeKFMGdmudjmcvj5iNoy7Oi6J4uo6gucOL 2EmQ== X-Gm-Message-State: ABuFfoj42jmAK6u+pC8lsAMT9Lu7jloniSroxvtfi0E0KJb30US/+sq6 EKc7yzZxZ3qvaHebwu0IC9ZVKKxNEA== X-Received: by 2002:a9d:3cd0:: with SMTP id t16mr7184592otf.158.1538758765884; Fri, 05 Oct 2018 09:59:25 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:25 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Neil Armstrong , linux-oxnas@groups.io Subject: [PATCH 25/36] dt-bindings: arm: Convert Oxford Semi board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:37 -0500 Message-Id: <20181005165848.3474-26-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Oxford Semi SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Neil Armstrong Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-oxnas@groups.io Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/oxnas.txt | 14 ----------- .../devicetree/bindings/arm/oxnas.yaml | 25 +++++++++++++++++++ 2 files changed, 25 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt create mode 100644 Documentation/devicetree/bindings/arm/oxnas.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt deleted file mode 100644 index ac64e60f99f1..000000000000 --- a/Documentation/devicetree/bindings/arm/oxnas.txt +++ /dev/null @@ -1,14 +0,0 @@ -Oxford Semiconductor OXNAS SoCs Family device tree bindings -------------------------------------------- - -Boards with the OX810SE SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox810se" - -Boards with the OX820 SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox820" - -Board compatible values: - - "wd,mbwe" (OX810SE) - - "cloudengines,pogoplugv3" (OX820) diff --git a/Documentation/devicetree/bindings/arm/oxnas.yaml b/Documentation/devicetree/bindings/arm/oxnas.yaml new file mode 100644 index 000000000000..c847a5707417 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/oxnas.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/oxnas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Oxford Semiconductor OXNAS SoCs Family device tree bindings + +maintainers: + - Neil Armstrong + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - wd,mbwe + - const: oxsemi,ox810se + + - items: + - enum: + - cloudengines,pogoplugv3 + - const: oxsemi,ox820 From patchwork Fri Oct 5 16:58:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148250 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689385lji; Fri, 5 Oct 2018 09:59:32 -0700 (PDT) X-Google-Smtp-Source: ACcGV60HokC00t767xVzeNZJCt2WPPYT7t2Vj9ySMBt+Boiw/j06QZK4ZK4lOKEJPIyIilAadpCz X-Received: by 2002:a63:de46:: with SMTP id y6-v6mr10934307pgi.198.1538758772136; Fri, 05 Oct 2018 09:59:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758772; cv=none; d=google.com; s=arc-20160816; b=FSuYQsuqc74LVz4c3g+BJ9kdrVlrOKw7N5trQLaAoS/nam18AGYfkS3Rhf9JAXiusC 1RlBw9yXPEwRPUgO4MUVMQzapisCCId3v4DD2MLnAMx8uODx97mVjOqUuH+CUo7LyRi6 1pO07i1t5jRTrS3z1AHmNU0fXV2v2x/URFSjRLl9yOGji2IxncDACfrRl6rcVB3gjguI FOkGTJ2yjCl6htCT+7awW8U7yozvnQvcqm28c5lHvwRNi6JXwAoNuss/W81eXpHQ+a7d inqEw0w7MrkYKCEJ2xsz16P0DcTucRG+jeVRxlAgdeoW4vOVLhxrLhy747GhmrsEmmE6 5ZYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=6vZiAwZ/FaAxsaPwcmZJkmnX3wWUiSpbkZC8KjnTZio=; b=TtKcFvaHhNLFaoYmez3DBSXked8ZpeXu6Gz64eKlAJRH8c/var3T5mo+kyoZ+XNcFN qvuA6qa+z/WGwGD+s4yt4Fj/ysh2xbbWxtoqPO1km5ZvOpyobBU7MR6qpbFo7g7aGHjD o7hM1WGfj4FUXvuitRnYknUjOAL/7fXguQOHg9BBqtrlIuWq6kq4G6RdqVv/G9A5yGEM S1Uj5PeBH+gB+DWhloys4P+1Thq9Daljc0b/IKrz7k2vApAhUyi38KrLAfprh7dAcUAr +8HBv6mubVel53fhCqmKMJD40Vf2qrVxq57cD+tddcaPWValKehT1KgKC0OlzsQYF2gJ QxrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v9-v6si10861318pfj.167.2018.10.05.09.59.31; Fri, 05 Oct 2018 09:59:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729524AbeJEX7D (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:03 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:42955 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729490AbeJEX7C (ORCPT ); Fri, 5 Oct 2018 19:59:02 -0400 Received: by mail-ot1-f68.google.com with SMTP id h26-v6so13361309otl.9; Fri, 05 Oct 2018 09:59:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6vZiAwZ/FaAxsaPwcmZJkmnX3wWUiSpbkZC8KjnTZio=; b=GhlHFUgH4XUbu68NseO+PXLf8YlNEwr0OmmC6QTKKRs9eQI9k/8T5mP32R35zacmda Q9qyeb2r++dBYOl6YX/TiQjTnxNOs85BN4dGXo2OFdEmuy6eSt21XeQEdVSEW98ZSwN8 NHjipDXxG8si50HW9BzQYRfvIkQL9Kun1MYZX/eXrk6EWG9cYjmj0SvPImixdy+1vcLq EKmTyIyt19dcdT5j4sBeOsOJ5CWgSISOQ2UNlBUROjCYp2a6dMY6NnufClZu2mshV08Y BAeqJb36CjH3NuLNEvSqD9ZwnTeb7FwBDmzGyHcpeQHnU83bB/ovrGxf5FaaWCeb6BUN ff1Q== X-Gm-Message-State: ABuFfogY5BV/dzrLDjk+I4xkTHmsuKDThhducdwulQlzWUfxfDzCWf3H 3S5q2PP17J3bD9XAuch8mM0bqtSxRQ== X-Received: by 2002:a9d:2992:: with SMTP id n18mr663229otb.54.1538758767174; Fri, 05 Oct 2018 09:59:27 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:26 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Andy Gross , David Brown Subject: [PATCH 26/36] dt-bindings: arm: Convert QCom board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:38 -0500 Message-Id: <20181005165848.3474-27-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert QCom SoC bindings to DT schema format using json-schema. Cc: Andy Gross Cc: David Brown Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/qcom.txt | 57 -------- .../devicetree/bindings/arm/qcom.yaml | 125 ++++++++++++++++++ 2 files changed, 125 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/qcom.txt create mode 100644 Documentation/devicetree/bindings/arm/qcom.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt deleted file mode 100644 index ee532e705d6c..000000000000 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ /dev/null @@ -1,57 +0,0 @@ -QCOM device tree bindings -------------------------- - -Some qcom based bootloaders identify the dtb blob based on a set of -device properties like SoC and platform and revisions of those components. -To support this scheme, we encode this information into the board compatible -string. - -Each board must specify a top-level board compatible string with the following -format: - - compatible = "qcom,[-][-]-[/][-]" - -The 'SoC' and 'board' elements are required. All other elements are optional. - -The 'SoC' element must be one of the following strings: - - apq8016 - apq8074 - apq8084 - apq8096 - msm8916 - msm8974 - msm8992 - msm8994 - msm8996 - mdm9615 - ipq8074 - sdm845 - -The 'board' element must be one of the following strings: - - cdp - liquid - dragonboard - mtp - sbc - hk01 - -The 'soc_version' and 'board_version' elements take the form of v. -where the minor number may be omitted when it's zero, i.e. v1.0 is the same -as v1. If all versions of the 'board_version' elements match, then a -wildcard '*' should be used, e.g. 'v*'. - -The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. - -Examples: - - "qcom,msm8916-v1-cdp-pm8916-v2.1" - -A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version -2.1. - - "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" - -A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in -foundry 2. diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml new file mode 100644 index 000000000000..d8fcd8deed5c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM device tree bindings + +maintainers: + - Stephen Boyd + +description: | + Some qcom based bootloaders identify the dtb blob based on a set of + device properties like SoC and platform and revisions of those components. + To support this scheme, we encode this information into the board compatible + string. + + Each board must specify a top-level board compatible string with the following + format: + + compatible = "qcom,[-][-]-[/][-]" + + The 'SoC' and 'board' elements are required. All other elements are optional. + + The 'SoC' element must be one of the following strings: + + apq8016 + apq8074 + apq8084 + apq8096 + msm8916 + msm8974 + msm8992 + msm8994 + msm8996 + mdm9615 + ipq8074 + sdm845 + + The 'board' element must be one of the following strings: + + cdp + liquid + dragonboard + mtp + sbc + hk01 + + The 'soc_version' and 'board_version' elements take the form of v. + where the minor number may be omitted when it's zero, i.e. v1.0 is the same + as v1. If all versions of the 'board_version' elements match, then a + wildcard '*' should be used, e.g. 'v*'. + + The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9. + + Examples: + + "qcom,msm8916-v1-cdp-pm8916-v2.1" + + A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version + 2.1. + + "qcom,apq8074-v2.0-2-dragonboard/1-v0.1" + + A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in + foundry 2. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,apq8016-sbc + - const: qcom,apq8016 + + - items: + - enum: + - qcom,apq8064-cm-qs600 + - qcom,apq8064-ifc6410 + - const: qcom,apq8064 + + - items: + - enum: + - qcom,apq8074-dragonboard + - const: qcom,apq8074 + + - items: + - enum: + - qcom,apq8060-dragonboard + - qcom,msm8660-surf + - const: qcom,msm8660 + + - items: + - enum: + - qcom,apq8084-mtp + - qcom,apq8084-sbc + - const: qcom,apq8084 + + - items: + - enum: + - qcom,msm8960-cdp + - const: qcom,msm8960 + + - items: + - const: qcom,msm8916-mtp/1 + - const: qcom,msm8916-mtp + - const: qcom,msm8916 + + - items: + - const: qcom,msm8996-mtp + + - items: + - const: qcom,ipq4019 + + - items: + - enum: + - qcom,ipq8064-ap148 + - const: qcom,ipq8064 + + - items: + - enum: + - qcom,ipq8074-hk01 + - const: qcom,ipq8074 + +... From patchwork Fri Oct 5 16:58:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148260 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp690523lji; Fri, 5 Oct 2018 10:00:34 -0700 (PDT) X-Google-Smtp-Source: ACcGV61halmb5iTT0eXkR/NMC/+/V8IzF6spiwxogiWKK1kOj4mjs+SVRkWlXEcA+/rsfoskyIam X-Received: by 2002:a63:82c6:: with SMTP id w189-v6mr10952480pgd.211.1538758834785; Fri, 05 Oct 2018 10:00:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758834; cv=none; d=google.com; s=arc-20160816; b=MMrYa4TBpvkr6CldQHS7XlhLCKUAlR4KTpK0CoY44VYbYOisqfQvynWcJAIQZyh9yH eK2vPoKgdWp6psZ/2WPWQohcGVrsXkss51LnHZ3/h/vI/eJkIaK6sK8loGJpQHvG6lW+ B3T04GzFOcdZH+PUYUpc/EW0s0RiKOnyNEmb5YZuVx65epUQLasCjy1uIKZ+VA6DjTiz DqzBn0y2NJP0glpB6XgTSegsv7LvEyIafqV7TdQk3wpuOucfMpx50I6DUORuc1rzMpEo 4tgJe5Hj0sC9bxgDinqwO4U1nGHsYMOS3KVpJDRsuKEJzTkdN/zPfppbtp29wzLNJxFr 7UHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=dAy5qx+6J1oOwRzhSrnPqWe3tAf3nbvPmD7N4uqhtmQ=; b=QGG23xfGdWDqb2S4RKKFCfxfkhPqXQbqfegqVNmPfTq8elf7bnmePoATYkZntDu7/W fB8v/Z6hUdF0gYuXSJuhaAvzJqwwzGU0OxdnYSANSz992Ga2XFYapr641up925k0PJgc ilKGkNnaT7RbLTmfjQCdiWV1iyim7ksxH8JF9yCgEe6GJnpij8sPD4fTSQH7QNdc9zER uEzYq54loha2qF4PV/QbqRMP4f9XId183yZMKz4lxcVvO89kBI9Oy+ViGOj7f/qMopeN ahezzzNINiFOW5m7FUz9hwBOx5S0upVHUfFxFelPoJqtTiMuCAZQZpvKv70dN2KZBdzn qkDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b12-v6si8860280pgj.87.2018.10.05.10.00.34; Fri, 05 Oct 2018 10:00:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729712AbeJFAAH (ORCPT + 32 others); Fri, 5 Oct 2018 20:00:07 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:38956 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728147AbeJEX7D (ORCPT ); Fri, 5 Oct 2018 19:59:03 -0400 Received: by mail-ot1-f68.google.com with SMTP id c20-v6so13347085otl.6; Fri, 05 Oct 2018 09:59:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dAy5qx+6J1oOwRzhSrnPqWe3tAf3nbvPmD7N4uqhtmQ=; b=YsKOCJE7caFxwCNjtpSfkmGlNQZMjhZd/jl5UN8zqDqlPJRrBTCLrxKG3RWG63Jdkr c+R2zHAkpKNOrOJsc6mm2QvfD+gHf3qK5cjPgLC9JiiM1kv1IrLdkRzzmHUVtgfe3h/B FImCe4/0KXAtgQwT5WdYcoggxz9PR+Bwwwr9BiE6ouuW/SB0uXsoMJUfIWPSQ2rax0X6 uriKTIIKAnDtFE+q6IFR4txkpnF/ZGgMLc6aeJAP4faK4/4ZkbymAONltuA8ki+kv/uG U7+sPWjQPDyQqzFlXkd33eYZclGlMdcnPNz/Dc1jTqttBebckg24YWNPj9iCD2MDkulI c7Yw== X-Gm-Message-State: ABuFfoiIP14IItlucnaf2l3b6GakQc3iXu2EbtntjLi5fr5bfnC74wVd XrA1h5nEetv7NK8exm3qW0VwhmD8mw== X-Received: by 2002:a9d:41f6:: with SMTP id v51mr4448257oti.368.1538758768482; Fri, 05 Oct 2018 09:59:28 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:27 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH 27/36] dt-bindings: arm: Convert Realtek board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:39 -0500 Message-Id: <20181005165848.3474-28-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Realtek SoC bindings to DT schema format using json-schema. Cc: "Andreas Färber" Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/realtek.txt | 22 ---------------- .../devicetree/bindings/arm/realtek.yaml | 25 +++++++++++++++++++ 2 files changed, 25 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/realtek.txt create mode 100644 Documentation/devicetree/bindings/arm/realtek.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/realtek.txt b/Documentation/devicetree/bindings/arm/realtek.txt deleted file mode 100644 index 95839e19ae92..000000000000 --- a/Documentation/devicetree/bindings/arm/realtek.txt +++ /dev/null @@ -1,22 +0,0 @@ -Realtek platforms device tree bindings --------------------------------------- - - -RTD1295 SoC -=========== - -Required root node properties: - - - compatible : must contain "realtek,rtd1295" - - -Root node property compatible must contain, depending on board: - - - MeLE V9: "mele,v9" - - ProBox2 AVA: "probox2,ava" - - Zidoo X9S: "zidoo,x9s" - - -Example: - - compatible = "zidoo,x9s", "realtek,rtd1295"; diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml new file mode 100644 index 000000000000..9e3bb3249c77 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/realtek.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek platforms device tree bindings + +maintainers: + - Andreas Färber + +description: |+ + RTD1295 SoC + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - mele,v9 + - probox2,ava + - zidoo,x9s + - const: realtek,rtd1295 +... From patchwork Fri Oct 5 16:58:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148254 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689470lji; Fri, 5 Oct 2018 09:59:37 -0700 (PDT) X-Google-Smtp-Source: ACcGV61kCfyHEI/Ep7ZglQOZvtYGOb92wxUgXD3JcQ2pwfNPD+IVZRNkaEm5tGcjxPrP1nqkC6NG X-Received: by 2002:a63:e818:: with SMTP id s24-v6mr10598763pgh.90.1538758777447; Fri, 05 Oct 2018 09:59:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758777; cv=none; d=google.com; s=arc-20160816; b=TarFRgaZvDQh7TEX5ljh1D2ijbYUP7WIt1xSra1NK10AFuhGI2243d0A2NuweQJyD1 veHh0HhidUUPmcuoprJf1ODEDquEWshAyiCeUyXukqHnbNlmn68/U835fvRLakqQsP2B zKyCIuBxLbb03NPhDDaIY4og/TJUWChey7cpEXcqzvJuLZS+SlZFYwaBKv7WyOpVN9yw 0r0vmj/jDntP5Mwq9rSpuNvzmvznWDTEa6IWIVfDK0CH2fC46Es0hfvhHdTea434Fn9W Q8cQ0jML/UYO4QKKi0zrHJvIZPLrSgg8RzrRgZbhSFHDVs+NmyMgzJr6eJpEsl/6rbHE q9VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=LOORFh/urY2tpLal8351MZgFcixXf0zNiASmMRG8pbs=; b=Hnl+gEBu7+o/AQo+/JgnBqVgAT/Mgg7uy4MvUUyCpgwzxeY9ka0GMoP6wxXW9D8KTH E/lA47h71C2eY7k+EGUESuWriwkdB9IN8Rpu2SWEIPMxEZKI+Z23lquTirjvIaZnwYmr Ee8lhoP8XTG4OpvKuRA/eJ3REn7HWRDaPV5ydRF+3OC+ca3MrbzxRRfxLBkRRe4g9Pv1 BdrzkjpP6kYFpSelgvgwExuxh4Clh99BnqCABh2R1vwOPvu3bKjOQGKx4PVGBb4Vth6Q El4rEpcOl7wp/NcbA8qhYIVJdHzha8yvlLU5Yy/4LG6/F4fBi9Wq64me9//WfNeoLT73 tq9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f62-v6si9756983pfb.218.2018.10.05.09.59.36; Fri, 05 Oct 2018 09:59:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729580AbeJEX7I (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:08 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:34087 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729525AbeJEX7H (ORCPT ); Fri, 5 Oct 2018 19:59:07 -0400 Received: by mail-ot1-f67.google.com with SMTP id i12-v6so13401498otl.1; Fri, 05 Oct 2018 09:59:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LOORFh/urY2tpLal8351MZgFcixXf0zNiASmMRG8pbs=; b=aO+hPOVThkAQIsD+y0HyFf5XHnpMAnsGwkvXwmgJU1aSZ3I2WmfZnl29L1i5dbzqta e9F5U9ZF9t0BCY9xJWmQkzveY7DSsKSCGdqX8WcqEYRK1NteEI00QJxYQzBx6IPl5H01 S/V8IU7e3Ffg+wjMhUZQlY+wrotquFGFD4r+uxuD8AGOTNnEnwzuIH6kwswtfzT1Tc0S AYXAF6NOQkO3ZGzPsDvvFDl934mk85UmqdhR8lI5x9DbFWsnfFvuovEedNFKzhcMLrZS HxGT5ZFyIQpaFFwrcVTGhi8NHt15RHgSdCWV0rLodyHD9/F0PJM0tk2v+uywMb/5eW5l bljA== X-Gm-Message-State: ABuFfojUJwfEY7lEl6LBw0ruuv8VP5YKBW7rVX7ABjDTQHyIfFMxtukj UJQzvAe5lnIDDSnsURvwWtdwGKKmaQ== X-Received: by 2002:a9d:308d:: with SMTP id s13mr7264781otc.359.1538758771196; Fri, 05 Oct 2018 09:59:31 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:30 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org Subject: [PATCH 29/36] dt-bindings: arm: Convert Renesas board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:41 -0500 Message-Id: <20181005165848.3474-30-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Renesas SoC bindings to DT schema format using json-schema. Cc: Simon Horman Cc: Magnus Damm Cc: Mark Rutland Cc: linux-renesas-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/shmobile.txt | 143 ------------ .../devicetree/bindings/arm/shmobile.yaml | 205 ++++++++++++++++++ 2 files changed, 205 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt create mode 100644 Documentation/devicetree/bindings/arm/shmobile.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt deleted file mode 100644 index 619b765e5bee..000000000000 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ /dev/null @@ -1,143 +0,0 @@ -Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings --------------------------------------------------------------------- - -SoCs: - - - Emma Mobile EV2 - compatible = "renesas,emev2" - - RZ/A1H (R7S72100) - compatible = "renesas,r7s72100" - - SH-Mobile AG5 (R8A73A00/SH73A0) - compatible = "renesas,sh73a0" - - R-Mobile APE6 (R8A73A40) - compatible = "renesas,r8a73a4" - - R-Mobile A1 (R8A77400) - compatible = "renesas,r8a7740" - - RZ/G1H (R8A77420) - compatible = "renesas,r8a7742" - - RZ/G1M (R8A77430) - compatible = "renesas,r8a7743" - - RZ/G1N (R8A77440) - compatible = "renesas,r8a7744" - - RZ/G1E (R8A77450) - compatible = "renesas,r8a7745" - - RZ/G1C (R8A77470) - compatible = "renesas,r8a77470" - - R-Car M1A (R8A77781) - compatible = "renesas,r8a7778" - - R-Car H1 (R8A77790) - compatible = "renesas,r8a7779" - - R-Car H2 (R8A77900) - compatible = "renesas,r8a7790" - - R-Car M2-W (R8A77910) - compatible = "renesas,r8a7791" - - R-Car V2H (R8A77920) - compatible = "renesas,r8a7792" - - R-Car M2-N (R8A77930) - compatible = "renesas,r8a7793" - - R-Car E2 (R8A77940) - compatible = "renesas,r8a7794" - - R-Car H3 (R8A77950) - compatible = "renesas,r8a7795" - - R-Car M3-W (R8A77960) - compatible = "renesas,r8a7796" - - R-Car M3-N (R8A77965) - compatible = "renesas,r8a77965" - - R-Car V3M (R8A77970) - compatible = "renesas,r8a77970" - - R-Car V3H (R8A77980) - compatible = "renesas,r8a77980" - - R-Car E3 (R8A77990) - compatible = "renesas,r8a77990" - - R-Car D3 (R8A77995) - compatible = "renesas,r8a77995" - - RZ/N1D (R9A06G032) - compatible = "renesas,r9a06g032" - -Boards: - - - Alt (RTP0RC7794SEB00010S) - compatible = "renesas,alt", "renesas,r8a7794" - - APE6-EVM - compatible = "renesas,ape6evm", "renesas,r8a73a4" - - Atmark Techno Armadillo-800 EVA - compatible = "renesas,armadillo800eva", "renesas,r8a7740" - - Blanche (RTP0RC7792SEB00010S) - compatible = "renesas,blanche", "renesas,r8a7792" - - BOCK-W - compatible = "renesas,bockw", "renesas,r8a7778" - - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) - compatible = "renesas,condor", "renesas,r8a77980" - - Draak (RTP0RC77995SEB0010S) - compatible = "renesas,draak", "renesas,r8a77995" - - Eagle (RTP0RC77970SEB0010S) - compatible = "renesas,eagle", "renesas,r8a77970" - - Ebisu (RTP0RC77990SEB0010S) - compatible = "renesas,ebisu", "renesas,r8a77990" - - Genmai (RTK772100BC00000BR) - compatible = "renesas,genmai", "renesas,r7s72100" - - GR-Peach (X28A-M01-E/F) - compatible = "renesas,gr-peach", "renesas,r7s72100" - - Gose (RTP0RC7793SEB00010S) - compatible = "renesas,gose", "renesas,r8a7793" - - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) - H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - compatible = "renesas,h3ulcb", "renesas,r8a7795" - - Henninger - compatible = "renesas,henninger", "renesas,r8a7791" - - iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) - compatible = "iwave,g23s", "renesas,r8a77470" - - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) - compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) - compatible = "iwave,g22m", "renesas,r8a7745" - - iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) - compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743" - - iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) - compatible = "iwave,g20m", "renesas,r8a7743" - - Kingfisher (SBEV-RCAR-KF-M03) - compatible = "shimafuji,kingfisher" - - Koelsch (RTP0RC7791SEB00010S) - compatible = "renesas,koelsch", "renesas,r8a7791" - - Kyoto Microcomputer Co. KZM-A9-Dual - compatible = "renesas,kzm9d", "renesas,emev2" - - Kyoto Microcomputer Co. KZM-A9-GT - compatible = "renesas,kzm9g", "renesas,sh73a0" - - Lager (RTP0RC7790SEB00010S) - compatible = "renesas,lager", "renesas,r8a7790" - - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) - compatible = "renesas,m3ulcb", "renesas,r8a7796" - - Marzen (R0P7779A00010S) - compatible = "renesas,marzen", "renesas,r8a7779" - - Porter (M2-LCDP) - compatible = "renesas,porter", "renesas,r8a7791" - - RSKRZA1 (YR0K77210C000BE) - compatible = "renesas,rskrza1", "renesas,r7s72100" - - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - compatible = "renesas,rzn1d400-db", "renesas,r9a06g032" - - Salvator-X (RTP0RC7795SIPB0010S) - compatible = "renesas,salvator-x", "renesas,r8a7795" - - Salvator-X (RTP0RC7796SIPB0011S) - compatible = "renesas,salvator-x", "renesas,r8a7796" - - Salvator-X (RTP0RC7796SIPB0011S (M3-N)) - compatible = "renesas,salvator-x", "renesas,r8a77965" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7795" - - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) - compatible = "renesas,salvator-xs", "renesas,r8a7796" - - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) - compatible = "renesas,salvator-xs", "renesas,r8a77965" - - SILK (RTP0RC7794LCB00011S) - compatible = "renesas,silk", "renesas,r8a7794" - - SK-RZG1E (YR8A77450S000BE) - compatible = "renesas,sk-rzg1e", "renesas,r8a7745" - - SK-RZG1M (YR8A77430S000BE) - compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) - compatible = "renesas,stout", "renesas,r8a7790" - - V3HSK (Y-ASK-RCAR-V3H-WS10) - compatible = "renesas,v3hsk", "renesas,r8a77980" - - V3MSK (Y-ASK-RCAR-V3M-WS10) - compatible = "renesas,v3msk", "renesas,r8a77970" - - Wheat (RTP0RC7792ASKB0000JE) - compatible = "renesas,wheat", "renesas,r8a7792" diff --git a/Documentation/devicetree/bindings/arm/shmobile.yaml b/Documentation/devicetree/bindings/arm/shmobile.yaml new file mode 100644 index 000000000000..31009e7fb0ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/shmobile.yaml @@ -0,0 +1,205 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/shmobile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings + +maintainers: + - Geert Uytterhoeven + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Emma Mobile EV2 + items: + - enum: + - renesas,kzm9d # Kyoto Microcomputer Co. KZM-A9-Dual + - const: renesas,emev2 + + - description: RZ/A1H (R7S72100) + items: + - enum: + - renesas,genmai # Genmai (RTK772100BC00000BR) + - renesas,gr-peach # GR-Peach (X28A-M01-E/F) + - renesas,rskrza1 # RSKRZA1 (YR0K77210C000BE) + - const: renesas,r7s72100 + + - description: SH-Mobile AG5 (R8A73A00/SH73A0) + items: + - enum: + - renesas,kzm9g # Kyoto Microcomputer Co. KZM-A9-GT + - const: renesas,sh73a0 + + - description: R-Mobile APE6 (R8A73A40) + items: + - enum: + - renesas,ape6evm + - const: renesas,r8a73a4 + + - description: R-Mobile A1 (R8A77400) + items: + - enum: + - renesas,armadillo800eva # Atmark Techno Armadillo-800 EVA + - const: renesas,r8a7740 + + - description: RZ/G1H (R8A77420) + items: + - const: renesas,r8a7742 + + - description: RZ/G1M (R8A77430) + items: + - enum: + # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven) + - iwave,g20d + - const: iwave,g20m + - const: renesas,r8a7743 + + - items: + - enum: + # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven) + - iwave,g20m + - const: renesas,r8a7743 + + - description: RZ/G1N (R8A77440) + items: + - enum: + - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE) + - const: renesas,r8a7744 + + - description: RZ/G1E (R8A77450) + items: + - enum: + - iwave,g22m # iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM) + - renesas,sk-rzg1e # SK-RZG1E (YR8A77450S000BE) + - const: renesas,r8a7745 + - items: + # iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D) + - const: iwave,g22d + - const: iwave,g22m + - const: renesas,r8a7745 + + - description: RZ/G1C (R8A77470) + items: + - enum: + - iwave,g23s #iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S) + - const: renesas,r8a77470 + + - description: R-Car M1A (R8A77781) + items: + - enum: + - renesas,bockw + - const: renesas,r8a7778 + + - description: R-Car H1 (R8A77790) + items: + - enum: + - renesas,marzen # Marzen (R0P7779A00010S) + - renesas,stout # Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) + - const: renesas,r8a7779 + + - description: R-Car H2 (R8A77900) + items: + - enum: + - renesas,lager # Lager (RTP0RC7790SEB00010S) + - const: renesas,r8a7790 + + - description: R-Car M2-W (R8A77910) + items: + - enum: + - renesas,henninger + - renesas,koelsch # Koelsch (RTP0RC7791SEB00010S) + - renesas,porter # Porter (M2-LCDP) + - const: renesas,r8a7791 + + - description: R-Car V2H (R8A77920) + items: + - enum: + - renesas,blanche # Blanche (RTP0RC7792SEB00010S) + - renesas,wheat # Wheat (RTP0RC7792ASKB0000JE) + - const: renesas,r8a7792 + + - description: R-Car M2-N (R8A77930) + items: + - enum: + - renesas,gose # Gose (RTP0RC7793SEB00010S) + - const: renesas,r8a7793 + + - description: R-Car E2 (R8A77940) + items: + - enum: + - renesas,alt # Alt (RTP0RC7794SEB00010S) + - renesas,silk # SILK (RTP0RC7794LCB00011S) + - const: renesas,r8a7794 + + - description: R-Car H3 (R8A77950) + items: + - enum: + # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) + # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) + - renesas,h3ulcb + - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) + - const: renesas,r8a7795 + + - description: R-Car M3-W (R8A77960) + items: + - enum: + - renesas,m3ulcb # M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0)) + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) + - const: renesas,r8a7796 + + - description: Kingfisher (SBEV-RCAR-KF-M03) + items: + - const: shimafuji,kingfisher + - enum: + - renesas,h3ulcb + - renesas,m3ulcb + - enum: + - renesas,r8a7795 + - renesas,r8a7796 + + - description: R-Car M3-N (R8A77965) + items: + - enum: + - renesas,salvator-x # Salvator-X (RTP0RC7796SIPB0011S (M3-N)) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) + - const: renesas,r8a77965 + + - description: R-Car V3M (R8A77970) + items: + - enum: + - renesas,eagle # Eagle (RTP0RC77970SEB0010S) + - renesas,v3msk # V3MSK (Y-ASK-RCAR-V3M-WS10) + - const: renesas,r8a77970 + + - description: R-Car V3H (R8A77980) + items: + - enum: + - renesas,condor # Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) + - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) + - const: renesas,r8a77980 + + - description: R-Car E3 (R8A77990) + items: + - enum: + - renesas,ebisu # Ebisu (RTP0RC77990SEB0010S) + - const: renesas,r8a77990 + + - description: R-Car D3 (R8A77995) + items: + - enum: + - renesas,draak # Draak (RTP0RC77995SEB0010S) + - const: renesas,r8a77995 + + - description: RZ/N1D (R9A06G032) + items: + - enum: + - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) + - const: renesas,r9a06g032 + +... From patchwork Fri Oct 5 16:58:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148259 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp690022lji; Fri, 5 Oct 2018 10:00:10 -0700 (PDT) X-Google-Smtp-Source: ACcGV62N6j0BrPN7MKN/K2TKZtl9cytzyAIBJlCpDYUfOWeSPf5dKl5/w5hfSIsjm8sz+U9HGxj3 X-Received: by 2002:a62:4681:: with SMTP id o1-v6mr2610897pfi.108.1538758809990; Fri, 05 Oct 2018 10:00:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758809; cv=none; d=google.com; s=arc-20160816; b=ZGHPuuPcvrkF/k5qEGqWrFuPGjUsd4gwetBwhgG2ljrVow8vhz6LhTX7VcoDuZthR6 E9tC2FJvKBFX9zXx7IH9eCD8bxdtnOi38WzTgvGIRgJNM+h7nddp6rzFsmIVaRA8IbRi ULCWrAFG5C0ds+NLECcgaDyAbnAt0ttlqmG5zQF8ZZYm8agHrVVptYf46xNf46Sce0ol H7Ogf2AaFVoPD6zVKkZxqEpOfZar+uAbFa0Rg8vdJrPvdf0SV6eUc/+/J09zZG6A6ji7 +QgOZqNnWi/2TNLPGCREr0QHRyRLr4NqpL0yQLHI50FHWDxbC5xXea6jB4I3+hn6284m oP1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=3VPklCipOuWldUvPpbh0zr7j2Wj5BAxPOt4Q1LfEFxc=; b=KEiH8H9FyZbjqMKsqTYlixl68GDtUS2y9/5H0vle1TOVctOOSK4ry/ub0mNINwDPFP fpOWatursY+8MATdGgsp/6IT2WvbKGKEDO9AUANFu+1Kxm9t8oZi3mGZ8ejTwoRse5ms Bpq/St3m0MuVUQIjmidUu1jaw84pdZofYTqPXZtAsuROqd9/CbAuakWFMhvnEHWAvWHB JkG4hFQs9CJKSzDak/KuVrG2YmxToOeS2GJdZyTG/6zXOqV8mstHSmjHOpQBIwBIfz+S iRodCT1YRsBygavoZ+IWEcL7y3emkv6npYbPubTaQjkpA3Q0cYy6rIIZWO46HMnO4Cor 2FjQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t21-v6si8919935pgn.56.2018.10.05.10.00.09; Fri, 05 Oct 2018 10:00:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729705AbeJEX7l (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:41 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:45350 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729525AbeJEX7J (ORCPT ); Fri, 5 Oct 2018 19:59:09 -0400 Received: by mail-ot1-f67.google.com with SMTP id u22so13321507ota.12; Fri, 05 Oct 2018 09:59:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3VPklCipOuWldUvPpbh0zr7j2Wj5BAxPOt4Q1LfEFxc=; b=d12UDYbF4coJEYvH35b/XEEHeKtZVgcav1+EKG1Zjpccpf9mjWw5VKcoj/Bx/zKRQ8 KOU0s4e7A3YNvLsVvct/K4M7KKtZGKw6MJ/mrWiuClWqpKrvzcIRPZ48mgQXRKfbf/NS xh/KRHHwyWdeAhO6XY++IG6Oe1KBl4bcbzT0JaDjk68LrLJA/RFMoDNo65I+6YwccoIs lk8Weisa8IuXFYdV48E44JMzUIjaSDrjVXrv2JlkxLMYZbivtUEGpME0chYTb7a7tj0L XNP66B1CXHVZ/RJMgZpHVUmiXraJhHvkWp6HcUusEe831g6GCAQOqQ1P8z+3S0kjV45Q Ncdw== X-Gm-Message-State: ABuFfoi3SYMD3uT8gWcHV1+TRIaNhQ+y6ZXPhKtO2+Aev4SGcuFRmTXY dDNxa8RB3U7UjKkM+RxUj0zRDXztvQ== X-Received: by 2002:a9d:f2:: with SMTP id 47mr7503473otk.43.1538758775042; Fri, 05 Oct 2018 09:59:35 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:34 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Patrice Chotard Subject: [PATCH 32/36] dt-bindings: arm: Convert ST STi board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:44 -0500 Message-Id: <20181005165848.3474-33-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ST STi SoC bindings to DT schema format using json-schema. Cc: Patrice Chotard Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/sti.txt | 23 ------------------- .../devicetree/bindings/arm/sti.yaml | 23 +++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/sti.txt create mode 100644 Documentation/devicetree/bindings/arm/sti.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/sti.txt b/Documentation/devicetree/bindings/arm/sti.txt deleted file mode 100644 index 8d27f6b084c7..000000000000 --- a/Documentation/devicetree/bindings/arm/sti.txt +++ /dev/null @@ -1,23 +0,0 @@ -ST STi Platforms Device Tree Bindings ---------------------------------------- - -Boards with the ST STiH415 SoC shall have the following properties: -Required root node property: -compatible = "st,stih415"; - -Boards with the ST STiH416 SoC shall have the following properties: -Required root node property: -compatible = "st,stih416"; - -Boards with the ST STiH407 SoC shall have the following properties: -Required root node property: -compatible = "st,stih407"; - -Boards with the ST STiH410 SoC shall have the following properties: -Required root node property: -compatible = "st,stih410"; - -Boards with the ST STiH418 SoC shall have the following properties: -Required root node property: -compatible = "st,stih418"; - diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml new file mode 100644 index 000000000000..10814334cfc9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/sti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST STi Platforms Device Tree Bindings + +maintainers: + - Maxime Coquelin + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - st,stih415 + - st,stih416 + - st,stih407 + - st,stih410 + - st,stih418 +... From patchwork Fri Oct 5 16:58:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148255 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689538lji; Fri, 5 Oct 2018 09:59:41 -0700 (PDT) X-Google-Smtp-Source: ACcGV61c/vnhodKFWUZnziBpr7y7KVJaL26mHzhx7zDxvYjeSOu0NDwayFGj7TFTpmBeEUkgS47u X-Received: by 2002:a17:902:8606:: with SMTP id f6-v6mr12462410plo.271.1538758780976; Fri, 05 Oct 2018 09:59:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758780; cv=none; d=google.com; s=arc-20160816; b=MgzmWs/XyfY/BaF3AwQP/D8LPNTuRQzFZANN0xQSWCUpHF2R9+HW6aZotdP+mWG84C 3euHmgPFTInXqlxI6XzTb51qoaKUvmKT33CDYJC6ms09w6q0q4CFluhEqKQjIhgSKWNv 7o/wDCFO6Bh39WtVq7GC8XW619CRqGxpZMsVAAEblaMpPIRARkOBfAU3wWnKW4LUbsqf Hp4ABZO4bCqhE2v9/DPN9PCSueorPDIc2hVIkCHFylmP0LNS4MxwgX3ZnozQjS4fPGdl PMBcjljlYqDMRsrYV+kNGBhWPFTz97ayGiEM/fpIVtVl5uAst1UAK2lCpjPWAvlr36IJ 8j0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Pw0v9K8eQLjlmD9GNG38KcZSA/yO1NRAOL0GIrmfslI=; b=O7Ri1lvN+hLHB1/SUq39h86ipnK8OeYx1yeXXBY+xpWGx9wmpZa0nmaW1xjlcUzsTY VRab1LddHj/PgRenWEBLvLvDyXx5WgPCevr0SoZL6en7GL+GFGvEHuUo6vbQVBBreVLh 1rOcuw6RoTJuAG1ZCHTniR8vmgcMLQ5MWCKOKaqI94Zxjlz22p/41SeV3aDp/A7iaYtQ 8CEbv3xjxlko10bpbe3UnSPDRRqM/V/ee2uHcNOxu898RGIHnjDkJtLjYfYvfKYQNk/m KHOezpNa8Yxt1B/g+A1WE9uFNQMe4lq++udc1u1vFBL0jWXR6gjGec7tgyJU461mc566 wz3A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w134-v6si9921868pfd.55.2018.10.05.09.59.40; Fri, 05 Oct 2018 09:59:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729620AbeJEX7M (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:12 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:34097 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729541AbeJEX7L (ORCPT ); Fri, 5 Oct 2018 19:59:11 -0400 Received: by mail-ot1-f67.google.com with SMTP id i12-v6so13401761otl.1; Fri, 05 Oct 2018 09:59:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pw0v9K8eQLjlmD9GNG38KcZSA/yO1NRAOL0GIrmfslI=; b=eyi2KGBxrO/e1p3kbJs1R/aI0p2DXLrtmqbKs5TUJO+1G9WwXdkBmDhozg7KgyMPE1 BwmYfWK/uqvZX+LUMmmQkd1yINI99MN3T761QeB4Gp074z2ow+CbGROAPWNsrMlK0G+M iw7Z8q5VCYl2agwoFXQz5VAFiU++9BZP7O0JTGen1EMGXN4r1QjdcQR/+j54Tep7ANPI 87skJZqyMDTrVYLoUetgptgZGGWB9eTnPK2enj/5Be1ktYWIo376HlhHbfaQddleXga+ 3S2IcMlro30xiKnmL76iuYh8KbgCkgKYHEc6CaCwkuifx4XkQdCA2BYyW4uj2jLfjVwa BJIA== X-Gm-Message-State: ABuFfojcYRw6ao2uBq/G2bmezUGjmI5ktGn642hMVoLVSCA7qGCVP6Yz AWFQ3o4s0w+jox4Vwa4BS57T5f2uzg== X-Received: by 2002:a9d:1723:: with SMTP id i35mr7449054ota.223.1538758776434; Fri, 05 Oct 2018 09:59:36 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:35 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 33/36] dt-bindings: arm: Convert Tegra board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:45 -0500 Message-Id: <20181005165848.3474-34-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Tegra SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Thierry Reding Cc: Jonathan Hunter Cc: devicetree@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/tegra.txt | 60 ------------- .../devicetree/bindings/arm/tegra.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt deleted file mode 100644 index 32f62bb7006d..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ /dev/null @@ -1,60 +0,0 @@ -NVIDIA Tegra device tree bindings -------------------------------------------- - -SoCs -------------------------------------------- - -Each device tree must specify which Tegra SoC it uses, using one of the -following compatible values: - - nvidia,tegra20 - nvidia,tegra30 - nvidia,tegra114 - nvidia,tegra124 - nvidia,tegra132 - nvidia,tegra210 - nvidia,tegra186 - nvidia,tegra194 - -Boards -------------------------------------------- - -Each device tree must specify which one or more of the following -board-specific compatible values: - - ad,medcom-wide - ad,plutux - ad,tamonten - ad,tec - compal,paz00 - compulab,trimslice - nvidia,beaver - nvidia,cardhu - nvidia,cardhu-a02 - nvidia,cardhu-a04 - nvidia,dalmore - nvidia,harmony - nvidia,jetson-tk1 - nvidia,norrin - nvidia,p2371-0000 - nvidia,p2371-2180 - nvidia,p2571 - nvidia,p2771-0000 - nvidia,p2972-0000 - nvidia,roth - nvidia,seaboard - nvidia,tn7 - nvidia,ventana - toradex,apalis_t30 - toradex,apalis_t30-eval - toradex,apalis-tk1 - toradex,apalis-tk1-eval - toradex,colibri_t20-512 - toradex,colibri_t30 - toradex,colibri_t30-eval-v3 - toradex,iris - -Trusted Foundations -------------------------------------------- -Tegra supports the Trusted Foundation secure monitor. See the -"tlm,trusted-foundations" binding's documentation for more details. diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml new file mode 100644 index 000000000000..9cebcfaaad1e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/tegra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra device tree bindings + +maintainers: + - Marcel Ziswiler + - Peter De Schrijver + +properties: + compatible: + oneOf: + - items: + - enum: + - compal,paz00 + - compulab,trimslice + - nvidia,harmony + - nvidia,seaboard + - nvidia,ventana + - const: nvidia,tegra20 + - items: + - enum: + - ad,medcom-wide + - ad,plutux + - ad,tec + - const: ad,tamonten + - const: nvidia,tegra20 + - items: + - const: toradex,iris + - const: toradex,colibri_t20-512 + - const: nvidia,tegra20 + - items: + - enum: + - nvidia,beaver + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,cardhu-a02 + - nvidia,cardhu-a04 + - const: nvidia,cardhu + - const: nvidia,tegra30 + - items: + - enum: + - toradex,apalis_t30-eval + - const: toradex,apalis_t30 + - const: nvidia,tegra30 + - items: + - enum: + - toradex,colibri_t30-eval-v3 + - const: toradex,colibri_t30 + - const: nvidia,tegra30 + - items: + - enum: + - nvidia,dalmore + - nvidia,roth + - nvidia,tn7 + - const: nvidia,tegra114 + - items: + - enum: + - nvidia,jetson-tk1 + - nvidia,venice2 + - const: nvidia,tegra124 + - items: + - const: toradex,apalis-tk1-eval + - const: toradex,apalis-tk1 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,norrin + - const: nvidia,tegra132 + - const: nvidia,tegra124 + - items: + - enum: + - nvidia,p2371-0000 + - nvidia,p2371-2180 + - nvidia,p2571 + - const: nvidia,tegra210 + - items: + - enum: + - nvidia,p2771-0000 + - const: nvidia,tegra186 + - items: + - enum: + - nvidia,p2972-0000 + - const: nvidia,tegra194 From patchwork Fri Oct 5 16:58:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148256 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689562lji; Fri, 5 Oct 2018 09:59:42 -0700 (PDT) X-Google-Smtp-Source: ACcGV6230OXD6EM3FxLJ7FaB2j0c7SG9DPOR1q+/1G9r3PfFe8nsWx1haT51PoktAebDaUYtX0n8 X-Received: by 2002:a62:7788:: with SMTP id s130-v6mr12807819pfc.189.1538758782850; Fri, 05 Oct 2018 09:59:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758782; cv=none; d=google.com; s=arc-20160816; b=XD9SlsYztPZVDPPzdaRkwY7qJ3zl6N2Tb+mFSeGK0s2iHYb4hzB1/N4/xds6XAOeKZ dVP5V4qbeuGoE1rLrhmvqbIfAA+2gTbhXc3D/7V3AxA4VxmmK32AqpRQu4Kd/M1+h6r6 JH6/qBYhXxFlqjVqwFk3lY1k/iuDSl1WOx7TC5DZnIxTRZGB2IrIlaJloXjJoDks+AHr oyFNkBO5E6UN70EnW2NQMXQfso20dxTamJcyXIVkY8nHVcIK0z+KmtbGXPfEubfap1rK jYl5TOAQ5DLqUX3/FGAdAsKIsu5Bn1fN5bC8oegztxUFwljFiO02GY3ZICRtMHmtTVnV 35Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=NPLYmq8r2xM4JEKhhNKIpjB9p0qLt//yMuDdja+hyKo=; b=EnEIVP09ItKQeMQmPa2kNFfbKSs/Kbvx1NImRwam6ZqTjx0flngFI6jbQwEx/M78W8 L/oUolXhCvhXs+JjvrrI/rp4Yy0QefmFkZANV53bJQM7NM2gG6klfQAZKpPsIzG3587+ MFIuK8uRewTzHDB21lu/0w6IORExRIiaJqX87cHQ7FKVdN6Ghaf4Bjom8B1LlRo9tW+u ODg8wf8Z15ddlHcgUGi+prIC3zXf1objbGNwFoqZ182fYOWZKGNPRnQCo1TErg70xq0t MGlLtDxrGcIlt/9kwq3e2PgahsQw8kNfWBiS6ZsMZoFw09VcuWVEDFldzLWf9isgzG/A 9K6g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z75-v6si9140293pfd.259.2018.10.05.09.59.42; Fri, 05 Oct 2018 09:59:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729637AbeJEX7N (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:13 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:37001 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729613AbeJEX7M (ORCPT ); Fri, 5 Oct 2018 19:59:12 -0400 Received: by mail-ot1-f67.google.com with SMTP id o13-v6so13351422otl.4; Fri, 05 Oct 2018 09:59:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NPLYmq8r2xM4JEKhhNKIpjB9p0qLt//yMuDdja+hyKo=; b=YOL4QAkHe5Y/RTEZ8z6kaP42IP8Pz8HYENV6hdQmN78qKJeIBVffyihPTZ09qdZFR6 0m/Aijql/+2gfBlYKA3eodD1ECBpsso9AaC2xYnZFB1CSdoc0JTn9w61EmvWIRA+jr7R i7v/2zPGS24JrwGIu1B7KbJKs9wneFDAD+Ldtfq1c/Nnid+v6vEOQ9x7RlvPKeG29tpY GXt71IsfU4sOMVP3a4o6W7SI5xM7y67wRdiDjQKYIH+vmUm2Jg/KIaIeLC+LSR3ejZuJ ic2KiWf/ymYEsu+M9ShlvToh06DToeY64Fgt1eaAsSjcUeSMI1c0TbanLN0fW3rkALCl MsNw== X-Gm-Message-State: ABuFfojA5UqW3BAmfyB7QQWYSkKWmi7pdv8pNzMMyoNN6BdbJU/1+3fa Aq25MdpF+2k2IHX9nyaB6O7YQkslQQ== X-Received: by 2002:a9d:538c:: with SMTP id w12mr1624159otg.139.1538758777856; Fri, 05 Oct 2018 09:59:37 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:37 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Tony Prisk Subject: [PATCH 34/36] dt-bindings: arm: Convert VIA board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:46 -0500 Message-Id: <20181005165848.3474-35-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert VIA SoC bindings to DT schema format using json-schema. Cc: Tony Prisk Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/vt8500.txt | 22 ------------------ .../devicetree/bindings/arm/vt8500.yaml | 23 +++++++++++++++++++ 2 files changed, 23 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt create mode 100644 Documentation/devicetree/bindings/arm/vt8500.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt deleted file mode 100644 index 87dc1ddf4770..000000000000 --- a/Documentation/devicetree/bindings/arm/vt8500.txt +++ /dev/null @@ -1,22 +0,0 @@ -VIA/Wondermedia VT8500 Platforms Device Tree Bindings ---------------------------------------- - -Boards with the VIA VT8500 SoC shall have the following properties: -Required root node property: -compatible = "via,vt8500"; - -Boards with the Wondermedia WM8505 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8505"; - -Boards with the Wondermedia WM8650 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8650"; - -Boards with the Wondermedia WM8750 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8750"; - -Boards with the Wondermedia WM8850 SoC shall have the following properties: -Required root node property: -compatible = "wm,wm8850"; diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml new file mode 100644 index 000000000000..6e07775b160f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/vt8500.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings + +maintainers: + - Tony Prisk +description: test + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - via,vt8500 + - wm,wm8505 + - wm,wm8650 + - wm,wm8750 + - wm,wm8850 From patchwork Fri Oct 5 16:58:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148257 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689576lji; Fri, 5 Oct 2018 09:59:44 -0700 (PDT) X-Google-Smtp-Source: ACcGV63I17O7szOmWB25O/WBOHGo1mjAogPXDgTJOAZJ2670GKAW2jbgQXpR7Wzmy1YFiKyCaKCD X-Received: by 2002:a62:8910:: with SMTP id v16-v6mr12842183pfd.106.1538758783996; Fri, 05 Oct 2018 09:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758783; cv=none; d=google.com; s=arc-20160816; b=oLWwLfTX1RAF97jQi7WHhUf4Sl8QKWjzXALnfBlUx2raZEyHYoOGCciUWnEh7oh+C/ H6R9Q65DvjOmd/hKX0io6N/ITCmn+298iCfFKoXsWNIrPAbwCNWHtCUBuAVosTgin8jC glzZiCL5BcNSzzBmSvhCiJqyHWV01FfcD/CNIbHnyGq2Q081INoYyS6315gmoGUL9s9/ ALB9/cFHN+8k5EpBNRpRTt8wtpg+1CVxHJqQmKfEvpm6MmvvcBuiubNo+4EJbqsHT3O2 IdgmnZmUonPaatiYk3IAA6L8NVwf5WbSP6Ls730Ie878LwZyxc6lL18esNXg4dFvIB8r geOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=K6DS5KOWh37k/+Xlr9IAvySrcc8KgKImzo5J4g96Byg=; b=DeT4ZoBLI6wYUSFyvduqTiqxTXA3nwYXi1XWCw8G9M1ZVq2utyfvBoc/yZ46pnubEa oLkj19mfx5gbXZfWabnrry+NFPuKoAN306JImQXaubDPWhSwkb2YZUnXpfTWzh/jrgC5 tQB7F+FOTS0ZXo68ttZ5rucItRpTCCfQItd0B+3h6OzCnzTqY3laEFHh1psUoF+59W+1 JUrpMe7NiBPsi37lKXLY2MH3M81qdYrvjNUcNopHoktyGJ7YwrVBaw3LcxcmVQAHw/HG OGd7PriaSAuLX2L/gvfWwE8OMzewVFv+8LU4106LvQ+rT1gVPi3j3CPA4UWSvMrgb8uN +j/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b124-v6si8408354pgc.45.2018.10.05.09.59.43; Fri, 05 Oct 2018 09:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729656AbeJEX7P (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:15 -0400 Received: from mail-ot1-f67.google.com ([209.85.210.67]:40366 "EHLO mail-ot1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729613AbeJEX7O (ORCPT ); Fri, 5 Oct 2018 19:59:14 -0400 Received: by mail-ot1-f67.google.com with SMTP id w67so13339726ota.7; Fri, 05 Oct 2018 09:59:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=K6DS5KOWh37k/+Xlr9IAvySrcc8KgKImzo5J4g96Byg=; b=TPrBswVj/sq1wTM6RxyK5d/2wXKnKdMGcaGE+wfcTB6Msk6ItDtDzzv1uxu/w7k8u/ AQf/NHJv2oJDf3dN8Aaf0ZfoWG3A6MVXYVoVL8/ZgtOLyDBdYaIWqGYmKBQJzpNuGvF/ KwkTjVd0aFVBx4tfiZu+MREvQcMVRVboI9AGKsqdcNZf9QgJHjJLNcxgcGOtPNYaDouh 27CSLJ/6izM3QKMiVYQTsYeBbyjH+P05CnmnhSG5Fyc7M1Q5jITRuERdWyVYRC8eQ4hD 5w5T+CMJ1VKUP1H26UaV6NHFw1YNWAB3hjq2TTKpPeWR5j4FwpYxiNQVGi4GYe36dUvM s3Og== X-Gm-Message-State: ABuFfojobTrEzBlXXvFR2jg1Q/K2xXLZIDR0ZOe+S8FwvlgqWkGAiM+3 4rMm+dyNtPfs+A6CayRTFVVJ7G3/pw== X-Received: by 2002:a9d:2e30:: with SMTP id q45mr6730173otb.69.1538758779232; Fri, 05 Oct 2018 09:59:39 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:38 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Michal Simek Subject: [PATCH 35/36] dt-bindings: arm: Convert Xilinx board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:47 -0500 Message-Id: <20181005165848.3474-36-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert Xilinx SoC bindings to DT schema format using json-schema. Cc: Mark Rutland Cc: Michal Simek Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/xilinx.txt | 83 ------------------- .../devicetree/bindings/arm/xilinx.yaml | 81 ++++++++++++++++++ 2 files changed, 81 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/xilinx.txt create mode 100644 Documentation/devicetree/bindings/arm/xilinx.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt deleted file mode 100644 index 26fe5ecc4332..000000000000 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Xilinx Zynq Platforms Device Tree Bindings - -Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynq-7000"; - -Additional compatible strings: - -- Adapteva Parallella board - "adapteva,parallella" - -- Avnet MicroZed board - "avnet,zynq-microzed" - "xlnx,zynq-microzed" - -- Avnet ZedBoard board - "avnet,zynq-zed" - "xlnx,zynq-zed" - -- Digilent Zybo board - "digilent,zynq-zybo" - -- Digilent Zybo Z7 board - "digilent,zynq-zybo-z7" - -- Xilinx CC108 internal board - "xlnx,zynq-cc108" - -- Xilinx ZC702 internal board - "xlnx,zynq-zc702" - -- Xilinx ZC706 internal board - "xlnx,zynq-zc706" - -- Xilinx ZC770 internal board, with different FMC cards - "xlnx,zynq-zc770-xm010" - "xlnx,zynq-zc770-xm011" - "xlnx,zynq-zc770-xm012" - "xlnx,zynq-zc770-xm013" - ---------------------------------------------------------------- - -Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings - -Boards with ZynqMP SOC based on an ARM Cortex A53 processor -shall have the following properties. - -Required root node properties: - - compatible = "xlnx,zynqmp"; - - -Additional compatible strings: - -- Xilinx internal board zc1232 - "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232" - -- Xilinx internal board zc1254 - "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254" - -- Xilinx internal board zc1275 - "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275" - -- Xilinx internal board zc1751 - "xlnx,zynqmp-zc1751" - -- Xilinx 96boards compatible board zcu100 - "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" - -- Xilinx evaluation board zcu102 - "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102" - "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102" - -- Xilinx evaluation board zcu104 - "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104" - -- Xilinx evaluation board zcu106 - "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106" - -- Xilinx evaluation board zcu111 - "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111" diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Documentation/devicetree/bindings/arm/xilinx.yaml new file mode 100644 index 000000000000..dd227bccf015 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml @@ -0,0 +1,81 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/arm/xilinx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Platforms Device Tree Bindings + +maintainers: + - Michal Simek + +description: | + Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - adapteva,parallella + - digilent,zynq-zybo + - digilent,zynq-zybo-z7 + - xlnx,zynq-cc108 + - xlnx,zynq-zc702 + - xlnx,zynq-zc706 + - xlnx,zynq-zc770-xm010 + - xlnx,zynq-zc770-xm011 + - xlnx,zynq-zc770-xm012 + - xlnx,zynq-zc770-xm013 + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-microzed + - const: xlnx,zynq-microzed + - const: xlnx,zynq-7000 + + - items: + - const: avnet,zynq-zed + - const: xlnx,zynq-zed + - const: xlnx,zynq-7000 + + - items: + - enum: + - xlnx,zynqmp-zc1751 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1232 + items: + - const: xlnx,zynqmp-zc1232-revA + - const: xlnx,zynqmp-zc1232 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1254 + items: + - const: xlnx,zynqmp-zc1254-revA + - const: xlnx,zynqmp-zc1254 + - const: xlnx,zynqmp + + - description: Xilinx internal board zc1275 + items: + - const: xlnx,zynqmp-zc1275-revA + - const: xlnx,zynqmp-zc1275 + - const: xlnx,zynqmp + + - description: Xilinx 96boards compatible board zcu100 + items: + - const: xlnx,zynqmp-zcu100-revC + - const: xlnx,zynqmp-zcu100 + - const: xlnx,zynqmp + + - description: Xilinx evaluation board zcu102 + items: + - enum: + - xlnx,zynqmp-zcu102-revA + - xlnx,zynqmp-zcu102-revB + - xlnx,zynqmp-zcu102-rev1.0 + - const: xlnx,zynqmp-zcu102 + - const: xlnx,zynqmp + +... From patchwork Fri Oct 5 16:58:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 148258 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp689640lji; Fri, 5 Oct 2018 09:59:48 -0700 (PDT) X-Google-Smtp-Source: ACcGV604irfOCnRlZYaQwavcux2JwNXBUsUBst4tEV79mS8+fnvBulhAnSszyNBcDVErxL40199L X-Received: by 2002:a65:5304:: with SMTP id m4-v6mr11287575pgq.250.1538758787928; Fri, 05 Oct 2018 09:59:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538758787; cv=none; d=google.com; s=arc-20160816; b=s6SPKoI2hbZNdPGg3S8eLNHBvww0ABk0ZRtvvxtI0+903d8zlfoXl0TrPTxhkAShYT eBdNecAeMsSflAvtYIO4T+jnM4IxOafe+jDDDTEKtlzNTPmQ8kAOU3TUrCBQASUKgZvB kEVzd9cUubr/Tp48gNwOjDAWjRFOz+50v814c5ZVdVR4vPQcaeSSUAnx2qb011040n14 VzSk1kmjrr1+9vGiskyuhXiH2/ih1PjQPYIbZ9TNRxryFhWhhshK4EdQGz/snHdMLoUh vo0QIqpeEp3rjq+Y2HfSU1CSI7PjdVPbmyc7U4/D/KqKxZ1qe8cKL1m0cmn5+0watRc+ tk/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=x4wwXdEDKonGexnyVd35qeAgk07Sz5QTv+CVm/iQtLQ=; b=wEdcUHabE9vszaVxEkWVO8lTPOq0k/pcCU0kHDJlG3pDo+zRPFLWvysyfTWwn0s1hT H010+bPZ8iwIOGlV5yAWRU/CiTAZsTgtQOpuIly5OmcwwCvpc4vPc/HxxWb5iDUOaCZ9 oWT0cCEe4EpgB9H4FVqx9gX9v7/EYwe/U/7VTDswMjwBN1beOHKwLjD2bUf0JM7zmeWN eietg08bdVqAm9ZFZH6s1VEX9CkYocY3R/w6gElQ3xu76AChyolFe1yfs/7C/gJsnJPo aAHn0BC40pxfTA+Z4SII7d/d/NGEbdkESKCcZekxKsz3msU5X6Ecqrz7eg8OqIVrL/le lXUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t21-v6si9951562plj.352.2018.10.05.09.59.47; Fri, 05 Oct 2018 09:59:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729673AbeJEX7T (ORCPT + 32 others); Fri, 5 Oct 2018 19:59:19 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:38620 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728502AbeJEX7P (ORCPT ); Fri, 5 Oct 2018 19:59:15 -0400 Received: by mail-ot1-f68.google.com with SMTP id l1so30852otj.5; Fri, 05 Oct 2018 09:59:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x4wwXdEDKonGexnyVd35qeAgk07Sz5QTv+CVm/iQtLQ=; b=RTp5XNM2F//A2Hbm937cb81CKpwWBSr82KcWk2qLw8UFlnpuKMKl8evGiqd3STtFaM vq+z83Gi39wbu1b+NFD0eNr8r4HGGRX8CtRoNOT0SJQNF20aKCnVkgJCB++ISyi2Pdtj j97wCTZI+Zo3SWtlLExb8iKellE82LZdpCX+j0z1GWmzpMvxKNJtxEqyIJI4mAoaKgWj GvpoL5Pys/iXlbK0z/et3Z13pj3a6Ef5hvelmEf0Ons1J75BHke6vYdto9OTN5tnLXGV e0CbAQ3gAHVrIQtdK6KlEgwBQoXUjrtCABSmNEFsI/aqZfV8EanMf5RqUUvtCjTwxFtN rwRQ== X-Gm-Message-State: ABuFfoiPHYzg9eZf4EO20Jxf8rcCMP8t7ejYhOT5+BtkM2Kht7FcL0eW V/rf89A9Ucf6CNQsXrjL6yPQ8766YQ== X-Received: by 2002:a9d:3bc7:: with SMTP id k65-v6mr6751836otc.23.1538758780591; Fri, 05 Oct 2018 09:59:40 -0700 (PDT) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id u63-v6sm2904328ota.75.2018.10.05.09.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Oct 2018 09:59:40 -0700 (PDT) From: Rob Herring To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org Cc: Grant Likely , Kumar Gala , Frank Rowand , Mark Rutland , Linus Walleij , Olof Johansson , Arnd Bergmann , Mark Brown , Tom Rini , Pantelis Antoniou , Geert Uytterhoeven , Jonathan Cameron , Bjorn Andersson , Jun Nie , Baoyou Xie , Shawn Guo Subject: [PATCH 36/36] dt-bindings: arm: Convert ZTE board/soc bindings to json-schema Date: Fri, 5 Oct 2018 11:58:48 -0500 Message-Id: <20181005165848.3474-37-robh@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181005165848.3474-1-robh@kernel.org> References: <20181005165848.3474-1-robh@kernel.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert ZTE SoC bindings to DT schema format using json-schema. Cc: Jun Nie Cc: Baoyou Xie Cc: Shawn Guo Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/zte.txt | 14 ---------- .../devicetree/bindings/arm/zte.yaml | 26 +++++++++++++++++++ 2 files changed, 26 insertions(+), 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/zte.txt create mode 100644 Documentation/devicetree/bindings/arm/zte.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt deleted file mode 100644 index 340612794a37..000000000000 --- a/Documentation/devicetree/bindings/arm/zte.txt +++ /dev/null @@ -1,14 +0,0 @@ -ZTE platforms device tree bindings - ---------------------------------------- -- ZX296702 board: - Required root node properties: - - compatible = "zte,zx296702-ad1", "zte,zx296702" - ---------------------------------------- -- ZX296718 SoC: - Required root node properties: - - compatible = "zte,zx296718" - -ZX296718 EVB board: - - "zte,zx296718-evb" diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000000..147bd78f27ed --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: None +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE platforms device tree bindings + +maintainers: + - Jun Nie + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - zte,zx296702-ad1 + - const: zte,zx296702 + - items: + - enum: + - zte,zx296718-evb + - const: zte,zx296718 + +...