From patchwork Mon Oct 8 18:33:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148423 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982040lji; Mon, 8 Oct 2018 11:36:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV63nWUNfgWNuIxd1iepGcppbPtd4+yUw52wqJbdwBkCLFyaow4x6SruYgJ3tJ5fdVNc0zheB X-Received: by 2002:a6b:17c6:: with SMTP id 189-v6mr15624180iox.226.1539023774847; Mon, 08 Oct 2018 11:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023774; cv=none; d=google.com; s=arc-20160816; b=QXJXVCfGqxUpQm+L4UBGjxducChS/pwkFg51lZaXT9K0oYY0/oRkm2RvKPaX1BMgEk DCgDQUmKnGNmCjVlaTJkmH8AUQIiBrSuyj/I83IMGOUxuaMN7pTR1aIVmRacnrbzBuQC MlC4DWbKAouZRWtOjCeqGat0WAVVieEF/rH0vmx2j8FgNds7nSpQFeJZtU9scj6G4s2P PAiHBx2rMOkSi3JoTmrBJ5BvQk+jhOG2N/DqHk8w7pHJ+8E7amkmwXX+VC2Ih6/s1A8W xuOtEiCXSEGXAOzG9dS13YIjrI6bVTsfVpKtzMmokHjio73Tu3Rxdp7zHNuN8sby/Asu SDZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=fBxzx/ylrxhPN0trHPCae+ajKX9gnnqL7zJbS2wJc6c=; b=bnbxqbgceBmypSy//3TsZWBtvkN8kvwvgjQh+c/BbPj52x0h8Xez+i9WnbmGijmHIM dWEZMBm8u7jWtqp37UwvYXT9wUEyiqkp4aGaUPKGFwkE29B4J51hT0FWOF8C0x2cfb6k KXHhr/m+znG30LugMFTOkfL4wrt3cY4NEwHieTnA5o1/mWzf+Y+eiQgL90iocLyEq3hx fail6CtArH1Xp6vhsZpLyjn1Ne6UZCl7HvLApLIc1+kh7br+431Xis2u7AHZWneBrwVN HnpzhK1GMtmfx/6vZpeCrHhPdJPoT7Qq9W6C1d2dqDX2EW00QJ4yNRS2sse/dYOUlFaQ w+VQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id k6-v6si8523693ith.134.2018.10.08.11.36.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM0-0005du-Rp; Mon, 08 Oct 2018 18:34:04 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aLz-0005df-EI for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:03 +0000 X-Inumbo-ID: e82eebbf-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e82eebbf-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:19 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B6491596; Mon, 8 Oct 2018 11:34:02 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2174C3F5B3; Mon, 8 Oct 2018 11:34:00 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:37 +0100 Message-Id: <20181008183352.16291-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 01/16] xen/arm: Introduce helpers to clear/flags flags in HCR_EL2 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A couple of places in the code will need to clear/set flags in HCR_EL2 for a given vCPU and then replicate into the hardware. Introduce helpers and replace open-coded version. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- The patch was previously sent separately and reviewed by Stefano. I haven't find a good place for those new helpers so stick to processor.h at the moment. This require to use macro rather than inline helpers given that processor.h is usually the root of all headers. --- xen/arch/arm/traps.c | 3 +-- xen/include/asm-arm/processor.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 51d2e42c77..9251ae50b8 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -682,8 +682,7 @@ static void inject_vabt_exception(struct cpu_user_regs *regs) break; } - current->arch.hcr_el2 |= HCR_VA; - WRITE_SYSREG(current->arch.hcr_el2, HCR_EL2); + vcpu_hcr_set_flags(current, HCR_VA); } /* diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 8016cf306f..975c8ff097 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -840,6 +840,24 @@ void abort_guest_exit_end(void); : : : "memory"); \ } while (0) +/* + * Clear/Set flags in HCR_EL2 for a given vCPU. It only supports the current + * vCPU for now. + */ +#define vcpu_hcr_clear_flags(v, flags) \ + do { \ + ASSERT((v) == current); \ + (v)->arch.hcr_el2 &= ~(flags); \ + WRITE_SYSREG((v)->arch.hcr_el2, HCR_EL2); \ + } while (0) + +#define vcpu_hcr_set_flags(v, flags) \ + do { \ + ASSERT((v) == current); \ + (v)->arch.hcr_el2 |= (flags); \ + WRITE_SYSREG((v)->arch.hcr_el2, HCR_EL2); \ + } while (0) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_PROCESSOR_H */ /* From patchwork Mon Oct 8 18:33:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148428 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982106lji; Mon, 8 Oct 2018 11:36:18 -0700 (PDT) X-Google-Smtp-Source: ACcGV63be7uXcKdLuyVFAz3It9/8PtUA0WmOWPukdC9ZptsrTamVlBthAiYVC4JLb9roJwBOkftg X-Received: by 2002:a5e:d613:: with SMTP id w19-v6mr16896543iom.75.1539023778313; Mon, 08 Oct 2018 11:36:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023778; cv=none; d=google.com; s=arc-20160816; b=Wv9DW4CXbYIvsHRNr4XvCS1PwPTDbswP3lwyJo/5bccswZEkvyk9G+/SIQWMANGQWX hSBxMprcn3nD4lyxgrKI0BUxvnmEdJTKWlfRcECg1admH+OGjbRnRTqnh6khigjnBumi Enokoy76Y9qZsz2FLMdMLDUcJ+diLSQXI16gRFpbm+rs4sc+OtzNMi1XA9tyoZ9qcgPX cZzVL62IQ5U4d5VEbbFfxRu/aAnbc2fI/s4HsoK8tmbmSabHH401exoAQyT8UOCYBqmc BmmlRcU0CEYWdsFO2jiN0FQCkIrz673Dgsu2HlaXVgUs9/KS5EQ/D30S1WOCbRP5yyhE 8mxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=hUp7zwAdEWFYS40lUeUu/mJ0xHqB9WpceGezKZgO/6o=; b=p1ONBMH0WWX2/cTq2atzpSwpLYjmHTulU0CjMmjZ432fj/I1CpD915RVWdVgtYS9rz dWgPESV1VakxbDiLP42jiabESDmcBfxTqUZWYXC8u6iU676QwL2ewD1ub0MlF2t854M+ e68EhsRhDBr91akKLMVSSp6noSZEBJDItDsMI8UdUmqbTx3zPq+3teL88z2gDpL01A3V KDcc21WNu6cFIdyNv8Q5aaAvX2F2pynluRcimsDbPyL0UjJT4nQEu45xOXWf04UfMB5h uKRLJOpXbdaD0Y9Ajzkrgyg6IjtRVeEKh1YIhRnFEQ2Z0lKcOGh8yTITZQe0/dE2Fku2 R9oA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 63-v6si8590164itq.70.2018.10.08.11.36.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM2-0005eA-66; Mon, 08 Oct 2018 18:34:06 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM1-0005e0-7i for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:05 +0000 X-Inumbo-ID: 60d16fe4-cb28-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 60d16fe4-cb28-11e8-a8a5-bc764e045a96; Mon, 08 Oct 2018 20:31:31 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3410515B2; Mon, 8 Oct 2018 11:34:03 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 49F823F5B3; Mon, 8 Oct 2018 11:34:02 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:38 +0100 Message-Id: <20181008183352.16291-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 02/16] xen/arm: Introduce helpers to get/set an MFN from/to an LPAE entry X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new helpers make it easier to read the code by abstracting the way to set/get an MFN from/to an LPAE entry. The helpers are using "walk" as the bits are common across different LPAE stages. At the same time, use the new helpers to replace the various open-coding place. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- This patch was originally sent separately. --- xen/arch/arm/mm.c | 10 +++++----- xen/arch/arm/p2m.c | 19 ++++++++++--------- xen/include/asm-arm/lpae.h | 3 +++ 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 7a06a33e21..0bc31b1d9b 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -238,7 +238,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, /* For next iteration */ unmap_domain_page(mapping); - mapping = map_domain_page(_mfn(pte.walk.base)); + mapping = map_domain_page(lpae_get_mfn(pte)); } unmap_domain_page(mapping); @@ -323,7 +323,7 @@ static inline lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned attr) ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK)); - e.pt.base = mfn_x(mfn); + lpae_set_mfn(e, mfn); return e; } @@ -490,7 +490,7 @@ mfn_t domain_page_map_to_mfn(const void *ptr) ASSERT(slot >= 0 && slot < DOMHEAP_ENTRIES); ASSERT(map[slot].pt.avail != 0); - return _mfn(map[slot].pt.base + offset); + return mfn_add(lpae_get_mfn(map[slot]), offset); } #endif @@ -851,7 +851,7 @@ void __init setup_xenheap_mappings(unsigned long base_mfn, /* mfn_to_virt is not valid on the 1st 1st mfn, since it * is not within the xenheap. */ first = slot == xenheap_first_first_slot ? - xenheap_first_first : __mfn_to_virt(p->pt.base); + xenheap_first_first : mfn_to_virt(lpae_get_mfn(*p)); } else if ( xenheap_first_first_slot == -1) { @@ -1007,7 +1007,7 @@ static int create_xen_entries(enum xenmap_operation op, BUG_ON(!lpae_is_valid(*entry)); - third = __mfn_to_virt(entry->pt.base); + third = mfn_to_virt(lpae_get_mfn(*entry)); entry = &third[third_table_offset(addr)]; switch ( op ) { diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 30cfb01498..f8a2f6459e 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -265,7 +265,7 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, if ( lpae_is_mapping(*entry, level) ) return GUEST_TABLE_SUPER_PAGE; - mfn = _mfn(entry->p2m.base); + mfn = lpae_get_mfn(*entry); unmap_domain_page(*table); *table = map_domain_page(mfn); @@ -349,7 +349,7 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, if ( a ) *a = p2m_mem_access_radix_get(p2m, gfn); - mfn = _mfn(entry.p2m.base); + mfn = lpae_get_mfn(entry); /* * The entry may point to a superpage. Find the MFN associated * to the GFN. @@ -519,7 +519,7 @@ static lpae_t mfn_to_p2m_entry(mfn_t mfn, p2m_type_t t, p2m_access_t a) ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK)); - e.p2m.base = mfn_x(mfn); + lpae_set_mfn(e, mfn); return e; } @@ -621,7 +621,7 @@ static void p2m_put_l3_page(const lpae_t pte) */ if ( p2m_is_foreign(pte.p2m.type) ) { - mfn_t mfn = _mfn(pte.p2m.base); + mfn_t mfn = lpae_get_mfn(pte); ASSERT(mfn_valid(mfn)); put_page(mfn_to_page(mfn)); @@ -655,7 +655,7 @@ static void p2m_free_entry(struct p2m_domain *p2m, return; } - table = map_domain_page(_mfn(entry.p2m.base)); + table = map_domain_page(lpae_get_mfn(entry)); for ( i = 0; i < LPAE_ENTRIES; i++ ) p2m_free_entry(p2m, *(table + i), level + 1); @@ -669,7 +669,7 @@ static void p2m_free_entry(struct p2m_domain *p2m, */ p2m_tlb_flush_sync(p2m); - mfn = _mfn(entry.p2m.base); + mfn = lpae_get_mfn(entry); ASSERT(mfn_valid(mfn)); pg = mfn_to_page(mfn); @@ -688,7 +688,7 @@ static bool p2m_split_superpage(struct p2m_domain *p2m, lpae_t *entry, bool rv = true; /* Convenience aliases */ - mfn_t mfn = _mfn(entry->p2m.base); + mfn_t mfn = lpae_get_mfn(*entry); unsigned int next_level = level + 1; unsigned int level_order = level_orders[next_level]; @@ -719,7 +719,7 @@ static bool p2m_split_superpage(struct p2m_domain *p2m, lpae_t *entry, * the necessary fields. So the correct permission are kept. */ pte = *entry; - pte.p2m.base = mfn_x(mfn_add(mfn, i << level_order)); + lpae_set_mfn(pte, mfn_add(mfn, i << level_order)); /* * First and second level pages set p2m.table = 0, but third @@ -952,7 +952,8 @@ static int __p2m_set_entry(struct p2m_domain *p2m, * Free the entry only if the original pte was valid and the base * is different (to avoid freeing when permission is changed). */ - if ( lpae_is_valid(orig_pte) && entry->p2m.base != orig_pte.p2m.base ) + if ( lpae_is_valid(orig_pte) && + !mfn_eq(lpae_get_mfn(*entry), lpae_get_mfn(orig_pte)) ) p2m_free_entry(p2m, orig_pte, level); if ( need_iommu_pt_sync(p2m->domain) && diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h index 15595cd35c..17fdc6074f 100644 --- a/xen/include/asm-arm/lpae.h +++ b/xen/include/asm-arm/lpae.h @@ -153,6 +153,9 @@ static inline bool lpae_is_superpage(lpae_t pte, unsigned int level) return (level < 3) && lpae_is_mapping(pte, level); } +#define lpae_get_mfn(pte) (_mfn((pte).walk.base)) +#define lpae_set_mfn(pte, mfn) ((pte).walk.base = mfn_x(mfn)) + /* * AArch64 supports pages with different sizes (4K, 16K, and 64K). To enable * page table walks for various configurations, the following helpers enable From patchwork Mon Oct 8 18:33:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148425 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982062lji; Mon, 8 Oct 2018 11:36:15 -0700 (PDT) X-Google-Smtp-Source: ACcGV61FfKIXFS6N2LDhcbkIusu/PcH0QAqLV+DcI/JKznXzF1qS/HiRiQ8/3981kZ+//T8cxSIk X-Received: by 2002:a6b:f919:: with SMTP id j25-v6mr15285633iog.280.1539023775816; Mon, 08 Oct 2018 11:36:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023775; cv=none; d=google.com; s=arc-20160816; b=JfkAxC2RDufi9sEdKz3Qr3liwfNkUufYs7NUvC1N2rYld+kfg8gJO3jfdS/tt4E/bn HKxvYtSx9GRtq8Z0+g/yUowQ5bOjHMF+8aOK+xK4unHRza9xDbQWYW/wOvs0kDyoAxCi St8CfZQzk7CN32H2b7GtOiEsDV9oKZq+/UTVQixd3yveUFRSqWmJ1AOen6p8BypCQjQe iam+2Zslf8eAc9Mw42HzqDU0DtitGo2DnkcrN0Y3Ap9FGAqUdBJmLj/WMsWJNiFJM4gC 9yqELM3AVxF0t/U9/UhoLPm6kRY4IydeYLhaTm641F4JA3uDd5eU8lAVpKZwxVqypB0S 5Z1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=eo6o0cn4A3QV/iGDzrBmKXT38/RatXTtxAp8GNzN0WM=; b=xNDBa6jthbzzNmnJTlh/4t6G6JapnmJvn6V51e5pxO7BLSl4v8jP/u8gfii28QFJVL ie9yvL5yTxc8bE3BtGm1GACxroIdS/KyKB8kzub6efpEyFMWIU0+P1YmmXWCGEYGxN2a agg2NAHomVkSAVHhYB5NIXn3QIXWz8wAJESZqTdH7QAx14q/pOs8xXwbTQvDEBfr4Zwm sA8msSrTUpOx4P/wcX8bwFXEmY5mbPEV1TX5Eg2hLvbFh3hM5PiLf0UqTrS4HOWBtUF2 KBoqWtVs2KqSnK/EsuyuH0SmQ/NS9cfq58D0aeCM5N9ITpGbUKij0WB9wPlD1CNPrjja eeHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b63-v6si11317654iof.71.2018.10.08.11.36.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM3-0005eR-J9; Mon, 08 Oct 2018 18:34:07 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM1-0005e5-Ul for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:05 +0000 X-Inumbo-ID: e99036c7-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id e99036c7-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5C616ED1; Mon, 8 Oct 2018 11:34:04 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 728E33F5B3; Mon, 8 Oct 2018 11:34:03 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:39 +0100 Message-Id: <20181008183352.16291-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 03/16] xen/arm: Allow lpae_is_{table, mapping} helpers to work on invalid entry X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, lpae_is_{table, mapping} helpers will always return false on entries with the valid bit unset. However, it would be useful to have them operating on any entry. For instance to store information in advance but still request a fault. With that change, the p2m is now providing an overlay for *_is_{table, mapping} that will check the valid bit of the entry. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- The patch was previously sent separately. --- xen/arch/arm/guest_walk.c | 2 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/p2m.c | 22 ++++++++++++++++++---- xen/include/asm-arm/lpae.h | 11 +++++++---- 4 files changed, 27 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index e3e21bdad3..4a1b4cf2c8 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -566,7 +566,7 @@ static int guest_walk_ld(const struct vcpu *v, * PTE is invalid or holds a reserved entry (PTE<1:0> == x0)) or if the PTE * maps a memory block at level 3 (PTE<1:0> == 01). */ - if ( !lpae_is_mapping(pte, level) ) + if ( !lpae_is_valid(pte) || !lpae_is_mapping(pte, level) ) return -EFAULT; /* Make sure that the lower bits of the PTE's base address are zero. */ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 0bc31b1d9b..987fcb9162 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -996,7 +996,7 @@ static int create_xen_entries(enum xenmap_operation op, for(; addr < addr_end; addr += PAGE_SIZE, mfn = mfn_add(mfn, 1)) { entry = &xen_second[second_linear_offset(addr)]; - if ( !lpae_is_table(*entry, 2) ) + if ( !lpae_is_valid(*entry) || !lpae_is_table(*entry, 2) ) { rc = create_xen_table(entry); if ( rc < 0 ) { diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index f8a2f6459e..8fffb42889 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -219,6 +219,20 @@ static p2m_access_t p2m_mem_access_radix_get(struct p2m_domain *p2m, gfn_t gfn) return radix_tree_ptr_to_int(ptr); } +/* + * lpae_is_* helpers don't check whether the valid bit is set in the + * PTE. Provide our own overlay to check the valid bit. + */ +static inline bool p2m_is_mapping(lpae_t pte, unsigned int level) +{ + return lpae_is_valid(pte) && lpae_is_mapping(pte, level); +} + +static inline bool p2m_is_superpage(lpae_t pte, unsigned int level) +{ + return lpae_is_valid(pte) && lpae_is_superpage(pte, level); +} + #define GUEST_TABLE_MAP_FAILED 0 #define GUEST_TABLE_SUPER_PAGE 1 #define GUEST_TABLE_NORMAL_PAGE 2 @@ -262,7 +276,7 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, /* The function p2m_next_level is never called at the 3rd level */ ASSERT(level < 3); - if ( lpae_is_mapping(*entry, level) ) + if ( p2m_is_mapping(*entry, level) ) return GUEST_TABLE_SUPER_PAGE; mfn = lpae_get_mfn(*entry); @@ -642,7 +656,7 @@ static void p2m_free_entry(struct p2m_domain *p2m, return; /* Nothing to do but updating the stats if the entry is a super-page. */ - if ( lpae_is_superpage(entry, level) ) + if ( p2m_is_superpage(entry, level) ) { p2m->stats.mappings[level]--; return; @@ -697,7 +711,7 @@ static bool p2m_split_superpage(struct p2m_domain *p2m, lpae_t *entry, * a superpage. */ ASSERT(level < target); - ASSERT(lpae_is_superpage(*entry, level)); + ASSERT(p2m_is_superpage(*entry, level)); page = alloc_domheap_page(NULL, 0); if ( !page ) @@ -836,7 +850,7 @@ static int __p2m_set_entry(struct p2m_domain *p2m, /* We need to split the original page. */ lpae_t split_pte = *entry; - ASSERT(lpae_is_superpage(*entry, level)); + ASSERT(p2m_is_superpage(*entry, level)); if ( !p2m_split_superpage(p2m, &split_pte, level, target, offsets) ) { diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h index 17fdc6074f..545b0c8f24 100644 --- a/xen/include/asm-arm/lpae.h +++ b/xen/include/asm-arm/lpae.h @@ -133,16 +133,19 @@ static inline bool lpae_is_valid(lpae_t pte) return pte.walk.valid; } +/* + * lpae_is_* don't check the valid bit. This gives an opportunity for the + * callers to operate on the entry even if they are not valid. For + * instance to store information in advance. + */ static inline bool lpae_is_table(lpae_t pte, unsigned int level) { - return (level < 3) && lpae_is_valid(pte) && pte.walk.table; + return (level < 3) && pte.walk.table; } static inline bool lpae_is_mapping(lpae_t pte, unsigned int level) { - if ( !lpae_is_valid(pte) ) - return false; - else if ( level == 3 ) + if ( level == 3 ) return pte.walk.table; else return !pte.walk.table; From patchwork Mon Oct 8 18:33:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148431 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982168lji; Mon, 8 Oct 2018 11:36:21 -0700 (PDT) X-Google-Smtp-Source: ACcGV61j/7pMt5HGGZaR6sx3LbTlq9bOUvxQRYVb33LcxwvIrDJuywcu0ZGDcnW8tgCI+2DtEzAk X-Received: by 2002:a02:b716:: with SMTP id g22-v6mr20007935jam.79.1539023781786; Mon, 08 Oct 2018 11:36:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023781; cv=none; d=google.com; s=arc-20160816; b=bKihuRbygHCOvd+LbMgMamNeQ206AfWiGJIYsRTt2j49TT+BsqUD8CLR5/xPB5EA7N pB/8sx/uG8q6Hoo4MWPdIhO58IDcMUawX6g+4yBFoSayI7usWUpPeUHx1IkyAFTnww+d lqdlFDwqePUwyLcQYsQT9D6bu+rBtdINFdIj3PSG2GP9JdFMYR/esgGP2wWoQ+9W0HxC thfjvSzd25SorT97cnpLlkTWiVsufG/FNFfNTvVFC4QNmq65jvSayvF+WZvi2EKi+Ka7 QOvnHoWSQYDFz08DPJJbwTGJecjZ8LUcZRyjdr2rRqD4L66aAcfE6OZJbSCegVuDOC8T OclA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=jo24vmXJfrxSf0Lxp5/U86EZTp5UgRGnA0GR1OHbQaI=; b=0fukyIKczqU+vCJizkts3mvwQF5YtMozg6fxBMtN01MF+iLxhT4c6xrieliRDB9GtN z7uCgnj8yhp1vGp27NJk5PKSBtTXFX/kI93pEGyrROwiMBFRQBaFSnev8tbc8pEC+HIc swAnAF4a+WbrDc8nWhpfh8PSlAuQYWwHnsnZgYwa0Va2qobPGDhZcaa/+dQqfdEW24MZ t2f8Xka0OvuRp6ZsfE/J/jmkzlXOc+c15nd6qGXl44IpVZNDQqx7zhy09nSbJTcvbHty o7xmEIojNLyDZM7X79E8xn0UsxAaZvN738rBC+BtMmMOiKl+7aV0v6bIg0tLcYa8uwU1 jOZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q6-v6si14329228jak.105.2018.10.08.11.36.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM4-0005eh-29; Mon, 08 Oct 2018 18:34:08 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM2-0005eF-IG for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:06 +0000 X-Inumbo-ID: ea587156-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ea587156-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:22 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A81701596; Mon, 8 Oct 2018 11:34:05 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B06B3F5B3; Mon, 8 Oct 2018 11:34:04 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:40 +0100 Message-Id: <20181008183352.16291-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 04/16] xen/arm: guest_walk_tables: Switch the return to bool X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, guest_walk_tables can either return 0, -EFAULT, -EINVAL. The use of the last 2 are not clearly defined and used inconsistently in the code. The current only caller does not care about the return value and the value of it seems very limited (no way to differentiate between the 15ish error paths). So switch to bool to simplify the return and make the developer life a bit easier. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- This patch was originally sent separately and reviewed by Stefano. --- xen/arch/arm/guest_walk.c | 50 ++++++++++++++++++++-------------------- xen/arch/arm/mem_access.c | 2 +- xen/include/asm-arm/guest_walk.h | 8 +++---- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 4a1b4cf2c8..7db7a7321b 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -28,9 +28,9 @@ * page table on a different vCPU, the following registers would need to be * loaded: TCR_EL1, TTBR0_EL1, TTBR1_EL1, and SCTLR_EL1. */ -static int guest_walk_sd(const struct vcpu *v, - vaddr_t gva, paddr_t *ipa, - unsigned int *perms) +static bool guest_walk_sd(const struct vcpu *v, + vaddr_t gva, paddr_t *ipa, + unsigned int *perms) { int ret; bool disabled = true; @@ -79,7 +79,7 @@ static int guest_walk_sd(const struct vcpu *v, } if ( disabled ) - return -EFAULT; + return false; /* * The address of the L1 descriptor for the initial lookup has the @@ -97,12 +97,12 @@ static int guest_walk_sd(const struct vcpu *v, /* Access the guest's memory to read only one PTE. */ ret = access_guest_memory_by_ipa(d, paddr, &pte, sizeof(short_desc_t), false); if ( ret ) - return -EINVAL; + return false; switch ( pte.walk.dt ) { case L1DESC_INVALID: - return -EFAULT; + return false; case L1DESC_PAGE_TABLE: /* @@ -122,10 +122,10 @@ static int guest_walk_sd(const struct vcpu *v, /* Access the guest's memory to read only one PTE. */ ret = access_guest_memory_by_ipa(d, paddr, &pte, sizeof(short_desc_t), false); if ( ret ) - return -EINVAL; + return false; if ( pte.walk.dt == L2DESC_INVALID ) - return -EFAULT; + return false; if ( pte.pg.page ) /* Small page. */ { @@ -175,7 +175,7 @@ static int guest_walk_sd(const struct vcpu *v, *perms |= GV2M_EXEC; } - return 0; + return true; } /* @@ -355,9 +355,9 @@ static bool check_base_size(unsigned int output_size, uint64_t base) * page table on a different vCPU, the following registers would need to be * loaded: TCR_EL1, TTBR0_EL1, TTBR1_EL1, and SCTLR_EL1. */ -static int guest_walk_ld(const struct vcpu *v, - vaddr_t gva, paddr_t *ipa, - unsigned int *perms) +static bool guest_walk_ld(const struct vcpu *v, + vaddr_t gva, paddr_t *ipa, + unsigned int *perms) { int ret; bool disabled = true; @@ -442,7 +442,7 @@ static int guest_walk_ld(const struct vcpu *v, */ if ( (input_size > TCR_EL1_IPS_48_BIT_VAL) || (input_size < TCR_EL1_IPS_MIN_VAL) ) - return -EFAULT; + return false; } else { @@ -487,7 +487,7 @@ static int guest_walk_ld(const struct vcpu *v, } if ( disabled ) - return -EFAULT; + return false; /* * The starting level is the number of strides (grainsizes[gran] - 3) @@ -498,12 +498,12 @@ static int guest_walk_ld(const struct vcpu *v, /* Get the IPA output_size. */ ret = get_ipa_output_size(d, tcr, &output_size); if ( ret ) - return -EFAULT; + return false; /* Make sure the base address does not exceed its configured size. */ ret = check_base_size(output_size, ttbr); if ( !ret ) - return -EFAULT; + return false; /* * Compute the base address of the first level translation table that is @@ -523,12 +523,12 @@ static int guest_walk_ld(const struct vcpu *v, /* Access the guest's memory to read only one PTE. */ ret = access_guest_memory_by_ipa(d, paddr, &pte, sizeof(lpae_t), false); if ( ret ) - return -EFAULT; + return false; /* Make sure the base address does not exceed its configured size. */ ret = check_base_size(output_size, pfn_to_paddr(pte.walk.base)); if ( !ret ) - return -EFAULT; + return false; /* * If page granularity is 64K, make sure the address is aligned @@ -537,7 +537,7 @@ static int guest_walk_ld(const struct vcpu *v, if ( (output_size < TCR_EL1_IPS_52_BIT_VAL) && (gran == GRANULE_SIZE_INDEX_64K) && (pte.walk.base & 0xf) ) - return -EFAULT; + return false; /* * Break if one of the following conditions is true: @@ -567,7 +567,7 @@ static int guest_walk_ld(const struct vcpu *v, * maps a memory block at level 3 (PTE<1:0> == 01). */ if ( !lpae_is_valid(pte) || !lpae_is_mapping(pte, level) ) - return -EFAULT; + return false; /* Make sure that the lower bits of the PTE's base address are zero. */ mask = GENMASK_ULL(47, grainsizes[gran]); @@ -583,11 +583,11 @@ static int guest_walk_ld(const struct vcpu *v, if ( !pte.pt.xn && !xn_table ) *perms |= GV2M_EXEC; - return 0; + return true; } -int guest_walk_tables(const struct vcpu *v, vaddr_t gva, - paddr_t *ipa, unsigned int *perms) +bool guest_walk_tables(const struct vcpu *v, vaddr_t gva, + paddr_t *ipa, unsigned int *perms) { uint32_t sctlr = READ_SYSREG(SCTLR_EL1); register_t tcr = READ_SYSREG(TCR_EL1); @@ -595,7 +595,7 @@ int guest_walk_tables(const struct vcpu *v, vaddr_t gva, /* We assume that the domain is running on the currently active domain. */ if ( v != current ) - return -EFAULT; + return false; /* Allow perms to be NULL. */ perms = perms ?: &_perms; @@ -619,7 +619,7 @@ int guest_walk_tables(const struct vcpu *v, vaddr_t gva, /* Memory can be accessed without any restrictions. */ *perms = GV2M_READ|GV2M_WRITE|GV2M_EXEC; - return 0; + return true; } if ( is_32bit_domain(v->domain) && !(tcr & TTBCR_EAE) ) diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c index ba4ec780fd..9239bdf323 100644 --- a/xen/arch/arm/mem_access.c +++ b/xen/arch/arm/mem_access.c @@ -125,7 +125,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag, * The software gva to ipa translation can still fail, e.g., if the gva * is not mapped. */ - if ( guest_walk_tables(v, gva, &ipa, &perms) < 0 ) + if ( !guest_walk_tables(v, gva, &ipa, &perms) ) return NULL; /* diff --git a/xen/include/asm-arm/guest_walk.h b/xen/include/asm-arm/guest_walk.h index 4ed8476e08..8768ac9894 100644 --- a/xen/include/asm-arm/guest_walk.h +++ b/xen/include/asm-arm/guest_walk.h @@ -2,10 +2,10 @@ #define _XEN_GUEST_WALK_H /* Walk the guest's page tables in software. */ -int guest_walk_tables(const struct vcpu *v, - vaddr_t gva, - paddr_t *ipa, - unsigned int *perms); +bool guest_walk_tables(const struct vcpu *v, + vaddr_t gva, + paddr_t *ipa, + unsigned int *perms); #endif /* _XEN_GUEST_WALK_H */ From patchwork Mon Oct 8 18:33:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148434 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982210lji; Mon, 8 Oct 2018 11:36:24 -0700 (PDT) X-Google-Smtp-Source: ACcGV60RodEfetXUjJpkwyESbQ08HPU0PPBEhUr9JZEusAUozJbQ1qhdX/xgEZHsqcXGS9VzFsl1 X-Received: by 2002:a6b:7312:: with SMTP id e18-v6mr15409536ioh.94.1539023783945; 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[192.237.175.120]) by mx.google.com with ESMTPS id v191-v6si1931875ita.72.2018.10.08.11.36.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM4-0005f0-Od; Mon, 08 Oct 2018 18:34:08 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM3-0005eU-My for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:07 +0000 X-Inumbo-ID: eb09c9ec-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id eb09c9ec-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:23 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D06CDED1; Mon, 8 Oct 2018 11:34:06 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E6A9E3F5B3; Mon, 8 Oct 2018 11:34:05 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:41 +0100 Message-Id: <20181008183352.16291-6-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 05/16] xen/arm: traps: Move the implementation of GUEST_BUG_ON in traps.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" GUEST_BUG_ON may be used in other files doing guest emulation. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- The patch was previously sent separately. --- xen/arch/arm/traps.c | 24 ------------------------ xen/include/asm-arm/traps.h | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9251ae50b8..b40798084d 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -68,30 +68,6 @@ static inline void check_stack_alignment_constraints(void) { #endif } -/* - * GUEST_BUG_ON is intended for checking that the guest state has not been - * corrupted in hardware and/or that the hardware behaves as we - * believe it should (i.e. that certain traps can only occur when the - * guest is in a particular mode). - * - * The intention is to limit the damage such h/w bugs (or spec - * misunderstandings) can do by turning them into Denial of Service - * attacks instead of e.g. information leaks or privilege escalations. - * - * GUEST_BUG_ON *MUST* *NOT* be used to check for guest controllable state! - * - * Compared with regular BUG_ON it dumps the guest vcpu state instead - * of Xen's state. - */ -#define guest_bug_on_failed(p) \ -do { \ - show_execution_state(guest_cpu_user_regs()); \ - panic("Guest Bug: %pv: '%s', line %d, file %s\n", \ - current, p, __LINE__, __FILE__); \ -} while (0) -#define GUEST_BUG_ON(p) \ - do { if ( unlikely(p) ) guest_bug_on_failed(#p); } while (0) - #ifdef CONFIG_ARM_32 static int debug_stack_lines = 20; #define stack_words_per_line 8 diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 70b52d1d16..0acf7de67d 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -9,6 +9,30 @@ # include #endif +/* + * GUEST_BUG_ON is intended for checking that the guest state has not been + * corrupted in hardware and/or that the hardware behaves as we + * believe it should (i.e. that certain traps can only occur when the + * guest is in a particular mode). + * + * The intention is to limit the damage such h/w bugs (or spec + * misunderstandings) can do by turning them into Denial of Service + * attacks instead of e.g. information leaks or privilege escalations. + * + * GUEST_BUG_ON *MUST* *NOT* be used to check for guest controllable state! + * + * Compared with regular BUG_ON it dumps the guest vcpu state instead + * of Xen's state. + */ +#define guest_bug_on_failed(p) \ +do { \ + show_execution_state(guest_cpu_user_regs()); \ + panic("Guest Bug: %pv: '%s', line %d, file %s\n", \ + current, p, __LINE__, __FILE__); \ +} while (0) +#define GUEST_BUG_ON(p) \ + do { if ( unlikely(p) ) guest_bug_on_failed(#p); } while (0) + int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); From patchwork Mon Oct 8 18:33:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148424 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982039lji; Mon, 8 Oct 2018 11:36:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV60C8jA3vZcuRa6hxHyuc3UOsv4286MYQ/Xnd8k6Ts9KnWDeLZnAyYMGufOe/P2QHMrSHktl X-Received: by 2002:a24:f982:: with SMTP id l124-v6mr220375ith.65.1539023774846; Mon, 08 Oct 2018 11:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023774; cv=none; d=google.com; s=arc-20160816; b=xxKzDDFKBTCNrpRA8DpAhBHriEV12oioD62qFTWLsgE4+eVI+JwxJvDUcKrR5bzLB0 wFDMJncy6M1iQcFOiYkNV7vYZBUnrTHUJS5Q0RWyoIqGO7pAwHeWVpe/Yej3AnfymSSf fBh7OfNJoHwYO1aKyplQAkYalo9l77Rb5iPRoSTWF4i/G5aYxCEKMC9KN5QYGMnUJBkt ErsWHQWGB1Lfx+rTlV7dyB1PYc64tOOBo9/RZ/yD3G9tCrGvHCX97BJ01ifhlj3qDb+G dZSRhtdAqImPtmwchspxPEYxuN4+CWurQKk4iIBvinV4zj25L1jTCzxoeVcvNTspNZ9u AfkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=891B/hX1lG34VHZvfF4AZk4NIAmHiPKZjYBtlr7GHbg=; b=GDFfChWbTvWiNSlIl8rLMbC2Kl5BGWiSk0FJDlnCohHapCH59D4vyWFK3j2/LzBKRH qEzDX4XFeKyEPi6JO8u09TfWeft2au1oCGOvwb0Tdujay6ontXnK7DWiqGGaodgYLHx5 5eU/FhvUrPFL6ZQgUJLTQr6+sqd9Z8vMc9mrG/Dt1eXgEP0msDULp0elBm+Od2pYtqKS aDLE3zin0s7FUtGR26zr8vJaMDSI9Q+g/Awjo1brHVuRHipAKKRXfTtjZTCaFDvc1vq9 lIlt55zdtDD7WZayJm3oBRLh+6Pb8CjSgqUCtcHAlCCdeaWSJuW2QYh8uclAy57XdBfv nqcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t75-v6si9650342iof.159.2018.10.08.11.36.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM7-0005fg-6D; Mon, 08 Oct 2018 18:34:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM4-0005f3-Sx for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:08 +0000 X-Inumbo-ID: ebbbabe0-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ebbbabe0-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:25 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04E5E1596; Mon, 8 Oct 2018 11:34:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AE243F5B3; Mon, 8 Oct 2018 11:34:06 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:42 +0100 Message-Id: <20181008183352.16291-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 06/16] xen/arm: p2m: Introduce a helper to generate P2M table entry from a page X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Generate P2M table entry requires to set some default values which are worth to explain in a comment. At the moment, there are 2 places where such entry are created but only one as proper comment. Some move the code to generate P2M table entry in a separate helper. This will be helpful in a follow-up patch to make modification on the defaults. At the same time, switch the default access from p2m->default_access to p2m_access_rwx. This should not matter as permission are ignored for table by the hardware. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/p2m.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 8fffb42889..6c76298ebc 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -538,6 +538,16 @@ static lpae_t mfn_to_p2m_entry(mfn_t mfn, p2m_type_t t, p2m_access_t a) return e; } +/* Generate table entry with correct attributes. */ +static lpae_t page_to_p2m_table(struct page_info *page) +{ + /* + * The access value does not matter because the hardware will ignore + * the permission fields for table entry. + */ + return mfn_to_p2m_entry(page_to_mfn(page), p2m_invalid, p2m_access_rwx); +} + static inline void p2m_write_pte(lpae_t *p, lpae_t pte, bool clean_pte) { write_pte(p, pte); @@ -558,7 +568,6 @@ static int p2m_create_table(struct p2m_domain *p2m, lpae_t *entry) { struct page_info *page; lpae_t *p; - lpae_t pte; ASSERT(!lpae_is_valid(*entry)); @@ -576,14 +585,7 @@ static int p2m_create_table(struct p2m_domain *p2m, lpae_t *entry) unmap_domain_page(p); - /* - * The access value does not matter because the hardware will ignore - * the permission fields for table entry. - */ - pte = mfn_to_p2m_entry(page_to_mfn(page), p2m_invalid, - p2m->default_access); - - p2m_write_pte(entry, pte, p2m->clean_pte); + p2m_write_pte(entry, page_to_p2m_table(page), p2m->clean_pte); return 0; } @@ -764,14 +766,11 @@ static bool p2m_split_superpage(struct p2m_domain *p2m, lpae_t *entry, unmap_domain_page(table); - pte = mfn_to_p2m_entry(page_to_mfn(page), p2m_invalid, - p2m->default_access); - /* * Even if we failed, we should install the newly allocated LPAE * entry. The caller will be in charge to free the sub-tree. */ - p2m_write_pte(entry, pte, p2m->clean_pte); + p2m_write_pte(entry, page_to_p2m_table(page), p2m->clean_pte); return rv; } From patchwork Mon Oct 8 18:33:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148430 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982124lji; Mon, 8 Oct 2018 11:36:19 -0700 (PDT) X-Google-Smtp-Source: ACcGV62WbhRVlbN1a+AYxAbiIs3tvMRfvqI2gslhFFhRgxs3IizGXsm0NYYwB64qt9Jv250C+3pJ X-Received: by 2002:a24:ce41:: with SMTP id v62-v6mr222558itg.52.1539023778980; Mon, 08 Oct 2018 11:36:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023778; cv=none; d=google.com; s=arc-20160816; b=A2YEM4ORwaPxUT01kthy9HBrLJucOCtkm+E1s6DZpqes5p/dC1+ykBZM2rzPiYMspY pR6za30arOfhm55mw9y99wbdVHLayFge8n4C+5VUos1JzHAKXMhMpI3T03jnbdsx+tj8 M8oZqG4myLBRTq/y0988CgoW/PbmcBs7lQpPtdaRecLPt3/y9+ejUkSIewLZRRBwgaRX PAyRWTyKzygaz5PSTMweP651rFDj9AS570R+LqAqeSDB6K3lXuasQCX61hylYfJYU5Wg 9i2VgMz5jCjQwvluTu5tcx5JSAzlRZbfmmbQvhW9EQ4+ZMKnTEQvoHBQ2bdaRVWrLrFj bU8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=vvDlwkwEkvjFoKcEGjUV7I3v9srAd95uUOXGzNB7JSk=; b=GrAAE4rDTDpF32pDe9O8Uo0AU+P/qoxjSFc5ptdO3zfTrfBXm1fJcAsRWBaoyhjVvx 5NzxTAa/OAzRJqUr/yKAhzJ2VPGsAQza42cam2CvzkC4zbFxNSSwsTZUCHIX2i6/Ag/e lxsxT+zLUmUG/RdEjX5S3RaTpqPHdI2MIVGyZSk3TIbOJTbcJWHkcjCIVwBEPfXTYbMt xNb6AGspq2zqRIYXmshEq2KrY13r6lT9CIGXP2OdaDSO9jkKOsCJZwQPFhUGIMnTabE8 eIBudrl11FmtkZMBZKXK3ugwFI4O++YzOY+BZ7qZ3jTtY6MrNFornfv9ZUP65e/uUFhQ 3TRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d17-v6si11984110ioh.76.2018.10.08.11.36.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM7-0005gr-Ov; Mon, 08 Oct 2018 18:34:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM6-0005fV-3G for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:10 +0000 X-Inumbo-ID: ec6dcde4-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ec6dcde4-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D533ED1; Mon, 8 Oct 2018 11:34:09 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 436F53F5B3; Mon, 8 Oct 2018 11:34:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:43 +0100 Message-Id: <20181008183352.16291-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 07/16] xen/arm: p2m: Introduce p2m_is_valid and use it X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The LPAE format allows to store information in an entry even with the valid bit unset. In a follow-up patch, we will take advantage of this feature to re-purpose the valid bit for generating a translation fault even if an entry contains valid information. So we need a different way to know whether an entry contains valid information. It is possible to use the information hold in the p2m_type to know for that purpose. Indeed all entries containing valid information will have a valid p2m type (i.e p2m_type != p2m_invalid). This patch introduces a new helper p2m_is_valid, which implements that idea, and replace most of lpae_is_valid call with the new helper. The ones remaining are for TLBs handling and entries accounting. With the renaming there are 2 others changes required: - Generate table entry with a valid p2m type - Detect new mapping for proper stats accounting Signed-off-by: Julien Grall --- xen/arch/arm/p2m.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 6c76298ebc..2a1e7e9be2 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -220,17 +220,26 @@ static p2m_access_t p2m_mem_access_radix_get(struct p2m_domain *p2m, gfn_t gfn) } /* + * In the case of the P2M, the valid bit is used for other purpose. Use + * the type to check whether an entry is valid. + */ +static inline bool p2m_is_valid(lpae_t pte) +{ + return pte.p2m.type != p2m_invalid; +} + +/* * lpae_is_* helpers don't check whether the valid bit is set in the * PTE. Provide our own overlay to check the valid bit. */ static inline bool p2m_is_mapping(lpae_t pte, unsigned int level) { - return lpae_is_valid(pte) && lpae_is_mapping(pte, level); + return p2m_is_valid(pte) && lpae_is_mapping(pte, level); } static inline bool p2m_is_superpage(lpae_t pte, unsigned int level) { - return lpae_is_valid(pte) && lpae_is_superpage(pte, level); + return p2m_is_valid(pte) && lpae_is_superpage(pte, level); } #define GUEST_TABLE_MAP_FAILED 0 @@ -264,7 +273,7 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, entry = *table + offset; - if ( !lpae_is_valid(*entry) ) + if ( !p2m_is_valid(*entry) ) { if ( read_only ) return GUEST_TABLE_MAP_FAILED; @@ -356,7 +365,7 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, entry = table[offsets[level]]; - if ( lpae_is_valid(entry) ) + if ( p2m_is_valid(entry) ) { *t = entry.p2m.type; @@ -544,8 +553,11 @@ static lpae_t page_to_p2m_table(struct page_info *page) /* * The access value does not matter because the hardware will ignore * the permission fields for table entry. + * + * We use p2m_ram_rw so the entry has a valid type. This is important + * for p2m_is_valid() to return valid on table entries. */ - return mfn_to_p2m_entry(page_to_mfn(page), p2m_invalid, p2m_access_rwx); + return mfn_to_p2m_entry(page_to_mfn(page), p2m_ram_rw, p2m_access_rwx); } static inline void p2m_write_pte(lpae_t *p, lpae_t pte, bool clean_pte) @@ -569,7 +581,7 @@ static int p2m_create_table(struct p2m_domain *p2m, lpae_t *entry) struct page_info *page; lpae_t *p; - ASSERT(!lpae_is_valid(*entry)); + ASSERT(!p2m_is_valid(*entry)); page = alloc_domheap_page(NULL, 0); if ( page == NULL ) @@ -626,7 +638,7 @@ static int p2m_mem_access_radix_set(struct p2m_domain *p2m, gfn_t gfn, */ static void p2m_put_l3_page(const lpae_t pte) { - ASSERT(lpae_is_valid(pte)); + ASSERT(p2m_is_valid(pte)); /* * TODO: Handle other p2m types @@ -654,11 +666,11 @@ static void p2m_free_entry(struct p2m_domain *p2m, struct page_info *pg; /* Nothing to do if the entry is invalid. */ - if ( !lpae_is_valid(entry) ) + if ( !p2m_is_valid(entry) ) return; /* Nothing to do but updating the stats if the entry is a super-page. */ - if ( p2m_is_superpage(entry, level) ) + if ( level == 3 && entry.p2m.table ) { p2m->stats.mappings[level]--; return; @@ -951,7 +963,7 @@ static int __p2m_set_entry(struct p2m_domain *p2m, else p2m->need_flush = true; } - else /* new mapping */ + else if ( !p2m_is_valid(orig_pte) ) /* new mapping */ p2m->stats.mappings[level]++; p2m_write_pte(entry, pte, p2m->clean_pte); @@ -965,7 +977,7 @@ static int __p2m_set_entry(struct p2m_domain *p2m, * Free the entry only if the original pte was valid and the base * is different (to avoid freeing when permission is changed). */ - if ( lpae_is_valid(orig_pte) && + if ( p2m_is_valid(orig_pte) && !mfn_eq(lpae_get_mfn(*entry), lpae_get_mfn(orig_pte)) ) p2m_free_entry(p2m, orig_pte, level); From patchwork Mon Oct 8 18:33:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148426 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982071lji; Mon, 8 Oct 2018 11:36:16 -0700 (PDT) X-Google-Smtp-Source: ACcGV63XHX4lZnDuQDojv/1yq8ea/DkTn/D3V8bU82P3II73zesIP9idTGjoCmnbgG+9flLI2XUj X-Received: by 2002:a6b:c085:: with SMTP id q127-v6mr15992379iof.255.1539023776378; Mon, 08 Oct 2018 11:36:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023776; cv=none; d=google.com; s=arc-20160816; b=JiPuEvPrQO84NLBUSOCHQ55PzN4SSWgyuq41Yi7VBGcvQ6oeSZvRYZp8pBm05Q4S7F +E7Sr7Y8iQ48OdfHffR4ij1+wCTDRGywUq69/TFucI2igzBckb50JsUPbQRKMdvfrUvR MhHzvOfJcYdaTZnanC26JruUsZYTH1kC6oYy/iIF+RsIopkEnbzSLG9pG0JK35CA0REv DoFhpqS9XrgbOu5z7U9MEjduL/L1CS3Km5J+hU3FHk5EGEwYlnDpceIH8jGNVWno8pBa Qxmtjkyg9ctMOpbZ/vn5c63o0OLfBhVNnn+6y9MqES5mA3KF24o5iGi2du3aIOfzhg3U 8sdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=0JFENIUQeQwMjFdJPynNiFis7jZN8IA6Ps5BA1mQ+JU=; b=JG6/WvyGIaahy+sGzYWYcAbNeGQ3hiEtqTBMkrV+2ziPGiUdBJIibtHMBOV4RWe6G0 Oned0S2PdHctMppt3XQpjr4vaHfo5GbsGRJ8XkwBkxA6I4WcuLK4uejrXcO/tq2QLmMi 2yhhZTo4BuFeT7oG9+Mu+G+b22sEBugWAtioSihbZvhO6mfWJaEk+H2zsWWP89B25yyz z/80lpfeDAcvuWdBGpBDUa0D1QVg/iC5jtRbxZU8qfkcMQDI8nD82rJ+7pvK5QMtB8OA X/JSyUfCCK77Ig88+7e9SqWuTdLQJoi6dHUxy45gJfNGILcsYIuPgEHF1rpiGufEPfn7 e4kA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g10-v6si11820236ioa.38.2018.10.08.11.36.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM9-0005hj-8V; Mon, 08 Oct 2018 18:34:13 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM7-0005fi-9U for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:11 +0000 X-Inumbo-ID: ed1f928e-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ed1f928e-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55FE91596; Mon, 8 Oct 2018 11:34:10 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C04C3F5B3; Mon, 8 Oct 2018 11:34:09 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:44 +0100 Message-Id: <20181008183352.16291-9-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 08/16] xen/arm: p2m: Handle translation fault in get_page_from_gva X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will re-purpose the valid bit of LPAE entries to generate fault even on entry containing valid information. This means that when translation a guest VA to guest PA (e.g IPA) will fail if the Stage-2 entries used have the valid bit unset. Because of that, we need to fallback to walk the page-table in software to check whether the fault was expected. This patch adds the software page-table walk on all the translation fault. It would be possible in the future to avoid pointless walk when the fault in PAR_EL1 is not a translation fault. Signed-off-by: Julien Grall --- There are a couple of TODO in the code. They are clean-up and performance improvement (e.g when the fault cannot be handled) that could be delayed after the series has been merged. --- xen/arch/arm/p2m.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2a1e7e9be2..ec956bc151 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -1438,6 +1439,8 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, struct page_info *page = NULL; paddr_t maddr = 0; uint64_t par; + mfn_t mfn; + p2m_type_t t; /* * XXX: To support a different vCPU, we would need to load the @@ -1454,8 +1457,30 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, par = gvirt_to_maddr(va, &maddr, flags); p2m_read_unlock(p2m); + /* + * gvirt_to_maddr may fail if the entry does not have the valid bit + * set. Fallback + * to the second method: + * 1) Translate the VA to IPA using software lookup -> Stage-1 page-table + * may not be accessible because the stage-2 entries may have valid + * bit unset. + * 2) Software lookup of the MFN + * + * Note that when memaccess is enabled, we instead all directly + * p2m_mem_access_check_and_get_page(...). Because the function is a + * a variant of the methods described above, it will be able to + * handle entry with valid bit unset. + * + * TODO: Integrate more nicely memaccess with the rest of the + * function. + * TODO: Use the fault error in PAR_EL1 to avoid pointless + * translation. + */ if ( par ) { + paddr_t ipa; + unsigned int perms; + /* * When memaccess is enabled, the translation GVA to MADDR may * have failed because of a permission fault. @@ -1463,20 +1488,46 @@ struct page_info *get_page_from_gva(struct vcpu *v, vaddr_t va, if ( p2m->mem_access_enabled ) return p2m_mem_access_check_and_get_page(va, flags, v); - dprintk(XENLOG_G_DEBUG, - "%pv: gvirt_to_maddr failed va=%#"PRIvaddr" flags=0x%lx par=%#"PRIx64"\n", - v, va, flags, par); - return NULL; + /* + * The software stage-1 table walk can still fail, e.g, if the + * GVA is not mapped. + */ + if ( !guest_walk_tables(v, va, &ipa, &perms) ) + { + dprintk(XENLOG_G_DEBUG, "%pv: Failed to walk page-table va %#"PRIvaddr"\n", v, va); + return NULL; + } + + /* + * Check permission that are assumed by the caller. For instance + * in case of guestcopy, the caller assumes that the translated + * page can be accessed with the requested permissions. If this + * is not the case, we should fail. + * + * Please note that we do not check for the GV2M_EXEC + * permission. This is fine because the hardware-based translation + * instruction does not test for execute permissions. + */ + if ( (flags & GV2M_WRITE) && !(perms & GV2M_WRITE) ) + return NULL; + + mfn = p2m_lookup(d, gaddr_to_gfn(ipa), &t); + if ( mfn_eq(INVALID_MFN, mfn) ) + return NULL; + + /* We consider that RAM is always mapped read-write */ } + else + mfn = maddr_to_mfn(maddr); - if ( !mfn_valid(maddr_to_mfn(maddr)) ) + if ( !mfn_valid(mfn) ) { dprintk(XENLOG_G_DEBUG, "%pv: Invalid MFN %#"PRI_mfn"\n", - v, mfn_x(maddr_to_mfn(maddr))); + v, mfn_x(mfn)); return NULL; } - page = mfn_to_page(maddr_to_mfn(maddr)); + page = mfn_to_page(mfn); ASSERT(page); if ( unlikely(!get_page(page, d)) ) From patchwork Mon Oct 8 18:33:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148429 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982111lji; Mon, 8 Oct 2018 11:36:18 -0700 (PDT) X-Google-Smtp-Source: ACcGV60iccuaKH+sqnJkqxKZmyjn6ww2WZz3F6a523c3aThLuyp9mLvUOw1e2Bj17bgNJA9eNtvo X-Received: by 2002:a6b:7f48:: with SMTP id m8-v6mr16265105ioq.16.1539023778598; Mon, 08 Oct 2018 11:36:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023778; cv=none; d=google.com; s=arc-20160816; b=LVx2Rx+vyVmzyS6h6Lr4E4aLsUxSbA75qJjOem2aj4/ZXyngsrj6sEZJV+d26xRzgi lrB/WT+zYHyvV3WNE7ACTJrn+Td7oSYtroLlbBD+GMV13vtWF5Zlvn2ehZsqOvdnRecd yDVRYd6z652LZ5MjtU/a+xm39HeEEzKwMYsAeivwFvFsM6usCpgOryBOiOrH5BmPimUk Y0oDofTMCarL1Ozbr321cxXFEJ6aT8nHHrP+o59C+lC10kFfwt+n/viJrb4GSDO0Ki69 Mr64XXyakVNz833QDmp/ZVIMyQ4sTR0koqxNxvlE9dUkvqdalzyyOQ12SsAY6BZDaqO4 SG3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=aKbRXplMN15ia1xhCqtYiiuP67OMpfBtpE7BdCHXDEs=; b=p9VIwm/7oBlYa93huxumF6KgcKyeVbVQIdQ8SKuX3VM93o8Yz4yHX+DNvbFJF9QZRh X840jmB0p2tKvsOjHbs7Uems+fXMVU7lke3+ml1/U33VPRRiyheGFUfWf9Nn+SUahfGp hkalMvtytLvfTU5f2HQVeBpYiOjhTiTHOl3N0SS9P75pAaEpOzBEvcouF+s7GcT4N0Jt Q0fR9ccQasBaUWt9CWkCAn1lhLzfrWdhmQL4E/pBIymGLNzt6/OA4Dc0P4EkqDxVXyo2 FUoRSiBqj2wQ1coqiHyvVItGZktbCA2N3KbArZNrIaBsNzFKpEiyE6NextAzS/4u6Ymo zfeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w79-v6si13763241jad.109.2018.10.08.11.36.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM9-0005iQ-SV; Mon, 08 Oct 2018 18:34:13 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM8-0005hN-Nz for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:12 +0000 X-Inumbo-ID: edd184ef-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id edd184ef-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:28 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E4B9ED1; Mon, 8 Oct 2018 11:34:11 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 948603F5B3; Mon, 8 Oct 2018 11:34:10 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:45 +0100 Message-Id: <20181008183352.16291-10-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 09/16] xen/arm: p2m: Introduce a function to resolve translation fault X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently a Stage-2 translation fault could happen: 1) MMIO emulation 2) When the page-tables is been updated using Break-Before-Make 3) Page not mapped A follow-up patch will re-purpose the valid bit in an entry to generate translation fault. This would be used to do an action on each entries to track page used for a given period. A new function is introduced to try to resolve a translation fault. This will include 2) and the new way to generate fault explained above. To avoid invalidating all the page-tables entries in one go. It is possible to invalidate the top-level table and then on trap invalidate the table one-level down. This will be repeated until a block/page entry has been reached. At the moment, there are no action done when reaching a block/page entry but setting the valid bit to 1. Signed-off-by: Julien Grall --- xen/arch/arm/p2m.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 7 +-- 2 files changed, 131 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ec956bc151..af445d3313 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1043,6 +1043,133 @@ int p2m_set_entry(struct p2m_domain *p2m, return rc; } +/* Invalidate all entries in the table. The p2m should be write locked. */ +static void p2m_invalidate_table(struct p2m_domain *p2m, mfn_t mfn) +{ + lpae_t *table; + unsigned int i; + + ASSERT(p2m_is_write_locked(p2m)); + + table = map_domain_page(mfn); + + for ( i = 0; i < LPAE_ENTRIES; i++ ) + { + lpae_t pte = table[i]; + + pte.p2m.valid = 0; + + p2m_write_pte(&table[i], pte, p2m->clean_pte); + } + + unmap_domain_page(table); + + p2m->need_flush = true; +} + +bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + unsigned int level = 0; + bool resolved = false; + lpae_t entry, *table; + paddr_t addr = gfn_to_gaddr(gfn); + + /* Convenience aliases */ + const unsigned int offsets[4] = { + zeroeth_table_offset(addr), + first_table_offset(addr), + second_table_offset(addr), + third_table_offset(addr) + }; + + p2m_write_lock(p2m); + + /* This gfn is higher than the highest the p2m map currently holds */ + if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) ) + goto out; + + table = p2m_get_root_pointer(p2m, gfn); + /* + * The table should always be non-NULL because the gfn is below + * p2m->max_mapped_gfn and the root table pages are always present. + */ + BUG_ON(table == NULL); + + /* + * Go down the page-tables until an entry has the valid bit unset or + * a block/page entry has been hit. + */ + for ( level = P2M_ROOT_LEVEL; level <= 3; level++ ) + { + int rc; + + entry = table[offsets[level]]; + + if ( level == 3 ) + break; + + /* Stop as soon as we hit an entry with the valid bit unset. */ + if ( !lpae_is_valid(entry) ) + break; + + rc = p2m_next_level(p2m, true, level, &table, offsets[level]); + if ( rc == GUEST_TABLE_MAP_FAILED ) + goto out_unmap; + else if ( rc != GUEST_TABLE_NORMAL_PAGE ) + break; + } + + /* + * If the valid bit of the entry is set, it means someone was playing with + * the Stage-2 page table. Nothing to do and mark the fault as resolved. + */ + if ( lpae_is_valid(entry) ) + { + resolved = true; + goto out_unmap; + } + + /* + * The valid bit is unset. If the entry is still not valid then the fault + * cannot be resolved, exit and report it. + */ + if ( !p2m_is_valid(entry) ) + goto out_unmap; + + /* + * Now we have an entry with valid bit unset, but still valid from + * the P2M point of view. + * + * For entry pointing to a table, the table will be invalidated. + * For entry pointing to a block/page, no work to do for now. + */ + if ( lpae_is_table(entry, level) ) + p2m_invalidate_table(p2m, lpae_get_mfn(entry)); + + /* + * Now that the work on the entry is done, set the valid bit to prevent + * another fault on that entry. + */ + resolved = true; + entry.p2m.valid = 1; + + p2m_write_pte(table + offsets[level], entry, p2m->clean_pte); + + /* + * No need to flush the TLBs as the modified entry had the valid bit + * unset. + */ + +out_unmap: + unmap_domain_page(table); + +out: + p2m_write_unlock(p2m); + + return resolved; +} + static inline int p2m_insert_mapping(struct domain *d, gfn_t start_gfn, unsigned long nr, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index b40798084d..169b57cb6b 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1882,6 +1882,8 @@ static bool try_map_mmio(gfn_t gfn) return !map_regions_p2mt(d, gfn, 1, mfn, p2m_mmio_direct_c); } +bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn); + static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, const union hsr hsr) { @@ -1894,7 +1896,6 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, vaddr_t gva; paddr_t gpa; uint8_t fsc = xabt.fsc & ~FSC_LL_MASK; - mfn_t mfn; bool is_data = (hsr.ec == HSR_EC_DATA_ABORT_LOWER_EL); /* @@ -1977,8 +1978,8 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, * with the Stage-2 page table. Walk the Stage-2 PT to check * if the entry exists. If it's the case, return to the guest */ - mfn = gfn_to_mfn(current->domain, gaddr_to_gfn(gpa)); - if ( !mfn_eq(mfn, INVALID_MFN) ) + if ( p2m_resolve_translation_fault(current->domain, + gaddr_to_gfn(gpa)) ) return; if ( is_data && try_map_mmio(gaddr_to_gfn(gpa)) ) From patchwork Mon Oct 8 18:33:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148433 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982196lji; Mon, 8 Oct 2018 11:36:23 -0700 (PDT) X-Google-Smtp-Source: ACcGV60nTIDUlV6P9643uhno3xO2g9gxCqEL08WxSByMm3tb548Ebqhwj6znI0YZqKwYN1jzno+t X-Received: by 2002:a6b:9357:: with SMTP id v84-v6mr12799650iod.148.1539023783401; Mon, 08 Oct 2018 11:36:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023783; cv=none; d=google.com; s=arc-20160816; b=PzsLyApH21NoAVXGOP1VBg7VP7C6ONXd07VXNp+0QLeK5RkZd3LZs+BJ4YS0RcFA2w Ch7jhgYohJ15zXxgM5jf56D31VYbal6yDJ6RxVYIdPdi/E4RB3cO3zk8exf5hLLT72zN uW9f/AOm40QmGOUxxpSAlr0TYtSx4Mb5Cyd55hOH2nqjOqFK1mrMjhhtk7zKV9z6X+av CkocnNet4fU6qUZuyBzbhE82bUGIxLgAhJQzmS4mQkiNBWINDIO6mGmbo+xboPuUJ3Xo MB5b78OdDtaWhEsjWSGY+nkTk4k1qkgR96iV/N8VRaUziCPYtZ1gEtEe9+kCJgQA8Hnh 3GCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=bxSWjIcocjSUTYw1GXwp3dULqfOIGq7f+wTZfmNWq9A=; b=HD+c/ggKvCc/MMXfO3zxgqzR5bNP98yOfB0mZysAUMfnDKkQEvWKhe+LXPoJ4J/KzB GWxfTnw9sgFcqBnwQ1xySHkjY5YhLjMWuwedfYmFvC28ROuX+NkXy9PhhfKTIIGRnuKL hcxy23aotcgKDkaRdsjXRVc9AWZAz+ejLmqbGbUpuboZsYy1L19f2AlGD5D9Ujzv04EI rJ03cnjeDBRSRm5uf6whK40elHNAfrNcFnZf8ceEydmrCO6YE5nXiU1NT2vNakYdJcrP nDsOPMhXLaT2bNW/IGwGdWKma9Wls5YTo4740Mpx92FO9f66oYsGGhq4hHZkbbjUTyp7 g0rQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x71-v6si8437745ite.103.2018.10.08.11.36.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMA-0005jf-Q7; Mon, 08 Oct 2018 18:34:14 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aM9-0005iS-VH for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:13 +0000 X-Inumbo-ID: ee835bfe-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ee835bfe-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:29 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A6E631596; Mon, 8 Oct 2018 11:34:12 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BD0183F5B3; Mon, 8 Oct 2018 11:34:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:46 +0100 Message-Id: <20181008183352.16291-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 10/16] xen/arm: vcpreg: Add wrappers to handle co-proc access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to some co-processors registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to host registers. For convenience a bunch of helpers have been added to generate the different helpers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall --- xen/arch/arm/vcpreg.c | 144 +++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 1 + 2 files changed, 145 insertions(+) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index b04d996fd3..49529b97cd 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -24,6 +24,122 @@ #include #include +/* + * Macros to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + * + * - TVM_REG() should not be used outside of the macros. It is there to + * help defining TVM_REG32() and TVM_REG64() + * - TVM_REG32(regname, xreg) and TVM_REG64(regname, xreg) are used to + * resp. generate helper accessing 32-bit and 64-bit register. "regname" + * been the Arm32 name and "xreg" the Arm64 name. + * - UPDATE_REG32_COMBINED(lowreg, hireg, xreg) are used to generate a + * pair of registers share the same Arm32 registers. "lowreg" and + * "higreg" been resp. the Arm32 name and "xreg" the Arm64 name. "lowreg" + * will use xreg[31:0] and "hireg" will use xreg[63:32]. + */ + +/* The name is passed from the upper macro to workaround macro expansion. */ +#define TVM_REG(sz, func, reg...) \ +static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG##sz(*r, reg); \ + \ + return true; \ +} + +#define TVM_REG32(regname, xreg) TVM_REG(32, vreg_emulate_##regname, xreg) +#define TVM_REG64(regname, xreg) TVM_REG(64, vreg_emulate_##regname, xreg) + +#ifdef CONFIG_ARM_32 +#define TVM_REG32_COMBINED(lowreg, hireg, xreg) \ + /* Use TVM_REG directly to workaround macro expansion. */ \ + TVM_REG(32, vreg_emulate_##lowreg, lowreg) \ + TVM_REG(32, vreg_emulate_##hireg, hireg) + +#else /* CONFIG_ARM_64 */ +#define TVM_REG32_COMBINED(lowreg, hireg, xreg) \ +static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read, bool hi) \ +{ \ + register_t reg = READ_SYSREG(xreg); \ + \ + GUEST_BUG_ON(read); \ + if ( hi ) /* reg[63:32] is AArch32 register hireg */ \ + { \ + reg &= GENMASK(31, 0); \ + reg |= ((uint64_t)*r) << 32; \ + } \ + else /* reg[31:0] is AArch32 register lowreg. */ \ + { \ + reg &= GENMASK(31, 0); \ + reg |= *r; \ + } \ + WRITE_SYSREG(reg, xreg); \ + \ + return true; \ +} \ + \ +static bool vreg_emulate_##lowreg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read) \ +{ \ + return vreg_emulate_##xreg(regs, r, read, false); \ +} \ + \ +static bool vreg_emulate_##hireg(struct cpu_user_regs *regs, uint32_t *r, \ + bool read) \ +{ \ + return vreg_emulate_##xreg(regs, r, read, true); \ +} +#endif + +/* Defining helpers for emulating co-processor registers. */ +TVM_REG32(SCTLR, SCTLR_EL1) +/* + * AArch32 provides two way to access TTBR* depending on the access + * size, whilst AArch64 provides one way. + * + * When using AArch32, for simplicity, use the same access size as the + * guest. + */ +#ifdef CONFIG_ARM_32 +TVM_REG32(TTBR0_32, TTBR0_32) +TVM_REG32(TTBR1_32, TTBR1_32) +#else +TVM_REG32(TTBR0_32, TTBR0_EL1) +TVM_REG32(TTBR1_32, TTBR1_EL1) +#endif +TVM_REG64(TTBR0, TTBR0_EL1) +TVM_REG64(TTBR1, TTBR1_EL1) +/* AArch32 registers TTBCR and TTBCR2 share AArch64 register TCR_EL1. */ +TVM_REG32_COMBINED(TTBCR, TTBCR2, TCR_EL1) +TVM_REG32(DACR, DACR32_EL2) +TVM_REG32(DFSR, ESR_EL1) +TVM_REG32(IFSR, IFSR32_EL2) +/* AArch32 registers DFAR and IFAR shares AArch64 register FAR_EL1. */ +TVM_REG32_COMBINED(DFAR, IFAR, FAR_EL1) +TVM_REG32(ADFSR, AFSR0_EL1) +TVM_REG32(AIFSR, AFSR1_EL1) +/* AArch32 registers MAIR0 and MAIR1 share AArch64 register MAIR_EL1. */ +TVM_REG32_COMBINED(MAIR0, MAIR1, MAIR_EL1) +/* AArch32 registers AMAIR0 and AMAIR1 share AArch64 register AMAIR_EL1. */ +TVM_REG32_COMBINED(AMAIR0, AMAIR1, AMAIR_EL1) +TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation. */ +#define GENERATE_CASE(reg, sz) \ + case HSR_CPREG##sz(reg): \ + { \ + bool res; \ + \ + res = vreg_emulate_cp##sz(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 = hsr.cp32; @@ -64,6 +180,31 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487B.b): Table D1-37 + */ + GENERATE_CASE(SCTLR, 32) + GENERATE_CASE(TTBR0_32, 32) + GENERATE_CASE(TTBR1_32, 32) + GENERATE_CASE(TTBCR, 32) + GENERATE_CASE(TTBCR2, 32) + GENERATE_CASE(DACR, 32) + GENERATE_CASE(DFSR, 32) + GENERATE_CASE(IFSR, 32) + GENERATE_CASE(DFAR, 32) + GENERATE_CASE(IFAR, 32) + GENERATE_CASE(ADFSR, 32) + GENERATE_CASE(AIFSR, 32) + /* AKA PRRR */ + GENERATE_CASE(MAIR0, 32) + /* AKA NMRR */ + GENERATE_CASE(MAIR1, 32) + GENERATE_CASE(AMAIR0, 32) + GENERATE_CASE(AMAIR1, 32) + GENERATE_CASE(CONTEXTIDR, 32) + + /* * MDCR_EL2.TPM * * ARMv7 (DDI 0406C.b): B1.14.17 @@ -192,6 +333,9 @@ void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr) return inject_undef_exception(regs, hsr); break; + GENERATE_CASE(TTBR0, 64) + GENERATE_CASE(TTBR1, 64) + /* * CPTR_EL2.T{0..9,12..13} * diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 07e5791983..f1cbac5e5d 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -142,6 +142,7 @@ /* CP15 CR2: Translation Table Base and Control Registers */ #define TTBCR p15,0,c2,c0,2 /* Translation Table Base Control Register */ +#define TTBCR2 p15,0,c2,c0,3 /* Translation Table Base Control Register 2 */ #define TTBR0 p15,0,c2 /* Translation Table Base Reg. 0 */ #define TTBR1 p15,1,c2 /* Translation Table Base Reg. 1 */ #define HTTBR p15,4,c2 /* Hyp. Translation Table Base Register */ From patchwork Mon Oct 8 18:33:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148422 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982023lji; Mon, 8 Oct 2018 11:36:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV62evaISXo/IK4AY4pex8ogfqN8Z9a8X7zLXSd+9m4QXoBdBffyb30wtgono+nMvaBbLWlbv X-Received: by 2002:a24:6907:: with SMTP id e7-v6mr216542itc.113.1539023774418; Mon, 08 Oct 2018 11:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023774; cv=none; d=google.com; s=arc-20160816; b=Soeo6oX2/yOktDemSRO0sqU6St2x0bLvT4J4aldy94fpETmJXzvUz+OP+0LcSCNejj rmdrUyRbSTE3xa5xc1wyrpKxiwjPeHG04TLrgZaAk+QQBpjqKu8tLrNpbDKV4Fh8vVA6 eiq34AELNBubxeJf++AW1qV165yR9zlQWhzpDXTIEcAuajGD9BuEjSQiQ2POd3PpNb+Q cx8yMlGH8urVJkYFnkO5KLVu9OvJcEx7BlAocKFXW4M6VtwAoNRzgyq7zgK3if2rsctA soVxy4064ctu3XGOmqQwt/sNVBaBqNDvh23WVKGCbL9UeXum4omlDYALYSfqI1pZHicD 2ulA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=w3/kZYZI1JWQaiMp+++HsyTaNqWuc3Hh6dx7GIqX+18=; b=Vcvcm5OhincetbOm85N6iCJKjIGm8cWWJ2WgcOtgI1CraFAjaEcIPyLL4byy6p5U3q PFWzXg7lYJ1RMrAejTffv2dtUrzs7ZlveG8yWXiuszzxavYzX9RTSL5JVtZNH7XN2tfa EaejMui8DIWuKXIgeN+33z85VSvAwTUXHZq7cJZGrY+zEGeoMHomtDqqibP19PMYizVO 1emssb7O1YnsSqrcnxje2zCVPsLBDn1cKyemYR2lIVel1jDgZu7/JiZBJY79kIlkkzfE 6nMAzi3RAw3UYZOfMOZeyapMHAkFtelZwlxNALIeLIOQ6CR8VMTPUYsDBzHnNBF6XKYQ 6/qw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h79-v6si8117867ita.135.2018.10.08.11.36.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMC-0005lc-A4; Mon, 08 Oct 2018 18:34:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMB-0005k6-6A for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:15 +0000 X-Inumbo-ID: ef3678fa-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ef3678fa-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D042715B2; Mon, 8 Oct 2018 11:34:13 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E582C3F5B3; Mon, 8 Oct 2018 11:34:12 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:47 +0100 Message-Id: <20181008183352.16291-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 11/16] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm64/vsysreg.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..1517879697 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -23,6 +23,46 @@ #include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +84,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487B.b): Table D1-37 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57 From patchwork Mon Oct 8 18:33:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148435 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982221lji; Mon, 8 Oct 2018 11:36:24 -0700 (PDT) X-Google-Smtp-Source: ACcGV60WlvpO1zamULPBvMCqUboX7gg9xUNu0V9cs6+c+KUwBXYMVQ5XzU0IIv2TpO/OGxg0uEG2 X-Received: by 2002:a6b:c652:: with SMTP id w79-v6mr15466501iof.142.1539023784492; Mon, 08 Oct 2018 11:36:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023784; cv=none; d=google.com; s=arc-20160816; b=bCBK+58rYQQxr+Ythqg1wPfu7mFLv+Rew5wJHYaza7XKmt/RCL/y2jWrvpTj+iJm+V XNegkFCqon0E9ZNC/V6YkekaP+eoa8RZR7kuR8XDf2zPsQZqgmugcjjbFY/HLSeaZNZo XPXRYdFVd643cupSXPDYK5sJ5ASsFv+EqEItX/ZPr6zmy/C63vlEwxBzGfJGsPOrVyic 0BN99sH/Cc909ia7kge6wjWhcfOJYaokgsX4rM8LNSf4qQcc7hTti0S4FVMw0E5Izful mTbnXkVbuLSoC3xb97ZPmMBAOID7cp3FUJ3zBiis8G4JV9X7ayJh4DS7sml/xEhetz/+ 4n/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=LtS3/z8S8W+LSOXIDJxIzaxHGiuiR+B/JeNTGciDr3A=; b=mzE6YqKWHNuxfhmaufIjMACGdplw4wXz9Xzysy9TpwuQHo5LDhP6+RZydKhPMElRn+ tmXW3N22X4SdeFAUzDfSolDEsPODdaIVXgbV+QvSRCMu2DGQHhpk+LciaYGOpp7yA0Qr aq3BAHeB6HMrD/j0k40vJeCbCPiHsOiM7u3ZgWLkpNC6uxF4lC74TMAX1wsNPtVqMFhy GPKw3CS9VuS5+5s9hr5NW3CRwfWgKMj0Q9cT0IAe/jpIvrkTKloMoVjYXQxZ0vPov33p WaM8JROD87egwswxXru5lIe4USrp5xkP6vyguxvEucdvY7Q9msK7omM0OeSo9r+o8HV3 r7hQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id u9-v6si9127322iof.127.2018.10.08.11.36.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMD-0005mw-OG; Mon, 08 Oct 2018 18:34:17 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMC-0005li-E2 for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:16 +0000 X-Inumbo-ID: 67d9cc9d-cb28-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 67d9cc9d-cb28-11e8-a8a5-bc764e045a96; Mon, 08 Oct 2018 20:31:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03EE2ED1; Mon, 8 Oct 2018 11:34:15 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 19F043F5B3; Mon, 8 Oct 2018 11:34:13 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:48 +0100 Message-Id: <20181008183352.16291-13-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 12/16] xen/arm: Rework p2m_cache_flush to take a range [begin, end) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function will be easier to re-use in a follow-up patch if you have only the begin and end. At the same time, rename the function to reflect the change in the prototype. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/domctl.c | 2 +- xen/arch/arm/p2m.c | 3 +-- xen/include/asm-arm/p2m.h | 7 +++++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index 4587c75826..c10f568aad 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -61,7 +61,7 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, if ( e < s ) return -EINVAL; - return p2m_cache_flush(d, _gfn(s), domctl->u.cacheflush.nr_pfns); + return p2m_cache_flush_range(d, _gfn(s), _gfn(e)); } case XEN_DOMCTL_bind_pt_irq: { diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index af445d3313..8537b7bab1 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1507,10 +1507,9 @@ int relinquish_p2m_mapping(struct domain *d) return rc; } -int p2m_cache_flush(struct domain *d, gfn_t start, unsigned long nr) +int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - gfn_t end = gfn_add(start, nr); gfn_t next_gfn; p2m_type_t t; unsigned int order; diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index c03557544a..d7afa2bbe8 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -224,8 +224,11 @@ int p2m_set_entry(struct p2m_domain *p2m, p2m_type_t t, p2m_access_t a); -/* Clean & invalidate caches corresponding to a region of guest address space */ -int p2m_cache_flush(struct domain *d, gfn_t start, unsigned long nr); +/* + * Clean & invalidate caches corresponding to a region [start,end) of guest + * address space. + */ +int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end); /* * Map a region in the guest p2m with a specific p2m type. From patchwork Mon Oct 8 18:33:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148432 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982187lji; Mon, 8 Oct 2018 11:36:22 -0700 (PDT) X-Google-Smtp-Source: ACcGV61/VAAMluI7BILH12Fb+cb7Fej21BC3/Lit/W9vrrRZGRpoh2Jq2+QkDxVHS8xJOg7WNElp X-Received: by 2002:a24:ac01:: with SMTP id s1-v6mr218141ite.69.1539023782764; Mon, 08 Oct 2018 11:36:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023782; cv=none; d=google.com; s=arc-20160816; b=0+2dlYKJk4LIjiGYGzdk7a3kOTnwYhrkSPCUt20YiteTbgTk9xvCAkLtZWLQ9JIkEL 19Hdc4PZvGcRyBUU+LRaZBf+N3eXTOq9lUgvZJurcBatFXfOZkyn4hmJbRk5GgFPMzYU tlJcYxS2L0mlkdjPSBd9EJKEFnpUThrsmou27joKp4GrHcoXdj/I8Kgdis3fRlemDo41 PPwjrRodFVS4nqYpNj6xC6e8CcChaJNbGIrAqSYWLuyBA8pbMwtKfN0hL2/45RdqO7X9 0Y7EOhuTqU66GgR9JcohBteWj0DxRBe3J6xjX6GoOvUDakWIAcAC231Zc71e8xgHRP11 8W6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=63uWvx+ZL8mmoIcGJxuVWNtkXPqI8ynOdiWzXFj51I0=; b=DxZS0KxQTqV6CLvlq9OTUiRnBYOMzlvOs9diIlfcr5YnJectwxuz57R8UdqmJVZZsr S9Q+BGTdBYt95kGVxh62MOCs+cbAOgaGcf0KUmhU++kBV0S9Np9pDaOAm52h3lJqHMRY hmbjMP8Goq+uYhoJqbRB4FCUso0r9g1om9/41yDN9ig5fTvHNbcXq0itFo3XOkyb2uE9 QWhoQZzYf5zkMBig0RaRHzfvfc+NJg1mde4S+/La8b2P0SqfjOYp/adlER3nAbgyKYek gYg8wALPtyCbMEY4PNkWnLrjy6xYGHnVfRs88lPyDrrjbeqbX4/a7oNT35rZ03cq2lmo xGBg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v15-v6si8418770itb.108.2018.10.08.11.36.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMF-0005og-4u; Mon, 08 Oct 2018 18:34:19 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMD-0005mr-La for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:17 +0000 X-Inumbo-ID: 688bbb0d-cb28-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 688bbb0d-cb28-11e8-a8a5-bc764e045a96; Mon, 08 Oct 2018 20:31:44 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C6341596; Mon, 8 Oct 2018 11:34:16 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 429D73F5B3; Mon, 8 Oct 2018 11:34:15 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:49 +0100 Message-Id: <20181008183352.16291-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 13/16] xen/arm: p2m: Allow to flush cache on any RAM region X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently, we only allow to flush cache on region mapped as p2m_ram_{rw,ro}. There are no real problem to flush cache on any RAM region such as grants and foreign mapping. Therefore, relax the cache to allow flushing the cache on any RAM region. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 8537b7bab1..12b459924b 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1532,7 +1532,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) next_gfn = gfn_next_boundary(start, order); /* Skip hole and non-RAM page */ - if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_ram(t) ) + if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) continue; /* XXX: Implement preemption */ From patchwork Mon Oct 8 18:33:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148436 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982244lji; Mon, 8 Oct 2018 11:36:26 -0700 (PDT) X-Google-Smtp-Source: ACcGV61KACZI5lk+ESKfCkuGs4EZdiavq/t9cRaB7yCT6vOE9e5hNCfw+Xk0hBr1saB4GD+yCXDT X-Received: by 2002:a24:22d0:: with SMTP id o199-v6mr16153433ito.67.1539023785901; Mon, 08 Oct 2018 11:36:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023785; cv=none; d=google.com; s=arc-20160816; b=dWdQycJJEZp1anLowxYSxbI0XZPn3+bYK7ZRBzK6ibxvmEgi/C45hl1MOa+46thY0M klrjdsy7wl/v5txS/Th9mqcHhqI4imaYx0WrHpIfKVMvemKC1PDu4bLkT1Py+Qg/Oy6y lwqcGRaWzIeWD+/4YBGZYVLiXvigJ4GP+QfqlwVS1JjZpBpJMZIkgDOdoArjYcjjmqv4 VsaHKOa3z16A3oFaQg4tNs8oNytMaqrRg4KFfpKGhfWojBtSF8MqQ6mtgVQI+7PI7qEb xbuqAWwZvDgTtSQpv2vZtBE6tg62xv6nBpavoxqdQR8G3fiUce4Z4Bk8XVXwingaAjWq CuYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=+5xVqlSM0pSrKqei5YQtScR4D5yGyKdTs+Y7d+AbWpo=; b=eOkT38yylXe11Jp9fhhXfV0gCw47FJCTS+OeLO045i1tTd6GjMUQig59H3NUcv9srX pyuvWiPLlDsalOxciLFSGts3p+5UpJGQQTNnySOHts+Zfyy1LGKl8gxwk7DY0o/OcU/K JTZ230zDlFIOw8ng3AhpvnoCoy6xdh9IreW8axkR4vA6HjqU/8b4EVRd9+K+E2ia/wYH P0W9cydSbqc74iN4Kr4vaZGacJkkwDK8VfnfS42DcwlKcqJGv/V5g2Zi9GOWklMt3MzW yAyRcUj6NX4QLvrEyGSBTJMKLcR10oJS/yPmTwgrJgrWU4e6SjSxffN1aCLhdy/wh/A0 HLvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q74-v6si8229489itb.97.2018.10.08.11.36.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMF-0005pT-Ns; Mon, 08 Oct 2018 18:34:19 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aME-0005nI-1w for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:18 +0000 X-Inumbo-ID: f14b8f75-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id f14b8f75-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:34 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55363ED1; Mon, 8 Oct 2018 11:34:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B1F83F5B3; Mon, 8 Oct 2018 11:34:16 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:50 +0100 Message-Id: <20181008183352.16291-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 14/16] xen/arm: p2m: Extend p2m_get_entry to return the value of bit[0] (valid bit) X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" With the recent changes, a P2M entry may be populated but may as not valid. In some situation, it would be useful to know whether the entry has been marked available to guest in order to perform a specific action. So extend p2m_get_entry to return the value of bit[0] (valid bit). Signed-off-by: Julien Grall --- xen/arch/arm/mem_access.c | 6 +++--- xen/arch/arm/p2m.c | 20 ++++++++++++++++---- xen/include/asm-arm/p2m.h | 3 ++- 3 files changed, 21 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c index 9239bdf323..f434510b2a 100644 --- a/xen/arch/arm/mem_access.c +++ b/xen/arch/arm/mem_access.c @@ -70,7 +70,7 @@ static int __p2m_get_mem_access(struct domain *d, gfn_t gfn, * No setting was found in the Radix tree. Check if the * entry exists in the page-tables. */ - mfn_t mfn = p2m_get_entry(p2m, gfn, NULL, NULL, NULL); + mfn_t mfn = p2m_get_entry(p2m, gfn, NULL, NULL, NULL, NULL); if ( mfn_eq(mfn, INVALID_MFN) ) return -ESRCH; @@ -199,7 +199,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag, * We had a mem_access permission limiting the access, but the page type * could also be limiting, so we need to check that as well. */ - mfn = p2m_get_entry(p2m, gfn, &t, NULL, NULL); + mfn = p2m_get_entry(p2m, gfn, &t, NULL, NULL, NULL); if ( mfn_eq(mfn, INVALID_MFN) ) goto err; @@ -405,7 +405,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr, gfn = gfn_next_boundary(gfn, order) ) { p2m_type_t t; - mfn_t mfn = p2m_get_entry(p2m, gfn, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, gfn, &t, NULL, &order, NULL); if ( !mfn_eq(mfn, INVALID_MFN) ) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 12b459924b..df6b48d73b 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -306,10 +306,14 @@ static int p2m_next_level(struct p2m_domain *p2m, bool read_only, * * If the entry is not present, INVALID_MFN will be returned and the * page_order will be set according to the order of the invalid range. + * + * valid will contain the value of bit[0] (e.g valid bit) of the + * entry. */ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, p2m_access_t *a, - unsigned int *page_order) + unsigned int *page_order, + bool *valid) { paddr_t addr = gfn_to_gaddr(gfn); unsigned int level = 0; @@ -317,6 +321,7 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, int rc; mfn_t mfn = INVALID_MFN; p2m_type_t _t; + bool _valid; /* Convenience aliases */ const unsigned int offsets[4] = { @@ -334,6 +339,10 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, *t = p2m_invalid; + /* Allow valid to be NULL */ + valid = valid?: &_valid; + *valid = false; + /* XXX: Check if the mapping is lower than the mapped gfn */ /* This gfn is higher than the highest the p2m map currently holds */ @@ -379,6 +388,9 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, * to the GFN. */ mfn = mfn_add(mfn, gfn_x(gfn) & ((1UL << level_orders[level]) - 1)); + + if ( valid ) + *valid = lpae_is_valid(entry); } out_unmap: @@ -397,7 +409,7 @@ mfn_t p2m_lookup(struct domain *d, gfn_t gfn, p2m_type_t *t) struct p2m_domain *p2m = p2m_get_hostp2m(d); p2m_read_lock(p2m); - mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL); + mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL, NULL); p2m_read_unlock(p2m); return mfn; @@ -1464,7 +1476,7 @@ int relinquish_p2m_mapping(struct domain *d) for ( ; gfn_x(start) < gfn_x(end); start = gfn_next_boundary(start, order) ) { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); count++; /* @@ -1527,7 +1539,7 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) for ( ; gfn_x(start) < gfn_x(end); start = next_gfn ) { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order); + mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); next_gfn = gfn_next_boundary(start, order); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index d7afa2bbe8..92213dd1ab 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -211,7 +211,8 @@ mfn_t p2m_lookup(struct domain *d, gfn_t gfn, p2m_type_t *t); */ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, p2m_access_t *a, - unsigned int *page_order); + unsigned int *page_order, + bool *valid); /* * Direct set a p2m entry: only for use by the P2M code. From patchwork Mon Oct 8 18:33:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148420 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3981904lji; Mon, 8 Oct 2018 11:36:07 -0700 (PDT) X-Google-Smtp-Source: ACcGV63tCojUjljaodd1vhH0jCFW9bzUERTMfRC9CMxrJVnPPJ9PgPyIbuKwYiuztoUOpyYRliHr X-Received: by 2002:a5e:c90c:: with SMTP id z12-v6mr16687209iol.72.1539023767237; Mon, 08 Oct 2018 11:36:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023767; cv=none; d=google.com; s=arc-20160816; b=kOdssT/EaYZYq9aFwUvUmghvuei83k3guMvW5XjFLxPGqCSrMmHn8lVAN3T0eSXBp7 0/5l9C10Y3cPoMltoA30BalmAT4pLPitw4qE9HIgw0Y84NOLX8IsLuaAFIcQd0OW4nPx FTgmWknNx2TfoqE6S0JbgUWH8xVDaB5MAw6ARjYUxGtYfeDgxSavE3Qk1qnfp3prLM9Q ICZs5OS73N4Ccx831Z731Y6/I9tNza1sIPLVSfQgVrBKGngQOkNpddXjiaInwfwkcX2n 1AjQC8Pj3QjPRuxkGCG7Kh+wX//9p/eaOBC/PUD4dQdKkPVvzVaAdE/WR2gRhioTXhG+ eEPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=nxwPz/qt3PuJRfWnse2hjNSmv3bI4Yvq9wfshTMLlBc=; b=u2Tp+hiqQjn3ZmcAL9HqEGtIPXzzux3/009oQVAsamqVa2arsKlLvt6WMeNzAsZhCQ SAg0eWqK6cFvu55hX8roFytpefSPyG6nxiP3JetYNxW3zkTEBfRup64SUP7IK9I1XdXq hQnEHVjTZeW6PdYDicqBf7cQ7l3Uj46RmzDYfbJSiGxeuPQUN6bzh8L08R8jI7RTUG9P T4WkRgCtwzYuQd4MWxhoP2av2/9RRRxczK5oVBEXHQmTqRIR0sr+bKF8jMQAK1KoQ+zk iMK07+zRzyrSymWFOT59mIIhQ/pWT/y/vnCiNBzoJy3e7ElHhb3tSPGKyUyZPtfLH4GI jO6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o53-v6si8350654jaj.66.2018.10.08.11.36.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMH-0005so-KK; Mon, 08 Oct 2018 18:34:21 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMF-0005qA-W6 for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:20 +0000 X-Inumbo-ID: 69ef97ec-cb28-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 69ef97ec-cb28-11e8-a8a5-bc764e045a96; Mon, 08 Oct 2018 20:31:47 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DC9615B2; Mon, 8 Oct 2018 11:34:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 93D953F5B3; Mon, 8 Oct 2018 11:34:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:51 +0100 Message-Id: <20181008183352.16291-16-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 15/16] xen/arm: Implement Set/Way operations X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Set/Way operations are used to perform maintenance on a given cache. At the moment, Set/Way operations are not trapped and therefore a guest OS will directly act on the local cache. However, a vCPU may migrate to another pCPU in the middle of the processor. This will result to have cache with stall data (Set/Way are not propagated) potentially causing crash. This may be the cause of heisenbug noticed in Osstest [1]. Furthermore, Set/Way operations are not available on system cache. This means that OS, such as Linux 32-bit, relying on those operations to fully clean the cache before disabling MMU may break because data may sits in system caches and not in RAM. For more details about Set/Way, see the talk "The Art of Virtualizing Cache Maintenance" given at Xen Summit 2018 [2]. In the context of Xen, we need to trap Set/Way operations and emulate them. From the Arm Arm (B1.14.4 in DDI 046C.c), Set/Way operations are difficult to virtualized. So we can assume that a guest OS using them will suffer the consequence (i.e slowness) until developer removes all the usage of Set/Way. As the software is not allowed to infer the Set/Way to Physical Address mapping, Xen will need to go through the guest P2M and clean & invalidate all the entries mapped. Because Set/Way happen in batch (a loop on all Set/Way of a cache), Xen would need to go through the P2M for every instructions. This is quite expensive and would severely impact the guest OS. The implementation is re-using the KVM policy to limit the number of flush: - If we trap a Set/Way operations, we enable VM trapping (i.e HVC_EL2.TVM) to detect cache being turned on/off, and do a full clean. - We clean the caches when turning on and off - Once the caches are enabled, we stop trapping VM instructions [1] https://lists.xenproject.org/archives/html/xen-devel/2017-09/msg03191.html [2] https://fr.slideshare.net/xen_com_mgr/virtualizing-cache Signed-off-by: Julien Grall --- xen/arch/arm/arm64/vsysreg.c | 27 +++++++++++++++++- xen/arch/arm/p2m.c | 68 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 2 +- xen/arch/arm/vcpreg.c | 23 +++++++++++++++ xen/include/asm-arm/p2m.h | 16 +++++++++++ 5 files changed, 134 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 1517879697..43c6c3e30d 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -40,7 +40,20 @@ static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ } /* Defining helpers for emulating sysreg registers. */ -TVM_REG(SCTLR_EL1) +static bool vreg_emulate_SCTLR_EL1(struct cpu_user_regs *regs, uint64_t *r, + bool read) +{ + struct vcpu *v = current; + bool cache_enabled = vcpu_has_cache_enabled(v); + + GUEST_BUG_ON(read); + WRITE_SYSREG(*r, SCTLR_EL1); + + p2m_toggle_cache(v, cache_enabled); + + return true; +} + TVM_REG(TTBR0_EL1) TVM_REG(TTBR1_EL1) TVM_REG(TCR_EL1) @@ -84,6 +97,18 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TSW + * + * ARMv8 (DDI 0487B.b): Table D1-42 + */ + case HSR_SYSREG_DCISW: + case HSR_SYSREG_DCCSW: + case HSR_SYSREG_DCCISW: + if ( hsr.sysreg.read ) + p2m_set_way_flush(current); + break; + + /* * HCR_EL2.TVM * * ARMv8 (DDI 0487B.b): Table D1-37 diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index df6b48d73b..a3d4c563b1 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1564,6 +1564,74 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) return 0; } +static void p2m_flush_vm(struct vcpu *v) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(v->domain); + + /* XXX: Handle preemption */ + p2m_cache_flush_range(v->domain, p2m->lowest_mapped_gfn, + p2m->max_mapped_gfn); +} + +/* + * See note at ARMv7 ARM B1.14.4 (DDI 0406C.c) (TL;DR: S/W ops are not + * easily virtualized). + * + * Main problems: + * - S/W ops are local to a CPU (not broadcast) + * - We have line migration behind our back (speculation) + * - System caches don't support S/W at all (damn!) + * + * In the face of the above, the best we can do is to try and convert + * S/W ops to VA ops. Because the guest is not allowed to infer the S/W + * to PA mapping, it can only use S/W to nuke the whole cache, which is + * rather a good thing for us. + * + * Also, it is only used when turning caches on/off ("The expected + * usage of the cache maintenance instructions that operate by set/way + * is associated with the powerdown and powerup of caches, if this is + * required by the implementation."). + * + * We use the following policy: + * - If we trap a S/W operation, we enabled VM trapping to detect + * caches being turned on/off, and do a full clean. + * + * - We flush the caches on both caches being turned on and off. + * + * - Once the caches are enabled, we stop trapping VM ops. + */ +void p2m_set_way_flush(struct vcpu *v) +{ + /* This function can only work with the current vCPU. */ + ASSERT(v == current); + + if ( !(v->arch.hcr_el2 & HCR_TVM) ) + { + p2m_flush_vm(v); + vcpu_hcr_set_flags(v, HCR_TVM); + } +} + +void p2m_toggle_cache(struct vcpu *v, bool was_enabled) +{ + bool now_enabled = vcpu_has_cache_enabled(v); + + /* This function can only work with the current vCPU. */ + ASSERT(v == current); + + /* + * If switching the MMU+caches on, need to invalidate the caches. + * If switching it off, need to clean the caches. + * Clean + invalidate does the trick always. + */ + if ( was_enabled != now_enabled ) + p2m_flush_vm(v); + + /* Caches are now on, stop trapping VM ops (until a S/W op) */ + if ( now_enabled ) + vcpu_hcr_clear_flags(v, HCR_TVM); +} + mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) { return p2m_lookup(d, gfn, NULL); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 169b57cb6b..cdc10eee5a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB); + HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } static enum { diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 49529b97cd..dc46d9d0d7 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -45,9 +45,14 @@ #define TVM_REG(sz, func, reg...) \ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ { \ + struct vcpu *v = current; \ + bool cache_enabled = vcpu_has_cache_enabled(v); \ + \ GUEST_BUG_ON(read); \ WRITE_SYSREG##sz(*r, reg); \ \ + p2m_toggle_cache(v, cache_enabled); \ + \ return true; \ } @@ -65,6 +70,8 @@ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) \ static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ bool read, bool hi) \ { \ + struct vcpu *v = current; \ + bool cache_enabled = vcpu_has_cache_enabled(v); \ register_t reg = READ_SYSREG(xreg); \ \ GUEST_BUG_ON(read); \ @@ -80,6 +87,8 @@ static bool vreg_emulate_##xreg(struct cpu_user_regs *regs, uint32_t *r, \ } \ WRITE_SYSREG(reg, xreg); \ \ + p2m_toggle_cache(v, cache_enabled); \ + \ return true; \ } \ \ @@ -98,6 +107,7 @@ static bool vreg_emulate_##hireg(struct cpu_user_regs *regs, uint32_t *r, \ /* Defining helpers for emulating co-processor registers. */ TVM_REG32(SCTLR, SCTLR_EL1) + /* * AArch32 provides two way to access TTBR* depending on the access * size, whilst AArch64 provides one way. @@ -180,6 +190,19 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) break; /* + * HCR_EL2.TSW + * + * ARMv7 (DDI 0406C.b): B1.14.6 + * ARMv8 (DDI 0487B.b): Table D1-42 + */ + case HSR_CPREG32(DCISW): + case HSR_CPREG32(DCCSW): + case HSR_CPREG32(DCCISW): + if ( !cp32.read ) + p2m_set_way_flush(current); + break; + + /* * HCR_EL2.TVM * * ARMv8 (DDI 0487B.b): Table D1-37 diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index 92213dd1ab..c470f062db 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -231,6 +231,10 @@ int p2m_set_entry(struct p2m_domain *p2m, */ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end); +void p2m_set_way_flush(struct vcpu *v); + +void p2m_toggle_cache(struct vcpu *v, bool was_enabled); + /* * Map a region in the guest p2m with a specific p2m type. * The memory attributes will be derived from the p2m type. @@ -358,6 +362,18 @@ static inline int set_foreign_p2m_entry(struct domain *d, unsigned long gfn, return -EOPNOTSUPP; } +/* + * A vCPU has cache enabled only when the MMU is enabled and data cache + * is enabled. + */ +static inline bool vcpu_has_cache_enabled(struct vcpu *v) +{ + /* Only works with the current vCPU */ + ASSERT(current == v); + + return (READ_SYSREG32(SCTLR_EL1) & (SCTLR_C|SCTLR_M)) == (SCTLR_C|SCTLR_M); +} + #endif /* _XEN_P2M_H */ /* From patchwork Mon Oct 8 18:33:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148421 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3981957lji; Mon, 8 Oct 2018 11:36:10 -0700 (PDT) X-Google-Smtp-Source: ACcGV60n6M/QwQuAWwCT3m0eUSIoZdySALrK/5AxS9H98ho1vN8HTTFeHiiKEWTXkhD5oqhSiwFv X-Received: by 2002:a24:9d90:: with SMTP id f138-v6mr232925itd.57.1539023769984; Mon, 08 Oct 2018 11:36:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023769; cv=none; d=google.com; s=arc-20160816; b=YMQnJxlKJROn7rRp5j5QPw+Of68N4iAyt1qfpr67t4WDLXL1nC58lo2ZbIOKdr/0YR b3fM4DZk4UUPMUxQjA8d816NnXdcbQ9HUAiao5Utm5HBFomPTvKCjCoAO6GLgPf4UpBl A+WMK5Lgo1nJg/s0CXdE60eL9sA5bLPjSnOuLKPXcaYWCaVEtFagX3fo6Kf81jm/+Uro RYA9VdaOKkrl69GnOlQbZRfN513kb1QsCc1YBzkoJemIsXjzzbb4yXcXQXkdCKSF5Os/ bo1SmvTTKaJhS63uUs05UcjsM4git/u/NZhMJSPPdGxVhnr3DhYZTh8oW1ltM9bcs+3+ ztbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=g3rwvmlHgaV0Vu08ecPWtCsrKH6NcqQrqt+FLQKpElg=; b=Hx26nAe5SJGveN3Sb1nqifqUDJFkB6gFh0lRLhAwsVjPe1mEEBtJiyZPTU+WCAS9yg x478g6ZlxICxAKTcC8H3bC33++fbQb/EFSWGF80Qar/zptd1eOSz7uSKcFq8GLqoZ8Q/ vPe8H1+e8qVRuhjGyV9Jn56OWn2wY3L9r4unjJsaVwb4y+r+Wx5oOCQ/s3vU0Fn10eI9 Z+/Ob7dfobzuftvQnpyjt4mccg2no/rQ7E9OsSupfQdP0ND+/UYt5ooR3bys3JE8il5I HBMCfu53Pqf0i2DTpun7tXEZCMNrLPIdDchOiqh95924i4/Gkq3hsQjx1CVZk2T6eIQB tVsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b73-v6si8327588itc.127.2018.10.08.11.36.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMJ-0005wM-Ic; Mon, 08 Oct 2018 18:34:23 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMI-0005tx-Bk for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:22 +0000 X-Inumbo-ID: 6b3e1984-cb28-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 6b3e1984-cb28-11e8-a8a5-bc764e045a96; Mon, 08 Oct 2018 20:31:49 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ABCA2ED1; Mon, 8 Oct 2018 11:34:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BE78B3F5B3; Mon, 8 Oct 2018 11:34:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:52 +0100 Message-Id: <20181008183352.16291-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 16/16] xen/arm: Track page accessed between batch of Set/Way operations X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: sstabellini@kernel.org, Wei Liu , Konrad Rzeszutek Wilk , George Dunlap , Andrew Cooper , Ian Jackson , andre.przywara@linaro.org, Tim Deegan , Julien Grall , Jan Beulich MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, the implementation of Set/Way operations will go through all the entries of the guest P2M and flush them. However, this is very expensive and may render unusable a guest OS using them. For instance, Linux 32-bit will use Set/Way operations during secondary CPU bring-up. As the implementation is really expensive, it may be possible to hit the CPU bring-up timeout. To limit the Set/Way impact, we track what pages has been of the guest has been accessed between batch of Set/Way operations. This is done using bit[0] (aka valid bit) of the P2M entry. This patch adds a new per-arch helper is introduced to perform actions just before the guest is first unpaused. This will be used to invalidate the P2M to track access from the start of the guest. Signed-off-by: Julien Grall --- Cc: Stefano Stabellini Cc: Julien Grall Cc: Andrew Cooper Cc: George Dunlap Cc: Ian Jackson Cc: Jan Beulich Cc: Konrad Rzeszutek Wilk Cc: Tim Deegan Cc: Wei Liu --- xen/arch/arm/domain.c | 14 ++++++++++++++ xen/arch/arm/domain_build.c | 7 +++++++ xen/arch/arm/p2m.c | 32 +++++++++++++++++++++++++++++++- xen/arch/x86/domain.c | 4 ++++ xen/common/domain.c | 5 ++++- xen/include/asm-arm/p2m.h | 2 ++ xen/include/xen/domain.h | 2 ++ 7 files changed, 64 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index feebbf5a92..f439f4657a 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -738,6 +738,20 @@ int arch_domain_soft_reset(struct domain *d) return -ENOSYS; } +void arch_domain_creation_finished(struct domain *d) +{ + /* + * To avoid flushing the whole guest RAM on the first Set/Way, we + * invalidate the P2M to track what has been accessed. + * + * This is only turned when IOMMU is not used or the page-table are + * not shared because bit[0] (e.g valid bit) unset will result + * IOMMU fault that could be not fixed-up. + */ + if ( !iommu_use_hap_pt(d) ) + p2m_invalidate_root(p2m_get_hostp2m(d)); +} + static int is_guest_pv32_psr(uint32_t psr) { switch (psr & PSR_MODE_MASK) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index f552154e93..de96516faa 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2249,6 +2249,13 @@ int __init construct_dom0(struct domain *d) v->is_initialised = 1; clear_bit(_VPF_down, &v->pause_flags); + /* + * XXX: We probably want a command line option to invalidate or not + * the P2M. This is because invalidating the P2M will not work with + * IOMMU, however if this is not done there will be an impact. + */ + p2m_invalidate_root(p2m_get_hostp2m(d)); + return 0; } diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index a3d4c563b1..8e0c31d7ac 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1079,6 +1079,22 @@ static void p2m_invalidate_table(struct p2m_domain *p2m, mfn_t mfn) p2m->need_flush = true; } +/* + * Invalidate all entries in the root page-tables. This is + * useful to get fault on entry and do an action. + */ +void p2m_invalidate_root(struct p2m_domain *p2m) +{ + unsigned int i; + + p2m_write_lock(p2m); + + for ( i = 0; i < P2M_ROOT_LEVEL; i++ ) + p2m_invalidate_table(p2m, page_to_mfn(p2m->root + i)); + + p2m_write_unlock(p2m); +} + bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) { struct p2m_domain *p2m = p2m_get_hostp2m(d); @@ -1539,7 +1555,8 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) for ( ; gfn_x(start) < gfn_x(end); start = next_gfn ) { - mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, NULL); + bool valid; + mfn_t mfn = p2m_get_entry(p2m, start, &t, NULL, &order, &valid); next_gfn = gfn_next_boundary(start, order); @@ -1547,6 +1564,13 @@ int p2m_cache_flush_range(struct domain *d, gfn_t start, gfn_t end) if ( mfn_eq(mfn, INVALID_MFN) || !p2m_is_any_ram(t) ) continue; + /* + * Page with valid bit (bit [0]) unset does not need to be + * cleaned + */ + if ( !valid ) + continue; + /* XXX: Implement preemption */ while ( gfn_x(start) < gfn_x(next_gfn) ) { @@ -1571,6 +1595,12 @@ static void p2m_flush_vm(struct vcpu *v) /* XXX: Handle preemption */ p2m_cache_flush_range(v->domain, p2m->lowest_mapped_gfn, p2m->max_mapped_gfn); + + /* + * Invalidate the p2m to track which page was modified by the guest + * between call of p2m_flush_vm(). + */ + p2m_invalidate_root(p2m); } /* diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 9371efc8c7..2b6d1c01a1 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -723,6 +723,10 @@ int arch_domain_soft_reset(struct domain *d) return ret; } +void arch_domain_creation_finished(struct domain *d) +{ +} + /* * These are the masks of CR4 bits (subject to hardware availability) which a * PV guest may not legitimiately attempt to modify. diff --git a/xen/common/domain.c b/xen/common/domain.c index 65151e2ac4..b402c635f9 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1100,8 +1100,11 @@ int domain_unpause_by_systemcontroller(struct domain *d) * Creation is considered finished when the controller reference count * first drops to 0. */ - if ( new == 0 ) + if ( new == 0 && !d->creation_finished ) + { d->creation_finished = true; + arch_domain_creation_finished(d); + } domain_unpause(d); diff --git a/xen/include/asm-arm/p2m.h b/xen/include/asm-arm/p2m.h index c470f062db..2a4652e7f4 100644 --- a/xen/include/asm-arm/p2m.h +++ b/xen/include/asm-arm/p2m.h @@ -225,6 +225,8 @@ int p2m_set_entry(struct p2m_domain *p2m, p2m_type_t t, p2m_access_t a); +void p2m_invalidate_root(struct p2m_domain *p2m); + /* * Clean & invalidate caches corresponding to a region [start,end) of guest * address space. diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 5e393fd7f2..8d95ad4bf1 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -70,6 +70,8 @@ void arch_domain_unpause(struct domain *d); int arch_domain_soft_reset(struct domain *d); +void arch_domain_creation_finished(struct domain *d); + void arch_p2m_set_access_required(struct domain *d, bool access_required); int arch_set_info_guest(struct vcpu *, vcpu_guest_context_u);