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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.02.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:02:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:43 +0100 Message-Id: <20181023070253.6407-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 01/10] cputlb: Move tlb_lock to CPUTLBCommon X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the first of several moves to reduce the size of the CPU_COMMON_TLB macro and improve some locality of refernce. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 17 ++++++++++++--- accel/tcg/cputlb.c | 48 ++++++++++++++++++++--------------------- 2 files changed, 38 insertions(+), 27 deletions(-) -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4ff62f32bf..9005923b4d 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,10 +141,21 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; +/* + * Data elements that are shared between all MMU modes. + */ +typedef struct CPUTLBCommon { + /* lock serializes updates to tlb_table and tlb_v_table */ + QemuSpin lock; +} CPUTLBCommon; + +/* + * The meaning of each of the MMU modes is defined in the target code. + * Note that NB_MMU_MODES is not yet defined; we can only reference it + * within preprocessor defines that will be expanded later. + */ #define CPU_COMMON_TLB \ - /* The meaning of the MMU modes is defined in the target code. */ \ - /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ - QemuSpin tlb_lock; \ + CPUTLBCommon tlb_c; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af57aca5e4..d4e07056be 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -78,7 +78,7 @@ void tlb_init(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; - qemu_spin_init(&env->tlb_lock); + qemu_spin_init(&env->tlb_c.lock); } /* flush_all_helper: run fn across all cpus @@ -134,15 +134,15 @@ static void tlb_flush_nocheck(CPUState *cpu) tlb_debug("(count: %zu)\n", tlb_flush_count()); /* - * tlb_table/tlb_v_table updates from any thread must hold tlb_lock. + * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock. * However, updates from the owner thread (as is the case here; see the * above assert_cpu_is_self) do not need atomic_set because all reads * that do not hold the lock are performed by the same owner thread. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); @@ -195,7 +195,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -205,7 +205,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); @@ -262,7 +262,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, tlb_hit_page(tlb_entry->addr_code, page); } -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) { @@ -271,7 +271,7 @@ static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, } } -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, target_ulong page) { @@ -304,12 +304,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) } addr &= TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); tb_flush_jmp_cache(cpu, addr); } @@ -345,14 +345,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", addr, mmu_idx_bitmap); - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); tb_flush_jmp_cache(cpu, addr); } @@ -479,7 +479,7 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * te->addr_write with atomic_set. We don't need to worry about this for * oversized guests as MTTCG is disabled for them. * - * Called with tlb_lock held. + * Called with tlb_c.lock held. */ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, uintptr_t start, uintptr_t length) @@ -501,7 +501,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, } /* - * Called with tlb_lock held. + * Called with tlb_c.lock held. * Called only from the vCPU context, i.e. the TLB's owner thread. */ static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s) @@ -511,7 +511,7 @@ static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s) /* This is a cross vCPU call (i.e. another vCPU resetting the flags of * the target vCPU). - * We must take tlb_lock to avoid racing with another vCPU update. The only + * We must take tlb_c.lock to avoid racing with another vCPU update. The only * thing actually updated is the target TLB entry ->addr_write flags. */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) @@ -521,7 +521,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; env = cpu->env_ptr; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -535,10 +535,10 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) length); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } -/* Called with tlb_lock held */ +/* Called with tlb_c.lock held */ static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, target_ulong vaddr) { @@ -557,7 +557,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) assert_cpu_is_self(cpu); vaddr &= TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } @@ -568,7 +568,7 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); } } - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } /* Our TLB does not support large pages, so remember the area covered by @@ -669,7 +669,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, * a longer critical section, but this is not a concern since the TLB lock * is unlikely to be contended. */ - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); @@ -736,7 +736,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, } copy_tlb_helper_locked(te, &tn); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); } /* Add a new TLB entry, but without specifying the memory @@ -917,11 +917,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, /* Found entry in victim tlb, swap tlb and iotlb. */ CPUTLBEntry tmptlb, *tlb = &env->tlb_table[mmu_idx][index]; - qemu_spin_lock(&env->tlb_lock); + qemu_spin_lock(&env->tlb_c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env->tlb_lock); + qemu_spin_unlock(&env->tlb_c.lock); CPUIOTLBEntry tmpio, *io = &env->iotlb[mmu_idx][index]; CPUIOTLBEntry *vio = &env->iotlb_v[mmu_idx][vidx]; From patchwork Tue Oct 23 07:02:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149423 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp347077ljp; Tue, 23 Oct 2018 00:10:04 -0700 (PDT) X-Google-Smtp-Source: AJdET5dNom9f1M6XHpZ6j0J0JY49VN1ZRw2e8j6BzrlSFHmtPi1KwIoPcUCD5pnTELtZycLiBRQV X-Received: by 2002:ac8:1661:: with SMTP id x30-v6mr6971704qtk.67.1540278604264; Tue, 23 Oct 2018 00:10:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540278604; cv=none; d=google.com; s=arc-20160816; b=FRCzdjDquNv0+DI3PH6qKeP4j5RSWgV5gQq2bkHxsJIGcQAucnvN2b8SKkd60eJ5KS O+mEw32iwAOJICwiJzVUIVZymWbQHjDb2wfAaL7V9GcHlVTyPrR/6tXZEKETvU8PLraU gJ/ZI6Hwslvz6C5c1pwnC4B0A8z6bEaaWW2H2Tf3s0StmT13VbHfjQtn9hlIXw9ntNCr iZPfZpWhkVAFLauB5aholheM8AbPUG0j3T9A6ysZIxybKuCjR+aLQQIW2HCc78kV3QlA pQ2c8jqxkGFzyhBhLpbbJDfvaiU2Y4OMbAkEIPu1G8q7wrLFqVUXf/5TEQk4ijokT/13 /2lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JG7Osc2OOobhtx/Fv9qTLXYiyheVjnvDATRHzQrsPmE=; b=uuv/DGKerlRdMIQfHKJVKWaWf1Qkcumj2L/9xfXqreZMqdvPz82Xi+AAzPNiIxjaW5 mhDumvUJO/DxwZwBtKlHD1R/TehljHLGoa+/ZliBYfrvH1LGf9Y1b9wvQrlU0ChP8NTO a530cJVDrkivUvisKntbMzu+FS7zZXVp9WfFFn0TJH8IPG0J4QF5Wa20yNVxbvB4gry1 wF4NYj7Qsdldq/PWN1QbLwtFs/BY8fTHrBTtMy7XIEsMb0BrEHxvvv6wQjvHDh9LNuub sV3zu4gojpTlwxHTy0X0El/tcNBW39Qmz6+a/UM8zcZstK4TOPCe6RS/Y2VGXBODDTdn 5FOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c3hf+cbI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.02.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:45 +0100 Message-Id: <20181023070253.6407-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 02/10] cputlb: Remove tcg_enabled hack from tlb_flush_nocheck X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The bugs this was working around were fixed with commits 022d6378c7fd target/unicore32: remove tlb_flush from uc32_init_fn 6e11beecfde0 target/alpha: remove tlb_flush from alpha_cpu_initfn Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 7 ------- 1 file changed, 7 deletions(-) -- 2.17.2 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d4e07056be..d080769c83 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -122,13 +122,6 @@ static void tlb_flush_nocheck(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; - /* The QOM tests will trigger tlb_flushes without setting up TCG - * so we bug out here in that case. - */ - if (!tcg_enabled()) { - return; - } - assert_cpu_is_self(cpu); atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); tlb_debug("(count: %zu)\n", tlb_flush_count()); From patchwork Tue Oct 23 07:02:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149421 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp344805ljp; Tue, 23 Oct 2018 00:07:25 -0700 (PDT) X-Google-Smtp-Source: ACcGV605gOp76oN/Wei0fTUrgP9KgUHkVuss5dR5MhXpqqSvXfaAyUb/MZqQClLTeRTs4roAi1FA X-Received: by 2002:a0c:98a6:: with SMTP id f35mr31819791qvd.224.1540278445588; Tue, 23 Oct 2018 00:07:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540278445; cv=none; d=google.com; s=arc-20160816; b=izLbxbVp5Gp7js0vLwlvM8ADXARTpLzXYGafZduKq8TfY4nXzJ/AM3aFUU2OB4fWOH LlgH0V23SpfI1I8toE+tZeaw0psGCU+ZPxdk8SQ5DJgwpjv/HLPjW0rsOGwlqeNoYjpc uV51olZsqag5ioqHTxlj2IIaVxffmCXiLsgw/ycTJnp3A4esU7Off9GZ5USptzq2k7cj l//A9M/dFSngW9ywRYcwpZRs1XH4K8Z+rrNEWpjw2nNwyRDz5Q9nsV6EgNr60ckQuGPs UhMFbb9sTN9yYuCHNvTX85kh25Q+OQr7miw6Rp9jtapqmPOlKqr7DfwBK6KX0HgKWJrt cdZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QdTT+aLrclDVCRWmE+2W7664wr38LJMnccto55aX5rU=; b=MzVFnqP6EgMpmgnnatwNm9IiraIfMY7VOrLbPz3XS+8Mrtw3HXGr3fFoT3qRDqzBip F+6pZ4w3BhzYocqvCZjUCRGk0F1FtUTOAc85YrMtR5dYnbgWKEKnJ1bUVUTnqX3nSGaN +4upezlIyCh0SODfP9dAVkcYOTVy0XARYItpTIzSHrq7VnIXO41mK5sPWiiwmBOjgEEM 4xrNDwxjIOFkWsnHp7nNPBB/2m99KmyjDYftNQmZt647Z+AynMZsycIe1j+kYBzXF97x RX2jTIZnGkrwo8t2k3jrqPYoRqqHiGGAs664gxBCo0N8YaAhj+ri9BhEy73TwMerX0r3 WeWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C+L3V7zy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k2-v6si369395qta.193.2018.10.23.00.07.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 23 Oct 2018 00:07:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C+L3V7zy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqmi-00006c-88 for patch@linaro.org; Tue, 23 Oct 2018 03:07:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60133) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gEqm3-0008Ro-Kl for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gEqid-0003tD-S9 for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:17 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51615) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gEqid-0003kv-EJ for qemu-devel@nongnu.org; Tue, 23 Oct 2018 03:03:11 -0400 Received: by mail-wm1-x341.google.com with SMTP id 143-v6so529641wmf.1 for ; Tue, 23 Oct 2018 00:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QdTT+aLrclDVCRWmE+2W7664wr38LJMnccto55aX5rU=; b=C+L3V7zyozzMFDWJc+WI5FRj7HtMHHcz8Mtg56XUKHiGYVoo8f/d40jr1zIAn/B+nw f4+LRieEWfZV90BJfgbRUbvhYLNDX15SeNYcruW/o2O+FoLIcMNBB6cKmLtjKEsP9Sja C8yR89z3QoSPRT1Czv6e/xOlsngh5hjMPYzlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QdTT+aLrclDVCRWmE+2W7664wr38LJMnccto55aX5rU=; b=ZB2pgXQxSTVE1vmls2pNvkP2UOACoD/NiZK0hqpnjxoOX61NkpYS4Zj2E/lkZII2HF TyId3iPkDMq1xSa6PwHSyMeJGuCrupuub+LHNOPg5CkjTHuttZTwy6Tjv9geGWiCVdZd Ydia3m3DRlzcptTmmy18gYMXX0QMIsZ+oNZEd8yvjrJOuTCRGhTun5mkHV/tXa0UfXUx 0oP32AQrw/YXdEBcICH2xybz860hHeErm3DDtasMPHUXchXrwZfhsTXwe1eCtOq4q12y qIR8uLwPgTKZO6j+CFc6lltHzlA/B2fij9YE8wg3vb2n2M1tj7PvuikT95gyBD0Eafa9 eX8g== X-Gm-Message-State: ABuFfohdnx/5sx5duFlnx+GIQkSNBdHczxr9WZE/kgFuXP+hOVkdt4tr 9iEptGFFJkiuiDyNNqogmMl8j43VbcY= X-Received: by 2002:a1c:8bcc:: with SMTP id n195-v6mr20008600wmd.118.1540278182725; Tue, 23 Oct 2018 00:03:02 -0700 (PDT) Received: from cloudburst.twiddle.net.ASUS (host86-153-40-62.range86-153.btcentralplus.com. [86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:46 +0100 Message-Id: <20181023070253.6407-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 03/10] cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Protect it with the tlb_lock instead of using atomics. The move puts it in or near the same cacheline as the lock; using the lock means we don't need a second atomic operation in order to perform the update. Which makes it cheap to also update pending_flush in tlb_flush_by_mmuidx_async_work. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 8 +++++++- include/qom/cpu.h | 6 ------ accel/tcg/cputlb.c | 35 +++++++++++++++++++++++------------ 3 files changed, 30 insertions(+), 19 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9005923b4d..659c73d2a1 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -145,8 +145,14 @@ typedef struct CPUIOTLBEntry { * Data elements that are shared between all MMU modes. */ typedef struct CPUTLBCommon { - /* lock serializes updates to tlb_table and tlb_v_table */ + /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */ QemuSpin lock; + /* + * Within pending_flush, for each bit N, there exists an outstanding + * cross-cpu flush for mmu_idx N. Further cross-cpu flushes to that + * mmu_idx may be discarded. Protected by tlb_c.lock. + */ + uint16_t pending_flush; } CPUTLBCommon; /* diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4e238b0d9f..c0d13064c9 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -429,12 +429,6 @@ struct CPUState { struct hax_vcpu_state *hax_vcpu; - /* The pending_tlb_flush flag is set and cleared atomically to - * avoid potential races. The aim of the flag is to avoid - * unnecessary flushes. - */ - uint16_t pending_tlb_flush; - int hvf_fd; /* track IOMMUs whose translations we've cached in the TCG TLB */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d080769c83..abcd08a8a2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -133,6 +133,7 @@ static void tlb_flush_nocheck(CPUState *cpu) * that do not hold the lock are performed by the same owner thread. */ qemu_spin_lock(&env->tlb_c.lock); + env->tlb_c.pending_flush = 0; memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); qemu_spin_unlock(&env->tlb_c.lock); @@ -142,8 +143,6 @@ static void tlb_flush_nocheck(CPUState *cpu) env->vtlb_index = 0; env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; - - atomic_mb_set(&cpu->pending_tlb_flush, 0); } static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data) @@ -154,8 +153,15 @@ static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data) void tlb_flush(CPUState *cpu) { if (cpu->created && !qemu_cpu_is_self(cpu)) { - if (atomic_mb_read(&cpu->pending_tlb_flush) != ALL_MMUIDX_BITS) { - atomic_mb_set(&cpu->pending_tlb_flush, ALL_MMUIDX_BITS); + CPUArchState *env = cpu->env_ptr; + uint16_t pending; + + qemu_spin_lock(&env->tlb_c.lock); + pending = env->tlb_c.pending_flush; + env->tlb_c.pending_flush = ALL_MMUIDX_BITS; + qemu_spin_unlock(&env->tlb_c.lock); + + if (pending != ALL_MMUIDX_BITS) { async_run_on_cpu(cpu, tlb_flush_global_async_work, RUN_ON_CPU_NULL); } @@ -189,6 +195,8 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); qemu_spin_lock(&env->tlb_c.lock); + env->tlb_c.pending_flush &= ~mmu_idx_bitmask; + for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -210,19 +218,22 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); if (!qemu_cpu_is_self(cpu)) { - uint16_t pending_flushes = idxmap; - pending_flushes &= ~atomic_mb_read(&cpu->pending_tlb_flush); + CPUArchState *env = cpu->env_ptr; + uint16_t pending, to_clean; - if (pending_flushes) { - tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", pending_flushes); + qemu_spin_lock(&env->tlb_c.lock); + pending = env->tlb_c.pending_flush; + to_clean = idxmap & ~pending; + env->tlb_c.pending_flush = pending | idxmap; + qemu_spin_unlock(&env->tlb_c.lock); - atomic_or(&cpu->pending_tlb_flush, pending_flushes); + if (to_clean) { + tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", to_clean); async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, - RUN_ON_CPU_HOST_INT(pending_flushes)); + RUN_ON_CPU_HOST_INT(to_clean)); } } else { - tlb_flush_by_mmuidx_async_work(cpu, - RUN_ON_CPU_HOST_INT(idxmap)); + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); } } From patchwork Tue Oct 23 07:02:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149431 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp353736ljp; Tue, 23 Oct 2018 00:18:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV61ax/EUJsskxXRRh1pgmSDzRrHJJw7uX97eu81uTY9vYjTejyheIanPtF/wr3xRYoM13M9b X-Received: by 2002:a37:9442:: with SMTP id w63-v6mr46203093qkd.304.1540279131419; Tue, 23 Oct 2018 00:18:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540279131; cv=none; d=google.com; s=arc-20160816; b=syQodHJawES8ZBd16XALPRPqAfOl4CBhH0HBsxT0lqhii+2tPWa/PIbHbsUBM0qgI/ unqjYXVddyHZqDlC6hRK52YQHrzEkbeaVF/vlsMZNN+pMFIaQsgaQy34SuFtDk2B1HYM N0Wx7SekLrlEYHumRgTftTM996xK6It9EwHefLV93GxTAnhwEOCpZCKk4l27USd8zhTT 5K/0rNQZ3gVA8IK9s2LP74/vag9ZvOS8XkO/49rMNZmuappCv+hVKnCDMIXb3XDCyoKc gew10xYFD/l62FCM6Z5yPa8hk1NsucWPJuRtXdzTMT6Ae/3qy9s3uNuL5rzEG7/lzsv+ y/YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ei4NQbVPRIt5lqbMkVeEwvfJAULjrp+cmAiYYkxBlVk=; b=y9Vp+3yuV0ezUzrXSDAHs6ZUbYUrzm0RV46VbpRPl6N3/5D4d7Wk2UbRpLKBm9pSvA 4qJkk+20MzVWUR+iLQ+eOIQ51GcxWV7dpzrKxWU0/XtbeEN6vTygYaW6WWtIbz1XuEnT 8TAqT5wL1F3uRnzSOYCfI6omEyUQhjcp4crdKZagON91v2cx9sKSK/xgrKt58yR64B3H CEQ+bdtwR9cJNhNe9LoFWG0awj22mz8WVd6C8CpsfrhogfhYpCFlco61CBCZq4I/hfPB NANQ1Wa5Tkst73YX2sHfy0ugd9SyczzcxWfFPvyTRzaaOV9tRgy+4L2q/MOrd9syr0iJ /Lyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TBsGqLQd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:47 +0100 Message-Id: <20181023070253.6407-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 04/10] cputlb: Split large page tracking per mmu_idx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The set of large pages in the kernel is probably not the same as the set of large pages in the application. Forcing one range to cover both will flush more often than necessary. This allows tlb_flush_page_async_work to flush just the one mmu_idx implicated, which in turn allows us to remove tlb_check_page_and_flush_by_mmuidx_async_work. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 14 +++- accel/tcg/cputlb.c | 139 ++++++++++++++++++---------------------- 2 files changed, 74 insertions(+), 79 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 659c73d2a1..df8ae18d9d 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,6 +141,17 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; +typedef struct CPUTLBDesc { + /* + * Describe a region covering all of the large pages allocated + * into the tlb. When any page within this region is flushed, + * we must flush the entire tlb. The region is matched if + * (addr & large_page_mask) == large_page_addr. + */ + target_ulong large_page_addr; + target_ulong large_page_mask; +} CPUTLBDesc; + /* * Data elements that are shared between all MMU modes. */ @@ -162,13 +173,12 @@ typedef struct CPUTLBCommon { */ #define CPU_COMMON_TLB \ CPUTLBCommon tlb_c; \ + CPUTLBDesc tlb_d[NB_MMU_MODES]; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ size_t tlb_flush_count; \ - target_ulong tlb_flush_addr; \ - target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index abcd08a8a2..72b0567f70 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -113,6 +113,14 @@ size_t tlb_flush_count(void) return count; } +static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) +{ + memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); + memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); + env->tlb_d[mmu_idx].large_page_addr = -1; + env->tlb_d[mmu_idx].large_page_mask = -1; +} + /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so * flushing more entries than required is only an efficiency issue, @@ -121,6 +129,7 @@ size_t tlb_flush_count(void) static void tlb_flush_nocheck(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; + int mmu_idx; assert_cpu_is_self(cpu); atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); @@ -134,15 +143,14 @@ static void tlb_flush_nocheck(CPUState *cpu) */ qemu_spin_lock(&env->tlb_c.lock); env->tlb_c.pending_flush = 0; - memset(env->tlb_table, -1, sizeof(env->tlb_table)); - memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); + for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + tlb_flush_one_mmuidx_locked(env, mmu_idx); + } qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); env->vtlb_index = 0; - env->tlb_flush_addr = -1; - env->tlb_flush_mask = 0; } static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data) @@ -192,25 +200,19 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) assert_cpu_is_self(cpu); - tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); + tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask); qemu_spin_lock(&env->tlb_c.lock); env->tlb_c.pending_flush &= ~mmu_idx_bitmask; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmask)) { - tlb_debug("%d\n", mmu_idx); - - memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); - memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); + tlb_flush_one_mmuidx_locked(env, mmu_idx); } } qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); - - tlb_debug("done\n"); } void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) @@ -287,6 +289,25 @@ static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_idx, } } +static void tlb_flush_page_locked(CPUArchState *env, int midx, + target_ulong addr) +{ + target_ulong lp_addr = env->tlb_d[midx].large_page_addr; + target_ulong lp_mask = env->tlb_d[midx].large_page_mask; + + /* Check if we need to flush due to large pages. */ + if ((addr & lp_mask) == lp_addr) { + tlb_debug("forcing full flush midx %d (" + TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + midx, lp_addr, lp_mask); + tlb_flush_one_mmuidx_locked(env, midx); + } else { + int pidx = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_flush_entry_locked(&env->tlb_table[midx][pidx], addr); + tlb_flush_vtlb_page_locked(env, midx, addr); + } +} + static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) { CPUArchState *env = cpu->env_ptr; @@ -295,23 +316,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) assert_cpu_is_self(cpu); - tlb_debug("page :" TARGET_FMT_lx "\n", addr); - - /* Check if we need to flush due to large pages. */ - if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { - tlb_debug("forcing full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); - - tlb_flush(cpu); - return; - } + tlb_debug("page addr:" TARGET_FMT_lx "\n", addr); addr &= TARGET_PAGE_MASK; qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); - tlb_flush_vtlb_page_locked(env, mmu_idx, addr); + tlb_flush_page_locked(env, mmu_idx, addr); } qemu_spin_unlock(&env->tlb_c.lock); @@ -346,14 +356,13 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, assert_cpu_is_self(cpu); - tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", + tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%lx\n", addr, mmu_idx_bitmap); qemu_spin_lock(&env->tlb_c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); - tlb_flush_vtlb_page_locked(env, mmu_idx, addr); + tlb_flush_page_locked(env, mmu_idx, addr); } } qemu_spin_unlock(&env->tlb_c.lock); @@ -361,29 +370,6 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUState *cpu, tb_flush_jmp_cache(cpu, addr); } -static void tlb_check_page_and_flush_by_mmuidx_async_work(CPUState *cpu, - run_on_cpu_data data) -{ - CPUArchState *env = cpu->env_ptr; - target_ulong addr_and_mmuidx = (target_ulong) data.target_ptr; - target_ulong addr = addr_and_mmuidx & TARGET_PAGE_MASK; - unsigned long mmu_idx_bitmap = addr_and_mmuidx & ALL_MMUIDX_BITS; - - tlb_debug("addr:"TARGET_FMT_lx" mmu_idx: %04lx\n", addr, mmu_idx_bitmap); - - /* Check if we need to flush due to large pages. */ - if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) { - tlb_debug("forced full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); - - tlb_flush_by_mmuidx_async_work(cpu, - RUN_ON_CPU_HOST_INT(mmu_idx_bitmap)); - } else { - tlb_flush_page_by_mmuidx_async_work(cpu, data); - } -} - void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap) { target_ulong addr_and_mmu_idx; @@ -395,10 +381,10 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap) addr_and_mmu_idx |= idxmap; if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_check_page_and_flush_by_mmuidx_async_work, + async_run_on_cpu(cpu, tlb_flush_page_by_mmuidx_async_work, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } else { - tlb_check_page_and_flush_by_mmuidx_async_work( + tlb_flush_page_by_mmuidx_async_work( cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } } @@ -406,7 +392,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap) void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr, uint16_t idxmap) { - const run_on_cpu_func fn = tlb_check_page_and_flush_by_mmuidx_async_work; + const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work; target_ulong addr_and_mmu_idx; tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); @@ -420,10 +406,10 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr, } void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap) + target_ulong addr, + uint16_t idxmap) { - const run_on_cpu_func fn = tlb_check_page_and_flush_by_mmuidx_async_work; + const run_on_cpu_func fn = tlb_flush_page_by_mmuidx_async_work; target_ulong addr_and_mmu_idx; tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); @@ -577,25 +563,26 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) /* Our TLB does not support large pages, so remember the area covered by large pages and trigger a full TLB flush if these are invalidated. */ -static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, - target_ulong size) +static void tlb_add_large_page(CPUArchState *env, int mmu_idx, + target_ulong vaddr, target_ulong size) { - target_ulong mask = ~(size - 1); + target_ulong lp_addr = env->tlb_d[mmu_idx].large_page_addr; + target_ulong lp_mask = ~(size - 1); - if (env->tlb_flush_addr == (target_ulong)-1) { - env->tlb_flush_addr = vaddr & mask; - env->tlb_flush_mask = mask; - return; + if (lp_addr == (target_ulong)-1) { + /* No previous large page. */ + lp_addr = vaddr; + } else { + /* Extend the existing region to include the new page. + This is a compromise between unnecessary flushes and + the cost of maintaining a full variable size TLB. */ + lp_mask &= env->tlb_d[mmu_idx].large_page_mask; + while (((lp_addr ^ vaddr) & lp_mask) != 0) { + lp_mask <<= 1; + } } - /* Extend the existing region to include the new page. - This is a compromise between unnecessary flushes and the cost - of maintaining a full variable size TLB. */ - mask &= env->tlb_flush_mask; - while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) { - mask <<= 1; - } - env->tlb_flush_addr &= mask; - env->tlb_flush_mask = mask; + env->tlb_d[mmu_idx].large_page_addr = lp_addr & lp_mask; + env->tlb_d[mmu_idx].large_page_mask = lp_mask; } /* Add a new TLB entry. At most one entry for a given virtual address @@ -622,12 +609,10 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, assert_cpu_is_self(cpu); - if (size < TARGET_PAGE_SIZE) { + if (size <= TARGET_PAGE_SIZE) { sz = TARGET_PAGE_SIZE; } else { - if (size > TARGET_PAGE_SIZE) { - tlb_add_large_page(env, vaddr, size); - } + tlb_add_large_page(env, mmu_idx, vaddr, size); sz = size; } vaddr_page = vaddr & TARGET_PAGE_MASK; From patchwork Tue Oct 23 07:02:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149422 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp344835ljp; Tue, 23 Oct 2018 00:07:28 -0700 (PDT) X-Google-Smtp-Source: AJdET5cK6HrK91FleBcEOIVDQiqVu6MvR6LZcNLdKODyiCg1Lo5yDZJP8dtyz8GlxkYjsDumCHnv X-Received: by 2002:a37:d4d9:: with SMTP id s86mr2630626qks.190.1540278448198; Tue, 23 Oct 2018 00:07:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540278448; cv=none; d=google.com; s=arc-20160816; b=ikr4/uhrpc/HBkzprE3r8bq8wcBvkhHxmu5IfgyGMy988DruQRiaENuwwzPDbI/abQ qWxVrYT1Ia2QSKJ2n7sImJEybgGD/azIPI8IMIxLxEnoQ26SAJIDX27wMXkdU+aVVqfx ep60gU3yYVLG7Ru/V57zhDoeDtIolqgMhQlfJqQDjMfifgEBCMIuBcFgJHZ35dbnHHJo 2T/W8SZKPjU7TAVOEPwQMgJR+IJzhXX9S2h3ZtPaXwU7RgmkbudgNaFw1SFEhMI3TmI8 qGwT5FDQ/1jNsFxyvlGzk1Gkwy5uRTK2+2GdH7aVNFPjAeffDTaE0U8UPDzkOPMpHyeM 4IXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/KAHHOKz5/09uNy3szZc7ufuP1mXp9/ljoylRihFv20=; b=FbIHcO59mP0sZziU5nFw+M3w4A9WqSoI8zPWRWqQmdY8Xo8qnFDCX38HlbtMpkLXiw WtzJxDlsn9LJCoBCMnQNinl5OIIrfMUQnVKNHeJoZ5mz7eiX/UjkiAt1ZluN4+Fe8rI8 JL9en6aWT/01Em1LABVGR6Xun2HCRi8oL+1ERO9DzaErvaBruEokCvec5jMeQDFG76bo 9hfhsCJjheLDqhi7BhRH6iltL8mlWG+ZfBrhykypm6EYTytrXDzYcbrHhtCD9SkoRYdq dv1ZkgINR0077PImO5xwnCPiHPXPNJObbT+/tDYB1muTJYqK9mmJ/nCopYGOkl7KD09n C9Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SbIop8mc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:48 +0100 Message-Id: <20181023070253.6407-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 05/10] cputlb: Move env->vtlb_index to env->tlb_d.vindex X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The rest of the tlb victim cache is per-tlb, the next use index should be as well. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 5 +++-- accel/tcg/cputlb.c | 5 ++--- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index df8ae18d9d..181c0dbfa4 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -150,6 +150,8 @@ typedef struct CPUTLBDesc { */ target_ulong large_page_addr; target_ulong large_page_mask; + /* The next index to use in the tlb victim table. */ + size_t vindex; } CPUTLBDesc; /* @@ -178,8 +180,7 @@ typedef struct CPUTLBCommon { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - size_t tlb_flush_count; \ - target_ulong vtlb_index; \ + size_t tlb_flush_count; #else diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 72b0567f70..d3b37ffa85 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -119,6 +119,7 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0])); env->tlb_d[mmu_idx].large_page_addr = -1; env->tlb_d[mmu_idx].large_page_mask = -1; + env->tlb_d[mmu_idx].vindex = 0; } /* This is OK because CPU architectures generally permit an @@ -149,8 +150,6 @@ static void tlb_flush_nocheck(CPUState *cpu) qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); - - env->vtlb_index = 0; } static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data) @@ -668,7 +667,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, * different page; otherwise just overwrite the stale data. */ if (!tlb_hit_page_anyprot(te, vaddr_page)) { - unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; + unsigned vidx = env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; CPUTLBEntry *tv = &env->tlb_v_table[mmu_idx][vidx]; /* Evict the old entry into the victim tlb. */ From patchwork Tue Oct 23 07:02:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149420 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp344795ljp; Tue, 23 Oct 2018 00:07:24 -0700 (PDT) X-Google-Smtp-Source: AJdET5eIL+nsVtaOh8Z0rGblbSiJibRGbqGqUkxpUjnS86KU2GC6MRgbiwMWoj6oR4jCSCodf2ZO X-Received: by 2002:a37:1509:: with SMTP id f9mr1052953qkh.271.1540278444629; Tue, 23 Oct 2018 00:07:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540278444; cv=none; d=google.com; s=arc-20160816; b=UxfBietTiTNEQn1ZUAPlSTf8KcKi+nqzB6oSqcMxZgruaD5HysK7jQ51IXBESMk2Xs 8FVCl2XtHdZU/5BnR7MkYJSQgz2Ffq6ooZQiUvSZD+/jdYt2UnBAM9JqM7M9ZjaFr9dk /B5ju8zFa2xA+nTCD91jl43X+pyW7EyMmT5fWdEGQNNsmNcjo7klGap+wWRBktxopwK8 wCBPW/ek51ELCJ9RexiauRjXcWYEbadw1gtJd09GhO0iQ4pV4pgCcuFPNuy5Js5pM8wS eei00+WJ9WTgRgHbv/9PMFjlqa3bV2M/7xsK2W9cY2ScuP7TbXJBXTSsC41VXgsO0WB8 UI3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kk1qq57GJPL/Lh6dxNjkZlKloxkDADekJnNQMyq/28E=; b=P+T+H3KMNHB9Xh5iYOcuBbeIWJ4xxOKOHm6X2wQBSmmV1zwyDvQvRfeXh+HKzNRkGY v8Lekpwe55XEkEtcyeEXnze3a3C1pkjhm3+HB2AkcPsyWkdqLlDXKm0fJ7ZEk56YNCfy MoiBMv0zZBOjeD7FWotQ3E9c22CFQaRtOKXTnny9iyQLC9s5rBWhsLdyzDxyrLNwS9yh V8BaNOVQ/2Hkdyb92PBE9GLKccjhX9GdHVM6BNeBhUopOZCS3tqlIQU5cxqiqSRqLjtX 5dzkI3DRMneS0ijlCIR69O3mCOA3fzA5QQ0t3+F0xV+XT9BInxiC5amBRvKOr1p9EkZc aCpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CbFaDFGH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:49 +0100 Message-Id: <20181023070253.6407-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 06/10] cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_work X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The difference between the two sets of APIs is now miniscule. This allows tlb_flush, tlb_flush_all_cpus, and tlb_flush_all_cpus_synced to be merged with their corresponding by_mmuidx functions as well. For accounting, consider mmu_idx_bitmask = ALL_MMUIDX_BITS to be a full flush. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 93 +++++++++++----------------------------------- 1 file changed, 21 insertions(+), 72 deletions(-) -- 2.17.2 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d3b37ffa85..6b0f93ec01 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -122,75 +122,6 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) env->tlb_d[mmu_idx].vindex = 0; } -/* This is OK because CPU architectures generally permit an - * implementation to drop entries from the TLB at any time, so - * flushing more entries than required is only an efficiency issue, - * not a correctness issue. - */ -static void tlb_flush_nocheck(CPUState *cpu) -{ - CPUArchState *env = cpu->env_ptr; - int mmu_idx; - - assert_cpu_is_self(cpu); - atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); - tlb_debug("(count: %zu)\n", tlb_flush_count()); - - /* - * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock. - * However, updates from the owner thread (as is the case here; see the - * above assert_cpu_is_self) do not need atomic_set because all reads - * that do not hold the lock are performed by the same owner thread. - */ - qemu_spin_lock(&env->tlb_c.lock); - env->tlb_c.pending_flush = 0; - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_one_mmuidx_locked(env, mmu_idx); - } - qemu_spin_unlock(&env->tlb_c.lock); - - cpu_tb_jmp_cache_clear(cpu); -} - -static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data) -{ - tlb_flush_nocheck(cpu); -} - -void tlb_flush(CPUState *cpu) -{ - if (cpu->created && !qemu_cpu_is_self(cpu)) { - CPUArchState *env = cpu->env_ptr; - uint16_t pending; - - qemu_spin_lock(&env->tlb_c.lock); - pending = env->tlb_c.pending_flush; - env->tlb_c.pending_flush = ALL_MMUIDX_BITS; - qemu_spin_unlock(&env->tlb_c.lock); - - if (pending != ALL_MMUIDX_BITS) { - async_run_on_cpu(cpu, tlb_flush_global_async_work, - RUN_ON_CPU_NULL); - } - } else { - tlb_flush_nocheck(cpu); - } -} - -void tlb_flush_all_cpus(CPUState *src_cpu) -{ - const run_on_cpu_func fn = tlb_flush_global_async_work; - flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL); - fn(src_cpu, RUN_ON_CPU_NULL); -} - -void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ - const run_on_cpu_func fn = tlb_flush_global_async_work; - flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL); - async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_NULL); -} - static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) { CPUArchState *env = cpu->env_ptr; @@ -212,13 +143,17 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); + + if (mmu_idx_bitmask == ALL_MMUIDX_BITS) { + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + } } void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) { tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); - if (!qemu_cpu_is_self(cpu)) { + if (cpu->created && !qemu_cpu_is_self(cpu)) { CPUArchState *env = cpu->env_ptr; uint16_t pending, to_clean; @@ -238,6 +173,11 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) } } +void tlb_flush(CPUState *cpu) +{ + tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); +} + void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap) { const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work; @@ -248,8 +188,12 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap) fn(src_cpu, RUN_ON_CPU_HOST_INT(idxmap)); } -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - uint16_t idxmap) +void tlb_flush_all_cpus(CPUState *src_cpu) +{ + tlb_flush_by_mmuidx_all_cpus(src_cpu, ALL_MMUIDX_BITS); +} + +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap) { const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work; @@ -259,6 +203,11 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap)); } +void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ + tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS); +} + static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, target_ulong page) { From patchwork Tue Oct 23 07:02:50 2018 Content-Type: text/plain; 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:50 +0100 Message-Id: <20181023070253.6407-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 07/10] cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The difference between the two sets of APIs is now miniscule. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 58 ++++++++++------------------------------------ 1 file changed, 12 insertions(+), 46 deletions(-) -- 2.17.2 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6b0f93ec01..4447a5f028 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -256,38 +256,6 @@ static void tlb_flush_page_locked(CPUArchState *env, int midx, } } -static void tlb_flush_page_async_work(CPUState *cpu, run_on_cpu_data data) -{ - CPUArchState *env = cpu->env_ptr; - target_ulong addr = (target_ulong) data.target_ptr; - int mmu_idx; - - assert_cpu_is_self(cpu); - - tlb_debug("page addr:" TARGET_FMT_lx "\n", addr); - - addr &= TARGET_PAGE_MASK; - qemu_spin_lock(&env->tlb_c.lock); - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_page_locked(env, mmu_idx, addr); - } - qemu_spin_unlock(&env->tlb_c.lock); - - tb_flush_jmp_cache(cpu, addr); -} - -void tlb_flush_page(CPUState *cpu, target_ulong addr) -{ - tlb_debug("page :" TARGET_FMT_lx "\n", addr); - - if (!qemu_cpu_is_self(cpu)) { - async_run_on_cpu(cpu, tlb_flush_page_async_work, - RUN_ON_CPU_TARGET_PTR(addr)); - } else { - tlb_flush_page_async_work(cpu, RUN_ON_CPU_TARGET_PTR(addr)); - } -} - /* As we are going to hijack the bottom bits of the page address for a * mmuidx bit mask we need to fail to build if we can't do that */ @@ -337,6 +305,11 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap) } } +void tlb_flush_page(CPUState *cpu, target_ulong addr) +{ + tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr, uint16_t idxmap) { @@ -353,6 +326,11 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong addr, fn(src_cpu, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } +void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +{ + tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS); +} + void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, target_ulong addr, uint16_t idxmap) @@ -370,21 +348,9 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_TARGET_PTR(addr_and_mmu_idx)); } -void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) { - const run_on_cpu_func fn = tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - fn(src, RUN_ON_CPU_TARGET_PTR(addr)); -} - -void tlb_flush_page_all_cpus_synced(CPUState *src, - target_ulong addr) -{ - const run_on_cpu_func fn = tlb_flush_page_async_work; - - flush_all_helper(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); - async_safe_run_on_cpu(src, fn, RUN_ON_CPU_TARGET_PTR(addr)); + tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } /* update the TLBs so that writes to code in the virtual page 'addr' From patchwork Tue Oct 23 07:02:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149424 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp347522ljp; Tue, 23 Oct 2018 00:10:38 -0700 (PDT) X-Google-Smtp-Source: ACcGV61SGyO0FoYpkMPCtaUP3cpFe7HysCl8E62FrcGmXOQmFk1EOUzDbrwYq9YHMwvelvJaCGw9 X-Received: by 2002:ac8:1a41:: with SMTP id q1-v6mr10206829qtk.329.1540278638656; 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:51 +0100 Message-Id: <20181023070253.6407-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 08/10] cputlb: Count "partial" and "elided" tlb flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Our only statistic so far was "full" tlb flushes, where all mmu_idx are flushed at the same time. Now count "partial" tlb flushes where sets of mmu_idx are flushed, but the set is not maximal. Account one per mmu_idx flushed, as that is the unit of work performed. We don't actually count elided flushes yet, but go ahead and change the interface presented to the monitor all at once. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 12 ++++++++++-- include/exec/cputlb.h | 2 +- accel/tcg/cputlb.c | 18 +++++++++++++----- accel/tcg/translate-all.c | 8 ++++++-- 4 files changed, 30 insertions(+), 10 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 181c0dbfa4..c7b501d627 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -166,6 +166,15 @@ typedef struct CPUTLBCommon { * mmu_idx may be discarded. Protected by tlb_c.lock. */ uint16_t pending_flush; + + /* + * Statistics. These are not lock protected, but are read and + * written atomically. This allows the monitor to print a snapshot + * of the stats without interfering with the cpu. + */ + size_t full_flush_count; + size_t part_flush_count; + size_t elide_flush_count; } CPUTLBCommon; /* @@ -179,8 +188,7 @@ typedef struct CPUTLBCommon { CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ - CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - size_t tlb_flush_count; + CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; #else diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index c91db211bc..5373188be3 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,6 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -size_t tlb_flush_count(void); +void tlb_flush_counts(size_t *full, size_t *part, size_t *elide); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4447a5f028..5480115cb4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -100,17 +100,21 @@ static void flush_all_helper(CPUState *src, run_on_cpu_func fn, } } -size_t tlb_flush_count(void) +void tlb_flush_counts(size_t *pfull, size_t *ppart, size_t *pelide) { CPUState *cpu; - size_t count = 0; + size_t full = 0, part = 0, elide = 0; CPU_FOREACH(cpu) { CPUArchState *env = cpu->env_ptr; - count += atomic_read(&env->tlb_flush_count); + full += atomic_read(&env->tlb_c.full_flush_count); + part += atomic_read(&env->tlb_c.part_flush_count); + elide += atomic_read(&env->tlb_c.elide_flush_count); } - return count; + *pfull = full; + *ppart = part; + *pelide = elide; } static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) @@ -145,7 +149,11 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) cpu_tb_jmp_cache_clear(cpu); if (mmu_idx_bitmask == ALL_MMUIDX_BITS) { - atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + atomic_set(&env->tlb_c.full_flush_count, + env->tlb_c.full_flush_count + 1); + } else { + atomic_set(&env->tlb_c.part_flush_count, + env->tlb_c.part_flush_count + ctpop16(mmu_idx_bitmask)); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 356dcd0948..639f0b2728 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2290,7 +2290,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) { struct tb_tree_stats tst = {}; struct qht_stats hst; - size_t nb_tbs; + size_t nb_tbs, flush_full, flush_part, flush_elide; tcg_tb_foreach(tb_tree_stats_iter, &tst); nb_tbs = tst.nb_tbs; @@ -2326,7 +2326,11 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) cpu_fprintf(f, "TB flush count %u\n", atomic_read(&tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %zu\n", tcg_tb_phys_invalidate_count()); - cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); + + tlb_flush_counts(&flush_full, &flush_part, &flush_elide); + cpu_fprintf(f, "TLB full flushes %zu\n", flush_full); + cpu_fprintf(f, "TLB partial flushes %zu\n", flush_part); + cpu_fprintf(f, "TLB elided flushes %zu\n", flush_elide); tcg_dump_info(f, cpu_fprintf); } From patchwork Tue Oct 23 07:02:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149428 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp349374ljp; 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:52 +0100 Message-Id: <20181023070253.6407-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 09/10] cputlb: Filter flushes on already clean tlbs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Especially for guests with large numbers of tlbs, like ARM or PPC, we may well not use all of them in between flush operations. Remember which tlbs have been used since the last flush, and avoid any useless flushing. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++++++- accel/tcg/cputlb.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c7b501d627..ca0fea8b27 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -166,7 +166,12 @@ typedef struct CPUTLBCommon { * mmu_idx may be discarded. Protected by tlb_c.lock. */ uint16_t pending_flush; - + /* + * Within dirty, for each bit N, modifications have been made to + * mmu_idx N since the last time that mmu_idx was flushed. + * Protected by tlb_c.lock. + */ + uint16_t dirty; /* * Statistics. These are not lock protected, but are read and * written atomically. This allows the monitor to print a snapshot diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5480115cb4..c1b92083d4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -79,6 +79,9 @@ void tlb_init(CPUState *cpu) CPUArchState *env = cpu->env_ptr; qemu_spin_init(&env->tlb_c.lock); + + /* Ensure that cpu_reset performs a full flush. */ + env->tlb_c.dirty = ALL_MMUIDX_BITS; } /* flush_all_helper: run fn across all cpus @@ -129,31 +132,40 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data) { CPUArchState *env = cpu->env_ptr; - unsigned long mmu_idx_bitmask = data.host_int; - int mmu_idx; + uint16_t asked = data.host_int; + uint16_t all_dirty, work, to_clean; assert_cpu_is_self(cpu); - tlb_debug("mmu_idx:0x%04lx\n", mmu_idx_bitmask); + tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); qemu_spin_lock(&env->tlb_c.lock); - env->tlb_c.pending_flush &= ~mmu_idx_bitmask; - for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - if (test_bit(mmu_idx, &mmu_idx_bitmask)) { - tlb_flush_one_mmuidx_locked(env, mmu_idx); - } + all_dirty = env->tlb_c.dirty; + to_clean = asked & all_dirty; + all_dirty &= ~to_clean; + env->tlb_c.dirty = all_dirty; + + for (work = to_clean; work != 0; work &= work - 1) { + int mmu_idx = ctz32(work); + tlb_flush_one_mmuidx_locked(env, mmu_idx); } + qemu_spin_unlock(&env->tlb_c.lock); cpu_tb_jmp_cache_clear(cpu); - if (mmu_idx_bitmask == ALL_MMUIDX_BITS) { + if (to_clean == ALL_MMUIDX_BITS) { atomic_set(&env->tlb_c.full_flush_count, env->tlb_c.full_flush_count + 1); } else { atomic_set(&env->tlb_c.part_flush_count, - env->tlb_c.part_flush_count + ctpop16(mmu_idx_bitmask)); + env->tlb_c.part_flush_count + ctpop16(to_clean)); + if (to_clean != asked) { + atomic_set(&env->tlb_c.elide_flush_count, + env->tlb_c.elide_flush_count + + ctpop16(asked & ~to_clean)); + } } } @@ -582,6 +594,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, */ qemu_spin_lock(&env->tlb_c.lock); + /* Note that the tlb is no longer clean. */ + env->tlb_c.dirty |= 1 << mmu_idx; + /* Make sure there's no cached translation for the new page. */ tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); From patchwork Tue Oct 23 07:02:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149427 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp349355ljp; Tue, 23 Oct 2018 00:13:05 -0700 (PDT) X-Google-Smtp-Source: AJdET5dKmmuS7Zec+9CB5PshDGRpvrIrfg6GoMQWhCNqNt2z2IaHP/o7hpaMO0oMLdlOl2aZySIX X-Received: by 2002:a0c:c38d:: with SMTP id o13mr6600062qvi.100.1540278785871; Tue, 23 Oct 2018 00:13:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540278785; cv=none; d=google.com; s=arc-20160816; b=ND2c/SO01wCkwcUxfZC5AaMxostfFnshP92nczwuy9RBF4nl64vdiVHfg7oFCHAUUF DHBv30zag+9kwysG6UCYw2h/cWW8QNBliznnOz7LWd8jvNZAam5a7SHNSDJOk01rR6tB Pt86IwCofyc7+Xvi8mDjdEWLMGBvk1DTbkIcghnEjHZ0HiqzMa7E75CaKcEfrYV3+vU4 lRRJBxPLOOnf7GQLkRASBtqL2NJL07b4x0z7IjoVR7WkuC6mIlJIafWyB4vXQ8vAOb5c ugsTldPZPF9E+dcv0TRc4x0YnpLRYLqPaNgpiNMzANmWLiLRfeAUZPpIGiAS6SDApKf7 mXSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=j5xnUIyTOJGIGy9FEJsc6tCQO/KhtXScq8nSq+BVdsM=; b=xp2Pu7p5TZQ51Ad2YAwEsogJ0VyKQB+sszgBKDrNs76UUvKAVxVLxQaU58kIxCtrc3 4PH05F+nPcNWbhD9aO65OemlimbbRl1hLIdRVs0ia1fB1s/R6KQkeCMjxqOESP8ZqXhR pW2x/B+oeHbZ9nt75sYigYoQCDrqIE8Hk+pFyDhnpI/MzGv6nrR77OwUkmejfWqNCpEk PQC+YYZ6UoPEiIZkNWndEqaVBI9+tErusnylv+jc0sDkrvVrNMmj/vYfV5s7tuiR63N9 vzhgSen7at7MmYYRuymnU4+mJHph7J1/Wfk3TSVgHZxp/xRciWro7hVQSKduWvNsKNzt Q0gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bwxc7xLL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[86.153.40.62]) by smtp.gmail.com with ESMTPSA id t13-v6sm258355wrn.22.2018.10.23.00.03.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Oct 2018 00:03:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 08:02:53 +0100 Message-Id: <20181023070253.6407-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181023070253.6407-1-richard.henderson@linaro.org> References: <20181023070253.6407-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 10/10] cputlb: Remove tlb_c.pending_flushes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is essentially redundant with tlb_c.dirty. [??? Collect data to back up this supposition] Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 6 ------ accel/tcg/cputlb.c | 16 ++-------------- 2 files changed, 2 insertions(+), 20 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ca0fea8b27..6a60f94a41 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -160,12 +160,6 @@ typedef struct CPUTLBDesc { typedef struct CPUTLBCommon { /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */ QemuSpin lock; - /* - * Within pending_flush, for each bit N, there exists an outstanding - * cross-cpu flush for mmu_idx N. Further cross-cpu flushes to that - * mmu_idx may be discarded. Protected by tlb_c.lock. - */ - uint16_t pending_flush; /* * Within dirty, for each bit N, modifications have been made to * mmu_idx N since the last time that mmu_idx was flushed. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c1b92083d4..fec37bd3bd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -174,20 +174,8 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); if (cpu->created && !qemu_cpu_is_self(cpu)) { - CPUArchState *env = cpu->env_ptr; - uint16_t pending, to_clean; - - qemu_spin_lock(&env->tlb_c.lock); - pending = env->tlb_c.pending_flush; - to_clean = idxmap & ~pending; - env->tlb_c.pending_flush = pending | idxmap; - qemu_spin_unlock(&env->tlb_c.lock); - - if (to_clean) { - tlb_debug("reduced mmu_idx: 0x%" PRIx16 "\n", to_clean); - async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, - RUN_ON_CPU_HOST_INT(to_clean)); - } + async_run_on_cpu(cpu, tlb_flush_by_mmuidx_async_work, + RUN_ON_CPU_HOST_INT(idxmap)); } else { tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(idxmap)); }