From patchwork Wed Oct 24 11:37:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149492 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp474936ljp; Wed, 24 Oct 2018 04:43:20 -0700 (PDT) X-Google-Smtp-Source: AJdET5duPEy2iBrXK/osCaxszKVKYJrrtc2+FXCuSCsg4x3O5HFZPeP7R8gwKGQSRGFxJ/CE18VV X-Received: by 2002:ac8:47d2:: with SMTP id d18-v6mr1954894qtr.283.1540381400694; Wed, 24 Oct 2018 04:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540381400; cv=none; d=google.com; s=arc-20160816; b=RKFsZKEg8ZyLCDX4jU8vaGtBDIiGO+UyZ9wyafYPpHog6/mb9uBQP3ZMR8NLfh7r6b xEo5f543pWTg0mmF54Lg/qKgAdHfQUIkyUnZpZ7uz0OlZw4dl98PI7yPEomBpXGE3FkH 5q7V7FYFGMoQmAp4eSj0H7es9wg+ixrKn4fTHOlVIP60fGyz+Fup7EC7+jvzzAiV3AjG MmlvF2WIVb0WOdz8AsAU7m5j7Ndb1qhspBbR4339yPihh0g2UAh6344qA5eDoJ2OCVDL m8faJBZAxnyPTKBXe6Y7kDDyaI/TNjKbN+zhPOQwTkde/E7Ikryr3pZpDMWp9rEDmszI w11Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=TK0Mu/aguozz4Q5UAQWbHigk/WZ2HXR6efE27bzs4U0=; b=swjRlEc0HDnIMHo56x5YDeK2CEf29naPQWYnjOLJyaUh3yS3pHc+4rY9Kb2lekffi2 lLCLgSDU0ULUFY96V+EwIWrgcNmILa31OQNgfquha5DZup0e3zLqzAsAvoKgT05wV6/7 crVPHuwuYRYMafFUu0JJzCwyDcWbL62y9RqzxYtPKuGL1efEmz8Z9dFG8TvD/ey9Nl2c ei4ZBdOYDNzB206E8E+FRPZdE3VE4P5/YbpPOWIRjt/Nxu/RfyjR9JhkZrD9M7SzOdpp Opco3QhsXtr6bkWiVQYk3TlixRGqaZhlUw6c170M2cD4b+nyjONg8A1Thgr9++RTafTg hdPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FOV0Lojx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 1/5] target/arm: Install ARMISARegisters from kvm host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ID registers are replacing (some of) the feature bits. We need (some of) these values to determine the set of data to be handled during migration. Signed-off-by: Richard Henderson --- target/arm/kvm_arm.h | 1 + target/arm/kvm.c | 1 + 2 files changed, 2 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 21c0129da2..6393455b1d 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -183,6 +183,7 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); * by asking the host kernel) */ typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; uint64_t features; uint32_t target; const char *dtb_compatible; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 09a86e2820..44dd0ce6ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -158,6 +158,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->kvm_target = arm_host_cpu_features.target; cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + cpu->isar = arm_host_cpu_features.isar; env->features = arm_host_cpu_features.features; } From patchwork Wed Oct 24 11:37:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149494 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp476248ljp; Wed, 24 Oct 2018 04:44:51 -0700 (PDT) X-Google-Smtp-Source: AJdET5fF8tz+8WZGJR9kAvcMRZZkq4vk48fhfM1V/g73ozjWuy8y08ZqW8W6vtN5G8ZfhiSWl+4v X-Received: by 2002:a37:1bd3:: with SMTP id m80mr1857613qkh.259.1540381491867; Wed, 24 Oct 2018 04:44:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540381491; cv=none; d=google.com; s=arc-20160816; b=vyy4q6al75v9AmK6fTIc3ZZr2ft8zOOTJNLAdy5KH+7nt1JC/gRPun7FJf0r+30T7a HvCt2/g0/8mtTRubdzy3DBdh+A6Le3MopIgUoI6xD/ic85ACrBYIGAhvEn4RYwPvddIC G6YwIFEE7Y18cg/S/8FHidOmD5hQ1l2jnCfLzItas9CK7mgk3lgcOcldLVH5fiV78ZnY 2zSHZOBB51VyH4xlE7b5lfXOvhR1tyLyO5IVJ0Ezz2JIf8mDdUHEFBw0c10nN8xOui9s MfKprGOoYGqwGVlTQtw8gIKDaNkKhYcpBROQ92JnmKTuxhAH8NKICHcTAuUdc+Srj6rq 0s4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mhSijd16+NJw96dqXKla0uCq/J2KTUK4WGHUbEgJAIY=; b=FDbVsyajPlVA2ilrMTH6DQY4qftH442VG23s4WCZPbCnB9DbDbltcX01/Vxh0G7f/S fiB8BsGRK7BY0H37HfwsK49p0YCWR0SFiU/LHlly6n3wnXX8bpZ43hMeCgen1Bzl2zxs /h+JoJpd38y9jpU3r/zSaYVYeut8xviFpYSPyURbPYkst7Z7/TL3EC3d9f40rz2Zbg+1 Vhx2tLvgJjAXT4NIiXJYcnaAwVNLisg+OB+L7Jd6t6Mia9iFZBtBnauGezJjPWpTirwh LsLenyeonReud1VuiyfnRiuakIl6tJgk5kGPedTs9yUMo40L4rTInajFOuF8lZdFyZyu aUiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OQ21Bf9L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 2/5] target/arm: Fill in ARMISARegisters for kvm64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/kvm64.c | 63 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5de8ff0ac5..6ed80eadc2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,17 +443,41 @@ static inline void unset_feature(uint64_t *features, int feature) *features &= ~(1ULL << feature); } +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + err = ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + assert(ret <= UINT32_MAX); + *pret = ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. - * For AArch64 we currently don't care about ID registers at - * all; we just want to know the CPU type. */ int fdarray[3]; uint64_t features = 0; + int err = 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. Fortunately these old kernels @@ -474,8 +498,43 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ahcf->target = init.target; ahcf->dtb_compatible = "arm,arm-v8"; + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + kvm_arm_destroy_scratch_host_vcpu(fdarray); + if (err < 0) { + return false; + } + /* We can assume any KVM supporting CPU is at least a v8 * with VFPv4+Neon; this in turn implies most of the other * feature bits. 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h1si309712qvj.53.2018.10.24.04.40.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 24 Oct 2018 04:40:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ivHw1Mna; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47676 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHX0-0006Nk-9q for patch@linaro.org; Wed, 24 Oct 2018 07:40:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHTk-0003AI-MS for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFHTg-0005FN-Fa for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:36 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:55942) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gFHTc-0005CJ-Ko for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:31 -0400 Received: by mail-wm1-x341.google.com with SMTP id s10-v6so2958691wmc.5 for ; Wed, 24 Oct 2018 04:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7af4poIurUxCfGlMHJToqY/zCLOTj80OUUUjCdfupZY=; b=ivHw1MnauXB9k61LGDtvMyn0vKDbkmyxI7gk1ihuJ1CGeeC38jeLig4tgvBdmAkWnA +J5KWtFbE63O2er4Xd2dA6JVLeHY6EnKAjGKz37WFTSwfJBY+FKCxwJ8z6YDpYavgxw2 01SixRXBtucMt8AoGSZYvwF4cL17xFDCG1AmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7af4poIurUxCfGlMHJToqY/zCLOTj80OUUUjCdfupZY=; b=egU6b+oo1WRu4ALwkQQqsDmQ3NA68WEoQGEA+XXwrPrIvDB+6WIk/mCMlw1nWayWDU bmcS4n0y9pVQVgoc82HR4xyEMnLoyVxOFt9ZzVkbelaEnmXuo0WPDV92pK/iEHXhb1tF Kvbu93GkUN8sS+efyLouC/6m3mkL7bUXNYlBu0aJq0Na5pDvO2VRzuZofhaPuSesTsaD eKc094YavW0gr4PeDHFQx8NVm4Wwiiqz2li4eii8oK2Qn1lGZC/H6Hxm0SyLndUAh9Hq /uji0aJhGhNft1yLB6OdwPDbrZ259Tjvmbs8xlB/4Osdj61AH/hv5Ty6N5rAuswmyUi8 mfWA== X-Gm-Message-State: AGRZ1gK/8Uhh4KrzSkxMloNiv3f5MHciegqMNG0dum4IEMVrFnPGQRaQ /dykKUqclJ52AWp521t09p/WYE7buuU= X-Received: by 2002:a1c:8288:: with SMTP id e130-v6mr2246382wmd.84.1540381041930; Wed, 24 Oct 2018 04:37:21 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([185.7.230.213]) by smtp.gmail.com with ESMTPSA id c8-v6sm6769172wrb.6.2018.10.24.04.37.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Oct 2018 04:37:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:07 +0100 Message-Id: <20181024113709.16599-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 3/5] target/arm: Introduce read_sys_reg32 for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Assert that the value to be written is the correct size. No change in functionality here, just mirroring the same function from kvm64. Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 41 ++++++++++++++++------------------------- 1 file changed, 16 insertions(+), 25 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0f1e94c7b5..da08f7aab8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,6 +28,14 @@ static inline void set_feature(uint64_t *features, int feature) *features |= 1ULL << feature; } +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -35,9 +43,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * we have to create a scratch VM, create a single CPU inside it, * and then query that CPU for the relevant ID registers. */ - int i, ret, fdarray[3]; + int i, err = 0, fdarray[3]; uint32_t midr, id_pfr0, mvfr1; uint64_t features = 0; + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however * we know these will only support creating one kind of guest CPU, * which is its preferred CPU type. @@ -47,23 +56,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; - struct kvm_one_reg idregs[] = { - { - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), - .addr = (uintptr_t)&midr, - }, - { - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), - .addr = (uintptr_t)&id_pfr0, - }, - { - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, - .addr = (uintptr_t)&mvfr1, - }, - }; if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { return false; @@ -77,16 +69,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ ahcf->dtb_compatible = "arm,arm-v7"; - for (i = 0; i < ARRAY_SIZE(idregs); i++) { - ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); - if (ret) { - break; - } - } + err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); + err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); + err |= read_sys_reg32(fdarray[2], &mvfr1, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); kvm_arm_destroy_scratch_host_vcpu(fdarray); - if (ret) { + if (err < 0) { return false; } From patchwork Wed Oct 24 11:37:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149490 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp474327ljp; Wed, 24 Oct 2018 04:42:39 -0700 (PDT) X-Google-Smtp-Source: AJdET5dVBe+v/VEHVQvLXwUE/35p+QD9eN0z/Pt8P3og5prtXOL0AXLsIwQenwGQt8nXr3SftlYC X-Received: by 2002:a37:b782:: with SMTP id h124-v6mr1864585qkf.340.1540381359713; Wed, 24 Oct 2018 04:42:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540381359; cv=none; d=google.com; s=arc-20160816; b=d7jafME/5Ebg2uTxkkubYyXQrgz2mxnAcYQntY68LsyxefzIN3nInk0WrAGy6KT5+l CNsNo1bxXYZCblO5MR9y6olYsep3UyIqLJpsm2xsQpR9HHUa8S/nP5ocavWHBKi/ix18 REx2EOYVUqOyArYeuVcuXtrao3lFrb/njFPDn9t0AmKs8lw/G5HfphahDgSSvg5218Kw GCGgNFqMUOh+i66KhiMJ039SLcLEQsLyaH6mfEumRTdjQag1e+plM0oJbABCkocqEGDA vFzFN0lmisXoIa5879rq6v6v7ZzJdXb/1YTsuPb+lw2hJsIxDMsPGh/S9KQQZv7lYtZZ gbOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yZi5AVGAaLMSQ3Y1lct303kwXwDXnulw97+9IwZojBA=; b=sTlkQjy4ODviOi+MJgG8865EvryMpqg3uerqZXK4XsKqaayIg0JhC3I0jv/Y3PRxJg FNWPAkBk/gb6GXvaQdlrP6mD80az+0qXKZCXfjhJ2K2wZcWKccFuIoDlxHuOscsvXxq7 WtyQKXlMZDeYCBsS/p19awU7GvtUXGRzqDH3+ka4H+gDykhVjS3EOfSD624MGt4MuvkM Wj4GU67hqEUUqbaEq7QEjpUdzcJTwlTpWfmuZBcPN7/etRyhbseS7Q3HrCysUrtB6Bvh 3AwKJrGhGLTpBRG4G7O7g0W6r9nFujBjr//EtdQliAzZuwSyh5gASk94LtOPfTiaE58i n+sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SKNQ5jkx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 4/5] target/arm: Fill in ARMISARegisters for kvm32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/kvm32.c | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index da08f7aab8..f23cc77d9e 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -44,7 +44,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) * and then query that CPU for the relevant ID registers. */ int i, err = 0, fdarray[3]; - uint32_t midr, id_pfr0, mvfr1; + uint32_t midr, id_pfr0; uint64_t features = 0; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -71,9 +71,32 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); - err |= read_sys_reg32(fdarray[2], &mvfr1, + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM_CP15_REG32(0, 0, 2, 0)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM_CP15_REG32(0, 0, 2, 1)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM_CP15_REG32(0, 0, 2, 2)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM_CP15_REG32(0, 0, 2, 3)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM_CP15_REG32(0, 0, 2, 4)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM_CP15_REG32(0, 0, 2, 5)); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM_CP15_REG32(0, 0, 2, 7)); + + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + KVM_REG_ARM | KVM_REG_SIZE_U32 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); + /* + * FIXME: There is not yet a way to read MVFR2. + * Fortunately there is not yet anything in there that affects migration. + */ kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -95,13 +118,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) if (extract32(id_pfr0, 12, 4) == 1) { set_feature(&features, ARM_FEATURE_THUMB2EE); } - if (extract32(mvfr1, 20, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } - if (extract32(mvfr1, 12, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(mvfr1, 28, 4) == 1) { + if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) { /* FMAC support implies VFPv4 */ set_feature(&features, ARM_FEATURE_VFP4); } From patchwork Wed Oct 24 11:37:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 149493 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp475431ljp; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s3-v6si219366qvb.138.2018.10.24.04.43.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 24 Oct 2018 04:43:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JXtHu2mE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47695 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHZp-0001K5-NE for patch@linaro.org; Wed, 24 Oct 2018 07:43:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFHTm-0003HY-F2 for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFHTk-0005HU-TV for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:38 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:39136) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gFHTk-0005DS-KO for qemu-devel@nongnu.org; Wed, 24 Oct 2018 07:37:36 -0400 Received: by mail-wm1-x343.google.com with SMTP id y144-v6so5013872wmd.4 for ; Wed, 24 Oct 2018 04:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=alNykdPhAmQGBw8DApolghGIOI94fJkHQN66o4S0f1E=; b=JXtHu2mE7SIdRa0mllo2Ki17wkqv9qiSMcoB4MFG95VT454G/fzumNYF4Np8+rXDjV APz108S5aDKej7KLl3Zu4BHrEUUcj4I5Sx7VK5lvoYYTKH3yse9qBxazDqt6PgiaKBo+ vRWZH5z5lDOZ7FfRFj2sy+bOpi5bqTZOsdlm4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=alNykdPhAmQGBw8DApolghGIOI94fJkHQN66o4S0f1E=; b=oh+nCaToSNjilyD0s2qMXmgNJMNMbiqsGFGvphm3IvQzA2OFC3zb9H7CIFlaoRer0O gJx1SvlvuaRlWmsIaFdl6wMMGBmDVMp0epwWPLOemOh1ag0xKLBsD+ZAPQIMTK3m2ilj 7tz75IajqP/8X6ecaSnC2Lvw7StX5S2M4qvjH1y56+tzA+AGOcpjoMiopR5se9TXsA5E RLCggGctFzkbQT248ZaHtXDHh/CMKInwGvuVK6nHYL6XPPNA0ambrdH9bt3MnGjzEnOp rFr0CEZz1/iBL8pZziGUyyrumB48V2lLlVBNltraA6xuRAQaVjrIZWrcq3/ceY9nNqmM H7Og== X-Gm-Message-State: AGRZ1gKzRwIk14IO/gN+/i9Y8k7RQInhvpdgpYOMxls72yM+ASiq+4P9 TZhEv7AlrGCbVKD4afheEgA6fewMi7w= X-Received: by 2002:a1c:3403:: with SMTP id b3-v6mr2296125wma.108.1540381045315; Wed, 24 Oct 2018 04:37:25 -0700 (PDT) Received: from cloudburst.twiddle.net.net ([185.7.230.213]) by smtp.gmail.com with ESMTPSA id c8-v6sm6769172wrb.6.2018.10.24.04.37.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Oct 2018 04:37:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 Oct 2018 12:37:09 +0100 Message-Id: <20181024113709.16599-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181024113709.16599-1-richard.henderson@linaro.org> References: <20181024113709.16599-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 5/5] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/kvm32.c | 3 --- target/arm/machine.c | 3 +-- 6 files changed, 8 insertions(+), 12 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8e6779936e..895f9909d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1575,7 +1575,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3172,6 +3171,11 @@ static inline bool isar_feature_jazelle(const ARMISARegisters *id) return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; } +static inline bool isar_feature_t32ee(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) != 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 055f6a95ab..45d6836bb9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8f16e96b6c..e08a2d2d79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1440,7 +1440,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; @@ -1509,7 +1508,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1572,7 +1570,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1618,7 +1615,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b0815..bea4d5350d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5455,7 +5455,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (cpu_isar_feature(t32ee, cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f23cc77d9e..bf39937a08 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -115,9 +115,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); - if (extract32(id_pfr0, 12, 4) == 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); - } if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { set_feature(&features, ARM_FEATURE_VFP_FP16); } diff --git a/target/arm/machine.c b/target/arm/machine.c index 239fe4e84d..07f904709a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -321,9 +321,8 @@ static const VMStateDescription vmstate_m = { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu = opaque; - CPUARMState *env = &cpu->env; - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return cpu_isar_feature(t32ee, cpu); } static const VMStateDescription vmstate_thumb2ee = {