From patchwork Thu May 25 08:18:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100467 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655230qge; Thu, 25 May 2017 01:19:54 -0700 (PDT) X-Received: by 10.98.252.8 with SMTP id e8mr43941444pfh.190.1495700394218; Thu, 25 May 2017 01:19:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700394; cv=none; d=google.com; s=arc-20160816; b=zc1nkjRQScYAMqKBy5XN2qk/831Yf/C/Kn6WKxU6CzwIK14HouF5FRAiEQJ8EKyPXi k49+uWeBK/tvBkKh5zoTHLqeO8EYA1upFV8fx/xy5pxTRVmJNjejqwddAZykLk903zm+ gh9s/gXMBIEI2u5fUtbnbrfzmjAPZYMrmEP2Fz5dsKToJjnxRf5ubxWGAnLEiUsPpxyy tU6dOid/a4jGnYLjyu3VXX3j6rwIuO1Lnwz3Z8aUguz8x3kzdbk6yPQ9aN6k1Mi60ISP I28a0a3nu8FOzcyPrYFr0g/l1ULb//FJw7y+eStc3Asi1zQmsCfXnunNp57KhtkJc67n FdnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Uesb4CWKLcjTXANCnfqBxTQZMQYGsU14UKVBcMfzRL4=; b=TzKmhzqGHG2gBW/ImCxWJh4VbIn7OMvgU2B7nI9EP4uDzE+Fks3Ot0FpzdOmiBIl0U W19M7l6LDdy2rAWYoyOo2W9DHsG1aTUqpfCy62pDTaNZ3pSbozrj4XwQJgf4ipBwFkoG 9h1NGVohwLdfFJO3onS0YCK9be8TDrwo54uwq/mb3nOWE+M5j+OvYlpqPzl0/Wly9+h/ e6V/UfsNWdYglOaW+66zlFd8ASmlDHzyohOxwjEIMfzXsut1cuL/MIMAgybYkcs/T56F 39yCm/mv3XWYuUrnC3TBQPsOdj3F3W01YdsfB6QOh+n//f8kSgqIJeh770r+RxUvDlpe Eoog== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.19.53; Thu, 25 May 2017 01:19:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034711AbdEYITd (ORCPT + 7 others); Thu, 25 May 2017 04:19:33 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:35296 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968961AbdEYITO (ORCPT ); Thu, 25 May 2017 04:19:14 -0400 Received: by mail-pf0-f175.google.com with SMTP id n23so160501767pfb.2 for ; Thu, 25 May 2017 01:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=a1ujvZgLqYf1stoUha2pOOh0DgU8iYUen75xQ+OjvqKjpczM0YE1AKrvkRoPCzgSO3 P203y/OJO59WrPhPRRkkzR533fFTwXBC1UvizPqYjW/W59piMbHtyj8nFrsgsOmBywd5 Tu9LnmwSJrs/iytaRF9yXfffhiEOLyhaPohf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=DA+Sba25eSFLRL+jcQea8GBOBdZ1LIRxNszaLUH33ZKzCEpIZb7uMrb3+nfD1tsvn3 0Hq3fO+N0wVHggXk7Z5wxQTHiNGvIYPwOPnVlvf8r73w3tSjJukk33favEJAGDoWOGXq TemKH+GROFZn+NcjAWPVedKQpd8grV5nW1HTzredlfMgMquz3jOh3aacVOqULFDX//kc ZjVQgZ6XbVfJBQJBAPSL9gcmeZAxQEZBWaK49x+zrhiWqDYeOx40PlKkwXW4+gUW5gyE xK3NGGLTHkrtIGa1ZB4dJ8RrdtGK071aIzv4HytwsICdKTGOkZmcvQJu4oIPtuU22ngk RYEQ== X-Gm-Message-State: AODbwcAte3A+/b4OgaYAbSQglNpIwbsmOyT8F1AqjH8d48/0vbV9jot3 idtnq5Dm69esXrTe X-Received: by 10.98.192.143 with SMTP id g15mr42869796pfk.219.1495700353663; Thu, 25 May 2017 01:19:13 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:12 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH v2 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Date: Thu, 25 May 2017 16:18:43 +0800 Message-Id: <20170525081854.4701-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for HiKey960 Board. Signed-off-by: Guodong Xu Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 2e73215..7111fbc8 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -4,6 +4,10 @@ Hi3660 SoC Required root node properties: - compatible = "hisilicon,hi3660"; +HiKey960 Board +Required root node properties: + - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; + Hi3798cv200 SoC Required root node properties: - compatible = "hisilicon,hi3798cv200"; From patchwork Thu May 25 08:18:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100465 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655197qge; Thu, 25 May 2017 01:19:44 -0700 (PDT) X-Received: by 10.99.23.100 with SMTP id 36mr14492662pgx.118.1495700384071; Thu, 25 May 2017 01:19:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700384; cv=none; d=google.com; s=arc-20160816; b=o/FPfBeujXmr46CX0xPfBug8OgkpE7CDOZsEW2lx8CsJAlW7kBxrdttCUUQmtMzVof 4Jz9nedIuxWuo1/GNn6EPJl3LlU+DgKlzPNFEZXTP5b3DMzeqIGu/IpQuDhYhdq+CyMy uyyYc689nwphckkfpfZPV+/rJMJILJyyjQXTpRXgQEPU3+h0XVUud2NAFt+4X2/xV6wo 24K9JLUJLUDgHQoaZZQcGkN29ne8ut+3z04gGLsZhVqCkYNXS3+073XeNB1XR/Q7Kr8+ E9VKFXmIQY5DDyXBEbXZkpomqfBzAeyVTQ8hNE3bSf2KARm8oK3LMUruOrvb4tiSrG3H bUXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=gNRFOpFQ0zqTHfoAkDMI6LWgLqoqoNh20QJqR2kDsC8=; b=ap7kqh4tD4DafodtNHipfZ89DaNAMk1nUHgDKQfh00D7+1AQTViiNa4W0c+BO0y1O6 ZmzvRmCpxvZdlif5V088woU8m9A1HMtp7XEcXqmn7pXKVcuKxzz00z5ZotFBSAzXch+h uoWhQx2wrQQ3o+1R30C82Ik/HJ/lJ4Pk5MS5REf4dWJNbCVpyHY5C8cYbTbUOw6uYcJY fLyJT0XuDnguSJ60p/sQUt6KGvlHbMGBP1np0PgtiwPs9QwBKzogPxR6+ahvAd4dxVJA f+vpkPWRcEx+OsbrZGVOxrCJE3hFgKc6FNv7+PIPz7F4oxlqMyhxzV/JbbY98FbNCW0B UNhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.19.43; Thu, 25 May 2017 01:19:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034734AbdEYITf (ORCPT + 7 others); Thu, 25 May 2017 04:19:35 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:33551 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968989AbdEYITT (ORCPT ); Thu, 25 May 2017 04:19:19 -0400 Received: by mail-pf0-f171.google.com with SMTP id e193so160618857pfh.0 for ; Thu, 25 May 2017 01:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EBq2IasBSZxuDZmwkSIqzBM8qNIsBWTgHCK9Vwmd6Rc=; b=FmcG/S/pYjkSgTokB3aXQ3AIH8Gy/SCDjqMcZNuvKo+KtSE7PoXn7LUkaGr3LXZQiC 8a38Ma3m7kiS7rNTJ1mnJCxascHym90pq3emD2NHCLDZAr7+zmAa+xRDySqi26+vdVPY vlZRhmbQKRD72d/Me2O2MTHWYI2CyZ7uKZC+8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EBq2IasBSZxuDZmwkSIqzBM8qNIsBWTgHCK9Vwmd6Rc=; b=qkmFqXPLpSPn59pQ0+HwFSKbvpu1OknP+Sd09eWz0PAhFfd00FpysK/3/YwRK1Mxrc ung7HXKujixx863PAwHJanfJiTqT+SbccRVkN+HASlPMa5Qj46t07/MNzmLcIE+yLSoa KdBZb4sVLl+3KMHd4uVHJL6uwFw8lRAt8nxyFjRQioItfrIPgH5zP+F5zKWuajM3qHUt +zMK+7y/djd8+OcS7IYkQl+wJQdhQAOQcOO6J+B/y3fOs9n9FkjUbVCPTeddCyh8x7hk o8zOvMHnP/24odcp7F998YlYHBDXfxhSVgxi2jpWATHHgurlKRNxIDJCRPWUQsI/CVb4 P8NA== X-Gm-Message-State: AODbwcBThqZG4ABTxrmt8BqjzNWlU/DNgdowS+uUppMkwdyWUEDiAtLN ezc397JRqyabomhP X-Received: by 10.99.62.67 with SMTP id l64mr43072116pga.172.1495700358363; Thu, 25 May 2017 01:19:18 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:17 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH v2 02/12] arm64: dts: hisilicon: update compatible string for hikey960 Date: Thu, 25 May 2017 16:18:44 +0800 Message-Id: <20170525081854.4701-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update compatible string for hikey960. HiKey960 is a develpment board built with SoC Hi3660. Signed-off-by: Guodong Xu Signed-off-by: Chen Feng Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 186251f..64875a5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -12,7 +12,7 @@ / { model = "HiKey960"; - compatible = "hisilicon,hi3660"; + compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { serial5 = &uart5; /* console UART */ From patchwork Thu May 25 08:18:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100466 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655227qge; Thu, 25 May 2017 01:19:53 -0700 (PDT) X-Received: by 10.98.74.13 with SMTP id x13mr43558657pfa.149.1495700393250; Thu, 25 May 2017 01:19:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700393; cv=none; d=google.com; s=arc-20160816; b=zs8C83KIlPebw4eCTOTYl6AuD0wD6uphMMC0/baRCDYXJNzVdxF+QOG2Vr9nSNW6XK Yt0t4gb/xAAfExgnaN5SYCfc05CQH/hGOS5Eq/iIeqs2Oqfv7wG+zUPqBqBEepOpHcuV SJG6SDFqepx/occR48FY/HmIKYo2EFahXv7XgCgJWv30hLfj9Nd9HSc5hPnMlKcC7dyu 4qyHCkTW77SaWXEx1M7U+HPeyFyclg2cEhiPmuDySyZ6daeFO/wnxyaH1kDkOoPYW0lh cLyrkDtL8HgkytAdhxW8hgpKM1XUlrAztmqpJMfGBK8c+ejk1agIbqy2pV0+QFdXd3VQ RA9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=u7KboB2wUucslnMx7NO0cazqIhX4PTGobrAlJI9yvi8=; b=haYkvHH8UkFBlipymidOjI6OcWa9E8/mRFN9kftfIPu08sAWRhHeIGyGTwd2/hO8zO ivou2l7BQkNR4JvLY9HXLouLoPw4BPi0u40PDneflYvSZM/wBszZl/oOkS4SWwkBEW10 cNX2FL8ecG2XMrk+QODW0YNTLX7/6Nq/e2C1+0vIo6OMdptwe4mEV/s054Ajn0mkacUg eAGFmRG3hAZW9+uAlFd8OYQsVjqLQv5uLy5V8D7QxXOrzYIHVcIOt5YzKrbICxjFE1R2 Q4G2J79ciMfvs0jGgT57AFa9VKUHUK5FkEaQds7zvVWrQxyAn9Fju/S4doDJH1vb0Y+z Jl9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.19.53; Thu, 25 May 2017 01:19:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1034737AbdEYITi (ORCPT + 7 others); Thu, 25 May 2017 04:19:38 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:34529 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968992AbdEYITY (ORCPT ); Thu, 25 May 2017 04:19:24 -0400 Received: by mail-pf0-f175.google.com with SMTP id 9so160422764pfj.1 for ; Thu, 25 May 2017 01:19:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=Ox+5PR/5CT80jmsw97jt0AjrVrOTT5q4Xdk/v6mtWTkj8HvfQhUQPxvw9KiD5h2A0g kWpMQAYKachCsPAQ/Viyk3z/CYiDLvqpHP9rzeNug2yqIlTe0GHzEFmmhYsIENlIHJY5 jRjVnNwy+qv5z7yTw7X0XNdC1b/0rTJuLZ78E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=EQnQNIiFgrvMiIHkltWkL6aFmPIovk7luXoNYcBaU8uKqe6cFxlqoxB4wmLPVVV4T7 ekih0+xeV1EgWe2d7EmahdR3jY4Uhp/noJ9apoAPFnzUDUYnry5c4YJ5jZDfKHLHIuJC KotG9aaZulAw0C8oIwPp20U59K3k8ZUqRAmVaSVtX+was/tnk4qTPfJBwcSRFHNEzIcQ CSGFlcPDOEj0JTXWG5gxNcjI8bVfscZ97nf+zfn8AX5l94DFnaXHKelrg59Cy8G+0b+z gHXnzOyj3dDY1o2b0H1eWxjKkEfGhQNbYhu//hskpZZ1S0Tj+kBaqPQjcn5nOj6uCrvS 4hGA== X-Gm-Message-State: AODbwcChBb+RE4Tb4XVmOThQGl/1d7g2lvIgmJc+JGdRuvcLnugwTjMM okdLISqqt4PO+5c5 X-Received: by 10.99.43.137 with SMTP id r131mr12887986pgr.109.1495700364025; Thu, 25 May 2017 01:19:24 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:23 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Chen Jun , Guodong Xu Subject: [PATCH v2 03/12] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Date: Thu, 25 May 2017 16:18:45 +0800 Message-Id: <20170525081854.4701-4-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wang Xiaoyin This commit adds more pinmux and pinctrl information for devices on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key, isp, sd/sdio, i2s, and usb. Signed-off-by: Wang Xiaoyin Signed-off-by: Chen Jun Signed-off-by: Guodong Xu Acked-by: Rob Herring --- .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++-- 1 file changed, 715 insertions(+), 63 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 719c4bc..7e542d2 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -24,6 +24,27 @@ &range 0 7 0 &range 8 116 0>; + pmu_pmx_func: pmu_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* PMU1_SSI */ + 0x00c MUX_M1 /* PMU2_SSI */ + 0x010 MUX_M1 /* PMU_CLKOUT */ + 0x100 MUX_M1 /* PMU_HKADC_SSI */ + >; + }; + + csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CSI0_PWD_N */ + >; + }; + + csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x04c MUX_M0 /* CSI1_PWD_N */ + >; + }; + isp0_pmx_func: isp0_pmx_func { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ @@ -40,6 +61,12 @@ >; }; + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_034 */ + >; + }; + i2c3_pmx_func: i2c3_pmx_func { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ @@ -67,21 +94,10 @@ >; }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* SPI1_CLK */ - 0x038 MUX_M1 /* SPI1_DI */ - 0x03c MUX_M1 /* SPI1_DO */ - 0x040 MUX_M1 /* SPI1_CS_N */ - >; - }; - uart0_pmx_func: uart0_pmx_func { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ - 0x0d4 MUX_M2 /* UART0_RXD_M */ - 0x0d8 MUX_M2 /* UART0_TXD_M */ >; }; @@ -138,6 +154,18 @@ 0x0d8 MUX_M1 /* UART6_TXD */ >; }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x0c8 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x124 MUX_M0 /* CAM1_RST */ + >; + }; }; /* [IOMG_MMC0_000, IOMG_MMC0_005] */ @@ -174,6 +202,13 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; + ufs_pmx_func: ufs_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* UFS_REF_CLK */ + 0x004 MUX_M1 /* UFS_RST_N */ + >; + }; + spi3_pmx_func: spi3_pmx_func { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ @@ -248,17 +283,17 @@ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c7_pmx_func: i2c7_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M1 /* I2C2_SCL */ - 0x028 MUX_M1 /* I2C2_SDA */ + 0x024 MUX_M3 /* I2C7_SCL */ + 0x028 MUX_M3 /* I2C7_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + pcie_pmx_func: pcie_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ + 0x084 MUX_M1 /* PCIE_CLKREQ_N */ + 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; @@ -271,15 +306,6 @@ >; }; - spi4_pmx_func: spi4_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M4 /* SPI4_CLK */ - 0x090 MUX_M4 /* SPI4_DI */ - 0x094 MUX_M4 /* SPI4_DO */ - 0x098 MUX_M4 /* SPI4_CS0_N */ - >; - }; - i2s0_pmx_func: i2s0_pmx_func { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ @@ -290,17 +316,18 @@ }; }; - pmx5: pinmux@ff3fd800 { + pmx5: pinmux@e896c800 { compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; + reg = <0x0 0xe896c800 0x0 0x200>; #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + pmu_cfg_func: pmu_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ + 0x010 0x0 /* PMU1_SSI */ + 0x014 0x0 /* PMU2_SSI */ + 0x018 0x0 /* PMU_CLKOUT */ + 0x10c 0x0 /* PMU_HKADC_SSI */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -315,18 +342,35 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + i2c3_cfg_func: i2c3_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ + 0x038 0x0 /* I2C3_SCL */ + 0x03c 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* CSI0_PWD_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -335,29 +379,64 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* CSI1_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - }; - pmx6: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x064 0x0 /* ISP_CLK0 */ + 0x070 0x0 /* ISP_SCL0 */ + 0x074 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK>; + }; - sd_clk_cfg_func: sd_clk_cfg_func { + isp1_cfg_func: isp1_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ + 0x068 0x0 /* ISP_CLK1 */ + 0x078 0x0 /* ISP_SCL1 */ + 0x07c 0x0 /* ISP_SDA1 */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -372,18 +451,37 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + pwr_key_cfg_func: pwr_key_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ + 0x08c 0x0 /* GPIO_034 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* UART1_RXD */ + 0x0b8 0x0 /* UART1_TXD */ + 0x0bc 0x0 /* UART1_CTS_N */ + 0x0c0 0x0 /* UART1_RTS_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -392,14 +490,568 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART2_CTS_N */ + 0x0cc 0x0 /* UART2_RTS_N */ + 0x0d0 0x0 /* UART2_TXD */ + 0x0d4 0x0 /* UART2_RXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART5_RXD */ + 0x0cc 0x0 /* UART5_TXD */ + 0x0d0 0x0 /* UART5_CTS_N */ + 0x0d4 0x0 /* UART5_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART0_RXD */ + 0x0dc 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART6_CTS_N */ + 0x0dc 0x0 /* UART6_RTS_N */ + 0x0e0 0x0 /* UART6_RXD */ + 0x0e4 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x0e8 0x0 /* UART3_CTS_N */ + 0x0ec 0x0 /* UART3_RTS_N */ + 0x0f0 0x0 /* UART3_RXD */ + 0x0f4 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART4_CTS_N */ + 0x0fc 0x0 /* UART4_RTS_N */ + 0x100 0x0 /* UART4_RXD */ + 0x104 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x130 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + }; + + pmx6: pinmux@ff3b6800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3b6800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + ufs_cfg_func: ufs_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* UFS_REF_CLK */ + 0x004 0x0 /* UFS_RST_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_08MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x008 0x0 /* SPI3_CLK */ + 0x0 /* SPI3_DI */ + 0x010 0x0 /* SPI3_DO */ + 0x014 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + + pmx7: pinmux@ff3fd800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3fd800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; + }; + + pmx9: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0xbc>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x01c 0x0 /* I2C0_SCL */ + 0x020 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x024 0x0 /* I2C1_SCL */ + 0x028 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c7_cfg_func: i2c7_cfg_func { + pinctrl-single,pins = < + 0x02c 0x0 /* I2C7_SCL */ + 0x030 0x0 /* I2C7_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + slimbus_cfg_func: slimbus_cfg_func { + pinctrl-single,pins = < + 0x034 0x0 /* SLIMBUS_CLK */ + 0x038 0x0 /* SLIMBUS_DATA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s0_cfg_func: i2s0_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2S0_DI */ + 0x044 0x0 /* I2S0_DO */ + 0x048 0x0 /* I2S0_XCLK */ + 0x04c 0x0 /* I2S0_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* I2S2_DI */ + 0x054 0x0 /* I2S2_DO */ + 0x058 0x0 /* I2S2_XCLK */ + 0x05c 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + pcie_cfg_func: pcie_cfg_func { + pinctrl-single,pins = < + 0x094 0x0 /* PCIE_CLKREQ_N */ + 0x098 0x0 /* PCIE_WAKE_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x09c 0x0 /* SPI2_CLK */ + 0x0a0 0x0 /* SPI2_DI */ + 0x0a4 0x0 /* SPI2_DO */ + 0x0a8 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0ac 0x0 /* GPIO_219 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK >; }; }; From patchwork Thu May 25 08:18:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100470 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655312qge; Thu, 25 May 2017 01:20:08 -0700 (PDT) X-Received: by 10.98.59.148 with SMTP id w20mr42775030pfj.137.1495700408697; Thu, 25 May 2017 01:20:08 -0700 (PDT) ARC-Seal: i=1; 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Thu, 25 May 2017 01:19:28 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:28 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/12] arm64: dts: hi3660: add resources for clock and reset Date: Thu, 25 May 2017 16:18:46 +0800 Message-Id: <20170525081854.4701-5-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Zhangfei Gao Add some resource nodes for clock and reset Signed-off-by: Zhangfei Gao Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 7 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086..f55710a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "hisilicon,hi3660"; @@ -141,18 +142,56 @@ #size-cells = <2>; ranges; - fixed_uart5: fixed_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "fixed:uart5"; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; }; - uart5: uart@fdf05000 { + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = ; - clocks = <&fixed_uart5 &fixed_uart5>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From patchwork Thu May 25 08:18:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100468 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655237qge; Thu, 25 May 2017 01:19:55 -0700 (PDT) X-Received: by 10.99.171.65 with SMTP id k1mr13591541pgp.150.1495700395466; Thu, 25 May 2017 01:19:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700395; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.19.55; Thu, 25 May 2017 01:19:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423671AbdEYITx (ORCPT + 7 others); Thu, 25 May 2017 04:19:53 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:33675 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1034727AbdEYITe (ORCPT ); Thu, 25 May 2017 04:19:34 -0400 Received: by mail-pf0-f181.google.com with SMTP id e193so160624762pfh.0 for ; Thu, 25 May 2017 01:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=dBBPj9CaTMshRv3TopEGkkSuAJIatxZC3my7ynASfxSvc4wCgWlkzS1rUcnB/Dgj2m K8EFUeDBS7dl0CbmeZiuUhviBqJF5caR5mpcO4NDCN5mY1LL8bQmH56jIxKg6gl7y6kA LgzLIxjTw1g6emicPzvYamsyFu5Z20f8XTU48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=VfFD5n1zlVvOtPBYiGjX5tl+lsFuLyZlsf1G+hhznswZ+idGeqlYTKPoVZzvv+fa86 +nh9h9+KpRXzg8awjlhlDIYIMofFW138zMWZunGLuYKxB0npgupsZbA6amj62gazP45j sasaJkc0keuUcOPG+wxjI8d4vqoeOZWfPdMsfQwMB51o/VFhrUxb7IH8PMIQm4J5Liv9 fzhrYeCfIb5Wixj41eWXUwKAqHIyt5dxTnknx5k8H/WvICa8EX2zin4ITX5K/50Y76dY +VL8hFSSqOpa+Bb/WtalF8V4gGoiirEW1gk0pX64tkjU5i+tgysBwhmVCQbOGysEnXMC PhLw== X-Gm-Message-State: AODbwcD0vcOcLZtQ8huCy1VpVFcM1GLqMrRbF33j1CUl8lR+rXVIvew1 voiBhfGCqG4PCRDP X-Received: by 10.101.73.7 with SMTP id p7mr3192934pgs.144.1495700373688; Thu, 25 May 2017 01:19:33 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:33 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jarkko Nikula , Guodong Xu Subject: [PATCH v2 05/12] arm64: dts: Add I2C nodes for Hi3660 Date: Thu, 25 May 2017 16:18:47 +0800 Message-Id: <20170525081854.4701-6-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Zhangfei Gao Add I2C nodes for Hi3660-hikey960. On HiKey960, I2C0, I2C7 are connected to Low Speed Expansion Connector. I2C1 is connected to ADV7535. I2C3 is connected to USB5734. Cc: Jarkko Nikula Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 22 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 56 +++++++++++++++++++++++ 2 files changed, 78 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 64875a5..1a4d6c5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -29,6 +29,28 @@ }; }; +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + adv7533: adv7533@39 { + status = "ok"; + compatible = "adi,adv7533"; + reg = <0x39>; + }; +}; + +&i2c7 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f55710a..9abe84e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,62 @@ #reset-cells = <2>; }; + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@fdf0b000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0b000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; From patchwork Thu May 25 08:18:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100469 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp655277qge; Thu, 25 May 2017 01:20:03 -0700 (PDT) X-Received: by 10.99.102.7 with SMTP id a7mr43067591pgc.216.1495700402957; Thu, 25 May 2017 01:20:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700402; cv=none; d=google.com; s=arc-20160816; b=IzUXw7V0Y0ZL2MSBXYaixAvGIqx9DgP3wc/ukGEGLIH3iYl5gz5ia00b7z0sCh9ovo RlmkeheOpo9sGHWWQu+5R+UbSzgkrDZiVVDZ3PDu1thxExGVBQwNoHbL4XdfLQ9+cAqK hI1dY8YX0+7qqhZxxzA3iX+5vWo1FBcOroejOJyUbJmzhp/I4SFBCvqCzxxKkMc7DrTL BfoQGQcbCn8+cVgERfZ+n/mGe4nZDemunRx3cBFg41TH00+t40u3mUW9/BmYO1Fix0H9 Zo8MT8p/K0MXAp2b++cb7CPfzieaVOIIER+L+aIqRckdyeoPjImSw+7Xv/bq3zkzHD01 54RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=skX2zrABKz64V5W4JC5ykRxBO2i2zq+EzWynoROy5Jc=; b=T0gK9o3A8MdFfQkx3o7wgWRlbkGVF3Pux+keoMWFyC+GOpFNTff1xXQ76hmcm1b9y6 gtV5DNREKFEaoPJk9vtyZjGe/m9oucAFC67YguFrHDg9MrY1BNCIRYllYOfDspCV7vTl AYjlZNbBO0JTP0a2svMVqhvo9Yjc0TLmvHbtAqsVdtHIMpvUoJS6R3m8BQdKzDVXp6Iy 9N8aaLvxPHAcPuyj15ULRdUTELWmuZK05FRZK44I2rweezbu5WMGMBqq/6uA4T9c8PcZ HGcblH4snBndT55DuTFORmQ7uVbe/dVu6FdSJCV8XSvENeq00H/dS/SXSa5k6UoLlwVZ dZYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.20.02; Thu, 25 May 2017 01:20:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423673AbdEYITz (ORCPT + 7 others); Thu, 25 May 2017 04:19:55 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:33710 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423476AbdEYITj (ORCPT ); Thu, 25 May 2017 04:19:39 -0400 Received: by mail-pf0-f182.google.com with SMTP id e193so160626618pfh.0 for ; Thu, 25 May 2017 01:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SKle1N3Cdi0bgyCL3EILNiJD5thnQRze5cZRg4jGxMc=; b=ZYD3jk9jwQoDY0GfpD7+DboSVzm2YY/u/nyGEqdcR84k6rq8izRJ3DOpHD76WNKPzk cAASNiM5t05/n1vf0LdoNajsmZiGG+Rgv+O+WOGknDjeEkWNPMWEk7Qr02iT3AxpQsU/ Q3v0jh3EPKkpgGV7mSTWBN+loSEfEY/HVPoDs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SKle1N3Cdi0bgyCL3EILNiJD5thnQRze5cZRg4jGxMc=; b=DzgVSYvGlKzgA3P9tg7qaMeRfb2vyVDw2j0zyK6BC9XgZ87qqhbHJh6lLzpEAvonEt yLUUvguJTUBIBGZu2snjc5llsFqdfRMbJ8ih+zit8Qco6XMJONgAyJYcq5ZHjBNRblqa QY8/Y9oBUJS5M5Gc8XKxHeljCR1Sha2egsEeldxttq63zhyVqF3/dWl+nlUSKHr49bPq bT35irhhdSLci7FtY8acZ+aoJdvIySg59bcy15w3+m1dKuYdz3m338/qYklGfpRPRmba S5+jN9XaVAjA0cLDujUI+DKRRcc9xtUHgKL4n+XqUIqyEbMHhkv9PpLqIjahXwxq7KRC eUYQ== X-Gm-Message-State: AODbwcDthlisT8Nsn1K164HVece+cIy8WhHZCQgjGegIwox/OXGDDUqP O8PsVKw2ivCrVBSS X-Received: by 10.99.97.6 with SMTP id v6mr44372838pgb.186.1495700378392; Thu, 25 May 2017 01:19:38 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:37 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin Subject: [PATCH v2 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Date: Thu, 25 May 2017 16:18:48 +0800 Message-Id: <20170525081854.4701-7-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wang Xiaoyin This patch adds pl061 device nodes for Hi3660 SoC. Signed-off-by: Wang Xiaoyin --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 380 ++++++++++++++++++++++++++++++ 1 file changed, 380 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 9abe84e..b03be4d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -251,5 +251,385 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@e8a0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 0 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@e8a0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 7 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@e8a0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 14 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@e8a0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 22 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@e8a0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 30 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@e8a10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 38 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@e8a11000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a11000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@e8a12000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a12000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@e8a13000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a13000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 62 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@e8a14000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a14000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 70 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@e8a15000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a15000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 78 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@e8a16000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a16000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 86 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@e8a17000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a17000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@e8a18000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a18000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 102 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@e8a19000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a19000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 110 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@e8a1a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1a000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 118 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@e8a1b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@e8a1c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@ff3b4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b4000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@ff3b5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b5000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 8 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@e8a1f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 0 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@e8a20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a20000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pmx3 0 0 6>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; + clock-names = "apb_pclk"; + }; + + gpio22: gpio@fff0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO176 */ + gpio-ranges = <&pmx4 2 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio23: gpio@fff0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO184 */ + gpio-ranges = <&pmx4 0 6 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio24: gpio@fff0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO192 */ + gpio-ranges = <&pmx4 0 13 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio25: gpio@fff0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO200 */ + gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio26: gpio@fff0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO208 */ + gpio-ranges = <&pmx4 0 28 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio27: gpio@fff10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO216 */ + gpio-ranges = <&pmx4 0 36 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio28: gpio@fff1d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff1d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; + clock-names = "apb_pclk"; + }; }; }; From patchwork Thu May 25 08:18:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100471 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp731105obb; 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Enable uart3 and uart6, disable uart5, in hikey960 board dts. On HiKey960: - UART6 is used as default console, and is wired out through low speed expansion connector. - UART3 has RTS/CTS hardware handshake, and is wired out through low speed expansion connector. - UART5 is not used in commercial launched boards. So disable it. - UART4 is connected to Bluetooth, WL1837. Signed-off-by: Chen Feng Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu Reviewed-by: Zhangfei Gao --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 20 +++++- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 74 +++++++++++++++++++++++ 2 files changed, 91 insertions(+), 3 deletions(-) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 1a4d6c5..0a3f2e0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -15,11 +15,17 @@ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { - serial5 = &uart5; /* console UART */ + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; }; chosen { - stdout-path = "serial5:115200n8"; + stdout-path = "serial6:115200n8"; }; memory@0 { @@ -51,6 +57,14 @@ status = "okay"; }; -&uart5 { +&uart3 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&uart6 { + /* On Low speed expansion */ + label = "LS-UART1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index b03be4d..7a90c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -242,6 +242,66 @@ status = "disabled"; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; @@ -249,6 +309,20 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; + status = "disabled"; + }; + + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; status = "disabled"; }; From patchwork Thu May 25 08:18:51 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.20.48; Thu, 25 May 2017 01:20:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423685AbdEYIUZ (ORCPT + 7 others); Thu, 25 May 2017 04:20:25 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:34739 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423670AbdEYITx (ORCPT ); Thu, 25 May 2017 04:19:53 -0400 Received: by mail-pf0-f173.google.com with SMTP id 9so160433422pfj.1 for ; Thu, 25 May 2017 01:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4jQ3O/BMN/V4rkRyXEsB59sUYtfxxLmhwukoxiNK9cI=; b=c8LMCRLM8YbsxoncV7Xv8/2/t5fJtTmuRSqqusnTvlVGnOnPeeiFdOk1pHmcnd0VOR SSblEn14DoYbdAFZjxbHl6/HLfHoef6lZnl4qhSbJy15NAC0pPa5oZ1o9PZ6WfLkZqSB f/zWtLh3baYzZ4YcLyzoomj1q/sGzVe6drj/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4jQ3O/BMN/V4rkRyXEsB59sUYtfxxLmhwukoxiNK9cI=; b=mlAsqSH6PArq+/UQbImDSsCQ9UoHso6uPHGDDB1X1rW9rCZ3QaPAYMXYyCT3A+Ma8m 7JWMLuNFRRnCKy6+FV/1wHKuqyO1KOBXeQQeTMVxLrsNvkhSWCNzlLUxRpAhugi913sZ g8hkMNqte/16OLqlWs13xkgl19gqE2LGkLFxeTO9mRpN23p8HdXk3gb3PdfknDUv/lQ5 8T7By9KkREgMbFndQnw+Kt0Oib4J45aXkH+ZNA0rs0OuGuxht5ucXoyCitH7dubzuYdk CQv9s4poUSQjzdRBH+QhP49wR5tkJW0hrEJk/339Le1nVWkhPDhSgyQj2IRnQn5Ci+Jw V4DA== X-Gm-Message-State: AODbwcAL3PRsNcMppQA5Zr5c4bZ5Y/gfM8dw67XJT3S21JKn4N+5OX40 WA01amljOlWm/N0I X-Received: by 10.98.151.2 with SMTP id n2mr43679053pfe.29.1495700392646; Thu, 25 May 2017 01:19:52 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:52 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/12] arm64: dts: hi3660: Add pl031 rtc node Date: Thu, 25 May 2017 16:18:51 +0800 Message-Id: <20170525081854.4701-10-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chen Feng Add dts node to enable pl031 rtc. Signed-off-by: Chen Feng Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 7a90c92..3b2a3a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -326,6 +326,14 @@ status = "disabled"; }; + rtc0: rtc@fff04000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0Xfff04000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + }; + gpio0: gpio@e8a0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0b000 0 0x1000>; From patchwork Thu May 25 08:18:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100475 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp731771obb; Thu, 25 May 2017 01:22:31 -0700 (PDT) X-Received: by 10.99.149.94 with SMTP id t30mr44630126pgn.152.1495700551183; Thu, 25 May 2017 01:22:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700551; cv=none; d=google.com; s=arc-20160816; b=TYTniwbjqFXYQ43CxyYdtlJsqRMZ0CIL+rWW6muTbKFI8NGP1xC7SKZVAGWdvGtUJU LnQznK7EgSPXbDvENAUrSXr3mxWedfTJH2B7cedxglYNuSMCpTPcRtI+6zajFHxtNQSl C/7FVzXb6T8A47pu3L5EMugI5Dgm9mfR5Qamr4M/FNzitbJujsr4aFK2r7kgvMzyqAe9 6RYT1PVLI3kPxMxJKbHZ6jfQT1DODPe1L4RA/Du0U3sqZTDf2vwJWxyPRIfY5J1Cebgy iETZc1r/fFrZ5OH3vaBqhWYxY8eb5OsEvlR7JVC1SEH3Woo4Yz8lHoW37W4oDQKJP+k8 76pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Tc7X27Au8ddnZ54jPJ/PqZqGXGoqfxSEw96S0/te/AU=; b=GXyTjxCCCW3tBgIeSaXf6z8840HDRwaCVDXlnXTna20V+ZnsqjPuo1iS4Bbj8DV+Ku layXXGhHQBYbjIsPP546XmeOD53tgu3uUWpZxGhj9VCXz9YoodR5UcTBzbR00BVCyWX4 MYqBtAyBwBflpH65gtAeEZGJdCSSqVHlPP42NSTIqAaD+sDWutV88uAPVCE8VgnBZSrJ 7RzIft7tsfAizpa454IkNErl4ULOd1JqKFKuzWoGHv8vyl0H7reF1a6a7Ha0wVEkQWY8 EB2JI5o3MwUGjdD7Sxmg/cB5+BBDwcncrF427pAJcntXZoXE7y7ZDColesy3/G3kZRu1 3ujQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u201si26788965pgb.404.2017.05.25.01.22.30; Thu, 25 May 2017 01:22:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S937575AbdEYIWV (ORCPT + 7 others); Thu, 25 May 2017 04:22:21 -0400 Received: from mail-pf0-f177.google.com ([209.85.192.177]:36497 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423675AbdEYIT6 (ORCPT ); Thu, 25 May 2017 04:19:58 -0400 Received: by mail-pf0-f177.google.com with SMTP id m17so160498949pfg.3 for ; Thu, 25 May 2017 01:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X6/H86AoT9SYw5uZPqpjGBaeqytuolgQzVCEB6Bujm8=; b=b92Lwp6lRHcEC3hIVkMYZ+QdYRdiN5et963Kx9Ie/aCTfox4HrshbNeCEvjB+95jhR kfTp81unh6890oKFVlX9vD/B3gahTklAXVPrk0iFtAfIYoC9quwq3lZH3e/B1t4Bikkk WZ4dJiQuPaCQOtTwTkFzFL/MoI9620WcBB1DM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X6/H86AoT9SYw5uZPqpjGBaeqytuolgQzVCEB6Bujm8=; b=KFX6cbNrUMpNtZhcD4CwnDLhve8t/26MtD5D+gdZ5IvCqKlvUTliniwOhFtzeuVh+7 CL1wKSD/MQSTkd4ypeTh1EE8sgQBbRHME/erZEPYIqGULD+/PZ9wJPvIh/G6smomYC/8 nfY3W4bgD34RISYULzXVXQsQIn1c5UWqituNwp+l5SP+TzdQZ9jU4Ru3XPSKv1PMbO7H pXmO1MtnsfS7iSL4LgnwK49TbuucJPA6mIY5XwjpqzX3udGmRrDOzWv61c1gpWsH1VUe ZEyP7sN6yLz4WyUEBx/SB/irygEOf7xXfFNaVNQIvldDG/lPchA7cV+7pFJ/fzvpaGgV VwjA== X-Gm-Message-State: AODbwcBrjoWMVfWHX5bMHF9ydgHU6WnEhPXwPZxXP6oFP52JxdMk596E EZPfC3g/EbNYIBeyo9Tnag== X-Received: by 10.84.225.130 with SMTP id u2mr47915658plj.91.1495700397967; Thu, 25 May 2017 01:19:57 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:19:57 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chen Jun , John Stultz , Guodong Xu Subject: [PATCH v2 10/12] arm64: dts: hi3660: add power key dts node Date: Thu, 25 May 2017 16:18:52 +0800 Message-Id: <20170525081854.4701-11-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chen Jun We use gpio_034 as power key on hikey960, and set gpio with pull-up state, when key press the voltage on the gpio will come to lower, and power key event will be reported. Signed-off-by: Chen Jun Signed-off-by: John Stultz Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c25fff9..7aac35b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -10,6 +10,8 @@ #include "hi3660.dtsi" #include "hikey960-pinctrl.dtsi" #include +#include +#include / { model = "HiKey960"; @@ -34,6 +36,19 @@ /* rewrite this at bootloader */ reg = <0x0 0x0 0x0 0x0>; }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; + + power { + wakeup-source; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + }; + }; }; &i2c0 { From patchwork Thu May 25 08:18:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100474 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp731502obb; Thu, 25 May 2017 01:21:39 -0700 (PDT) X-Received: by 10.84.193.129 with SMTP id f1mr49316321pld.129.1495700499432; Thu, 25 May 2017 01:21:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700499; cv=none; d=google.com; s=arc-20160816; b=nHn8QiwkvhaUV2QcgSS8T2Ix62suRIwQNf+a7dLclN8RG18tvyClthA8vKfh5p5kjQ 56ax90iqsIUl9lJ49gJsBHar/N6GrLkfCkAldLQl5hHW20d1q/JE839/19efRaZRWBKW r2ZquoUlY4DeC2yjiTDIw+GlzAKqtHt99JvXdUessbepQ0bv4/vba7+ZCXKDQ0pjtpDn liZqbGYB1mDQT0AEyRdU3RCptGkGOvUcwSbceBDrf49o9ggDRshny1paNJCm0Mlq/l8z kr8chzJ2i/89ZmQhWc/WzzcdDwxXgVkG5iXgaYQn6m11wQHZUtrgoceGGdAX5qEB6l6B nidw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4E3Ok1x53uRD54MUCyEQpN3NBW5jVU3TurfWo8e60LI=; b=I7YtU5OfLidKL5KsQxZhjwbFO59FPtFSo3CIJW25ymmqQDrms0v5tbYognmIG32jCq HdYGAjcjl8OhFObXjHcDaTu/r2tStWinEWnYoZe71F4LLF/yH9XotlNxPftQS6VwYAAJ LO1w9Zh6e52SXTHV/rBJO0xtohOd8PBbZmAHszbE9bkQlWJorsiVQD2JE8RyXiYrXZBx 1Eus6tDRS9oIUYrVEhOy0VFt3uiNd1L+ka1djBRTr1fD9FhFWiTr925qbDY+IS/imWep A6EmDwggV1gcA28dsVGiRPf1o+v82atM9MoeVK/9xzweeX1YKHGAmjaHVW71zkMjQU6u Zfvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.21.39; Thu, 25 May 2017 01:21:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423692AbdEYIVB (ORCPT + 7 others); Thu, 25 May 2017 04:21:01 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:35679 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423678AbdEYIUD (ORCPT ); Thu, 25 May 2017 04:20:03 -0400 Received: by mail-pf0-f174.google.com with SMTP id n23so160520371pfb.2 for ; Thu, 25 May 2017 01:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CEk6ak4alSfIGm/cBrYd0NkRqFdpaNL+qzPQmngGnUA=; b=VysoN4LR7Ar+vcufLGinyeS5j46dZGP0useI/j0IEYdkkB/Xiu6S2S8/g3+eML5ahG MT2SfMNTBY7VIwSiwVx+E+LnSrBu4DdV3N/yuPjOz6eY0vRTL62TyiZ0+SNip+CsY3Lz +zFI4UPSyg1iek18Rz5P6FvRwOV2RjLwP9g78= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CEk6ak4alSfIGm/cBrYd0NkRqFdpaNL+qzPQmngGnUA=; b=IZ64qwjTshLs973DPMfSBsWXdsl+sGAfZR/bGImV9DbHUF5OOzwMpHH8zxc93/U7Z1 r3Q0KamodQX4TxbQ8Jiu2MntkEKWh+ijIEKtAh7tx3YNbYp4OUw8Gc/adSf/60v2+jqa 76fwwvfC2n04zn8EhFKEuRLVof/hoWqQ6zuI3VtJm3+rWxm2TAX5hBQ7+aHfZcYwfrWj 5A+d58pOd1LTz46FDtS4Q4SQmU+HRaTCZ7ft4ITd1lb5w/Gh33+RgSO76Y4+eEciu0aN n3aIuP0TOBe/vIzvYQBB6zqr7AcfFUzfo9fpHd2y+ROCkJBWU4RsR7E8Tuxjx4DtHrZR WFrw== X-Gm-Message-State: AODbwcCm+FtUoDnHim/HsQQWNIhmae3UYyrKLZPA7Cq3pyUrRjXzXAHx tQwhuBjS78R7N5um X-Received: by 10.84.194.37 with SMTP id g34mr49394882pld.182.1495700402731; Thu, 25 May 2017 01:20:02 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.19.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:20:02 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH v2 11/12] arm64: dts: hikey960: add LED nodes Date: Thu, 25 May 2017 16:18:53 +0800 Message-Id: <20170525081854.4701-12-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org HiKey960 has four user LEDs, and two special purpose LEDs: WiFi and BT respectively. All of them are implemented as GPIO. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 7aac35b..9ecf6c6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -49,6 +49,54 @@ linux,code = ; }; }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + /* gpio_150_user_led1 */ + gpios = <&gpio18 6 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "user_led2"; + /* gpio_151_user_led2 */ + gpios = <&gpio18 7 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "user_led3"; + /* gpio_189_user_led3 */ + gpios = <&gpio23 5 0>; + default-state = "off"; + }; + + user_led4 { + label = "user_led4"; + /* gpio_190_user_led4 */ + gpios = <&gpio23 6 0>; + linux,default-trigger = "cpu0"; + }; + + wlan_active_led { + label = "wifi_active"; + /* gpio_205_wifi_active */ + gpios = <&gpio25 5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "bt_active"; + gpios = <&gpio25 7 0>; + /* gpio_207_user_led1 */ + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; }; &i2c0 { From patchwork Thu May 25 08:18:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 100473 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp731489obb; Thu, 25 May 2017 01:21:37 -0700 (PDT) X-Received: by 10.99.227.81 with SMTP id o17mr43719397pgj.41.1495700497363; Thu, 25 May 2017 01:21:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495700497; cv=none; d=google.com; s=arc-20160816; b=GYsEp8ZIMKRUF66e78DyJ38kLFStXVgp7RMVEJyoEiSoI4ngkx63WmF+G+xiNO3zA2 QZ7bNWMtr2uZe6+XWcd2AoT0d9DTdA6cWR91RZJRuglhfb43S08nK/xDIvtQ5f2ANsnH dRHCvzlqWzVx2j5qbdFr5aBiLqh9cf03B6aWL8VcSlP54a4kZ/9c/jZ6cx4lxKRhvKXG rTdch29mWb1IoOJrPL83LxGlUZKH97bd2A62iyGBdmOgvKMAxEjOUlEktrWoZmhau3zZ /P3EMBRRhdSSWVdW3mvFT/5avseAEq6rtZiSLmKhVnUmuJHACZtT6Y/GwJES5I6QPQei ydYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wBaqRVwQW+ziMgwr71ygi0UDv0IpDOPwo0Z6IzmYsMw=; b=pViEN2vtO4I7BpDnciUyzalIKWDFOuD8uNlLQ9HrSI6hdAZ/TGl7iLvxgU8pDv8mhk st48Ecp2L95jfgn/nZiIwapCx6wBkD394KnJalU5BfOiBHYdqRt/hAICWsmpKQId9ula hf00omauxczx4l92ETLA7PtkNaCJg4V0yveAC4DNjXvMEKmYDDEkFYqFCZB9gbYkNrEI /nCK66JeJXvHTVFJsp7KJB+IxzwnDx4ZYQejGHyaSsqLd9b9OMGEx6S4/J9EijigICYo xNqDfZQf2he9uboOgEWZmu3mxUvjUZ7myuIWZpLbV4qOrJ3keuwZAIgu/Jng0TlA2/DQ XahA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si27179390plk.94.2017.05.25.01.21.37; Thu, 25 May 2017 01:21:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423678AbdEYIVL (ORCPT + 7 others); Thu, 25 May 2017 04:21:11 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35719 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423683AbdEYIUN (ORCPT ); Thu, 25 May 2017 04:20:13 -0400 Received: by mail-pf0-f181.google.com with SMTP id n23so160522487pfb.2 for ; Thu, 25 May 2017 01:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=dCcyZBuyrZSkKVNLffeQP85uXVKvTvvJ85ai+4Edg9zN4qdsdGwVzStU4i4X6cP1By ui1ZNDOcLgFhpIwahgv931Y06c2XjaFCfzJA3ygXc+oq5Bj9ZZ0AgpaiiR2Vj7H606Z8 QiJAFNkaR9syuqySJVvMgZDD1i5Siv3RLJaY0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=lUwOaXd1zt9oO8HbDlFHPoKhpw64Ll11QgMerH24khBtMq3eRYz8HZ4Xws7pjUb35d l91FbxrWGbqDXxuD3Y1Li5Ex3JF1H8XLSqUsbQ623jxoZA0n30zLZJfYqzsmcyHzBYP1 2mSlYArq0dhWFM4ssB1znEVaXSDf/Ha45KS/IiBI+tdN18WP2nxjcawIUILRmvr6pxXc yzUYz/VjhiPrNbmYI5x/Jj286J5CfYV6cFoxOHnZq/bxI5CTMkwYSuxbcALLQRNX0+9V pC767KOTMGAo4aYtY3ZW2htGl7yEHx9Zwylo2RywDwA1YtA3mfvQ4bSltlTtCP940OrU er4w== X-Gm-Message-State: AODbwcBRG8UtGUBYH8NHf+6q0yKi7OHOMqm3BM2VjJk2Ezb7mjufYuqc pY43yQuwELvN54pnjgTJBw== X-Received: by 10.99.126.92 with SMTP id o28mr45207549pgn.63.1495700407718; Thu, 25 May 2017 01:20:07 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id b72sm11574470pfd.118.2017.05.25.01.20.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 25 May 2017 01:20:07 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH v2 12/12] arm64: dts: hi3660: add spi device nodes Date: Thu, 25 May 2017 16:18:54 +0800 Message-Id: <20170525081854.4701-13-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170525081854.4701-1-guodong.xu@linaro.org> References: <20170525081854.4701-1-guodong.xu@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 9ecf6c6..ca448f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -142,3 +142,15 @@ label = "LS-UART1"; status = "okay"; }; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3b2a3a7..a6b91f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -713,5 +713,35 @@ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; };