From patchwork Wed Oct 31 21:21:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149882 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp11400ljp; Wed, 31 Oct 2018 14:25:56 -0700 (PDT) X-Google-Smtp-Source: AJdET5cNqqZ90TCyBpk0anX/4mrUSdMCTdkcty7efDO6Sl7M2qgZVrDcNrSleE2NLLyu4nF3PoJO X-Received: by 2002:aa7:c247:: with SMTP id y7-v6mr3283496edo.205.1541021155994; Wed, 31 Oct 2018 14:25:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541021155; cv=none; d=google.com; s=arc-20160816; b=XXsw8Pi6+fApgqBpyPKVnOH8Z7pf1DdEsGUerLmID74ZMKJ0a35NWdnlKZNVb+LGPD FcHnhUS0qsLvTB8u2uIosfWofghqQpha5Q8wIEYuT2DTyTsRsP8cGtFpxtehXL2toQqo iIIcniowu27SRjPkAEO85tF5Ofb7jRq49K0VMquOPXFfwg3dhMmfjB82voE1zmrEBiE7 hEKd9MVJliqh6cldAoVxaGq5D7j3F8OxGn7XZf6s4k3H7wtu+J4Sbv5+OvuRitsz8liD y9rblwtliWEm+iYjkumkOnhDk97Mi+tJIcJtXqZEWLZGOK7raQKQ1FQubdBu4KiH1ItC vvkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from; bh=wHSf8bmdlIiVjNyeEEiE3REmu6rSmLPFjZRQsev7bBI=; b=AxHBqnteNwyprl/wAJCJsYlprm9E0eWeME3b4HTh/he09CrsrnmNX571lRUKxiYcqR qQAXNC5PR71Z/oBlglyMmxskdtqqYe1wfnbQg5ZWyFbFhxG/ZUHkc/U3kW1kCALXv/r9 dBUyOsjXe64VDW68/M+WMTVb0sNuMpqFqc2x3D6eZYW7l8J/yc3BU1j3FQd8D2bjI6cy t1aOAAMBQ2zW3EyHJgaxkbSq/qaaPtKWGfDKIpajFE/KN+IR7AFtkRN9ilVu6nfte7Gt 9QrL5xBhJDdGitIeHDAbFD7iWlTOfWWrA0jf06tV7po+guY5uTXBfTvZv9k6VzYIHwjy PWrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t2-v6si4871107ejj.133.2018.10.31.14.25.55; Wed, 31 Oct 2018 14:25:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 58743C222FE; Wed, 31 Oct 2018 21:24:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A3870C222F1; Wed, 31 Oct 2018 21:22:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 80431C21E70; Wed, 31 Oct 2018 21:21:54 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id E2562C22008 for ; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLlFZ118720; Wed, 31 Oct 2018 16:21:47 -0500 Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLlZe068336 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:47 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:46 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLkKJ024888; Wed, 31 Oct 2018 16:21:46 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLkx26187; Wed, 31 Oct 2018 16:21:46 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:39 -0500 Message-ID: <20181031212145.32761-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 1/7] driver: net: consolidate ti's code in separate folder X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add drivers/net/ti/ folder and move all TI's code in this folder for better maintenance. Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- arch/arm/mach-davinci/dp83848.c | 2 +- arch/arm/mach-davinci/et1011c.c | 2 +- arch/arm/mach-davinci/ksz8873.c | 2 +- arch/arm/mach-davinci/lxt972.c | 2 +- drivers/net/Kconfig | 13 +------------ drivers/net/Makefile | 4 +--- drivers/net/ti/Kconfig | 15 +++++++++++++++ drivers/net/ti/Makefile | 7 +++++++ drivers/net/{ => ti}/cpsw-common.c | 0 drivers/net/{ => ti}/cpsw.c | 0 drivers/net/{ => ti}/davinci_emac.c | 0 drivers/net/{ => ti}/davinci_emac.h | 0 drivers/net/{ => ti}/keystone_net.c | 0 13 files changed, 28 insertions(+), 19 deletions(-) create mode 100644 drivers/net/ti/Kconfig create mode 100644 drivers/net/ti/Makefile rename drivers/net/{ => ti}/cpsw-common.c (100%) rename drivers/net/{ => ti}/cpsw.c (100%) rename drivers/net/{ => ti}/davinci_emac.c (100%) rename drivers/net/{ => ti}/davinci_emac.h (100%) rename drivers/net/{ => ti}/keystone_net.c (100%) diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c index 595e3ca..7115d7b 100644 --- a/arch/arm/mach-davinci/dp83848.c +++ b/arch/arm/mach-davinci/dp83848.c @@ -12,7 +12,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c index 3d02274..bfb7ff2 100644 --- a/arch/arm/mach-davinci/et1011c.c +++ b/arch/arm/mach-davinci/et1011c.c @@ -9,7 +9,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c index 899cff0..85b0c26 100644 --- a/arch/arm/mach-davinci/ksz8873.c +++ b/arch/arm/mach-davinci/ksz8873.c @@ -19,7 +19,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" int ksz8873_is_phy_connected(int phy_addr) { diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c index 170e4a5..b54f67d 100644 --- a/arch/arm/mach-davinci/lxt972.c +++ b/arch/arm/mach-davinci/lxt972.c @@ -13,7 +13,7 @@ #include #include #include -#include "../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/ti/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f1f0e2d..e904c5e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,5 +1,6 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" +source "drivers/net/ti/Kconfig" config DM_ETH bool "Enable Driver Model for Ethernet drivers" @@ -11,13 +12,6 @@ config DM_ETH This is currently implemented in net/eth-uclass.c Look in include/net.h for details. -config DRIVER_TI_CPSW - bool "TI Common Platform Ethernet Switch" - select PHYLIB - help - This driver supports the TI three port switch gigabit ethernet - subsystem found in the TI SoCs. - menuconfig NETDEVICES bool "Network device support" depends on NET @@ -322,11 +316,6 @@ config SH_ETHER help This driver supports the Ethernet for Renesas SH and ARM SoCs. -config DRIVER_TI_EMAC - bool "TI Davinci EMAC" - help - Support for davinci emac - config XILINX_AXIEMAC depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878..8e33d7a 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o -obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o @@ -56,9 +55,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o obj-$(CONFIG_RENESAS_RAVB) += ravb.o obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o -obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o -obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_ULI526X) += uli526x.o obj-$(CONFIG_VSC7385_ENET) += vsc7385.o @@ -73,3 +70,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-y += ti/ diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig new file mode 100644 index 0000000..35a6b5d --- /dev/null +++ b/drivers/net/ti/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + +config DRIVER_TI_CPSW + bool "TI Common Platform Ethernet Switch" + select PHYLIB + help + This driver supports the TI three port switch gigabit ethernet + subsystem found in the TI SoCs. + +config DRIVER_TI_EMAC + bool "TI Davinci EMAC" + help + Support for davinci emac diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile new file mode 100644 index 0000000..4ab4a27 --- /dev/null +++ b/drivers/net/ti/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o +obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o diff --git a/drivers/net/cpsw-common.c b/drivers/net/ti/cpsw-common.c similarity index 100% rename from drivers/net/cpsw-common.c rename to drivers/net/ti/cpsw-common.c diff --git a/drivers/net/cpsw.c b/drivers/net/ti/cpsw.c similarity index 100% rename from drivers/net/cpsw.c rename to drivers/net/ti/cpsw.c diff --git a/drivers/net/davinci_emac.c b/drivers/net/ti/davinci_emac.c similarity index 100% rename from drivers/net/davinci_emac.c rename to drivers/net/ti/davinci_emac.c diff --git a/drivers/net/davinci_emac.h b/drivers/net/ti/davinci_emac.h similarity index 100% rename from drivers/net/davinci_emac.h rename to drivers/net/ti/davinci_emac.h diff --git a/drivers/net/keystone_net.c b/drivers/net/ti/keystone_net.c similarity index 100% rename from drivers/net/keystone_net.c rename to drivers/net/ti/keystone_net.c From patchwork Wed Oct 31 21:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149881 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp10821ljp; Wed, 31 Oct 2018 14:25:19 -0700 (PDT) X-Google-Smtp-Source: AJdET5eUFMbUqgAOcrGEOng3QmGnJ8Wfw3NdwPYV00Z5nNZfpNEpcO+UnwPgYXLU5h71OPiy+QqC X-Received: by 2002:a50:aa48:: with SMTP id p8-v6mr3508726edc.82.1541021119153; Wed, 31 Oct 2018 14:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541021119; cv=none; d=google.com; s=arc-20160816; b=fl5o9kU1g2tb3e3V1rHYZgEdITgAZCbvGV7uz80wK5M4XDuxgKmu7MrvolZ6xPLwYE G5FiQBkBPipV53T4JZH3ZhAqxGenDcOdFKPIfiqWsM3YgAnZBM5IHxPYMskS/uabIaMx +IRHenge01YhfAF+2GNVvFbEYM5RVzdYFkfHamNhESxHSKlX/zTXSp/aFsv/0bUCVdME 1bYzsgY71EBEix7SfDNtAzIkznoYjSE5SSCoXF0i1B+sRCOZpWgpTIxeTokCrZLo/StJ sbBbJcxyh+ZmSDhjQuOpz2rkwPCx8LsX7X4+8ULzZZEXzodlW0dIfxXZOJ+w3p3mCNYk 5eNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from; bh=ORN3x//lwdQZctuD9dLZyaEVWUQvgxzCLQR905b0GJc=; b=U2L/TREjCMSE3laj1ZimWzJXK0QRncM3EK91P5D+oixmXgOpDYifsQnRzZcjXAEKUt CDZtLBfcCksi/K4l9pp/usrK9EkHok/zYXLwEZR6aimvWHZaXhRwYGlW9mvAbn2DEqy3 pfVKSeUFPxQYJOao84+ikj9YXKHd30WKaySEgxdIu9QlMBSMgAD8sneY69TVdzgGE/17 UKiK7qs3ye0EMX38kIx/x9TueYSmW78XTGXaB3LdpnCNoRrwDCeFrVlZPPDtMGGTOGU9 lkdszErVSwAAQ4l7QDXAwisr7i/XzhrQeLQX1sa2TwDvG9gQK0U339ZrBB0YzjMa0y53 u8kA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id j2-v6si2721629ejj.39.2018.10.31.14.25.18; Wed, 31 Oct 2018 14:25:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id B1DB4C2208C; Wed, 31 Oct 2018 21:24:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72BB1C22108; Wed, 31 Oct 2018 21:22:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 97CCBC22008; Wed, 31 Oct 2018 21:21:54 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id E2878C22009 for ; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLlQ8072318; Wed, 31 Oct 2018 16:21:47 -0500 Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLlMJ068339 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:47 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:47 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLl66024892; Wed, 31 Oct 2018 16:21:47 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLkx26191; Wed, 31 Oct 2018 16:21:46 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:40 -0500 Message-ID: <20181031212145.32761-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 2/7] configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Convert DRIVER_TI_KEYSTONE_NET to Kconfig. Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/net/ti/Kconfig | 5 +++++ include/configs/ti_armv7_keystone2.h | 1 - 10 files changed, 13 insertions(+), 1 deletion(-) diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index d744cb1..67b1f30 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -56,3 +56,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 87faf3d..1abda84 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -49,3 +49,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index a96029c..bc4b92b 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -60,3 +60,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 9e75500..66d8220 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -53,3 +53,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 8c7d362..f66d922 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -56,3 +56,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index c8f4bbe..dd91a51 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -49,3 +49,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index dd91aa5..4f04caa 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -56,3 +56,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index ac400e4..9ce23de 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -48,3 +48,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DRIVER_TI_KEYSTONE_NET=y diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 35a6b5d..c38e273 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -13,3 +13,8 @@ config DRIVER_TI_EMAC bool "TI Davinci EMAC" help Support for davinci emac + +config DRIVER_TI_KEYSTONE_NET + bool "TI Keystone 2 Ethernet" + help + This driver supports the TI Keystone 2 Ethernet subsystem \ No newline at end of file diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cc823c5..5e504f6 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -128,7 +128,6 @@ #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE /* Keystone net */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE From patchwork Wed Oct 31 21:21:41 2018 Content-Type: text/plain; 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[81.169.180.215]) by mx.google.com with ESMTP id b58-v6si9175466ede.270.2018.10.31.14.22.35; Wed, 31 Oct 2018 14:22:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=azU1OVOV; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 026EFC2208C; Wed, 31 Oct 2018 21:22:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52EA0C2208C; Wed, 31 Oct 2018 21:21:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BC9CDC22008; Wed, 31 Oct 2018 21:21:52 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id E4E1FC21FED for ; Wed, 31 Oct 2018 21:21:51 +0000 (UTC) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLlR0118724; Wed, 31 Oct 2018 16:21:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1541020907; bh=ZKz+PMn4moH1zyILk7G3/D+sFtKzIRr8c1nNemEeseY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=azU1OVOVvwH/PbIIvJ1yG/+lc2A//dBfO4RZA3Ep3ZrXuPHS15Prz5V2epGt0vjAK Bd63xIhbLUe85dhfXldby4LVglmAIioBuU6gGG/VJ2wERaHGddanHT9plyLO2Tnq2k Oti6D1/UTJsov1Oo27GjsYfcIMnWrYi+3LSaPRu4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLlaM062439 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:47 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:47 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLlth031379; Wed, 31 Oct 2018 16:21:47 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLlx26195; Wed, 31 Oct 2018 16:21:47 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:41 -0500 Message-ID: <20181031212145.32761-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 3/7] drivers: net: keystone_net: drop non dm code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Networking support for all TI K2 boards converted to use DM model and CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop unused non DM K2 networking code. Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- arch/arm/include/asm/ti-common/keystone_net.h | 14 -- board/ti/ks2_evm/board.c | 53 ----- board/ti/ks2_evm/board.h | 3 - board/ti/ks2_evm/board_k2e.c | 74 ------- board/ti/ks2_evm/board_k2g.c | 18 -- board/ti/ks2_evm/board_k2hk.c | 42 ---- board/ti/ks2_evm/board_k2l.c | 42 ---- drivers/net/ti/keystone_net.c | 287 +------------------------- 8 files changed, 1 insertion(+), 532 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index f89e043..bef1867 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -242,18 +242,4 @@ struct mdio_regs { u32 userphysel1; }; -struct eth_priv_t { - char int_name[32]; - int rx_flow; - int phy_addr; - int slave_port; - int sgmii_link_type; - phy_interface_t phy_if; - struct phy_device *phy_dev; -}; - -int keystone2_emac_initialize(struct eth_priv_t *eth_priv); -void sgmii_serdes_setup_156p25mhz(void); -void sgmii_serdes_shutdown(void); - #endif /* _KEYSTONE_NET_H_ */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index d81c8e6..72709c0 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -66,59 +66,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -#ifndef CONFIG_DM_ETH -int get_eth_env_param(char *env_name) -{ - char *env; - int res = -1; - - env = env_get(env_name); - if (env) - res = simple_strtol(env, NULL, 0); - - return res; -} - -int board_eth_init(bd_t *bis) -{ - int j; - int res; - int port_num; - char link_type_name[32]; - - if (cpu_is_k2g()) - writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); - - /* By default, select PA PLL clock as PA clock source */ -#ifndef CONFIG_SOC_K2G - if (psc_enable_module(KS2_LPSC_PA)) - return -1; -#endif - if (psc_enable_module(KS2_LPSC_CPGMAC)) - return -1; - if (psc_enable_module(KS2_LPSC_CRYPTO)) - return -1; - - if (cpu_is_k2e() || cpu_is_k2l()) - pll_pa_clk_sel(); - - port_num = get_num_eth_ports(); - - for (j = 0; j < port_num; j++) { - sprintf(link_type_name, "sgmii%d_link_type", j); - res = get_eth_env_param(link_type_name); - if (res >= 0) - eth_priv_cfg[j].sgmii_link_type = res; - - keystone2_emac_initialize(ð_priv_cfg[j]); - } - - return 0; -} -#endif -#endif - #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index 250b649..d0cfbf5 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -12,8 +12,6 @@ #include #include "../common/board_detect.h" -extern struct eth_priv_t eth_priv_cfg[]; - #if defined(CONFIG_TI_I2C_BOARD_DETECT) static inline int board_is_k2g_gp(void) { @@ -38,7 +36,6 @@ static inline int board_is_k2g_ice(void) } #endif -int get_num_eth_ports(void); void spl_init_keystone_plls(void); #endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index f86a836..ecd4a42 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -89,80 +89,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2E_EMAC0", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC1", - .rx_flow = 8, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC2", - .rx_flow = 16, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC3", - .rx_flow = 24, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC4", - .rx_flow = 32, - .phy_addr = 4, - .slave_port = 5, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC5", - .rx_flow = 40, - .phy_addr = 5, - .slave_port = 6, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC6", - .rx_flow = 48, - .phy_addr = 6, - .slave_port = 7, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2E_EMAC7", - .rx_flow = 56, - .phy_addr = 7, - .slave_port = 8, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #if defined(CONFIG_MULTI_DTB_FIT) int board_fit_config_name_match(const char *name) { diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 9bc94fb..87dc4d0 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -354,24 +354,6 @@ void spl_init_keystone_plls(void) } #endif -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2G_EMAC", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_TI_SECURE_DEVICE void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size) { diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index abc89d8..4c0acd6 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -96,48 +96,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2HK_EMAC", - .rx_flow = 22, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC1", - .rx_flow = 23, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC2", - .rx_flow = 24, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2HK_EMAC3", - .rx_flow = 25, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index c28fad5..e49d8b3 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -84,48 +84,6 @@ struct pll_init_data *get_pll_init_data(int pll) return data; } -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2L_EMAC", - .rx_flow = 0, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC1", - .rx_flow = 8, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC2", - .rx_flow = 16, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, - { - .int_name = "K2L_EMAC3", - .rx_flow = 32, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - .phy_if = PHY_INTERFACE_MODE_SGMII, - }, -}; - -int get_num_eth_ports(void) -{ - return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index d4d909b..5550572 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -24,12 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_ETH -unsigned int emac_open; -static struct mii_dev *mdio_bus; -static unsigned int sys_has_mdio = 1; -#endif - #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) #else @@ -43,17 +37,6 @@ static unsigned int sys_has_mdio = 1; static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); -#ifndef CONFIG_DM_ETH -struct rx_buff_desc net_rx_buffs = { - .buff_ptr = rx_buffs, - .num_buffs = RX_BUFF_NUMS, - .buff_len = RX_BUFF_LEN, - .rx_flow = 22, -}; -#endif - -#ifdef CONFIG_DM_ETH - enum link_type { LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0, LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1, @@ -83,7 +66,7 @@ enum link_type { #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ (x) * 0x30) -#elif defined CONFIG_KSNET_NETCP_V1_5 +#elif defined(CONFIG_KSNET_NETCP_V1_5) #define EMAC_EMACSW_PORT_BASE_OFS 0x222000 @@ -113,7 +96,6 @@ struct ks2_eth_priv { bool emac_open; bool has_mdio; }; -#endif /* MDIO */ @@ -184,31 +166,6 @@ static int keystone2_mdio_write(struct mii_dev *bus, return 0; } -#ifndef CONFIG_DM_ETH -static void __attribute__((unused)) - keystone2_eth_gigabit_enable(struct eth_device *dev) -{ - u_int16_t data; - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - - if (sys_has_mdio) { - data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr, - MDIO_DEVAD_NONE, 0); - /* speed selection MSB */ - if (!(data & (1 << 6))) - return; - } - - /* - * Check if link detected is giga-bit - * If Gigabit mode detected, enable gigbit in MAC - */ - writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + - CPGMACSL_REG_CTL) | - EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, - DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); -} -#else static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct udevice *dev) { @@ -232,7 +189,6 @@ static void __attribute__((unused)) EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); } -#endif #ifdef CONFIG_SOC_K2G int keystone_rgmii_config(struct phy_device *phy_dev) @@ -497,246 +453,6 @@ static void keystone2_net_serdes_setup(void) } #endif -#ifndef CONFIG_DM_ETH - -int keystone2_eth_read_mac_addr(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv; - u32 maca = 0; - u32 macb = 0; - - eth_priv = (struct eth_priv_t *)dev->priv; - - /* Read the e-fuse mac address */ - if (eth_priv->slave_port == 1) { - maca = __raw_readl(MAC_ID_BASE_ADDR); - macb = __raw_readl(MAC_ID_BASE_ADDR + 4); - } - - dev->enetaddr[0] = (macb >> 8) & 0xff; - dev->enetaddr[1] = (macb >> 0) & 0xff; - dev->enetaddr[2] = (maca >> 24) & 0xff; - dev->enetaddr[3] = (maca >> 16) & 0xff; - dev->enetaddr[4] = (maca >> 8) & 0xff; - dev->enetaddr[5] = (maca >> 0) & 0xff; - - return 0; -} - -int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) -{ - if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) - num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; - - return ksnav_send(&netcp_pktdma, buffer, - num_bytes, (slave_port_num) << 16); -} - -/* Eth device open */ -static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) -{ - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - debug("+ emac_open\n"); - - net_rx_buffs.rx_flow = eth_priv->rx_flow; - - sys_has_mdio = - (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; - - if (sys_has_mdio) - keystone2_mdio_reset(mdio_bus); - -#ifdef CONFIG_SOC_K2G - keystone_rgmii_config(phy_dev); -#else - keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, - eth_priv->sgmii_link_type); -#endif - - udelay(10000); - - /* On chip switch configuration */ - ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); - - /* TODO: add error handling code */ - if (qm_init()) { - printf("ERROR: qm_init()\n"); - return -1; - } - if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { - qm_close(); - printf("ERROR: netcp_init()\n"); - return -1; - } - - /* - * Streaming switch configuration. If not present this - * statement is defined to void in target.h. - * If present this is usually defined to a series of register writes - */ - hw_config_streaming_switch(); - - if (sys_has_mdio) { - keystone2_mdio_reset(mdio_bus); - - phy_startup(phy_dev); - if (phy_dev->link == 0) { - ksnav_close(&netcp_pktdma); - qm_close(); - return -1; - } - } - - emac_gigabit_enable(dev); - - ethss_start(); - - debug("- emac_open\n"); - - emac_open = 1; - - return 0; -} - -/* Eth device close */ -void keystone2_eth_close(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - debug("+ emac_close\n"); - - if (!emac_open) - return; - - ethss_stop(); - - ksnav_close(&netcp_pktdma); - qm_close(); - phy_shutdown(phy_dev); - - emac_open = 0; - - debug("- emac_close\n"); -} - -/* - * This function sends a single packet on the network and returns - * positive number (number of bytes transmitted) or negative for error - */ -static int keystone2_eth_send_packet(struct eth_device *dev, - void *packet, int length) -{ - int ret_status = -1; - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - struct phy_device *phy_dev = eth_priv->phy_dev; - - genphy_update_link(phy_dev); - if (phy_dev->link == 0) - return -1; - - if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) - return ret_status; - - return length; -} - -/* - * This function handles receipt of a packet from the network - */ -static int keystone2_eth_rcv_packet(struct eth_device *dev) -{ - void *hd; - int pkt_size; - u32 *pkt; - - hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); - if (hd == NULL) - return 0; - - net_process_received_packet((uchar *)pkt, pkt_size); - - ksnav_release_rxhd(&netcp_pktdma, hd); - - return pkt_size; -} - -#ifdef CONFIG_MCAST_TFTP -static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set) -{ - return 0; -} -#endif - -/* - * This function initializes the EMAC hardware. - */ -int keystone2_emac_initialize(struct eth_priv_t *eth_priv) -{ - int res; - struct eth_device *dev; - struct phy_device *phy_dev; - struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; - - dev = malloc(sizeof(struct eth_device)); - if (dev == NULL) - return -1; - - memset(dev, 0, sizeof(struct eth_device)); - - strcpy(dev->name, eth_priv->int_name); - dev->priv = eth_priv; - - keystone2_eth_read_mac_addr(dev); - - dev->iobase = 0; - dev->init = keystone2_eth_open; - dev->halt = keystone2_eth_close; - dev->send = keystone2_eth_send_packet; - dev->recv = keystone2_eth_rcv_packet; -#ifdef CONFIG_MCAST_TFTP - dev->mcast = keystone2_eth_bcast_addr; -#endif - - eth_register(dev); - - /* Register MDIO bus if it's not registered yet */ - if (!mdio_bus) { - mdio_bus = mdio_alloc(); - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR; - strcpy(mdio_bus->name, "ethernet-mdio"); - - res = mdio_register(mdio_bus); - if (res) - return res; - } - -#ifndef CONFIG_SOC_K2G - keystone2_net_serdes_setup(); -#endif - - /* Create phy device and bind it with driver */ -#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE - phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, - dev, eth_priv->phy_if); - phy_config(phy_dev); -#else - phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, - eth_priv->phy_if); - phy_dev->dev = dev; -#endif - eth_priv->phy_dev = phy_dev; - - return 0; -} - -#else - static int ks2_eth_start(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); @@ -1167,4 +883,3 @@ U_BOOT_DRIVER(eth_ks2) = { .platdata_auto_alloc_size = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif From patchwork Wed Oct 31 21:21:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149879 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9806ljp; Wed, 31 Oct 2018 14:24:03 -0700 (PDT) X-Google-Smtp-Source: AJdET5dGy4XwwCSpWinOUdRjecnBd5TyQjcSYHRVpW84TEtlUp/x8oZ74J09ej0lxO9IcfLhCrVg X-Received: by 2002:a50:9784:: with SMTP id e4-v6mr3401718edb.124.1541021043215; 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[81.169.180.215]) by mx.google.com with ESMTP id x24-v6si449000ejw.49.2018.10.31.14.24.02; Wed, 31 Oct 2018 14:24:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id C1FD3C2215D; Wed, 31 Oct 2018 21:23:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C2C27C22305; Wed, 31 Oct 2018 21:22:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 30567C21FED; Wed, 31 Oct 2018 21:21:54 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id C943EC21FFB for ; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLl8p072322; Wed, 31 Oct 2018 16:21:47 -0500 Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLlYt040005 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:47 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:47 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLlpI024895; Wed, 31 Oct 2018 16:21:47 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLlx26199; Wed, 31 Oct 2018 16:21:47 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:42 -0500 Message-ID: <20181031212145.32761-5-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 4/7] driver: net: ti: cpsw: update to use SPDX identifier X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update to use SPDX license identifier. Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- drivers/net/ti/cpsw.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 8e2a48c..fe43d14 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * CPSW Ethernet Switch Driver * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ */ #include From patchwork Wed Oct 31 21:21:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149876 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7928ljp; Wed, 31 Oct 2018 14:22:01 -0700 (PDT) X-Google-Smtp-Source: AJdET5cgyfAQmd+9do66Tp7NnquFhq36q4UKcl8H4KWCB5GNJtdXGG1bf6ZGCjs+Na+2WMEOvECk X-Received: by 2002:a17:906:6a11:: with SMTP id o17-v6mr2427055ejr.99.1541020920954; Wed, 31 Oct 2018 14:22:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541020920; cv=none; d=google.com; s=arc-20160816; b=PcVqftKK4yEeQU+AQIbjv6Uwgqv+B6s7LACV4WaXTTffverzCyvAGt/OAiCqrxCw4c TEUzccWwD1wDVj7wh+Dj3wPkgwWN0z977fyeiAufS38ToadEVwk7HUFyrBsQjUyXDOM6 CKHgy5+OtVrs+lXReSQ1yFH8iN21wGXS2YuVd4rhMtAjyeoKlerWzfog+yXKf4qIVoTQ xJg6uvIw9/raVUNLv45/4QVRaIDhJ/q9JTqPwN5e7zNTVMrrrRWs/wZGhcS9oXGLB/HB v7IbADXqgx+DGuf97kP93IDV5poTLZOevVGb5r6aSedPrPGFIdYeALT9cR6QxC/sy7Ft gGmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from; bh=1ArJb6/P/QxDRkgsbIgZc/jttauvNqN8pesdnJGtY0g=; b=03XkrJFYzs4BR5WUdkkRdiNpAY0wnjU7KdXvFSJqZ44d0Tp5um06sd/YrEeJcXxMuC hZYFgIfMPZPUQ6BrpFHjK1F9yR50xum9NE6KKHActqZfBNElZVLQ6P/g8566NVUAFGVm G4QjoHH0TUBH0pChPWbkOJQ7kk/Hn4KOn6qURywoznQ1YXXB0uhvIV24hwJPgQgejRCz /0XIHFszVyUt+15PANgvEsObjBfnjW2M6tDNKLHKQ0+VU5obvOTzZGsClw82lL6xCDLG sEmho/Pc2gSZdMoaIq7zNUjCaLJhoj6DS0o9hKl/CKINVLNL9EliWLs0CFp4dwMAOfE0 J9eA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c1-v6si7765294ejf.46.2018.10.31.14.22.00; Wed, 31 Oct 2018 14:22:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 17F51C222FF; Wed, 31 Oct 2018 21:21:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 99C03C22009; Wed, 31 Oct 2018 21:21:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ADCB1C21FFB; Wed, 31 Oct 2018 21:21:52 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id DDD52C21E70 for ; Wed, 31 Oct 2018 21:21:51 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLmc1118728; Wed, 31 Oct 2018 16:21:48 -0500 Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLmoC040008 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:48 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:47 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLliD015774; Wed, 31 Oct 2018 16:21:47 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLlx26203; Wed, 31 Oct 2018 16:21:47 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:43 -0500 Message-ID: <20181031212145.32761-6-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 5/7] driver: net: ti: introduce common mdio support library X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" All existing TI SoCs network HW have similar MDIO implementation, so introduce common mdio support library which can be reused by TI networking drivers. Reviewed-by: Tom Rini Signed-off-by: Grygorii Strashko Acked-by: Joe Hershberger --- drivers/net/ti/Makefile | 2 +- drivers/net/ti/cpsw_mdio.c | 203 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ti/cpsw_mdio.h | 18 ++++ 3 files changed, 222 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ti/cpsw_mdio.c create mode 100644 drivers/net/ti/cpsw_mdio.h diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index 4ab4a27..d2b6f20 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -2,6 +2,6 @@ # # Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o +obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c new file mode 100644 index 0000000..70f547e --- /dev/null +++ b/drivers/net/ti/cpsw_mdio.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include +#include + +struct cpsw_mdio_regs { + u32 version; + u32 control; +#define CONTROL_IDLE BIT(31) +#define CONTROL_ENABLE BIT(30) +#define CONTROL_FAULT BIT(19) +#define CONTROL_FAULT_ENABLE BIT(18) +#define CONTROL_DIV_MASK GENMASK(15, 0) + + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 __reserved_0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclr; + u32 __reserved_1[20]; + + struct { + u32 access; + u32 physel; +#define USERACCESS_GO BIT(31) +#define USERACCESS_WRITE BIT(30) +#define USERACCESS_ACK BIT(29) +#define USERACCESS_READ (0) +#define USERACCESS_PHY_REG_SHIFT (21) +#define USERACCESS_PHY_ADDR_SHIFT (16) +#define USERACCESS_DATA GENMASK(15, 0) + } user[0]; +}; + +#define CPSW_MDIO_DIV_DEF 0xff +#define PHY_REG_MASK 0x1f +#define PHY_ID_MASK 0x1f + +/* + * This timeout definition is a worst-case ultra defensive measure against + * unexpected controller lock ups. Ideally, we should never ever hit this + * scenario in practice. + */ +#define CPSW_MDIO_TIMEOUT 100 /* msecs */ + +struct cpsw_mdio { + struct cpsw_mdio_regs *regs; + struct mii_dev *bus; + int div; +}; + +/* wait until hardware is ready for another user access */ +static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio) +{ + return wait_for_bit_le32(&mdio->regs->user[0].access, + USERACCESS_GO, false, + CPSW_MDIO_TIMEOUT, false); +} + +static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, + int dev_addr, int phy_reg) +{ + struct cpsw_mdio *mdio = bus->priv; + int data, ret; + u32 reg; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + reg = (USERACCESS_GO | USERACCESS_READ | + (phy_reg << USERACCESS_PHY_REG_SHIFT) | + (phy_id << USERACCESS_PHY_ADDR_SHIFT)); + writel(reg, &mdio->regs->user[0].access); + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + + reg = readl(&mdio->regs->user[0].access); + data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; + return data; +} + +static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, + int phy_reg, u16 data) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 reg; + int ret; + + if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) + return -EINVAL; + + ret = cpsw_mdio_wait_for_user_access(mdio); + if (ret) + return ret; + reg = (USERACCESS_GO | USERACCESS_WRITE | + (phy_reg << USERACCESS_PHY_REG_SHIFT) | + (phy_id << USERACCESS_PHY_ADDR_SHIFT) | + (data & USERACCESS_DATA)); + writel(reg, &mdio->regs->user[0].access); + + return cpsw_mdio_wait_for_user_access(mdio); +} + +u32 cpsw_mdio_get_alive(struct mii_dev *bus) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 val; + + val = readl(&mdio->regs->control); + return val & GENMASK(15, 0); +} + +struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base, + u32 bus_freq, int fck_freq) +{ + struct cpsw_mdio *cpsw_mdio; + int ret; + + cpsw_mdio = calloc(1, sizeof(*cpsw_mdio)); + if (!cpsw_mdio) { + debug("failed to alloc cpsw_mdio\n"); + return NULL; + } + + cpsw_mdio->bus = mdio_alloc(); + if (!cpsw_mdio->bus) { + debug("failed to alloc mii bus\n"); + free(cpsw_mdio); + return NULL; + } + + cpsw_mdio->regs = (struct cpsw_mdio_regs *)mdio_base; + + if (!bus_freq || !fck_freq) + cpsw_mdio->div = CPSW_MDIO_DIV_DEF; + else + cpsw_mdio->div = (fck_freq / bus_freq) - 1; + cpsw_mdio->div &= CONTROL_DIV_MASK; + + /* set enable and clock divider */ + writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT | + CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control); + wait_for_bit_le32(&cpsw_mdio->regs->control, + CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true); + + /* + * wait for scan logic to settle: + * the scan time consists of (a) a large fixed component, and (b) a + * small component that varies with the mii bus frequency. These + * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x + * silicon. Since the effect of (b) was found to be largely + * negligible, we keep things simple here. + */ + mdelay(1); + + cpsw_mdio->bus->read = cpsw_mdio_read; + cpsw_mdio->bus->write = cpsw_mdio_write; + cpsw_mdio->bus->priv = cpsw_mdio; + snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name); + + ret = mdio_register(cpsw_mdio->bus); + if (ret < 0) { + debug("failed to register mii bus\n"); + goto free_bus; + } + + return cpsw_mdio->bus; + +free_bus: + mdio_free(cpsw_mdio->bus); + free(cpsw_mdio); + return NULL; +} + +void cpsw_mdio_free(struct mii_dev *bus) +{ + struct cpsw_mdio *mdio = bus->priv; + u32 reg; + + /* disable mdio */ + reg = readl(&mdio->regs->control); + reg &= ~CONTROL_ENABLE; + writel(reg, &mdio->regs->control); + + mdio_unregister(bus); + mdio_free(bus); + free(mdio); +} diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h new file mode 100644 index 0000000..4a76d4e --- /dev/null +++ b/drivers/net/ti/cpsw_mdio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#ifndef CPSW_MDIO_H_ +#define CPSW_MDIO_H_ + +struct cpsw_mdio; + +struct mii_dev *cpsw_mdio_init(const char *name, u32 mdio_base, + u32 bus_freq, int fck_freq); +void cpsw_mdio_free(struct mii_dev *bus); +u32 cpsw_mdio_get_alive(struct mii_dev *bus); + +#endif /* CPSW_MDIO_H_ */ From patchwork Wed Oct 31 21:21:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149878 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp9342ljp; Wed, 31 Oct 2018 14:23:31 -0700 (PDT) X-Google-Smtp-Source: AJdET5eSbWYQPrfi3iO+F48GTq4ofgLbcqytnMRluZuW8RVRcfIKisf6m5/6G7nc5blS/JjO5kbR X-Received: by 2002:a50:d2d4:: with SMTP id q20-v6mr3338079edg.212.1541021010990; Wed, 31 Oct 2018 14:23:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541021010; cv=none; d=google.com; s=arc-20160816; b=neWP+CwyszisrdMCfI9fE9Fofd6b5ukZ0tXC5aS1ZESUItRfwTw0v4+onBqwr06iea mYSjW6ucV+82eMo1QpXJRJOiE5JNKZZHpizd3xA3ea7TM3QEmFXAbtbPTFmYc4uNwNPG 4wVjbD/Sld1lHzMErjj78ZTTgLmAxC80DYUyXOOUMJmdIkDiMVxGNXMCy5V9I+hwa3yg 4pYhPOw9pA+dPqYLMkVQLmn4COc/7UbCeUyDZcITrCqU3jadgD39UcHaGFc1NHMtPYps sVyDE6xNFDX+pv2u/hMOroijpO9DRRfwJ9HhncrSqz2MaBtPxYLpk5UVzAkDe4r3m57G QMQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from; bh=r4A0TlaJnLVe2SVXruusQYfDw0nHQAzFFYjXRtaQJ/M=; b=YV8nElKnQl4TESkiNekYYV+B6KTm89RaHk2D9urdcIfxDK+qA3pPHphn9DfKUxDgX3 GMoM7XnTY3bV8Sp9GuOn+DNNcnKjQyw+yUdjyfUfKcI6MBZjBDcyedpplJcIwEbs2Wga N5NancFLIZWa5kNNF/EO/RfnAV5Hg4tL6q/z9//ywxp5bGcyeGmq4Z6Hnhme6i1M7vJb kfXlLfl+E8kQGcYisqwDcP4T/URaEGO3/IMEEQyMSZFw7XcpP8rHT9RutSindnIxckLm Pq9xaySeEL4s8eszxOrT+hxlVZCHa+M3R793UkFJnslc0W2Fr2zJy0qJmL4sTBmLfuUf +JxA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g3-v6si4195203edh.109.2018.10.31.14.23.30; Wed, 31 Oct 2018 14:23:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 895CAC220DC; Wed, 31 Oct 2018 21:23:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4701CC221C6; Wed, 31 Oct 2018 21:21:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F24F2C22045; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id B733AC21FED for ; Wed, 31 Oct 2018 21:21:52 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLmXt072326; Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLmbp068349 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLltH000319; Wed, 31 Oct 2018 16:21:48 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLlx26207; Wed, 31 Oct 2018 16:21:47 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:44 -0500 Message-ID: <20181031212145.32761-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 6/7] driver: net: ti: cpsw: switch to use common mdio lib X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update TI CPSW driver to re-use common mdio lib Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- drivers/net/ti/cpsw.c | 134 +++----------------------------------------------- 1 file changed, 6 insertions(+), 128 deletions(-) diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index fe43d14..f5fd02e 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -21,11 +21,11 @@ #include #include +#include "cpsw_mdio.h" + DECLARE_GLOBAL_DATA_PTR; #define BITMASK(bits) (BIT(bits) - 1) -#define PHY_REG_MASK 0x1f -#define PHY_ID_MASK 0x1f #define NUM_DESCS (PKTBUFSRX * 2) #define PKT_MIN 60 #define PKT_MAX (1500 + 14 + 4 + 4) @@ -76,37 +76,8 @@ DECLARE_GLOBAL_DATA_PTR; * unexpected controller lock ups. Ideally, we should never ever hit this * scenario in practice. */ -#define MDIO_TIMEOUT 100 /* msecs */ #define CPDMA_TIMEOUT 100 /* msecs */ -struct cpsw_mdio_regs { - u32 version; - u32 control; -#define CONTROL_IDLE BIT(31) -#define CONTROL_ENABLE BIT(30) - - u32 alive; - u32 link; - u32 linkintraw; - u32 linkintmasked; - u32 __reserved_0[2]; - u32 userintraw; - u32 userintmasked; - u32 userintmaskset; - u32 userintmaskclr; - u32 __reserved_1[20]; - - struct { - u32 access; - u32 physel; -#define USERACCESS_GO BIT(31) -#define USERACCESS_WRITE BIT(30) -#define USERACCESS_ACK BIT(29) -#define USERACCESS_READ (0) -#define USERACCESS_DATA (0xffff) - } user[0]; -}; - struct cpsw_regs { u32 id_ver; u32 control; @@ -484,100 +455,6 @@ static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, __raw_writel(tmp, priv->ale_regs + offset); } -static struct cpsw_mdio_regs *mdio_regs; - -/* wait until hardware is ready for another user access */ -static inline u32 wait_for_user_access(void) -{ - u32 reg = 0; - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO)) - udelay(10); - - if (timeout == -1) { - printf("wait_for_user_access Timeout\n"); - return -ETIMEDOUT; - } - return reg; -} - -/* wait until hardware state machine is idle */ -static inline void wait_for_idle(void) -{ - int timeout = MDIO_TIMEOUT; - - while (timeout-- && - ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0)) - udelay(10); - - if (timeout == -1) - printf("wait_for_idle Timeout\n"); -} - -static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, - int dev_addr, int phy_reg) -{ - int data; - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | - (phy_id << 16)); - __raw_writel(reg, &mdio_regs->user[0].access); - reg = wait_for_user_access(); - - data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1; - return data; -} - -static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr, - int phy_reg, u16 data) -{ - u32 reg; - - if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) - return -EINVAL; - - wait_for_user_access(); - reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | - (phy_id << 16) | (data & USERACCESS_DATA)); - __raw_writel(reg, &mdio_regs->user[0].access); - wait_for_user_access(); - - return 0; -} - -static void cpsw_mdio_init(const char *name, u32 mdio_base, u32 div) -{ - struct mii_dev *bus = mdio_alloc(); - - mdio_regs = (struct cpsw_mdio_regs *)mdio_base; - - /* set enable and clock divider */ - __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control); - - /* - * wait for scan logic to settle: - * the scan time consists of (a) a large fixed component, and (b) a - * small component that varies with the mii bus frequency. These - * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x - * silicon. Since the effect of (b) was found to be largely - * negligible, we keep things simple here. - */ - udelay(1000); - - bus->read = cpsw_mdio_read; - bus->write = cpsw_mdio_write; - strcpy(bus->name, name); - - mdio_register(bus); -} - /* Set a self-clearing bit in a register, and wait for it to clear */ static inline void setbit_and_wait_for_clear32(void *addr) { @@ -1003,7 +880,7 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) static void cpsw_phy_addr_update(struct cpsw_priv *priv) { struct cpsw_platform_data *data = &priv->data; - u16 alive = mdio_regs->alive & GENMASK(15, 0); + u16 alive = cpsw_mdio_get_alive(priv->bus); int active = data->active_slave; int new_addr = ffs(alive) - 1; @@ -1044,11 +921,12 @@ int _cpsw_register(struct cpsw_priv *priv) idx = idx + 1; } - cpsw_mdio_init(priv->dev->name, data->mdio_base, data->mdio_div); + priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0); + if (!priv->bus) + return -EFAULT; cpsw_phy_addr_update(priv); - priv->bus = miiphy_get_dev_by_name(priv->dev->name); for_active_slave(slave, priv) cpsw_phy_init(priv, slave); From patchwork Wed Oct 31 21:21:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 149880 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp10616ljp; Wed, 31 Oct 2018 14:25:04 -0700 (PDT) X-Google-Smtp-Source: AJdET5dS9zGM0nnv3+kEpJbtNWexNwC2eAG/dtLltc2GF2S0WzWQCIolw/Dx49tJhTITYwrzwJZN X-Received: by 2002:a50:a506:: with SMTP id y6-v6mr3441664edb.250.1541021104349; Wed, 31 Oct 2018 14:25:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1541021104; cv=none; d=google.com; s=arc-20160816; b=P0JQzb3ZoppYostzmaCFLn7ce1eKHSikHeCh/Ec7/iLrywy9BDPJ7dAVOrfk/vy/OT TcsMHMrN/Wqgh27LAuJLei9Ma7BzrDQ+lrrPvSEdukSF6dEiwtguNs1kZ+6tyR4kJklG 2vKDfKktN085XIAmrwxO+iLUhR1gGDqab3RlWAV/SAJu/lSI3qOH/v3+81+JMQQfEBTD caDT8J8CgP9in7WE54XfoQb875NBOE5uGwjyqAD0sQULno05bV0k2mIJQ1My0o3fziCq QTU9e742yRp0o64BO5W76Y1CibPWac2gER7aD+hpcOcLaCNy7AV2Kd/JS2qoNvox0JmC u0Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from; bh=N7DENWBo3rVtU4RO5TXzLHXe4JoXTUEaF9/pRojrGho=; b=RNRDzUOvmjWweFcPJJrPhY2D9SU4L1Ur8GcUeFMYzzQby0Z9MvrXd0H5NDyEvlTNyW lJ5NwCqgUdg0v3DmVvcFtrMqWuQNBskOueF/o9UJaOHkDt9EdOx5aqI7gbW7eYtLNgvS RcHJNe9OeOyTExfG8WAyEmU803FoXQZlmiSDgfqXdYQU31v5URACwUPWpcHZUgtL3Vwn 4g9wLehYEabJjU4rV8WVSzxGigpk23JxDfHwYaDK16ZzjUi5YVLWLdtcbWodaLlrFMKF SZMdCYsXRVBlIdZHl7PKXwZM7rQ2RPd/fmmRm/htBufSfQg9ea6DVU3gxLQzVn1xBGww fzHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id y14si1445309edw.172.2018.10.31.14.25.03; Wed, 31 Oct 2018 14:25:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id B43A7C22108; Wed, 31 Oct 2018 21:23:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 10128C222FE; Wed, 31 Oct 2018 21:22:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 152CFC21E70; Wed, 31 Oct 2018 21:21:53 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id B6B22C21E70 for ; Wed, 31 Oct 2018 21:21:52 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w9VLLmHG072331; Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id w9VLLm0d068352 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Oct 2018 16:21:48 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 31 Oct 2018 16:21:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 31 Oct 2018 16:21:48 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w9VLLmI1000323; Wed, 31 Oct 2018 16:21:48 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w9VLLmx26211; Wed, 31 Oct 2018 16:21:48 -0500 (CDT) From: Grygorii Strashko To: Vitaly Andrianov , Joe Hershberger , Lokesh Vutla , Tom Rini Date: Wed, 31 Oct 2018 16:21:45 -0500 Message-ID: <20181031212145.32761-8-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181031212145.32761-1-grygorii.strashko@ti.com> References: <20181031212145.32761-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 7/7] driver: net: ti: keystone_net: switch to use common mdio lib X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Update TI Keystone 2 driver to re-use common mdio lib. Reviewed-by: Tom Rini Acked-by: Joe Hershberger Signed-off-by: Grygorii Strashko --- arch/arm/include/asm/ti-common/keystone_net.h | 13 --- drivers/net/ti/Makefile | 2 +- drivers/net/ti/keystone_net.c | 118 ++++---------------------- 3 files changed, 18 insertions(+), 115 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index bef1867..bba1048 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -57,19 +57,6 @@ /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK 0x4 - -#define MDIO_CONTROL_IDLE 0x80000000 -#define MDIO_CONTROL_ENABLE 0x40000000 -#define MDIO_CONTROL_FAULT_ENABLE 0x40000 -#define MDIO_CONTROL_FAULT 0x80000 -#define MDIO_USERACCESS0_GO 0x80000000 -#define MDIO_USERACCESS0_WRITE_READ 0x0 -#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 -#define MDIO_USERACCESS0_ACK 0x20000000 - #define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 #define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index d2b6f20..ee3e4eb 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o -obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 5550572..a3ba91c 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -22,6 +22,8 @@ #include #include +#include "cpsw_mdio.h" + DECLARE_GLOBAL_DATA_PTR; #ifdef KEYSTONE2_EMAC_GIG_ENABLE @@ -97,93 +99,20 @@ struct ks2_eth_priv { bool has_mdio; }; -/* MDIO */ - -static int keystone2_mdio_reset(struct mii_dev *bus) -{ - u_int32_t clkdiv; - struct mdio_regs *adap_mdio = bus->priv; - - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - - writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE | - MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE, - &adap_mdio->control); - - while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) - ; - - return 0; -} - -/** - * keystone2_mdio_read - read a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_read(struct mii_dev *bus, - int addr, int devad, int reg) -{ - int tmp; - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16), - &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) - ; - - if (tmp & MDIO_USERACCESS0_ACK) - return tmp & 0xffff; - - return -1; -} - -/** - * keystone2_mdio_write - write to a PHY register via MDIO interface. - * Blocks until operation is complete. - */ -static int keystone2_mdio_write(struct mii_dev *bus, - int addr, int devad, int reg, u16 val) -{ - struct mdio_regs *adap_mdio = bus->priv; - - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | - ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) | - (val & 0xffff), &adap_mdio->useraccess0); - - /* Wait for command to complete */ - while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) - ; - - return 0; -} - static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - u_int16_t data; - - if (priv->has_mdio) { - data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, - MDIO_DEVAD_NONE, 0); - /* speed selection MSB */ - if (!(data & (1 << 6))) - return; - } /* * Check if link detected is giga-bit * If Gigabit mode detected, enable gigbit in MAC */ + if (priv->has_mdio) { + if (priv->phydev->speed != 1000) + return; + } + writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL) | EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, @@ -484,8 +413,6 @@ static int ks2_eth_start(struct udevice *dev) hw_config_streaming_switch(); if (priv->has_mdio) { - keystone2_mdio_reset(priv->mdio_bus); - phy_startup(priv->phydev); if (priv->phydev->link == 0) { pr_err("phy startup failed\n"); @@ -605,9 +532,9 @@ static int ks2_eth_probe(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); struct mii_dev *mdio_bus; - int ret; priv->dev = dev; + priv->emac_open = false; /* These clock enables has to be moved to common location */ if (cpu_is_k2g()) @@ -626,45 +553,36 @@ static int ks2_eth_probe(struct udevice *dev) if (cpu_is_k2e() || cpu_is_k2l()) pll_pa_clk_sel(); - priv->net_rx_buffs.buff_ptr = rx_buffs; priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; priv->net_rx_buffs.buff_len = RX_BUFF_LEN; if (priv->slave_port == 1) { +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif /* * Register MDIO bus for slave 0 only, other slave have * to re-use the same */ - mdio_bus = mdio_alloc(); + mdio_bus = cpsw_mdio_init("ethernet-mdio", + (u32)priv->mdio_base, + EMAC_MDIO_CLOCK_FREQ, + EMAC_MDIO_BUS_FREQ); if (!mdio_bus) { pr_err("MDIO alloc failed\n"); return -ENOMEM; } priv->mdio_bus = mdio_bus; - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = priv->mdio_base; - sprintf(mdio_bus->name, "ethernet-mdio"); - - ret = mdio_register(mdio_bus); - if (ret) { - pr_err("MDIO bus register failed\n"); - return ret; - } } else { /* Get the MDIO bus from slave 0 device */ struct ks2_eth_priv *parent_priv; parent_priv = dev_get_priv(dev->parent); priv->mdio_bus = parent_priv->mdio_bus; + priv->mdio_base = parent_priv->mdio_base; } -#ifndef CONFIG_SOC_K2G - keystone2_net_serdes_setup(); -#endif - priv->netcp_pktdma = &netcp_pktdma; if (priv->has_mdio) { @@ -680,9 +598,7 @@ int ks2_eth_remove(struct udevice *dev) { struct ks2_eth_priv *priv = dev_get_priv(dev); - free(priv->phydev); - mdio_unregister(priv->mdio_bus); - mdio_free(priv->mdio_bus); + cpsw_mdio_free(priv->mdio_bus); return 0; }