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X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH] softfloat: Don't execute divdeu without power7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The divdeu instruction was added to ISA 2.06 (Power7). Exclude this block from older cpus. Fixes: 27ae5109a2ba (softfloat: Specialize udiv_qrnnd for ppc64) Reported-by: Laurent Vivier Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.2 Tested-by: Laurent Vivier Reviewed-by: Laurent Vivier diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index c86687fa5e..b1d772e6d4 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -647,8 +647,8 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r = n >> 64; return n; -#elif defined(_ARCH_PPC64) - /* From Power ISA 3.0B, programming note for divdeu. */ +#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7) + /* From Power ISA 2.06, programming note for divdeu. */ uint64_t q1, q2, Q, r1, r2, R; asm("divdeu %0,%2,%4; divdu %1,%3,%4" : "=&r"(q1), "=r"(q2)