From patchwork Tue Sep 28 19:22:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring \(Arm\)" X-Patchwork-Id: 514808 Delivered-To: patch@linaro.org Received: by 2002:a02:c816:0:0:0:0:0 with SMTP id p22csp5464655jao; Tue, 28 Sep 2021 12:22:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZYdus/FDRu/1MQjuZQ+BID8G8/C3b52wVUlx1XVRIUx3FN7Pa8ycc5Ya+5KzDntnzkLTd X-Received: by 2002:a05:6402:21c5:: with SMTP id bi5mr9700440edb.367.1632856934761; Tue, 28 Sep 2021 12:22:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1632856934; cv=none; d=google.com; s=arc-20160816; b=wuOMLTNlFsoczdtD/rE1N9TAk0xaqSteXn5Bo1UStL439YoE8B3LLVkxUfy3uPfwZv UO9e6mbcs72F2+RKJEZSDSqbyMqimaU2hDRv/FM/nrqE2Ft1IwswNH5dLT18RRoRq/Mo oI7lhxb1bPojpc/gnGpVA/BaQR2eMVkrWQrdLkHgd2y8AENTlBabS4kVCUmyZBcPwrgg G6GKZjPE9ztMX2+k07oksESmc3daMb3kKt3ICnrUisMJWXnEei/JCr2hE9Q6TUUosbhb hVeWhXJMHVnFPBwrvuIQOWx2y/XAXF2itV+v7xK07lfqZwDaFSFHScCRhA7omopv/MYv rEUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=HA3GT61Bfe4GqvyvYQ3VJ5/vu2QZDpfW7PYB8qA2Bbk=; b=i9HyTtBczmdh6+mzH1lbeYIvs3uHIN+N8KxTA1GK0qalIUT37iBNXgc6rqe/9oz3OT PKf1p55AbzuLVtOny8VPB7ok2dNW+UK+0Nu/FrAgrHwxkdSyqEFm7A52BSkIfRLbVmoI vNaPNGJ6Ye9V8gwy5KrvyUJ+dM+4bume27lZPzwujiTqn/mMHHyMvXhkzLaL1BP9FZlu Dzmcyj0crk1+fSmOHOp4mRhQZtjTLgZWRNpHPApK6KdKVIk837+dRghwNVAE4+J/Wy08 BjovzRntiUsBFhrP5l2i4P/Cb8a32SHxplLVN0o0KNBQ7+QeTRsn8Lv22Of5hoUsiBzD 0d9w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r16si9514759edp.224.2021.09.28.12.22.13; Tue, 28 Sep 2021 12:22:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242530AbhI1TXw (ORCPT + 17 others); Tue, 28 Sep 2021 15:23:52 -0400 Received: from mail-ot1-f48.google.com ([209.85.210.48]:42652 "EHLO mail-ot1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242393AbhI1TXv (ORCPT ); Tue, 28 Sep 2021 15:23:51 -0400 Received: by mail-ot1-f48.google.com with SMTP id c26-20020a056830349a00b0054d96d25c1eso3806883otu.9; Tue, 28 Sep 2021 12:22:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HA3GT61Bfe4GqvyvYQ3VJ5/vu2QZDpfW7PYB8qA2Bbk=; b=LxYyACsYE1aXd5jqBuu0cmd+szKQNM4ua1ZEcXyaIKRcnx2iSBdwTai5SUwT05q+Mo hwDl896rVA8puIi2Gr+Bj9Lhq3WyZSl2E/YyDIoOXzjuWfiMEvWAAtBE6IMA0Af1sw2M tCE2E4Fgzb39xjAa3byD/Wg1WeA1eumO3uTtldg24YEjkQSgOtTHMWTlxZlwMN151EQL 1Y221eP+nwwifTKQyrKaibvc4J8uNpia0WKjOLiMrGNQJF+qoNBcaDa6aj8410n96Sya FzZTDsFDK6ESlLhZDSxJKk0Pn68N2cRugydFuH1bAwKbhHMby5HhjJI+icO9B8dHLnBY avmQ== X-Gm-Message-State: AOAM532FqxuAz0100wGO4qpof8wBhffRueut3SMaTGMvHRhTX2OF4Zvw CvYNt0FPjGh1DFv3eZRQuT4fdkyJDQ== X-Received: by 2002:a05:6830:2816:: with SMTP id w22mr6700430otu.351.1632856931534; Tue, 28 Sep 2021 12:22:11 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id h26sm3536155otn.67.2021.09.28.12.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Sep 2021 12:22:10 -0700 (PDT) From: Rob Herring To: Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: qcom: Fix 'interrupt-map' parent address cells Date: Tue, 28 Sep 2021 14:22:09 -0500 Message-Id: <20210928192210.1842377-1-robh@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The 'interrupt-map' in several QCom SoCs is malformed. The '#address-cells' size of the parent interrupt controller (the GIC) is not accounted for. Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 34039b5c8017..5a04a0427d08 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -954,10 +954,10 @@ pcie0: pci@1c00000 { interrupts = ; interrupt-names = "msi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6d7172e6f4c3..287c12666a3a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1990,10 +1990,10 @@ pcie0: pci@1c00000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -2095,10 +2095,10 @@ pcie1: pci@1c08000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>,