From patchwork Mon Oct 4 23:22:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515213 Delivered-To: patch@linaro.org Received: by 2002:adf:fbc8:0:0:0:0:0 with SMTP id d8csp4818254wrs; Mon, 4 Oct 2021 16:22:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyVmDs81FRoDr5YspGUgQliQLBzTCg3093RgrBiMmDmxBEMjz4JCj2ZGtA+w1/XlmrWyQSX X-Received: by 2002:a05:6a00:1693:b0:44c:64a3:d318 with SMTP id k19-20020a056a00169300b0044c64a3d318mr6648411pfc.81.1633389752992; Mon, 04 Oct 2021 16:22:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633389752; cv=none; d=google.com; s=arc-20160816; b=aNvrIO8lloV652BJl0YIqPWFe183tVq2Smw/bHQlrve4GWSZN3UMNJ9K7VS6U+kzTr N3Oi3lLBwLQhU0uGn23t70j5lQ6LNbdxAeaZqY1Yyu1kdEpTipMR5YIxAnvhAZwY9CuS iR/t8CqGQcSK5lE1BRd8f3WKL4hA16TGW83wMbXturq+ZMSOxF4zkFFsapD1j/CqpllY IL3RTVk2g2dPl5dn4holT5DzVGInc/9Q/1aMyizeWvNsZImx9aXQClnz6DQckIWKBQQs e5Ds7brJxc5K6nccL8y/T+ane5h7JxC6QpcKKp0f30G3yPoKvoEVNO+nd6RePpE8pxHE IIOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=B/3gcHOhfvp5xgv2qzZFowXoIFji/xpSd6P4+0tcW2M=; b=tJL+yeLsAk4bYjqDgNqGCtltIXd+WSwaSw7MawsKRPXKOlKPDEFV3zUjMEy9actXmg JiUT5hKSOo6AIKCExCTn/y0Ru5mfGyP0O0ezoUiAhAZ5/pCUALpV0bCKYLuABygZYjg4 vIUyiR3mS4fJ3a208+dRquwE2aUpLR8OPOPZQ3TR1TWNepXoAPDE+Uvv4bdgj/rGHFb/ hFR0ImTxwYcJ8C6CVkQTZNu/vgom0C3yLjX3s9p/BrPcm4rrunCKPfgS0BBpTrubKee+ d12g4DEfkWQO+S4+817qVPOliZEYVroI4/i2dXJINNXvMIkMsY6gShN8/hJ63aYyGIgm vi/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jszj49AV; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r15si26921829pjj.71.2021.10.04.16.22.32; Mon, 04 Oct 2021 16:22:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jszj49AV; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235796AbhJDXYU (ORCPT + 3 others); Mon, 4 Oct 2021 19:24:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235263AbhJDXYU (ORCPT ); Mon, 4 Oct 2021 19:24:20 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B382C061749 for ; Mon, 4 Oct 2021 16:22:30 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id g41so78151314lfv.1 for ; Mon, 04 Oct 2021 16:22:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B/3gcHOhfvp5xgv2qzZFowXoIFji/xpSd6P4+0tcW2M=; b=Jszj49AV0IRCR/6aj3lsthSylf5xGmLysq060qpQtofvFPU2sCZ7EdZg87qEBOrjge 2jLUsxyYJV9C5V0qvAFJJSbCjLlXBiUG6iT0ievKOOv6shNECfX3FBgdQTljaNPIF2A6 3sk9Q5wV8HNMLCkQzvRaY0mEyr5y8h/Gm1L7ij4NaQMxwE9IeE0FDbxUCMF4ddezgXpn eD8w7LGc+IRQRgbMC274s29F27fq9Rds901myS1THBWGdHTC38KjOtgMRirGcdwNTRLu 5W4uxzVhvFej93Z1ICRMPMRAmydi5IHaR/bGktWjgFy4bGlqqhBcZVWrgPwB3tQekDw+ Wp6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B/3gcHOhfvp5xgv2qzZFowXoIFji/xpSd6P4+0tcW2M=; b=C483ihhxUCbaB1MYcMia6LTSZODsSeiD4PdXJNm78vp34G6BvJ8WZRPZ0G2GEXJc/Q UprEUdwMxmn9EylVjFQ+o4oTYSwmSJ9Gs8JtBWW56CL0HbppThgWLBxq0L6uIuSW+ASL ytWbArZlKPsjKbGkHFfQVFKyC1SkG8mp4JIPpykFhE7NHsqewJHX9VEqNTyfS3jdlr+s n75p0FOC2QgGpIJdg8cwRSht+V/I0VOVXn5F6XmeLTPmP4uicTNGBInC5+IXiGP2xdHu 4f5NIY0RRXmJ7xgA514CexK1uOinVE7RY80SdZEXadBVzuuywGS/5OKtGpsQkBx/ocio rl3g== X-Gm-Message-State: AOAM530ouSncnLTR+JDGzT+sc0sPrPIs3eZq3nZoZAx0QrNcrP2qMokM yk1QLvHYOf3Ow5f6bcKAjsyj3Q== X-Received: by 2002:a2e:b6d3:: with SMTP id m19mr18391111ljo.161.1633389748410; Mon, 04 Oct 2021 16:22:28 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h23sm1786219lja.131.2021.10.04.16.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 16:22:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: pinctrl: qcom, pmic-mpp: Convert qcom pmic mpp bindings to YAML Date: Tue, 5 Oct 2021 02:22:20 +0300 Message-Id: <20211004232225.2260665-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> References: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert Qualcomm PMIC MPP bindings from .txt to .yaml format. Signed-off-by: Dmitry Baryshkov --- .../bindings/pinctrl/qcom,pmic-mpp.txt | 187 ------------------ .../bindings/pinctrl/qcom,pmic-mpp.yaml | 178 +++++++++++++++++ 2 files changed, 178 insertions(+), 187 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt deleted file mode 100644 index 5363d44cbb74..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ /dev/null @@ -1,187 +0,0 @@ -Qualcomm PMIC Multi-Purpose Pin (MPP) block - -This binding describes the MPP block(s) found in the 8xxx series -of PMIC's from Qualcomm. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,pm8018-mpp", - "qcom,pm8019-mpp", - "qcom,pm8038-mpp", - "qcom,pm8058-mpp", - "qcom,pm8821-mpp", - "qcom,pm8841-mpp", - "qcom,pm8916-mpp", - "qcom,pm8917-mpp", - "qcom,pm8921-mpp", - "qcom,pm8941-mpp", - "qcom,pm8950-mpp", - "qcom,pmi8950-mpp", - "qcom,pm8994-mpp", - "qcom,pma8084-mpp", - "qcom,pmi8994-mpp", - - And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" - if the device is on an spmi bus or an ssbi bus respectively. - -- reg: - Usage: required - Value type: - Definition: Register base of the MPP block and length. - -- interrupts: - Usage: required - Value type: - Definition: Must contain an array of encoded interrupt specifiers for - each available MPP - -- gpio-controller: - Usage: required - Value type: - Definition: Mark the device node as a GPIO controller - -- #gpio-cells: - Usage: required - Value type: - Definition: Must be 2; - the first cell will be used to define MPP number and the - second denotes the flags for this MPP - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin or a list of pins. This configuration can include the -mux function to select on those pin(s), and various pin configuration -parameters, as listed below. - -SUBNODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of MPP pins affected by the properties specified in - this subnode. Valid pins are: - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 - mpp1-mpp4 for pma8084 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Valid values are: - "digital", - "analog", - "sink" - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - Valid values are 600, 10000 and 30000 in bidirectional mode - only, i.e. when operating in qcom,analog-mode and input and - outputs are enabled. The hardware ignores the configuration - when operating in other modes. - -- bias-high-impedance: - Usage: optional - Value type: - Definition: The specified pins will put in high-Z mode and disabled. - -- input-enable: - Usage: optional - Value type: - Definition: The specified pins are put in input mode, i.e. their input - buffer is enabled - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- power-source: - Usage: optional - Value type: - Definition: Selects the power source for the specified pins. Valid power - sources are defined in - -- qcom,analog-level: - Usage: optional - Value type: - Definition: Selects the source for analog output. Valued values are - defined in - PMIC_MPP_AOUT_LVL_* - -- qcom,dtest: - Usage: optional - Value type: - Definition: Selects which dtest rail to be routed in the various functions. - Valid values are 1-4 - -- qcom,amux-route: - Usage: optional - Value type: - Definition: Selects the source for analog input. Valid values are - defined in - PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... -- qcom,paired: - Usage: optional - Value type: - Definition: Indicates that the pin should be operating in paired mode. - -Example: - - mpps@a000 { - compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; - - pinctrl-names = "default"; - pinctrl-0 = <&pm8841_default>; - - pm8841_default: default { - gpio { - pins = "mpp1", "mpp2", "mpp3", "mpp4"; - function = "digital"; - input-enable; - power-source = ; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml new file mode 100644 index 000000000000..96cb78ab6437 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC Multi-Purpose Pin (MPP) block + +maintainers: + - Bjorn Andersson + +description: + This binding describes the MPP block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + items: + - enum: + - qcom,pm8018-mpp + - qcom,pm8019-mpp + - qcom,pm8038-mpp + - qcom,pm8058-mpp + - qcom,pm8821-mpp + - qcom,pm8841-mpp + - qcom,pm8916-mpp + - qcom,pm8917-mpp + - qcom,pm8921-mpp + - qcom,pm8941-mpp + - qcom,pm8950-mpp + - qcom,pmi8950-mpp + - qcom,pm8994-mpp + - qcom,pma8084-mpp + - qcom,pmi8994-mpp + + - enum: + - qcom,spmi-mpp + - qcom,ssbi-mpp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 12 + description: + Must contain an array of encoded interrupt specifiers for + each available MPP + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-pmic-mpp-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-pmic-mpp-state" + +$defs: + qcom-pmic-mpp-state: + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - mpp1-mpp4 for pm8841 + - mpp1-mpp4 for pm8916 + - mpp1-mpp8 for pm8941 + - mpp1-mpp4 for pm8950 + - mpp1-mpp4 for pmi8950 + - mpp1-mpp4 for pma8084 + + items: + pattern: "^mpp([0-9]+)$" + + function: + items: + - enum: + - digital + - analog + - sink + + bias-disable: true + bias-pull-up: true + bias-high-impedance: true + input-enable: true + output-high: true + output-low: true + power-source: true + + qcom,analog-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog output. Valued values are defined in + PMIC_MPP_AOUT_LVL_* + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + qcom,amux-route: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog input. Valid values are defined in + PMIC_MPP_AMUX_ROUTE_CH5, + PMIC_MPP_AMUX_ROUTE_CH6... + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,paired: + - description: + Indicates that the pin should be operating in paired mode. + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + + pm8841_mpp: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000 0>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpp 0 0 4>; + interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8841_default>; + + default-state { + gpio { + pins = "mpp1", "mpp2", "mpp3", "mpp4"; + function = "digital"; + input-enable; + power-source = ; + }; + }; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id r15si26921829pjj.71.2021.10.04.16.22.36; Mon, 04 Oct 2021 16:22:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bZNltq/o"; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232582AbhJDXYX (ORCPT + 3 others); Mon, 4 Oct 2021 19:24:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236127AbhJDXYV (ORCPT ); Mon, 4 Oct 2021 19:24:21 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A92AC061745 for ; Mon, 4 Oct 2021 16:22:31 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id j5so73286734lfg.8 for ; Mon, 04 Oct 2021 16:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B1tfgMXD/HCZM2/dbxQ/czHnewIDG6QY34tUjSKvwfk=; b=bZNltq/oZbd2YVOmD/JOyx7+mRWiGRGSHOcZqLxUZ/OJ/a4X0CocMwnce8EI+bA0mr cYHYy3AcbjPmfqwtUgaug7V/ju9Jlk/9B8HiCZ0OGbeszUFlcZhCIoXa3mqrcVScykYK YaAx/nFHhpH8BtNYwHnxEWO+caFmC17qYD3j6jYWpUHPg3/s70fxTFRt6kjbZkhE7sMP iIcWH8IvN64mKUHMHBvLr0lKrpbKfTRuvXcH01R4SxlwYf8QTb3ZvO+pOdIKnJqC8k3U 0n2j4H5iI8LeXUw5XmMco55GxsF8PIYfV0KVCAq7lHwU7HP9yzS9eAV0MQeZlO+TLGtC lfPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B1tfgMXD/HCZM2/dbxQ/czHnewIDG6QY34tUjSKvwfk=; b=5sYEoTgiS23V7m7ZEglAeMoxQxIlqhOeuNaIqngIypefmEVaAPtun41/j1EHKj2/3Z BaxbgYshJBMi2R9ek8RDQIMTj+QtEXRxKt4/e3tZxnGO1h/d5MLBSk0GspIcFEmZjSS+ 11JJezJC/t9O53uxLZA/0vgxZR6kToDd4zzmF8DrIYb1AOIsOf1Upr9a2d9XEWneLVoG 3nkxdMpGzcYkyl1dF5MihBlCuJ9UQFe04nfpxiRWbjqws4kRVJlK7uz8g1s0BCgoDyYs oY5cDdu9UNlS3Jij6+Emiv6nAp909S2Brzx6cMJiMdRgsFCi3PfuOrZGUQHqOD9AvIrA QWkA== X-Gm-Message-State: AOAM531jAO9i1E8uMTsyOJGSg9JZYwZz5DG1l6oatvauFQXsR5RA7Pbn zcHU7ME2YnwX5bhqVuFya02k6g== X-Received: by 2002:ac2:4896:: with SMTP id x22mr17609034lfc.257.1633389749636; Mon, 04 Oct 2021 16:22:29 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h23sm1786219lja.131.2021.10.04.16.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 16:22:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 3/6] pinctrl: qcom: ssbi-mpp: hardcode IRQ counts Date: Tue, 5 Oct 2021 02:22:22 +0300 Message-Id: <20211004232225.2260665-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> References: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The probing of this driver calls platform_irq_count, which will setup all of the IRQs that are configured in device tree. In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,ssbi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 92e7f2602847..a90cada1d657 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -733,13 +733,12 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, } static const struct of_device_id pm8xxx_mpp_of_match[] = { - { .compatible = "qcom,pm8018-mpp" }, - { .compatible = "qcom,pm8038-mpp" }, - { .compatible = "qcom,pm8058-mpp" }, - { .compatible = "qcom,pm8917-mpp" }, - { .compatible = "qcom,pm8821-mpp" }, - { .compatible = "qcom,pm8921-mpp" }, - { .compatible = "qcom,ssbi-mpp" }, + { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8058-mpp", .data = (void *) 12 }, + { .compatible = "qcom,pm8821-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8917-mpp", .data = (void *) 10 }, + { .compatible = "qcom,pm8921-mpp", .data = (void *) 12 }, { }, }; MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); @@ -750,19 +749,14 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) struct pinctrl_pin_desc *pins; struct pm8xxx_mpp *pctrl; int ret; - int i, npins; + int i; pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; pctrl->dev = &pdev->dev; - npins = platform_irq_count(pdev); - if (!npins) - return -EINVAL; - if (npins < 0) - return npins; - pctrl->npins = npins; + pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev); pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL); if (!pctrl->regmap) { From patchwork Mon Oct 4 23:22:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515216 Delivered-To: patch@linaro.org Received: by 2002:adf:fbc8:0:0:0:0:0 with SMTP id d8csp4818301wrs; Mon, 4 Oct 2021 16:22:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxicxnzBtV9ANqF5KBkQrwfIb42IqVWv36gaQZZVWD14CGP7LgbTsGtxZs7sbYlUUQcU+ol X-Received: by 2002:aa7:9517:0:b0:44c:7b4a:8073 with SMTP id b23-20020aa79517000000b0044c7b4a8073mr1167484pfp.24.1633389756709; Mon, 04 Oct 2021 16:22:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633389756; cv=none; d=google.com; s=arc-20160816; b=MknUKuqRxtsU9SjClUfOXdI0jCw6m1OO+liaRSZZdAdtQBGe+jxcrZujLeyjycpMrM YMXEP24fg48Ux6OcX0c8o0xcIuxGWM3DMx2qStj6LTnJUqqWBwwgKVEPmX+LsO6WSFYo +69ccFU7PzQrN+jcp+w4EKt42K7JlODaxwHumrT6gwB+isEe0b8jQ82N3hc0cupo11lD AmT3aFfj2H0h0cHvA29P2+IeofOTMCm2OCFDS7DgegsGUDp6EZ5mEVO22w8gYqX9kQL2 8DgwMvUSwnvyCI6Uaiew2n3rj+BvoPGsHgDIQcSIos+YCR/LqWrMN7JMQOQm6VVrbg9t nqSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a82goinfuhMQndAZ1eqxYJiqwbzakFYRTc0Nku7E5EU=; b=KDnEFT/jGINXvjxnd45zIYe4pygJZ0nHTdIQDFuKTtlH/3RwcRxzpFyFJwNNdAa3n4 +npzRORKjpBeqrEp6sT4Ab6ZC1gzU1x2CWPR3kwnKMndRd92h9DWs909K8tex51SptgV KgpfBJOKU8rfqeDIHfVyRH62vVpMl6XU1qsnaG2tUEKXLF5jixV4wczIyli+qkVLFRlb gXSjzEUmCmtHXQvTAnRtG6Skdtz3jYw9SG3vwfPhjBA4eHky5m/bOQLD+Ee3hZxtK1a2 OhROXmAQA5VzSTvpSohaxKv9bo0IRDrGVGY3Wlyb8JxEJmUdGZejzq4YDZLoz9HL4+Ec /sJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ocQD0z+p; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 111 ++++++++++++++++++++---- 1 file changed, 93 insertions(+), 18 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index a90cada1d657..842940594c4a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -87,7 +87,6 @@ /** * struct pm8xxx_pin_data - dynamic configuration for a pin * @reg: address of the control register - * @irq: IRQ from the PMIC interrupt controller * @mode: operating mode for the pin (digital, analog or current sink) * @input: pin is input * @output: pin is output @@ -103,7 +102,6 @@ */ struct pm8xxx_pin_data { unsigned reg; - int irq; u8 mode; @@ -126,6 +124,7 @@ struct pm8xxx_mpp { struct regmap *regmap; struct pinctrl_dev *pctrl; struct gpio_chip chip; + struct irq_chip irq; struct pinctrl_desc desc; unsigned npins; @@ -148,6 +147,8 @@ static const struct pin_config_item pm8xxx_conf_items[] = { #endif #define PM8XXX_MAX_MPPS 12 +#define PM8XXX_MPP_PHYSICAL_OFFSET 1 + static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = { "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", @@ -492,12 +493,16 @@ static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; bool state; - int ret; + int ret, irq; if (!pin->input) return !!pin->output_value; - ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + irq = chip->to_irq(chip, offset); + if (irq < 0) + return irq; + + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, &state); if (!ret) ret = !!state; @@ -524,18 +529,10 @@ static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, if (flags) *flags = gpio_desc->args[1]; - return gpio_desc->args[0] - 1; + return gpio_desc->args[0] - PM8XXX_MPP_PHYSICAL_OFFSET; } -static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); - struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; - - return pin->irq; -} - #ifdef CONFIG_DEBUG_FS #include @@ -558,7 +555,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, "abus3", }; - seq_printf(s, " mpp%-2d:", offset + 1); + seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET); switch (pin->mode) { case PM8XXX_MPP_DIGITAL: @@ -640,7 +637,6 @@ static const struct gpio_chip pm8xxx_mpp_template = { .get = pm8xxx_mpp_get, .set = pm8xxx_mpp_set, .of_xlate = pm8xxx_mpp_of_xlate, - .to_irq = pm8xxx_mpp_to_irq, .dbg_show = pm8xxx_mpp_dbg_show, .owner = THIS_MODULE, }; @@ -732,6 +728,55 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, return 0; } +static int pm8xxx_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pm8xxx_mpp *pctrl = container_of(domain->host_data, + struct pm8xxx_mpp, chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < PM8XXX_MPP_PHYSICAL_OFFSET || + fwspec->param[0] > pctrl->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PM8XXX_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pm8xxx_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PM8XXX_MPP_PHYSICAL_OFFSET; +} + +static int pm8821_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 24; + *parent_type = child_type; + + return 0; +} + +static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0x80; + *parent_type = child_type; + + return 0; +} + static const struct of_device_id pm8xxx_mpp_of_match[] = { { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, @@ -746,7 +791,10 @@ MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); static int pm8xxx_mpp_probe(struct platform_device *pdev) { struct pm8xxx_pin_data *pin_data; + struct irq_domain *parent_domain; + struct device_node *parent_node; struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; struct pm8xxx_mpp *pctrl; int ret; int i; @@ -783,9 +831,6 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) for (i = 0; i < pctrl->desc.npins; i++) { pin_data[i].reg = SSBI_REG_ADDR_MPP(i); - pin_data[i].irq = platform_get_irq(pdev, i); - if (pin_data[i].irq < 0) - return pin_data[i].irq; ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); if (ret) @@ -816,6 +861,36 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.ngpio = pctrl->npins; + + parent_node = of_irq_find_parent(pctrl->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + pctrl->irq.name = "ssbi-mpp"; + pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; + pctrl->irq.irq_unmask = irq_chip_unmask_parent; + pctrl->irq.irq_set_type = irq_chip_set_type_parent; + pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; + + girq = &pctrl->chip.irq; + girq->chip = &pctrl->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->parent_domain = parent_domain; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp")) + girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq; + else + girq->child_to_parent_hwirq = pm8xxx_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; + girq->child_offset_to_irq = pm8xxx_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_mpp_domain_translate; + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(&pdev->dev, "failed register gpiochip\n"); From patchwork Mon Oct 4 23:22:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515217 Delivered-To: patch@linaro.org Received: by 2002:adf:fbc8:0:0:0:0:0 with SMTP id d8csp4818321wrs; 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In preparation for converting this driver to be a hierarchical IRQ chip, hardcode the IRQ count based on the hardware type so that all the IRQs are not configured immediately and are configured on an as-needed basis later in the boot process. This change will also allow for the removal of the interrupts property later in this patch series once the hierarchical IRQ chip support is in. This patch also removes the generic qcom,spmi-mpp OF match since we don't know the number of pins. All of the existing upstream bindings already include the more-specific binding. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 2da9b5f68f3f..a9f994863126 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -812,11 +812,7 @@ static int pmic_mpp_probe(struct platform_device *pdev) return ret; } - npins = platform_irq_count(pdev); - if (!npins) - return -EINVAL; - if (npins < 0) - return npins; + npins = (uintptr_t) device_get_match_data(&pdev->dev); BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); @@ -912,16 +908,15 @@ static int pmic_mpp_remove(struct platform_device *pdev) } static const struct of_device_id pmic_mpp_of_match[] = { - { .compatible = "qcom,pm8019-mpp" }, /* 6 MPP's */ - { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pm8950-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pmi8950-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ - { .compatible = "qcom,pmi8994-mpp" }, /* 4 MPP's */ - { .compatible = "qcom,spmi-mpp" }, /* Generic */ + { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pm8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pmi8950-mpp", .data = (void *) 4 }, + { .compatible = "qcom,pm8994-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pma8084-mpp", .data = (void *) 8 }, + { .compatible = "qcom,pmi8994-mpp", .data = (void *) 4 }, { }, }; From patchwork Mon Oct 4 23:22:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515218 Delivered-To: patch@linaro.org Received: by 2002:adf:fbc8:0:0:0:0:0 with SMTP id d8csp4818322wrs; Mon, 4 Oct 2021 16:22:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz5Ko/Yz7SV0i+mXakDncSUXyB0MVCirAGjhHeb4QT342jz0yoExgrpo68gUkj1/Cx34c/k X-Received: by 2002:a63:e11:: with SMTP id d17mr12976773pgl.297.1633389758914; Mon, 04 Oct 2021 16:22:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633389758; cv=none; d=google.com; s=arc-20160816; b=AP3MZbqdvjKrI2rUEXxGbD4ZKtBJ23BTpviUtp/waqEDmI8QC/vgmaQTmZbjbWJYeV /c4nEZfCDet+s9whzS3QqXR//DtAQP2yzPOH0Rg8E94cdsTx0l77qcdD6EnHPztQI67h kTNomqwIQSMYUhmx1tBXn/MO46XO4nfYcqVOPI/OsfEENfDhQva7Z2YCAbUCwSl6npqg VNhRqs8ko315NwUxtrXqvI46hIezRUgUkyaJynn/hRurmLuv8s8dkvsu8WTYKPGd6rTs Z05NPm1JiPt9siGOvjgEQgjLuOEGhzyhSIsvHFDruo1Pyxh3O41WbiHmrh+NxRH0lQUH x2Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=1KGjdRZpvRUbZN4znNYdKQQOrqdPeliSzAyZbKyKbjIO8OzNUpxAAjNCLWgf1UiDdY 416aHUBngibNFP0ywUvFArNpTkLs7P4B0ODuZcAN4kNupF+UjkY2gXR2SHrUlg+70jTt Jok97/7a4x5rJYr5JK4SdNArtKBK4qi/Ma+7E938TYzPZRP3mJV3HGsxXepfejbniE3C geKXoitG/y7SYhajMOs3riCq/YTJ40avKfOmuXQz95KguGAmc9a2mUpMpV+pFW25Zv3s 05AJfJiVhkG0DIMeEiBawOYNiZ4y5P6r3v7sbc02/et58eMEeIHG2kp/RRRnuyJx5hXu dT/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tmLsAFRW; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r15si26921829pjj.71.2021.10.04.16.22.38; Mon, 04 Oct 2021 16:22:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tmLsAFRW; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237117AbhJDXY0 (ORCPT + 3 others); Mon, 4 Oct 2021 19:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236984AbhJDXYY (ORCPT ); Mon, 4 Oct 2021 19:24:24 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17585C0613EC for ; Mon, 4 Oct 2021 16:22:33 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id m3so77353870lfu.2 for ; Mon, 04 Oct 2021 16:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=tmLsAFRWAIEPtpzVlS/gOOReWWq4xy49ClvN3lPA8l5FWZ93q03KKbpX8N/IlDlo0V swUqkVEKR8wjb4PZ1eA64EWzlweGdHVzDLZ4bxEyLtBCgIz+gNDjcQfGYR523X58bRgY MNUT8hRkBROCkfAozPODs3YPvJE3/hRXDiAQTAvcb3SpUCJF6pfhOXRhuzrrt3751R8d +ejVY4sfCAjE2LvBx8GJKl/IUEcMqblSpn/VyXR6NwgJ08lh3zIuhQacoo0InrM4qKXv eeRs7sKGX4P88medj/dMXcc//jNDnj2c5MUxricWV2jBjgTZVRBqVXwt+yhCNJCRLS8i +Q+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E2YJV+cRv0tFDhiSivfR6SvH37WdzUlDmvLwCor6dDY=; b=6OaDokhXUW9yqQs1mEYnvMA9ll8RM9dZs4Q06TjQ+mHszHY6HvCqcLJf8Heg1QASJX 3aWOpXWKabag4tpPQcwzsmFoGd3MAP42mTFPjSVYAPA5NMIocxWO28Arp4VC43ZDumuL 4sAE50WE7EQ74y8kvKZo1hufrsXCVJilRcw6bg5KEY6Df4UTUrQQ/NRvQM8TPopAW5Qa pen6A2JfXIIauk445F2LMLYSPPb/s/TkvIiWEHu6Ce9w+jQDe6pygOtQPNeCTuHSuOnW KZzqKT0r6+GTPVJuGwrJeMyAq/MKWRRX7pg6SMgoeOT5718OKEstYiG0eM+LUS7zxkWo rlaw== X-Gm-Message-State: AOAM531QgYi6x2MYhYsDNUQ2//D2dkmYgpIdBOdhl4vr28TzeJFkm/ig /++tdXPE/Nl2z1sznvc8Fkfpxg== X-Received: by 2002:a05:6512:3990:: with SMTP id j16mr17227941lfu.292.1633389751657; Mon, 04 Oct 2021 16:22:31 -0700 (PDT) Received: from umbar.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id h23sm1786219lja.131.2021.10.04.16.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Oct 2021 16:22:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 6/6] pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip Date: Tue, 5 Oct 2021 02:22:25 +0300 Message-Id: <20211004232225.2260665-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> References: <20211004232225.2260665-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org spmi-mpp did not have any irqchip support so consumers of this in device tree would need to call gpio[d]_to_irq() in order to get the proper IRQ on the underlying PMIC. IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the spmi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 86 ++++++++++++++++++++----- 1 file changed, 69 insertions(+), 17 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index a9f994863126..b80723928b7e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -103,7 +103,6 @@ /** * struct pmic_mpp_pad - keep current MPP settings * @base: Address base in SPMI device. - * @irq: IRQ number which this MPP generate. * @is_enabled: Set to false when MPP should be put in high Z state. * @out_value: Cached pin output value. * @output_enabled: Set to true if MPP output logic is enabled. @@ -121,7 +120,6 @@ */ struct pmic_mpp_pad { u16 base; - int irq; bool is_enabled; bool out_value; bool output_enabled; @@ -143,6 +141,7 @@ struct pmic_mpp_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; + struct irq_chip irq; }; static const struct pinconf_generic_params pmic_mpp_bindings[] = { @@ -622,16 +621,6 @@ static int pmic_mpp_of_xlate(struct gpio_chip *chip, return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; } -static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct pmic_mpp_state *state = gpiochip_get_data(chip); - struct pmic_mpp_pad *pad; - - pad = state->ctrl->desc->pins[pin].drv_data; - - return pad->irq; -} - static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct pmic_mpp_state *state = gpiochip_get_data(chip); @@ -651,7 +640,6 @@ static const struct gpio_chip pmic_mpp_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_mpp_of_xlate, - .to_irq = pmic_mpp_to_irq, .dbg_show = pmic_mpp_dbg_show, }; @@ -796,13 +784,53 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state, return 0; } +static int pmic_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pmic_mpp_state *state = container_of(domain->host_data, + struct pmic_mpp_state, + chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PMIC_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pmic_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PMIC_MPP_PHYSICAL_OFFSET; +} + +static int pmic_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; + + return 0; +} + static int pmic_mpp_probe(struct platform_device *pdev) { + struct irq_domain *parent_domain; + struct device_node *parent_node; struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pindesc; struct pinctrl_desc *pctrldesc; struct pmic_mpp_pad *pad, *pads; struct pmic_mpp_state *state; + struct gpio_irq_chip *girq; int ret, npins, i; u32 reg; @@ -857,10 +885,6 @@ static int pmic_mpp_probe(struct platform_device *pdev) pindesc->number = i; pindesc->name = pmic_mpp_groups[i]; - pad->irq = platform_get_irq(pdev, i); - if (pad->irq < 0) - return pad->irq; - pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; ret = pmic_mpp_populate(state, pad); @@ -880,6 +904,34 @@ static int pmic_mpp_probe(struct platform_device *pdev) if (IS_ERR(state->ctrl)) return PTR_ERR(state->ctrl); + parent_node = of_irq_find_parent(state->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + state->irq.name = "spmi-mpp", + state->irq.irq_ack = irq_chip_ack_parent, + state->irq.irq_mask = irq_chip_mask_parent, + state->irq.irq_unmask = irq_chip_unmask_parent, + state->irq.irq_set_type = irq_chip_set_type_parent, + state->irq.irq_set_wake = irq_chip_set_wake_parent, + state->irq.flags = IRQCHIP_MASK_ON_SUSPEND, + + girq = &state->chip.irq; + girq->chip = &state->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_mpp_domain_translate; + ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n");