From patchwork Tue Oct 5 14:43:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515251 Delivered-To: patch@linaro.org Received: by 2002:ac0:890a:0:0:0:0:0 with SMTP id 10csp1986678imy; Tue, 5 Oct 2021 07:43:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMWNNlQCQZ1tUIw0PbAbuJGmbT0c05KzO2UJ4R5l/zdp1S+2SAWtZZHGqqxqTIfh+z2IFi X-Received: by 2002:a17:906:eb86:: with SMTP id mh6mr7394963ejb.141.1633445028088; Tue, 05 Oct 2021 07:43:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633445028; cv=none; d=google.com; s=arc-20160816; b=bqS6vdRqV4OBXSnAyjcAKGeksbTqAhIvyoVyKL967dKh/YJzB4vI8z20/zsIIaTizJ LVKMRAQxnEVkobmjRiW23fWxfNtiaYPWHMYpvMK7oYIMD7QhB9PSpiDFT+nN8Z69uYNw Pkb4/CDNCfCMFWIH91ItvJds+jQofdOUavJiWSLsxjmYgerkXbMthCzBMIMiUeec7LCC bCFSPpAxR5K1SdWnuyvPsfsc/b2zuQqdaYfxoJAJi8hpU9PsZJ7WYJzzjIGanh7wkyIF uGCk8f7hZqWVWLXFtbPOqMFnghtb3xiYjgVC8bayveLCGLO1MnUBkxiwzSMiTZvd+AEr LGPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eb7cvTiXllNW2wJwYsGoR2tpvILpnhXsuAIehYc3HJU=; b=YQWwulVKK1cwZtYHfU/h2cL56DFurKP2Oq9vAvik/YGA3mlkMUbbPQi7/JKjXct7zk b2I69BreAJZlZnUdE7JnzAIf5Auhvnd66LRBxDeaIKp5r2mxAuUJO760vzqsL8X1B8w1 uPxFPHsxKmQuDDaAPyaXeCjAH10E80nwu34gLbApzaCKYh7rvqntNCvkoLjp7DsBwped hfp7XOrNJNSwDERFn9qATtW1vBqgz8BmKq9Mbrtv6ORQQuN5D+rUhd2e4dkXAxtHHOH5 9Yo7qaTQAt5K8KpKnVX/ITuuQJM6mJFsbmW/1rtOc8/02hx7quE3H0Np4X648Iki9sm0 dRWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ViN3AXWf; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Use #interrupt-cells instead as we are switching qcom,spmi-mpp and qcom,ssbi-mpp to hierarchical IRQ setup. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 6066857b5964..8a01a9b22e07 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -40,12 +40,10 @@ properties: reg: maxItems: 1 - interrupts: - minItems: 1 - maxItems: 12 - description: - Must contain an array of encoded interrupt specifiers for - each available MPP + interrupt-controller: true + + '#interrupt-cells': + const: 2 gpio-controller: true gpio-line-names: true @@ -67,6 +65,7 @@ required: - gpio-controller - '#gpio-cells' - gpio-ranges + - interrupt-controller patternProperties: '-state$': @@ -163,7 +162,8 @@ examples: gpio-ranges = <&pm8841_mpp 0 0 4>; gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", "BT_LED_CTRL", "GPIO-F"; - interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; + interrupt-controller; + #interrupt-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pm8841_default>; From patchwork Tue Oct 5 14:43:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 515254 Delivered-To: patch@linaro.org Received: by 2002:ac0:890a:0:0:0:0:0 with SMTP id 10csp1986707imy; Tue, 5 Oct 2021 07:43:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJySuaqIsBEQIKOJDqHGcafjaaaGhhfmvRtKcWUORlhXfmOf6geeIQb7tbTPlc8uUO12UgTp X-Received: by 2002:a17:906:9241:: with SMTP id c1mr26445591ejx.125.1633445029984; Tue, 05 Oct 2021 07:43:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633445029; cv=none; d=google.com; s=arc-20160816; b=fii+9V8FrFHiiNQxD18/7UmxDjphttdQ890VsLbMqTY5Tac1r3ov/F2fQFR7XKL+m1 OItsnd3nBpEwM0gmHWZutTa71FpvW/va/9oyK3BrBvuqllhpXrYWVtwlzwe2D+aVPpL5 fc6O9sRyVGhkPDZt06fBAoeBZI0ULO0+7E2kbPjzBgxCGe/YGxS06tgfFmnBuDaGoHgs d5wN1BemkacYaa2esLz+h4wVFoj/yPPuSSML54oN6RYC8GJ4KS/lJJaB3prU78rOHyLf 78dbhCd4ZfCLkPvj/qDZy8bNuq2omFD4lpZP6KSqhWFUTI7k1oB/ObL4NkOSxsY3peCL fe1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a82goinfuhMQndAZ1eqxYJiqwbzakFYRTc0Nku7E5EU=; b=QV2cdv602LSygv5SulxQ42DGcWm5BEnXwj8VEkyiHDsJWGklehLX2bRa2J5FsHVkg2 3buHSUYeCGzK5bbSXpD9K1OPPXzrmUYfsGPMbAL543DSc4os6Gm9NntCcbnSyY0/AHuH RUhGQpGJD5WT1z3+LG2KN0GJ25S5YOo2fW+8xm3juQ6enrTN0cNYQqe6r4x1GPRMCFXh C1XfClhQlvnclpjsOcuCIgh6GrYPwC8vpW9C2LIKqf7ArGQpvFOldWJTk48t66tTvfL6 B1TNWoMPytYCcnTiYOItY0DQ4x/u/bJy6Q6IxnuLS7QezeLzAzcTnhcNPMk4erSGHSIW 1eYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MklQJzuw; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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IRQ chips in device tree should be usable from the start without the consumer having to make an additional call to get the proper IRQ on the parent. This patch adds hierarchical IRQ chip support to the ssbi-mpp code to correct this issue. Signed-off-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 111 ++++++++++++++++++++---- 1 file changed, 93 insertions(+), 18 deletions(-) -- 2.30.2 diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index a90cada1d657..842940594c4a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -87,7 +87,6 @@ /** * struct pm8xxx_pin_data - dynamic configuration for a pin * @reg: address of the control register - * @irq: IRQ from the PMIC interrupt controller * @mode: operating mode for the pin (digital, analog or current sink) * @input: pin is input * @output: pin is output @@ -103,7 +102,6 @@ */ struct pm8xxx_pin_data { unsigned reg; - int irq; u8 mode; @@ -126,6 +124,7 @@ struct pm8xxx_mpp { struct regmap *regmap; struct pinctrl_dev *pctrl; struct gpio_chip chip; + struct irq_chip irq; struct pinctrl_desc desc; unsigned npins; @@ -148,6 +147,8 @@ static const struct pin_config_item pm8xxx_conf_items[] = { #endif #define PM8XXX_MAX_MPPS 12 +#define PM8XXX_MPP_PHYSICAL_OFFSET 1 + static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = { "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", @@ -492,12 +493,16 @@ static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset) struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; bool state; - int ret; + int ret, irq; if (!pin->input) return !!pin->output_value; - ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state); + irq = chip->to_irq(chip, offset); + if (irq < 0) + return irq; + + ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL, &state); if (!ret) ret = !!state; @@ -524,18 +529,10 @@ static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, if (flags) *flags = gpio_desc->args[1]; - return gpio_desc->args[0] - 1; + return gpio_desc->args[0] - PM8XXX_MPP_PHYSICAL_OFFSET; } -static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip); - struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data; - - return pin->irq; -} - #ifdef CONFIG_DEBUG_FS #include @@ -558,7 +555,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, "abus3", }; - seq_printf(s, " mpp%-2d:", offset + 1); + seq_printf(s, " mpp%-2d:", offset + PM8XXX_MPP_PHYSICAL_OFFSET); switch (pin->mode) { case PM8XXX_MPP_DIGITAL: @@ -640,7 +637,6 @@ static const struct gpio_chip pm8xxx_mpp_template = { .get = pm8xxx_mpp_get, .set = pm8xxx_mpp_set, .of_xlate = pm8xxx_mpp_of_xlate, - .to_irq = pm8xxx_mpp_to_irq, .dbg_show = pm8xxx_mpp_dbg_show, .owner = THIS_MODULE, }; @@ -732,6 +728,55 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl, return 0; } +static int pm8xxx_mpp_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct pm8xxx_mpp *pctrl = container_of(domain->host_data, + struct pm8xxx_mpp, chip); + + if (fwspec->param_count != 2 || + fwspec->param[0] < PM8XXX_MPP_PHYSICAL_OFFSET || + fwspec->param[0] > pctrl->chip.ngpio) + return -EINVAL; + + *hwirq = fwspec->param[0] - PM8XXX_MPP_PHYSICAL_OFFSET; + *type = fwspec->param[1]; + + return 0; +} + +static unsigned int pm8xxx_mpp_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) +{ + return offset + PM8XXX_MPP_PHYSICAL_OFFSET; +} + +static int pm8821_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 24; + *parent_type = child_type; + + return 0; +} + +static int pm8xxx_mpp_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0x80; + *parent_type = child_type; + + return 0; +} + static const struct of_device_id pm8xxx_mpp_of_match[] = { { .compatible = "qcom,pm8018-mpp", .data = (void *) 6 }, { .compatible = "qcom,pm8038-mpp", .data = (void *) 6 }, @@ -746,7 +791,10 @@ MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match); static int pm8xxx_mpp_probe(struct platform_device *pdev) { struct pm8xxx_pin_data *pin_data; + struct irq_domain *parent_domain; + struct device_node *parent_node; struct pinctrl_pin_desc *pins; + struct gpio_irq_chip *girq; struct pm8xxx_mpp *pctrl; int ret; int i; @@ -783,9 +831,6 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) for (i = 0; i < pctrl->desc.npins; i++) { pin_data[i].reg = SSBI_REG_ADDR_MPP(i); - pin_data[i].irq = platform_get_irq(pdev, i); - if (pin_data[i].irq < 0) - return pin_data[i].irq; ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); if (ret) @@ -816,6 +861,36 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) pctrl->chip.of_gpio_n_cells = 2; pctrl->chip.label = dev_name(pctrl->dev); pctrl->chip.ngpio = pctrl->npins; + + parent_node = of_irq_find_parent(pctrl->dev->of_node); + if (!parent_node) + return -ENXIO; + + parent_domain = irq_find_host(parent_node); + of_node_put(parent_node); + if (!parent_domain) + return -ENXIO; + + pctrl->irq.name = "ssbi-mpp"; + pctrl->irq.irq_mask_ack = irq_chip_mask_ack_parent; + pctrl->irq.irq_unmask = irq_chip_unmask_parent; + pctrl->irq.irq_set_type = irq_chip_set_type_parent; + pctrl->irq.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE; + + girq = &pctrl->chip.irq; + girq->chip = &pctrl->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node); + girq->parent_domain = parent_domain; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,pm8821-mpp")) + girq->child_to_parent_hwirq = pm8821_mpp_child_to_parent_hwirq; + else + girq->child_to_parent_hwirq = pm8xxx_mpp_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; + girq->child_offset_to_irq = pm8xxx_mpp_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pm8xxx_mpp_domain_translate; + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(&pdev->dev, "failed register gpiochip\n");