From patchwork Tue Dec 14 18:26:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 523761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B3BCC433F5 for ; Tue, 14 Dec 2021 18:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236964AbhLNS1C (ORCPT ); Tue, 14 Dec 2021 13:27:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231875AbhLNS1B (ORCPT ); Tue, 14 Dec 2021 13:27:01 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93D7AC061574; Tue, 14 Dec 2021 10:27:01 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 386E1616A1; Tue, 14 Dec 2021 18:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 912AFC34604; Tue, 14 Dec 2021 18:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506420; bh=JUqDleAAmmdXoCD3MpSn26A3e+dzkil8Xshl3lWRacM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DZs2p2u+doCFSWlU6AUx7+7jXEqhFiHKqNGF9eKt66KATiNhGu/BnoiweV9mFUPpL ZQjH+BBki2tvbrlHb1wJ3Cl8dOeQh+0sycpoQzBL+yig/6QrD5Q5H0kYagOzVrEjS3 xACB8XLbRe9nG5A7hNBYpDoR0VDDQwxzWPn30/bQk8obwGqDRPRKb1JtCVjT3YNsag GiHzwOPStAo4kw7HDvpGvKpAdIPZn7OS7xxnF0Gf83IrFu3qGQWXnxtnx4EJGh9oRz RFmoMfu/sHh0EQXWvZ5qb5yxqZstkhiEa1dMmzakHVTO36TpZbTVFcQ60IKftt43F4 bD5GKamDzuhEw== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVu-00C7Tq-PM; Tue, 14 Dec 2021 18:26:58 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v3 02/10] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Date: Tue, 14 Dec 2021 18:26:26 +0000 Message-Id: <20211214182634.727330-3-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC. We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 ++ include/dt-bindings/interrupt-controller/apple-aic.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index cf6c091a07b1..b95e41816953 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h index 604f2bb30ac0..bf3aac0e5491 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 #endif From patchwork Tue Dec 14 18:26:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 523757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E20C433FE for ; Tue, 14 Dec 2021 18:27:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237024AbhLNS1L (ORCPT ); Tue, 14 Dec 2021 13:27:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236988AbhLNS1D (ORCPT ); Tue, 14 Dec 2021 13:27:03 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75BD6C06173E; Tue, 14 Dec 2021 10:27:03 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 34B6CB81C53; Tue, 14 Dec 2021 18:27:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8F1CC34610; Tue, 14 Dec 2021 18:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506420; bh=eE+a2Gf7Eb4EYOYDngrt1iDAhmc9juBU3zk7/0ma9Sc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=os5pRyO0rdjqOLkQJWCJ7sJu0uYgcvsGd9/1RFSDShk1VWOiR/x9LfZF2/NIAMYGA VVlQe0dxP4u0OkBsPgCzfUOWMeor1rZ7jzoJpgOeDSr+YnmXOLikHVjcblk8HWsX6b 06DWpUaH52pgfWcR90HGDro7uz8iKio+3noA8qdW3eG/o6BUe/l+JNW+aLrvReKzuk rh06pF8C8Vziuhw8dudc04/vxpqvOZDZIR8cgYZFpkDJHG56SYi60xPj1tq5qAAsNK TYsgCsPbYd7zWsyKbfasVO7T44Yj5sNLlU4y4D2Z4ADXrsEDw8Zj+kvRsT0/p1Rpns pVUJcm+b8jS6A== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVv-00C7Tq-0M; Tue, 14 Dec 2021 18:26:59 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v3 03/10] dt-bindings: apple, aic: Add affinity description for per-cpu pseudo-interrupts Date: Tue, 14 Dec 2021 18:26:27 +0000 Message-Id: <20211214182634.727330-4-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier --- .../interrupt-controller/apple,aic.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index b95e41816953..ac1c82cffa0a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -67,6 +67,32 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - affinity + required: - compatible - '#interrupt-cells' From patchwork Tue Dec 14 18:26:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 523760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01572C433FE for ; Tue, 14 Dec 2021 18:27:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236986AbhLNS1D (ORCPT ); Tue, 14 Dec 2021 13:27:03 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:45126 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234282AbhLNS1C (ORCPT ); Tue, 14 Dec 2021 13:27:02 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A0E01616A2; Tue, 14 Dec 2021 18:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 059EAC34613; Tue, 14 Dec 2021 18:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506421; bh=WpijYVmW1mn0d1H0aJ8oMDdr/yhn6zPfMyIhyDwj62g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=scGKsBrctpsshGUsuVsEk5XRfEkiRbkfqam/upYWtIAmTsHeBarpsW/nc3y0yErp4 L8AlIghgo2rYWV6ZmsvmRglZIRYmg5tr92KUXD6qhD1JmZN7XwGLofSBZ3YZwqDhFa wDBeOOE6nw8kwIE7PUWtgToARDP8yNqIUs8SgUkPNEF6FCz3ZDj85vF5KpQJGRJkSG YHkbm/O+QPnNdQ+KD9cxOb/J6+89NfAF9/NWnjHTeChEhyOrzWYCjZ+w/t7lTqvAzl rd20ZMaRbgIrW9ngf+Rc89tFVjRAY7N2MsxqykJxcL/SINqekLYhdDuMoDbF2hfiVW 2Q+sidNEVPQKA== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVv-00C7Tq-8U; Tue, 14 Dec 2021 18:26:59 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v3 04/10] irqchip/apple-aic: Parse FIQ affinities from device-tree Date: Tue, 14 Dec 2021 18:26:28 +0000 Message-Id: <20211214182634.727330-5-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to be able to tell the core IRQ code about the affinity of the PMU interrupt in later patches, parse the affinities kindly provided in the device-tree. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-apple-aic.c | 50 +++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c index 2543ef65825b..b51eb9468701 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -177,6 +177,9 @@ struct aic_irq_chip { void __iomem *base; struct irq_domain *hw_domain; struct irq_domain *ipi_domain; + struct { + cpumask_t aff; + } *fiq_aff[AIC_NR_FIQ]; int nr_hw; int ipi_hwirq; }; @@ -794,12 +797,51 @@ static struct gic_kvm_info vgic_info __initdata = { .no_hw_deactivation = true, }; +static void build_fiq_affinity(struct aic_irq_chip *ic, struct device_node *aff) +{ + int i, n; + u32 fiq; + + if (of_property_read_u32(aff, "fiq-index", &fiq) || + WARN_ON(fiq >= AIC_NR_FIQ)) + return; + + n = of_property_count_elems_of_size(aff, "affinity", sizeof(u32)); + if (WARN_ON(n < 0)) + return; + + ic->fiq_aff[fiq] = kzalloc(sizeof(ic->fiq_aff[fiq]), GFP_KERNEL); + if (!ic->fiq_aff[fiq]) + return; + + for (i = 0; i < n; i++) { + struct device_node *cpu_node; + u32 cpu_phandle; + int cpu; + + if (of_property_read_u32_index(aff, "affinity", + i, &cpu_phandle)) + continue; + + cpu_node = of_find_node_by_phandle(cpu_phandle); + if (WARN_ON(!cpu_node)) + continue; + + cpu = of_cpu_node_to_id(cpu_node); + if (WARN_ON(cpu < 0)) + continue; + + cpumask_set_cpu(cpu, &ic->fiq_aff[fiq]->aff); + } +} + static int __init aic_of_ic_init(struct device_node *node, struct device_node *parent) { int i; void __iomem *regs; u32 info; struct aic_irq_chip *irqc; + struct device_node *affs; regs = of_iomap(node, 0); if (WARN_ON(!regs)) @@ -833,6 +875,14 @@ static int __init aic_of_ic_init(struct device_node *node, struct device_node *p return -ENODEV; } + affs = of_get_child_by_name(node, "affinities"); + if (affs) { + struct device_node *chld; + + for_each_child_of_node(affs, chld) + build_fiq_affinity(irqc, chld); + } + set_handle_irq(aic_handle_irq); set_handle_fiq(aic_handle_fiq); From patchwork Tue Dec 14 18:26:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 523758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D45DCC4332F for ; Tue, 14 Dec 2021 18:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237017AbhLNS1K (ORCPT ); Tue, 14 Dec 2021 13:27:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236991AbhLNS1F (ORCPT ); Tue, 14 Dec 2021 13:27:05 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8981BC061401; Tue, 14 Dec 2021 10:27:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 551CAB81C59; Tue, 14 Dec 2021 18:27:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FEAEC34600; Tue, 14 Dec 2021 18:27:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506422; bh=5FPb0en3K/kHlXy/QXK/zRcJPMyP7gGlqh93jb8Od1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ENpUEX5Nme8hl5zukZhD0hiHTsK8mSTBfWY7g4yAC717MHGOAAEpR2nRKUrTREisj GVNFEcCH2411kOKYLpr7f6OEMbQdR55iar/pm5KADjLFgrbtq87XXfv/gBYWSyh/gY Pwpqiyla7QG0S+JuRZBFqR6ENP7FPVLNJymeuo1hDzUGm+c+7+x2D43d/ZKdW/+C2+ n1m4ByXqsdamDjulCKC99QMWHpT69UPgustSLyxgYbSy7FS4PspoN04wp7I+hzsamJ 5JaRWUAkw1PVpe79bkWT7ZLYrTp9lkSnVkKCQH3nn8vsIHEgC2wGDgEaSzgNQ5aTcB L56FWZdvtnNhg== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVw-00C7Tq-7v; Tue, 14 Dec 2021 18:27:00 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v3 08/10] irqchip/apple-aic: Move PMU-specific registers to their own include file Date: Tue, 14 Dec 2021 18:26:32 +0000 Message-Id: <20211214182634.727330-9-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are about to have a PMU driver, move the PMU bits from the AIC driver into a common include file. Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/apple_m1_pmu.h | 19 +++++++++++++++++++ drivers/irqchip/irq-apple-aic.c | 11 +---------- 2 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/include/asm/apple_m1_pmu.h diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm/apple_m1_pmu.h new file mode 100644 index 000000000000..b848af7faadc --- /dev/null +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef __ASM_APPLE_M1_PMU_h +#define __ASM_APPLE_M1_PMU_h + +#include +#include + +/* Core PMC control register */ +#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) +#define PMCR0_IMODE GENMASK(10, 8) +#define PMCR0_IMODE_OFF 0 +#define PMCR0_IMODE_PMI 1 +#define PMCR0_IMODE_AIC 2 +#define PMCR0_IMODE_HALT 3 +#define PMCR0_IMODE_FIQ 4 +#define PMCR0_IACT BIT(11) + +#endif /* __ASM_APPLE_M1_PMU_h */ diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-aic.c index ceb7a68101e1..a5927382172a 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -109,16 +110,6 @@ * Note: sysreg-based IPIs are not supported yet. */ -/* Core PMC control register */ -#define SYS_IMP_APL_PMCR0_EL1 sys_reg(3, 1, 15, 0, 0) -#define PMCR0_IMODE GENMASK(10, 8) -#define PMCR0_IMODE_OFF 0 -#define PMCR0_IMODE_PMI 1 -#define PMCR0_IMODE_AIC 2 -#define PMCR0_IMODE_HALT 3 -#define PMCR0_IMODE_FIQ 4 -#define PMCR0_IACT BIT(11) - /* IPI request registers */ #define SYS_IMP_APL_IPI_RR_LOCAL_EL1 sys_reg(3, 5, 15, 0, 0) #define SYS_IMP_APL_IPI_RR_GLOBAL_EL1 sys_reg(3, 5, 15, 0, 1)