From patchwork Tue Nov 27 14:54:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152133 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1369481ljp; Tue, 27 Nov 2018 06:54:29 -0800 (PST) X-Google-Smtp-Source: AFSGD/ULWP8Epep89frvngirVclxrpMNEbx9e1qr+JSCON9XVZWXfzUQ/T5QXofTo8mdZ/TDxsZ1 X-Received: by 2002:a62:1a8e:: with SMTP id a136mr18648903pfa.76.1543330469016; Tue, 27 Nov 2018 06:54:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543330469; cv=none; d=google.com; s=arc-20160816; b=I/BwXFKTXqb6E2Xq3ZofsGuaDYML8um5Q2sRn3AnsGhRJb/6PQHXyuGm3lOOtZuKLz aJx+0QLFBUFJslSgSMENpB/5ETibOkNZanUveMEHq6a6662U2IxzpJEE+mj5jNCt7rFu 4UO0EnX1M5Q8Lfuvm13bBzgBQEePOHRjEyzff0HS+/sawxy7w49wN3P1Kng1vckWsnYt rVz4FOJsYNpSFpTupHHrQHSvNkZ0TwuELBzOqluRLfsTjKseRvSx+ca1+KlDib3qF+2R W8KwnzSx2y8ioHRXqtewUY1kAjv70Yk8LV2GZ/E7A611Q0wF9plpBolw2a/kv5GWYIfc fkRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=plotLcSxJ6X2qjqxBCZdRlTiLpmhZhJ3c7g051Ny9Mc=; b=iq8hfp9VcDkNTw66/af6wfet53UYMCfnVna5WmPo9DL5746i4OeGlxBAAJr/jKTv8p i/j0IBqRUXQeMEPKlFB8bumNNaUMecQcOM7VzOtP7m//D3rsrzUsesXHvh27T3mBQ0tY uz9UQLnh6D1fZjJtPBjavKwN+L2CR2XdEdHxmidQXSW8Xu/zkD2K1MBhohxBtu3MDH2a w3NdqJLL2VA5APoL3zRDArn6QRu75N5urE8jw5uRhWtDjkeBgYtME2cmUc6siEwlNLG1 2mhs0M5baYq4Tz/x3xYm1GXnwCoQnUsUzMYjXe963yx9AqV4q1bCard+7Vftu/xa2Uof VgIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ZB+ebDJW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w11si3953609pgf.452.2018.11.27.06.54.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Nov 2018 06:54:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ZB+ebDJW; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 833BC21195BF0; Tue, 27 Nov 2018 06:54:28 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::344; helo=mail-wm1-x344.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 28A2721195BDA for ; Tue, 27 Nov 2018 06:54:26 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id z18so7434172wmc.4 for ; Tue, 27 Nov 2018 06:54:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZ9tHQXB4Z+ntuv5cvpirNh36JERSCZLGNcUzo4/wjE=; b=ZB+ebDJW5d3SfkqeIzlS13rfd3XzDjU3kZvOhQRVVNQduxO/1/h0D/Vk647AtpKrHT LFNqxIqHDj7ymRYpilOhAg5ELMUb43m5F4skh1+idaBD2XbicEcpu2HkgasOY/SqXUU9 ZexacLBDKZCa4iKrMKeavs3fRvg8HWwnRE1K8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vZ9tHQXB4Z+ntuv5cvpirNh36JERSCZLGNcUzo4/wjE=; b=agbEVnALUrWwKrsP9y/szGLF6omEeuuUKdo9R7yqdFF6V/wI4XeIHerEZYu2c+mB5o eq5MTowxGs+94F73y8RQ3O2ZQ7NnyzMVS+2exRgFa/nRk8uLbEI34sCaxx8vvOuIs9oH nSI3mlDC4zmqRbNG9him40X+N938G9aBQoVYyNdV8Q5a0F797aXhygGd45Q+G0ep6xdD MQI0na39s9tkOdBVyDsfuLex8u3U8/xX66qydZ4wc/I3nLbE6tOj7hSZUPXReX0guZrB 0VJSRKOFzUeShtTCoiPG/1pqQn0pZjS6FUsC+9IN09HknMPPbn2afmm9uxSgeRlDv3m/ EqVQ== X-Gm-Message-State: AA+aEWYNZY7F3NnAVFmB6bP5b6qxVRgGwz8y15ReEtiUYCrZoMQ3LGU0 U7ADZm0Ju307E/iC5+ZVWJb5f5TUInQ= X-Received: by 2002:a1c:b1d5:: with SMTP id a204mr28403193wmf.32.1543330464277; Tue, 27 Nov 2018 06:54:24 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:f523:5d63:a56a:3d76]) by smtp.gmail.com with ESMTPSA id v19sm4828490wrd.46.2018.11.27.06.54.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Nov 2018 06:54:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 27 Nov 2018 15:54:17 +0100 Message-Id: <20181127145418.11992-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181127145418.11992-1-ard.biesheuvel@linaro.org> References: <20181127145418.11992-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 1/2] ArmVirtPkg/FdtPciHostBridgeLib: map ECAM and I/O spaces in GCD memory map X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Laszlo Ersek Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Up until now, we have been getting away with not declaring the ECAM and translated I/O spaces at all in the GCD memory map, simply because we map the entire address space with device attributes in the early PEI code, and so these regions will be mapped wherever they end up. Now that we are about to make changes to how ArmVirtQemu reasons about the size of the address space, it would be better to get rid of this mapping of the entire address space, since it can get arbitrarily large without real benefit. So start by mapping the ECAM and translated I/O spaces explicitly, instead of relying on the early PEI mapping. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 + ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 46 +++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) -- 2.19.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laszlo Ersek diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index 0995f4b7a156..4011336a353b 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -42,6 +42,7 @@ [Packages] [LibraryClasses] DebugLib DevicePathLib + DxeServicesTableLib MemoryAllocationLib PciPcdProducerLib diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index 5b9c887db35d..ba177353122e 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -82,6 +83,33 @@ typedef struct { #define DTB_PCI_HOST_RANGE_IO BIT24 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24) +STATIC +EFI_STATUS +MapGcdMmioSpace ( + IN UINT64 Base, + IN UINT64 Size + ) +{ + EFI_STATUS Status; + + Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Base, Size, + EFI_MEMORY_UC); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, + "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n", + __FUNCTION__, Base, Size)); + return Status; + } + + Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, + "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n", + __FUNCTION__, Base, Size)); + } + return Status; +} + STATIC EFI_STATUS ProcessPciHost ( @@ -266,7 +294,23 @@ ProcessPciHost ( "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size)); - return EFI_SUCCESS; + + // Map the ECAM space in the GCD memory map + Status = MapGcdMmioSpace (ConfigBase, ConfigSize); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Map the MMIO window that provides I/O access - the PCI host bridge code + // is not aware of this translation and so it will only map the I/O view + // in the GCD I/O map. + // + Status = MapGcdMmioSpace (IoTranslation, *IoSize); + ASSERT_EFI_ERROR (Status); + + return Status; } STATIC PCI_ROOT_BRIDGE mRootBridge; From patchwork Tue Nov 27 14:54:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 152134 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1369537ljp; Tue, 27 Nov 2018 06:54:31 -0800 (PST) X-Google-Smtp-Source: AFSGD/UhmLQ3Cnp8tpHiHlxjkt0CbttCAxS70rM9taJqSThxLF9OhhCHsI/tzCJFEHSuw6Z4Aa8U X-Received: by 2002:a62:5658:: with SMTP id k85mr22781165pfb.231.1543330471384; Tue, 27 Nov 2018 06:54:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543330471; cv=none; d=google.com; s=arc-20160816; b=NpKB4AqAzTj2jrOIx1tfVaJz+Pwpq3tWoatzf2h/9fdGIB/My4j9GSPZy7DPwn6MVO bSjtaUE/yVZGr1s5dBoJGSw7K1PeWi29WphfLMWNhFBsJkIn1Xe327/K4m+m3fFOKydu oyyHtVyZLV3qG1qWvC+no09HNBd4L3ijwoIEe06vEkHgAThYR77K0YPFXIQRfryGu1/p OXultj0JLi9rXj2BHAodeYnScEA8rODrmzCMCt1Bif29lzSlMRwBBcLBbcgKmL/xEZRb MAKMeTlY+Ls7684g+5GL9dP01njAHaq+54TI0+HAtwgYWZDYQL1fHFVGQA6LImQf/UKu rAtw== ARC-Message-Signature: i=1; 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Now that we are relaxing the address space limit to more than 40 bits, mapping all that address space actually takes up more space in page tables than we have so far made available as temporary RAM. So let's get rid of the mapping rather than increasing the available RAM, given that the mapping is not particularly useful anyway. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) -- 2.19.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Laszlo Ersek diff --git a/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c b/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c index 815ca145b644..70863abb2e7b 100644 --- a/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c +++ b/ArmVirtPkg/Library/QemuVirtMemInfoLib/QemuVirtMemInfoLib.c @@ -73,21 +73,14 @@ ArmVirtGetMemoryMap ( VirtualMemoryTable[1].Length = VirtualMemoryTable[0].PhysicalBase; VirtualMemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - // Peripheral space after DRAM - VirtualMemoryTable[2].PhysicalBase = VirtualMemoryTable[0].Length + VirtualMemoryTable[1].Length; - VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase; - VirtualMemoryTable[2].Length = TopOfAddressSpace - - VirtualMemoryTable[2].PhysicalBase; - VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - // Remap the FD region as normal executable memory - VirtualMemoryTable[3].PhysicalBase = PcdGet64 (PcdFdBaseAddress); - VirtualMemoryTable[3].VirtualBase = VirtualMemoryTable[3].PhysicalBase; - VirtualMemoryTable[3].Length = FixedPcdGet32 (PcdFdSize); - VirtualMemoryTable[3].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryTable[2].PhysicalBase = PcdGet64 (PcdFdBaseAddress); + VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase; + VirtualMemoryTable[2].Length = FixedPcdGet32 (PcdFdSize); + VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; // End of Table - ZeroMem (&VirtualMemoryTable[4], sizeof (ARM_MEMORY_REGION_DESCRIPTOR)); + ZeroMem (&VirtualMemoryTable[3], sizeof (ARM_MEMORY_REGION_DESCRIPTOR)); *VirtualMemoryMap = VirtualMemoryTable; }