From patchwork Thu Nov 29 10:51:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 152385 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2224481ljp; Thu, 29 Nov 2018 02:51:56 -0800 (PST) X-Google-Smtp-Source: AFSGD/WynkXz0acox8zE3ab85oK89PRYG8RtKDKz9n1LX/G97aEjwKGHJlP6D06th0BRbmkYONuJ X-Received: by 2002:a63:cc43:: with SMTP id q3mr772721pgi.291.1543488716392; Thu, 29 Nov 2018 02:51:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543488716; cv=none; d=google.com; s=arc-20160816; b=hE1LehhAOuefsVJwxxb+v/seMGqDAhUrf0yMD3JFB3pBEXpHUc3Q1vfxnD5Jmxm5LX kgcFGNWMhVNvwoqfiOgx6+YG7r9Ptj7q+nyXU4vKe56J0++BDhTugpgIlezS1kIX1pPS Z+npT2hUOGDnCUQZTIneEZwx6xDBx0Hm4hPrWy5YKygJv7mlD71qNKarNbHFikzFtX0w X7wuWgR4fV8sxSLdPDB+zYF8aMT1JCnb73qXLI1UUcV5ukRunoA82WiJbiDEdjj67skd m9p9o9yUw44a2kUNbl7Pc3ujirtoWpci/aFoU1/SszIPsdDFBsbCWDqJGZdUVIjVQ0Rw b8HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=to:subject:message-id:date:from:mime-version:dkim-signature :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=w6g7H+VCvpGFzQyCu+Jx7y2GJscpNNCQUmylBXp1j2c=; b=l/lzmX7mx6MSdC6Uhnk9UXvfNszh9G3NC9swIibC7EnjkyB44E85SiFtW2iuF71l6U QcPSbDIRe52Q35ZzVa6Gx/MmnYAUoNQB5QOHebbWsAtpy6IZLtxFf5sXYfDWX/QlLy9a DuBkkMbZr0007rCTwOozG3QPaY3O+m07SkNwbuCYqr4+QaOxO8IxY48kPOR3qNq5VVio rmFoyChEdFPs92qfJJT7MKqNcj3HkbeYNnIlyWuq/MRg3ATlRR/wAjAE+/LJoE/BwGid YIJnXVke+pTak6Up21mTVaV+W3+hyc0BUZkzfwSuMsGA4mh4w6eGPsZUn2VdR7qrnrZM 9KFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=s8BDmTGA; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Jmrorh8V; spf=pass (google.com: domain of gcc-patches-return-491227-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-491227-patch=linaro.org@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id p8si1762105pls.83.2018.11.29.02.51.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 02:51:56 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-491227-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=s8BDmTGA; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Jmrorh8V; spf=pass (google.com: domain of gcc-patches-return-491227-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-491227-patch=linaro.org@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=mTf27Zf/La1L93Z9cEpzx5eElITJ5AYnSYkDBmdl0TLw2+ bEH+/NQiT1WFg55y9itI0WTU7sCAiF7qamRjTzncDPWKmLV2YCg9aaTlKbNJTadS Nl/02xv38Hvxr12Zul/J92iKJezlq4JrzEEPj1eoS5HqVQHTN4YHFSzeBsg2s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=g/wz7D+doZLn8O+HmeofMx83WKY=; b=s8BDmTGAJif1LZpTOXa5 rIma3XAOyEbyus7moqBxtoVSSkxBxD6Rm/taYPlABLEt1Qp6h+9ejD5Gs03RmL9w /OrwsGNgf2hs0cBVjWdBnsxXGlwDHMjNi3fsCkvIizPqlWAzxE9lji1Y5V+7a7ik X9rYnZasfDgC0f1CLQDjleA= Received: (qmail 102462 invoked by alias); 29 Nov 2018 10:51:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102205 invoked by uid 89); 29 Nov 2018 10:51:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SEM_URI, SEM_URIRED, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:4516 X-HELO: mail-it1-f170.google.com Received: from mail-it1-f170.google.com (HELO mail-it1-f170.google.com) (209.85.166.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Nov 2018 10:51:41 +0000 Received: by mail-it1-f170.google.com with SMTP id z7so2915432iti.0 for ; Thu, 29 Nov 2018 02:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to; bh=2LUeKiu+Oee/SCKWgXvHImxyOEnA2pItskcwN/IeqoQ=; b=Jmrorh8ViuP84b6rzlvGx0XRIIUDLRyfqBlt7Y6EezGNCwYq3Tj6SYhssgjZGh8RsK L5nKaRpSkNwS6N28XnjYo94OxIl38JZqJ6ztppVVN3faWHJpAQJ2ovU6ObTRZVSSEEZW utIZxTH973cCeTifBpxi4oSXmrROMvuIOR1DI= MIME-Version: 1.0 From: Thomas Preudhomme Date: Thu, 29 Nov 2018 10:51:28 +0000 Message-ID: Subject: [PATCH, ARM] Error out when -mfpu set and targeting Thumb-1 To: kyrylo.tkachov@foss.arm.com, Ramana Radhakrishnan , Richard Earnshaw , gcc-patches@gcc.gnu.org X-IsSubscribed: yes Hi, FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is not set. Among other things, it makes some of the cmse tests (eg. gcc.target/arm/cmse/baseline/softfp.c) fail when targeting -march=armv8-m.base -mfpu= -mfloat-abi=softfp. This patch errors out when a Thumb-1 -like target is selected and a FPU is specified, thus making such tests being skipped. ChangeLog entries are as follows: *** gcc/ChangeLog *** 2018-11-28 thomas Preud'homme * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Error out if targeting Thumb-1 with an FPU specified. *** gcc/testsuite/ChangeLog *** 2018-11-28 thomas Preud'homme * gcc.target/arm/thumb1_mfpu-1.c: New testcase. * gcc.target/arm/thumb1_mfpu-2.c: Likewise. Testing: No testsuite regression when targeting arm-none-eabi Armv6S-M. Fails as expected when targeting Armv6-M with an -mfpu or a default FPU. Succeeds without. Is this ok for stage3? Best regards, Thomas >From 051e38552d7c596873e0303f6ec4272b26d50900 Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Tue, 27 Nov 2018 15:52:38 +0000 Subject: [PATCH] [PATCH, ARM] Error out when -mfpu set and targeting Thumb-1 Hi, FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is not set. Among other things, it makes some of the cmse tests (eg. gcc.target/arm/cmse/baseline/softfp.c) fail when targeting -march=armv8-m.base -mfpu= -mfloat-abi=softfp. This patch errors out when a Thumb-1 -like target is selected and a FPU is specified, thus making such tests being skipped. ChangeLog entries are as follows: *** gcc/ChangeLog *** 2018-11-28 thomas Preud'homme * config/arm/arm.c (arm_options_perform_arch_sanity_checks): Error out if targeting Thumb-1 with an FPU specified. *** gcc/testsuite/ChangeLog *** 2018-11-28 thomas Preud'homme * gcc.target/arm/thumb1_mfpu-1.c: New testcase. * gcc.target/arm/thumb1_mfpu-2.c: Likewise. Testing: No testsuite regression when targeting arm-none-eabi Armv6S-M. Fails as expected when targeting Armv6-M with an -mfpu or a default FPU. Succeeds without. Is this ok for stage3? Best regards, Thomas --- gcc/config/arm/arm.c | 3 +++ gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c | 7 +++++++ gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c | 8 ++++++++ 3 files changed, 18 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c create mode 100644 gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 40f0574e32e..1a205123cf5 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3747,6 +3747,9 @@ arm_options_perform_arch_sanity_checks (void) { if (arm_abi == ARM_ABI_IWMMXT) arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; + else if (TARGET_THUMB1 + && bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)) + error ("Thumb-1 does not allow FP instructions"); else if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; diff --git a/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c new file mode 100644 index 00000000000..5347e63f9b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ +/* { dg-options "-mthumb -mfpu=vfp -mfloat-abi=softfp" } */ +/* { dg-error "Thumb-1 does not allow FP instructions" "" { target *-*-* } 0 } */ + +int foo; diff --git a/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c new file mode 100644 index 00000000000..941ed26ed01 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/thumb1_mfpu-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "incompatible float ABI" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */ +/* No need to skip in presence of -mfpu since arm_thumb1_ok will already fail + due to Thumb-1 with -mfpu which is tested by thumb1_mfpu-1 testcase. */ +/* { dg-options "-mthumb -mfloat-abi=softfp" } */ + +int foo; -- 2.19.1