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rNgja8aKj4UBMlZD6oiEQjzkoNkk3+g4aCiASkWkkP93xZCdDcumv0ar6B5pGs/vAvIuB5xttHMHYiWOBEUHVPEj0Z0W47LgHwPjQLg9ow0cr2zKZ4R/8g/Bu28RSxBnHerwtnIgnfglgc1jRlUa6BpgToShRofohEylzO+6ONE/BgJVa5i/8xCNdwd9rhknDirG1oDtx/akkkEb2NZVRPo8zoeSgbaIBmEY2aGUI3ja6lf3z5anKiFvAcRLuOFrSIvXPmjcgXGedl7cFw8TiVg5ZAz2SWW7ADxEa747gU+3mdXBWKOoamU8P3ai2JYUHNsAqOgdkVvcIVXO1ngzAMtUW7BgwCihbPABmAJA2srTDCjg9CgcgdBVElK3NESxegDSQVqOF6TYbbronqm9wALJsw6m8FsOvkstsA/kCmUXUhQMhdvHl7pu93BRDVOIGrMAOwZOlP4xNqH9uOu2hzj0qGNhFyzpGdgQCJOMt/ZPdWtK2GkJfpdlGV7tuUN5xcoWiTwtVyg55tbOz0DB4XO11tOOr2OtxU7kXoWvoLAW8t+OlbmczocAZfzP5f6ICXFn2Y9ZXisicJlh/LqEIPjwr+idOGEcUbU0X8nP1gZftGZLph5aafxQ6SSPJpPFqMks5PS+HmUkysL2ULtI9oskwJ4EtDx6ppcL7EQ7dxJzRtLQ+cXYh9rYRrMAeOMYUvRkVdcv8daqcgS+SQhlaT6JVFadoaJMIXI50bb69OizIs0wfgoUkZjfG5qFWHZ6aNMfy7cCni9Tbp7lhsSqPtAAsGdTQQ9E7dlRBvfS5lapnItBYJDILxgJFeksUlGJmVEauWq5JnavD/hGmXzafXVXolQyIn6GmICUvJT3AHv05r+/2+Im4r1M7vD2urMXVr0VG9eSAHuYGOxrqEfZJAOp20z0tnWEzYONXerMYIJT2QkyENHxg6JrRDk06iZou56dE5IuJI/jzCk3I/g6VxDeXe+P4UKbBa8BlWPfWU70nG0u8A/SH7234J58PfGJF69JTWXfXfkTRM6J9vrzb2HRn9OneA8aqj8Yrg/xGF3FHHDjgKVwJTjuYAvb4k9ixqQZeJ7aCl79l0bYrC5UeEoWJ2KjV+58zwP+Y0lxFIRAqrvB42oYpklLE0k44/NG+U8mL0ukBcbDQeE5OoLjc88H2QknJWmHRnv7BlJOxt2W9ToqAreyQotELBtzbDngKP3+nmqOU+1JoDxMXPtM/gzhlz94OfZQwUVgS/gJ8esC/tUJpKvDugAd2AlmXkYA7rVmzmWNp1OsuMoQ4aYurLSmKSrGvZNKBheEA+MxwNNsazGv2b/McbplTUWEfulX9JiE+yuEBLWKRpDQJk7DedYR1FbDL8VuGrSFbjcsbP5p1RU1ywFAloyHiGZJXZKjbamNhkLIWRcad9gh07VjuDe6llgb8l/7db8bBx0Z9zy12lNQOgGCtPvd8bIWE22MCE2eyEgfFftPH35MVxgM4lzHYpp1KiP59tZcMPD2/KO4lcxF0PSP/+ETzA/byHdnK152aqP3MuEDZJLe1zmjM7MsdLNzKnw1oKPHVAn46Go+RsdpztZ8XotOo3LbbbueqaD70XtR37IApHjpPzreR9XrKWwemuQbZIapDAONgcc= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6650152e-b3cc-4c40-8595-08d9fa5f1080 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 02:07:25.7062 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kpQG8SWlPmd+g6vnYRNF8SRXLh4Rz8BDHaVDvEBeF5RGWPKtK2LgJOllYv6Wc0A14d3m5G9o8Xy5jiDv6T9A9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8734 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peng Fan Add i.MX93 clock definition Reviewed-by: Abel Vesa Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Peng Fan --- include/dt-bindings/clock/imx93-clock.h | 201 ++++++++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 include/dt-bindings/clock/imx93-clock.h diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h new file mode 100644 index 000000000000..21fda9c5cb5e --- /dev/null +++ b/include/dt-bindings/clock/imx93-clock.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H +#define __DT_BINDINGS_CLOCK_IMX93_CLK_H + +#define IMX93_CLK_DUMMY 0 +#define IMX93_CLK_24M 1 +#define IMX93_CLK_EXT1 2 +#define IMX93_CLK_SYS_PLL_PFD0 3 +#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 +#define IMX93_CLK_SYS_PLL_PFD1 5 +#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 +#define IMX93_CLK_SYS_PLL_PFD2 7 +#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 +#define IMX93_CLK_AUDIO_PLL 9 +#define IMX93_CLK_VIDEO_PLL 10 +#define IMX93_CLK_A55_PERIPH 11 +#define IMX93_CLK_A55_MTR_BUS 12 +#define IMX93_CLK_A55 13 +#define IMX93_CLK_M33 14 +#define IMX93_CLK_BUS_WAKEUP 15 +#define IMX93_CLK_BUS_AON 16 +#define IMX93_CLK_WAKEUP_AXI 17 +#define IMX93_CLK_SWO_TRACE 18 +#define IMX93_CLK_M33_SYSTICK 19 +#define IMX93_CLK_FLEXIO1 20 +#define IMX93_CLK_FLEXIO2 21 +#define IMX93_CLK_LPIT1 22 +#define IMX93_CLK_LPIT2 23 +#define IMX93_CLK_LPTMR1 24 +#define IMX93_CLK_LPTMR2 25 +#define IMX93_CLK_TPM1 26 +#define IMX93_CLK_TPM2 27 +#define IMX93_CLK_TPM3 28 +#define IMX93_CLK_TPM4 29 +#define IMX93_CLK_TPM5 30 +#define IMX93_CLK_TPM6 31 +#define IMX93_CLK_FLEXSPI1 32 +#define IMX93_CLK_CAN1 33 +#define IMX93_CLK_CAN2 34 +#define IMX93_CLK_LPUART1 35 +#define IMX93_CLK_LPUART2 36 +#define IMX93_CLK_LPUART3 37 +#define IMX93_CLK_LPUART4 38 +#define IMX93_CLK_LPUART5 39 +#define IMX93_CLK_LPUART6 40 +#define IMX93_CLK_LPUART7 41 +#define IMX93_CLK_LPUART8 42 +#define IMX93_CLK_LPI2C1 43 +#define IMX93_CLK_LPI2C2 44 +#define IMX93_CLK_LPI2C3 45 +#define IMX93_CLK_LPI2C4 46 +#define IMX93_CLK_LPI2C5 47 +#define IMX93_CLK_LPI2C6 48 +#define IMX93_CLK_LPI2C7 49 +#define IMX93_CLK_LPI2C8 50 +#define IMX93_CLK_LPSPI1 51 +#define IMX93_CLK_LPSPI2 52 +#define IMX93_CLK_LPSPI3 53 +#define IMX93_CLK_LPSPI4 54 +#define IMX93_CLK_LPSPI5 55 +#define IMX93_CLK_LPSPI6 56 +#define IMX93_CLK_LPSPI7 57 +#define IMX93_CLK_LPSPI8 58 +#define IMX93_CLK_I3C1 59 +#define IMX93_CLK_I3C2 60 +#define IMX93_CLK_USDHC1 61 +#define IMX93_CLK_USDHC2 62 +#define IMX93_CLK_USDHC3 63 +#define IMX93_CLK_SAI1 64 +#define IMX93_CLK_SAI2 65 +#define IMX93_CLK_SAI3 66 +#define IMX93_CLK_CCM_CKO1 67 +#define IMX93_CLK_CCM_CKO2 68 +#define IMX93_CLK_CCM_CKO3 69 +#define IMX93_CLK_CCM_CKO4 70 +#define IMX93_CLK_HSIO 71 +#define IMX93_CLK_HSIO_USB_TEST_60M 72 +#define IMX93_CLK_HSIO_ACSCAN_80M 73 +#define IMX93_CLK_HSIO_ACSCAN_480M 74 +#define IMX93_CLK_ML_APB 75 +#define IMX93_CLK_ML 76 +#define IMX93_CLK_MEDIA_AXI 77 +#define IMX93_CLK_MEDIA_APB 78 +#define IMX93_CLK_MEDIA_LDB 79 +#define IMX93_CLK_MEDIA_DISP_PIX 80 +#define IMX93_CLK_CAM_PIX 81 +#define IMX93_CLK_MIPI_TEST_BYTE 82 +#define IMX93_CLK_MIPI_PHY_CFG 83 +#define IMX93_CLK_ADC 84 +#define IMX93_CLK_PDM 85 +#define IMX93_CLK_TSTMR1 86 +#define IMX93_CLK_TSTMR2 87 +#define IMX93_CLK_MQS1 88 +#define IMX93_CLK_MQS2 89 +#define IMX93_CLK_AUDIO_XCVR 90 +#define IMX93_CLK_SPDIF 91 +#define IMX93_CLK_ENET 92 +#define IMX93_CLK_ENET_TIMER1 93 +#define IMX93_CLK_ENET_TIMER2 94 +#define IMX93_CLK_ENET_REF 95 +#define IMX93_CLK_ENET_REF_PHY 96 +#define IMX93_CLK_I3C1_SLOW 97 +#define IMX93_CLK_I3C2_SLOW 98 +#define IMX93_CLK_USB_PHY_BURUNIN 99 +#define IMX93_CLK_PAL_CAME_SCAN 100 +#define IMX93_CLK_A55_GATE 101 +#define IMX93_CLK_CM33_GATE 102 +#define IMX93_CLK_ADC1_GATE 103 +#define IMX93_CLK_WDOG1_GATE 104 +#define IMX93_CLK_WDOG2_GATE 105 +#define IMX93_CLK_WDOG3_GATE 106 +#define IMX93_CLK_WDOG4_GATE 107 +#define IMX93_CLK_WDOG5_GATE 108 +#define IMX93_CLK_SEMA1_GATE 109 +#define IMX93_CLK_SEMA2_GATE 110 +#define IMX93_CLK_MU_A_GATE 111 +#define IMX93_CLK_MU_B_GATE 112 +#define IMX93_CLK_EDMA1_GATE 113 +#define IMX93_CLK_EDMA2_GATE 114 +#define IMX93_CLK_FLEXSPI1_GATE 115 +#define IMX93_CLK_GPIO1_GATE 116 +#define IMX93_CLK_GPIO2_GATE 117 +#define IMX93_CLK_GPIO3_GATE 118 +#define IMX93_CLK_GPIO4_GATE 119 +#define IMX93_CLK_FLEXIO1_GATE 120 +#define IMX93_CLK_FLEXIO2_GATE 121 +#define IMX93_CLK_LPIT1_GATE 122 +#define IMX93_CLK_LPIT2_GATE 123 +#define IMX93_CLK_LPTMR1_GATE 124 +#define IMX93_CLK_LPTMR2_GATE 125 +#define IMX93_CLK_TPM1_GATE 126 +#define IMX93_CLK_TPM2_GATE 127 +#define IMX93_CLK_TPM3_GATE 128 +#define IMX93_CLK_TPM4_GATE 129 +#define IMX93_CLK_TPM5_GATE 130 +#define IMX93_CLK_TPM6_GATE 131 +#define IMX93_CLK_CAN1_GATE 132 +#define IMX93_CLK_CAN2_GATE 133 +#define IMX93_CLK_LPUART1_GATE 134 +#define IMX93_CLK_LPUART2_GATE 135 +#define IMX93_CLK_LPUART3_GATE 136 +#define IMX93_CLK_LPUART4_GATE 137 +#define IMX93_CLK_LPUART5_GATE 138 +#define IMX93_CLK_LPUART6_GATE 139 +#define IMX93_CLK_LPUART7_GATE 140 +#define IMX93_CLK_LPUART8_GATE 141 +#define IMX93_CLK_LPI2C1_GATE 142 +#define IMX93_CLK_LPI2C2_GATE 143 +#define IMX93_CLK_LPI2C3_GATE 144 +#define IMX93_CLK_LPI2C4_GATE 145 +#define IMX93_CLK_LPI2C5_GATE 146 +#define IMX93_CLK_LPI2C6_GATE 147 +#define IMX93_CLK_LPI2C7_GATE 148 +#define IMX93_CLK_LPI2C8_GATE 149 +#define IMX93_CLK_LPSPI1_GATE 150 +#define IMX93_CLK_LPSPI2_GATE 151 +#define IMX93_CLK_LPSPI3_GATE 152 +#define IMX93_CLK_LPSPI4_GATE 153 +#define IMX93_CLK_LPSPI5_GATE 154 +#define IMX93_CLK_LPSPI6_GATE 155 +#define IMX93_CLK_LPSPI7_GATE 156 +#define IMX93_CLK_LPSPI8_GATE 157 +#define IMX93_CLK_I3C1_GATE 158 +#define IMX93_CLK_I3C2_GATE 159 +#define IMX93_CLK_USDHC1_GATE 160 +#define IMX93_CLK_USDHC2_GATE 161 +#define IMX93_CLK_USDHC3_GATE 162 +#define IMX93_CLK_SAI1_GATE 163 +#define IMX93_CLK_SAI2_GATE 164 +#define IMX93_CLK_SAI3_GATE 165 +#define IMX93_CLK_MIPI_CSI_GATE 166 +#define IMX93_CLK_MIPI_DSI_GATE 167 +#define IMX93_CLK_LVDS_GATE 168 +#define IMX93_CLK_LCDIF_GATE 169 +#define IMX93_CLK_PXP_GATE 170 +#define IMX93_CLK_ISI_GATE 171 +#define IMX93_CLK_NIC_MEDIA_GATE 172 +#define IMX93_CLK_USB_CONTROLLER_GATE 173 +#define IMX93_CLK_USB_TEST_60M_GATE 174 +#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 +#define IMX93_CLK_PDM_GATE 176 +#define IMX93_CLK_MQS1_GATE 177 +#define IMX93_CLK_MQS2_GATE 178 +#define IMX93_CLK_AUD_XCVR_GATE 179 +#define IMX93_CLK_SPDIF_GATE 180 +#define IMX93_CLK_HSIO_32K_GATE 181 +#define IMX93_CLK_ENET1_GATE 182 +#define IMX93_CLK_ENET_QOS_GATE 183 +#define IMX93_CLK_SYS_CNT_GATE 184 +#define IMX93_CLK_TSTMR1_GATE 185 +#define IMX93_CLK_TSTMR2_GATE 186 +#define IMX93_CLK_TMC_GATE 187 +#define IMX93_CLK_PMRO_GATE 188 +#define IMX93_CLK_32K 189 +#define IMX93_CLK_END 190 + +#endif From patchwork Mon Feb 28 02:09:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 546816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org 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signed) header.d=none;dmarc=none action=none header.from=oss.nxp.com; Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by PAXPR04MB8734.eurprd04.prod.outlook.com (2603:10a6:102:21e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.26; Mon, 28 Feb 2022 02:07:29 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::552c:ed46:26dc:77cc]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::552c:ed46:26dc:77cc%4]) with mapi id 15.20.4995.018; Mon, 28 Feb 2022 02:07:29 +0000 From: "Peng Fan (OSS)" To: sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, abel.vesa@nxp.com Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH V6 3/5] clk: imx: add i.MX93 composite clk Date: Mon, 28 Feb 2022 10:09:06 +0800 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SrUgPSWi9TNwDQTmXNip0xy7YBTlYW5CYgx58w+H2kPRb0GErSQ3fF58fHOtCqpNZBDo6OpqgjfTYU7f0krRt+v+G2DveSL0e+aM6whr+oQgEfYmu1NueCWhbsTBIPlRFQqUrm3nI3ZSxIer6/Ht0ZjhH3PIOCZ5auAotN+EkDs9GkVi+yRK+/P1eVNkvUSl89NuTIZ3SfReig1M+UbUksrpAgAfJ2UkldxkgbePrivh9Zu4LfUFQpQAZ1OrVShM5B2WP6lbC7/qIE3Z8G4P4xNv4RDRmHVtcchO/dkH+LpkddzizE/S+TzavB2v8IGeY6OD9LBkvKeTpnLilHed9W3okS4b6ib0aOs3s9dwHmqaHyiQIwMggNzBdBXAPHRCyZ1oSR9nwOrTeFSLmEh2b5ei5cWGruC/aMvgBX/oE3GLynlL8ZC57UiK8gBKa5dE8Nwr2DO5NKEaqOZ+LRlNmWC7hhm76HboCA/VEpVHQaiORde932LRajwgZ7YK/8tkwV0y9PUtlHIXlJWfSPjnLXCTij7KSvcXlGRZIXZ9CfkkaC7n/Vf+Gh1afIVDygeoUmZFB66oDqlQ1YParfOFXVAgyfUXLghGQKWt3SsK9yRzwf99SHueqhfdxQzJ/fwqWEzdUJ1IiBozttpe30FxkwOL+Ud/+DI9NTzawzjxFnSVvEzzItGSM0BwfReC2FPVuZDarBRmlQ+wj5Zz2q8BeTPfy0wDkvUUukymkhF7xB5a51ehDsocFDymLJ9oHXqMXZhzuwAR3wcIW3vpC7J10esqXMfr9LEqVIWmU1giHAg18qRyWQnxr2lj4mWWabejQd3qmKlAGxA8T2rJ/bghF3ez7BL++LwIWro2vwvir4TK6H2uBqoOKJDX1xY5f7ElM8S0kLSakRAqyat1DRJdWdoyk3rmqjNH1uk2XP098Rlm8tljh1zNDopkMMTN1ynCQ5c/jvR1XvN4ur91QMivu96pYGXrCNQKGKfPBW/NzL1ssYMwab1D8fBxZsTIE2T5ZHuyoTq52/ndLXbw4gFBDtcDcit1QZYoKNMFTpOM5N/VOJuYZ4XpZ0A2XHftnwrQzFE1m8wGzgdTPXHByCGwf8IDyg/e0qUMz4OUNLFBD3c0s/+T3prGB2kJBeg1ckBh84iMMOC9qmIwWOSf3hepOcHnRuljGABcdG0B17lzkA9J5ZHsbt6080d8mYJRagVMAAW0pFY8f6W9KPRID1sLMMPNOlQXOb90etoKlm85MeBZW+Ny5IQbBsnVm9MT38GTudwpa13xlcuSfKKGuAYNbJ4vWXg1einqiFbCB+Ff1lNtwWQeaAsizeb4K1OMhM75DsimlJxmA7gLVh/zCO0v3sqTuS93mas/vJnYtm/l2ggNsYka1sZt1xMaAQMv0D5Lhtsp4x4qAU/M171m4jhA9ujr2KtoVpZTIlLJozM1MTQ2NuelyYrF+AQwZ11qqQ3LxWBq9Cl49p4rjsBGfdYtuZF6utc0+W9tRohjMn0zfvlkYX8TwZRxTdOYB9BWdsEH261mZEBALpK0/A0Pjm2w4AjvoVLsaAyFNbH0avvSn2CJID2yVKv5vyHZKYS7tx206I3Ew6hnzUDrRtgicTlIg+D4wCv4yfbokI4GsYldJx4= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f18fccef-8474-4866-e53f-08d9fa5f12e7 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2022 02:07:29.7234 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /7RZY8rRikj6B7SdhxzAZ20q+Gdg1JhPfpc/AN7EFVbahxe3fXXoVOIkapk9KyK6UN43CGHpnwXyFDMglvrRJg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8734 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peng Fan i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by: Abel Vesa Reviewed-by: Stephen Boyd Signed-off-by: Peng Fan --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite-93.c | 93 ++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 +++ 3 files changed, 103 insertions(+) create mode 100644 drivers/clk/imx/clk-composite-93.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index aa8f5204d7e1..36c04922d789 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -4,6 +4,7 @@ mxc-clk-objs += clk.o mxc-clk-objs += clk-busy.o mxc-clk-objs += clk-composite-7ulp.o mxc-clk-objs += clk-composite-8m.o +mxc-clk-objs += clk-composite-93.o mxc-clk-objs += clk-cpu.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c new file mode 100644 index 000000000000..b44619aa5ca5 --- /dev/null +++ b/drivers/clk/imx/clk-composite-93.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + * Peng Fan + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +#define CCM_DIV_SHIFT 0 +#define CCM_DIV_WIDTH 8 +#define CCM_MUX_SHIFT 8 +#define CCM_MUX_MASK 3 +#define CCM_OFF_SHIFT 24 + +#define AUTHEN_OFFSET 0x30 +#define TZ_NS_SHIFT 9 +#define TZ_NS_MASK BIT(9) + +struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; + struct clk_hw *div_hw, *gate_hw; + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + bool clk_ro = false; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux_hw = &mux->hw; + mux->reg = reg; + mux->shift = CCM_MUX_SHIFT; + mux->mask = CCM_MUX_MASK; + mux->lock = &imx_ccm_lock; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div_hw = &div->hw; + div->reg = reg; + div->shift = CCM_DIV_SHIFT; + div->width = CCM_DIV_WIDTH; + div->lock = &imx_ccm_lock; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; + + if (!(readl(reg + AUTHEN_OFFSET) & TZ_NS_MASK)) + clk_ro = true; + + if (clk_ro) { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ro_ops, div_hw, + &clk_divider_ro_ops, NULL, NULL, flags); + } else { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = CCM_OFF_SHIFT; + gate->lock = &imx_ccm_lock; + gate->flags = CLK_GATE_SET_TO_DISABLE; + + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ops, div_hw, + &clk_divider_ops, gate_hw, + &clk_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); + } + + if (IS_ERR(hw)) + goto fail; + + return hw; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(hw); +} +EXPORT_SYMBOL_GPL(imx93_clk_composite_flags); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 7d220a01de1f..63eb7c53b123 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -419,6 +419,15 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, IMX_COMPOSITE_FW_MANAGED, \ IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE) +struct clk_hw *imx93_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, + void __iomem *reg, + unsigned long flags); +#define imx93_clk_composite(name, parent_names, num_parents, reg) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table,