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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:36 -0600 Message-Id: <20181203160840.15115-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::244 Subject: [Qemu-devel] [PATCH for-4.0 1/5] tcg/i386: Propagate is64 to tcg_out_qemu_ld_direct X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This helps preserve the invariant that all TCG_TYPE_I32 values are stored zero-extended in the 64-bit host registers. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 28192f4608..6bf4f84b20 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1883,10 +1883,11 @@ static inline void setup_guest_base_seg(void) { } static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) + int seg, bool is64, TCGMemOp memop) { const TCGMemOp real_bswap = memop & MO_BSWAP; TCGMemOp bswap = real_bswap; + int rexw = is64 * P_REXW; int movop = OPC_MOVL_GvEv; if (have_movbe && real_bswap) { @@ -1900,7 +1901,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, base, index, 0, ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, base, index, 0, ofs); break; case MO_UW: @@ -1920,9 +1921,9 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, base, index, 0, ofs); tcg_out_rolw_8(s, datalo); } - tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo); + tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + P_REXW + seg, + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); } break; @@ -2010,7 +2011,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_read)); /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, opc); /* Record the current context of a load into ldst label */ add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, @@ -2045,7 +2046,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) } tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, opc); + base, index, offset, seg, is64, opc); } #endif } From patchwork Mon Dec 3 16:08:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 152708 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7029026ljp; Mon, 3 Dec 2018 08:49:38 -0800 (PST) X-Google-Smtp-Source: AFSGD/UcPNLaHT8CMIu7vG8zNJFP/LSregpcZ6U1Cjfy8tieEvUnl0cbK4McBaamJyx94WSlh1S1 X-Received: by 2002:ac8:36d9:: with SMTP id b25mr16521405qtc.49.1543855778248; Mon, 03 Dec 2018 08:49:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543855778; cv=none; d=google.com; s=arc-20160816; b=ITZZ/+ehZu1QnGBxuuGfRotVxFWnTzxUBAMObfVcJDkDfHhETT4zSofR2bZgicARkf 8zK6P/HXI/hUuMF3LjtX6EfsEsEHaLJP8iho5jwgB7DJCxpJxhnCOo8ojsuPGDpN1UXv mF98IgMc1DMEoO3bc9L7i1wjArV7SyoWIGg+40KvT9Wc2iwTCbvEpCZdEDVY+63Owr0W SBgTZ+xT99AVP5gDE4JZx/ON5uD27BI6xavykySEv0umez4xRjensjfKmifGmJkkTcdF U+cMmr/7ICO1uF50GFGfNMoeqI2KzSnSag1wzZ8Koqn3QNKWH7TFBTMmPupPaomWZdrH +fXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VGbbvWUE6rnQSaltbq2Rb0A4jW/k/dy2fVEq4xZiX2I=; b=b/3cZZqHOnFWx/SDbDYRjj6lAUkNFs0gmNOYTtuKr/JVNrGJyVcrUrw/Rs4dXrTujJ jQqP41OOgx/uNBl+QsuOc5VqbiKefczbH68nv4eqa9ZD/3MZkI4RkgCpuPcVSVneLot2 vBEcJf+VjpEnUp4gzhjPz8u2i+lX+/ufOmpAt7T0ICeBKKkgSktrbKV/wwbQWLLWL+aF 2qVyGtVVlKloGHVcwe+d7PN75CzVon8e6lgaGGEsSJYq/lOCQgue5TjgCFbzzXk7dWcI yy4okuNHnmMm4BCH5OXrVnbb2iCaer5omk1n1ny3VWlx8Lmp7ZikCWAuFxSUd+ldcw+V frDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QC0MTw72; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:37 -0600 Message-Id: <20181203160840.15115-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH for-4.0 2/5] tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This preserves the invariant that all TCG_TYPE_I32 values are zero-extended in the 64-bit host register. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 5 +++-- tcg/i386/tcg-target.inc.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2441658865..c523d5f5e1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -135,8 +135,9 @@ extern bool have_avx2; #define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 -#define TCG_TARGET_HAS_extrl_i64_i32 0 -#define TCG_TARGET_HAS_extrh_i64_i32 0 +/* Keep target addresses zero-extended in a register. */ +#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS == 32) +#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS == 32) #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6bf4f84b20..ab31dfa66d 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2546,12 +2546,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: + case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_ext32s(s, a0, a1); break; + case INDEX_op_extrh_i64_i32: + tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); + break; #endif OP_32_64(deposit): @@ -2915,6 +2919,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_neg_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extrh_i64_i32: return &r_0; case INDEX_op_ext8s_i32: @@ -2930,6 +2935,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: case INDEX_op_extract_i32: case INDEX_op_extract_i64: case INDEX_op_sextract_i32: From patchwork Mon Dec 3 16:08:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 152709 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7030841ljp; Mon, 3 Dec 2018 08:51:24 -0800 (PST) X-Google-Smtp-Source: AFSGD/UResJANi5CbQFTvhuyQwGjiSqI5P+eFmcaQXWbpzrB0EtmSAJFpS7GfptRAQ1p9XW9TDoc X-Received: by 2002:a37:4a47:: with SMTP id x68mr15804509qka.112.1543855884841; Mon, 03 Dec 2018 08:51:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543855884; cv=none; d=google.com; s=arc-20160816; b=olS003o0MjGDMS42IhoR8rGIRg8u1/Y8Rd0i/GOwTLbmfh97v97iZGnGzoKq68H2ZZ OTwI4OAFyJSwvr5VYcxx9IX1dPoSbdFlqJI1l2ebqxvAEzUS2IHjc3VR5w+f/0LaO6xb I1VwqqxbvRoJKqYiiOfRDBLIj7WgHJvjtSmr+136kuqye1inL4IBuo83PP6FIuyPrbl/ wCSCaAC5jhXsm/S2sRYcWEL7uNYP6OGSCeulELoddX/MlkO5NUvSr2DHYlQuGU1k4HYh 0rJyUGq+MsrPUbWmUsYHJ4+aUNd+ZuGk1Ti9xGc2/9SnbYqLirwxHuqRom3BIXyjrAky QaQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=OX2SVM+SGv9AntTuQIyBfb8LvK9XD54FYkUpBz/1FwI=; b=zvHkvWf7EUjMSRqRtFKa7d/+HPWsP8woZzlWzbzQHBj+UQMna630GD5DWrkxmcgmwp l3vh/p8aDrfmMWTLMa4z/9z2zxf0PDVhQBCFZoSNBRiex05rrrMVfiAwzU8zVg2IhLFw wEnWm16JcgW+Q56i1IuDXcCsrYpiQt+EiRK2rSkC1cbbHqOP6fwyDCWttzFErD4Tpnrl 0AxAVxW77CYStG5o2CGP0lztoC/P3Rr108A/cZyENim012C/EoPsDKY9sf6c7RQ+Ss8H zir17N8HopqSs68tbi8N5v/cetmj8/ApVM04z/9YMQQRDMnPsbezv3hiWvct8SSqyprw RxKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="UZwmU/Vs"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:38 -0600 Message-Id: <20181203160840.15115-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH for-4.0 3/5] tcg/i386: Assume 32-bit values are zero-extended X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now have an invariant that all TCG_TYPE_I32 values are zero-extended, which means that we do not need to extend them again during qemu_ld/st, either explicitly via a separate tcg_out_ext32u or implicitly via P_ADDR32. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 103 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 63 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index ab31dfa66d..853c3c8465 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -309,13 +309,11 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ #define P_DATA16 0x400 /* 0x66 opcode prefix */ #if TCG_TARGET_REG_BITS == 64 -# define P_ADDR32 0x800 /* 0x67 opcode prefix */ # define P_REXW 0x1000 /* Set REX.W = 1 */ # define P_REXB_R 0x2000 /* REG field as byte register */ # define P_REXB_RM 0x4000 /* R/M field as byte register */ # define P_GS 0x8000 /* gs segment override */ #else -# define P_ADDR32 0 # define P_REXW 0 # define P_REXB_R 0 # define P_REXB_RM 0 @@ -528,9 +526,6 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) tcg_debug_assert((opc & P_REXW) == 0); tcg_out8(s, 0x66); } - if (opc & P_ADDR32) { - tcg_out8(s, 0x67); - } if (opc & P_SIMDF3) { tcg_out8(s, 0xf3); } else if (opc & P_SIMDF2) { @@ -1659,11 +1654,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0); /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. There are two cases worth note: - For 32-bit guest and x86_64 host, MOVL zero-extends the guest address - before the fastpath ADDQ below. For 64-bit guest and x32 host, MOVQ - copies the entire guest address for the slow path, while truncation - for the 32-bit host happens with the fastpath ADDL below. */ + path function argument setup. */ tcg_out_mov(s, ttype, r1, addrlo); /* jne slow_path */ @@ -2019,41 +2010,31 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) #else { int32_t offset = guest_base; - TCGReg base = addrlo; int index = -1; int seg = 0; - /* For a 32-bit guest, the high 32 bits may contain garbage. - We can do this with the ADDR32 prefix if we're not using - a guest base, or when using segmentation. Otherwise we - need to zero-extend manually. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base == 0 || guest_base_flags) { seg = guest_base_flags; offset = 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |= P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS == 64) { - if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base = TCG_REG_L0; - } - if (offset != guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index = TCG_REG_L1; - offset = 0; - } + } else if (TCG_TARGET_REG_BITS == 64 && offset != guest_base) { + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index = TCG_REG_L1; + offset = 0; } tcg_out_qemu_ld_direct(s, datalo, datahi, - base, index, offset, seg, is64, opc); + addrlo, index, offset, seg, is64, opc); } #endif } static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, - TCGReg base, intptr_t ofs, int seg, - TCGMemOp memop) + TCGReg base, int index, intptr_t ofs, + int seg, TCGMemOp memop) { /* ??? Ideally we wouldn't need a scratch register. For user-only, we could perform the bswap twice to restore the original value @@ -2077,8 +2058,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); datalo = scratch; } - tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, + datalo, base, index, 0, ofs); break; case MO_16: if (bswap) { @@ -2086,7 +2067,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_rolw_8(s, scratch); datalo = scratch; } - tcg_out_modrm_offset(s, movop + P_DATA16 + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, + base, index, 0, ofs); break; case MO_32: if (bswap) { @@ -2094,7 +2076,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_bswap32(s, scratch); datalo = scratch; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, ofs); break; case MO_64: if (TCG_TARGET_REG_BITS == 64) { @@ -2103,22 +2085,27 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, tcg_out_bswap64(s, scratch); datalo = scratch; } - tcg_out_modrm_offset(s, movop + P_REXW + seg, datalo, base, ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, + base, index, 0, ofs); } else if (bswap) { tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs); tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); tcg_out_bswap32(s, scratch); - tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs+4); + tcg_out_modrm_sib_offset(s, OPC_MOVL_EvGv + seg, scratch, + base, index, 0, ofs + 4); } else { if (real_bswap) { int t = datalo; datalo = datahi; datahi = t; } - tcg_out_modrm_offset(s, movop + seg, datalo, base, ofs); - tcg_out_modrm_offset(s, movop + seg, datahi, base, ofs+4); + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); } break; default: @@ -2151,7 +2138,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_write)); /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); /* Record the current context of a store into ldst label */ add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, @@ -2159,35 +2146,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) #else { int32_t offset = guest_base; - TCGReg base = addrlo; + int index = -1; int seg = 0; - /* See comment in tcg_out_qemu_ld re zero-extension of addrlo. */ + /* + * Recall we store 32-bit values zero-extended. No need for + * further manual extension or an addr32 (0x67) prefix. + */ if (guest_base == 0 || guest_base_flags) { seg = guest_base_flags; offset = 0; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - seg |= P_ADDR32; - } - } else if (TCG_TARGET_REG_BITS == 64) { - /* ??? Note that we can't use the same SIB addressing scheme - as for loads, since we require L0 free for bswap. */ - if (offset != guest_base) { - if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L0, base); - base = TCG_REG_L0; - } - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base); - base = TCG_REG_L1; - offset = 0; - } else if (TARGET_LONG_BITS == 32) { - tcg_out_ext32u(s, TCG_REG_L1, base); - base = TCG_REG_L1; - } + } else if (TCG_TARGET_REG_BITS == 64 && offset != guest_base) { + /* ??? Note that we require L0 free for bswap. */ + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); + index = TCG_REG_L1; + offset = 0; } - tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, + addrlo, index, offset, seg, opc); } #endif } From patchwork Mon Dec 3 16:08:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 152713 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7053110ljp; Mon, 3 Dec 2018 09:10:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/UXGqDLpWLTIIuT/Vw5Co9Y5JTypz1VDO3WXOgHQYutKGhrsH9Ca1JIkqocFkalbaCdpvsM X-Received: by 2002:ac8:2881:: with SMTP id i1mr16775353qti.382.1543857041510; Mon, 03 Dec 2018 09:10:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543857041; cv=none; d=google.com; s=arc-20160816; b=I+6K0OzD8kMdw0WESGH2eEUuRgZFbm9rCTiKzub3YSQ1O6bQHYYwSlqNlPqL5FRCj9 275D7YVu9FPlZczkTfIMSQy/7v2lTb9AMNbA1JyAqQ7zAfrhXvI67dfxzKuV41ORifWd LXZKj4QxIl8uTgECvYgllEhk06e7p1kwdXjHMVyHOg7aUeen/SetdR0iwo6+a1PpP2aw EGTPxz+WIYco5+rDQB5qMWZueG1BcDiwBIBquqKHBLNntK7EE1b6xkqW72SAHzNLScWA IvWdRK1X4vIila0bACBKpO99Y7rrqF4unxqhfryC5vgqa+6UjC4ESs23jdNAiJqQb4LW 1GZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=a2J3CQI2OQ70TK1sm7OIeOp1575wsiXhLstcSeE4Wk8=; b=xHR3YctTTfJ8u8leWGNVZOI/94KwCNd/a/CO9LVduFw5gKJyWqvbsGjgldsFjq9Wkf LSFbgd+58t+sSoXLmd67/31v5FNpDeJKfywF5Sb3h2yJIRvfVig+a3a/ueJ/aCgDaIPh KRhd3m1P005ZIgJtZnpnuVhcjkgfxbBgHj1asOltpC7upV8ccpnvwgm9v/d/dMipxYZR pxZl+jVqbkXtxli4LMQOlzqB0fo6/1afoZFL5DuiDkxAppuRig8UrXtdIokICQPJHtk3 GeHj4OovVfWE41GgftVFgLf9xIONSpmsjLAGsO7FxT2ouXXQJBdet6C6gh1vkYe/YJAZ NKqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="RRRN/YhD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:39 -0600 Message-Id: <20181203160840.15115-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH for-4.0 4/5] tcg/i386: Precompute all guest_base parameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These values are constant between all qemu_ld/st invocations; there is no need to figure this out each time. If we cannot use a segment or an offset directly for guest_base, load the value into a register in the prologue. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 101 +++++++++++++++----------------------- 1 file changed, 40 insertions(+), 61 deletions(-) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 853c3c8465..b8d2dd5ba3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1854,22 +1854,31 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_push(s, retaddr); tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); } -#elif defined(__x86_64__) && defined(__linux__) -# include -# include - +#elif TCG_TARGET_REG_BITS == 32 +# define x86_guest_base_seg 0 +# define x86_guest_base_index -1 +# define x86_guest_base_offset guest_base +#else +static int x86_guest_base_seg; +static int x86_guest_base_index = -1; +static int32_t x86_guest_base_offset; +# if defined(__x86_64__) && defined(__linux__) +# include +# include int arch_prctl(int code, unsigned long addr); - -static int guest_base_flags; -static inline void setup_guest_base_seg(void) +static inline int setup_guest_base_seg(void) { if (arch_prctl(ARCH_SET_GS, guest_base) == 0) { - guest_base_flags = P_GS; + return P_GS; } + return 0; } -#else -# define guest_base_flags 0 -static inline void setup_guest_base_seg(void) { } +# else +static inline int setup_guest_base_seg(void) +{ + return 0; +} +# endif #endif /* SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2008,27 +2017,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset = guest_base; - int index = -1; - int seg = 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base == 0 || guest_base_flags) { - seg = guest_base_flags; - offset = 0; - } else if (TCG_TARGET_REG_BITS == 64 && offset != guest_base) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index = TCG_REG_L1; - offset = 0; - } - - tcg_out_qemu_ld_direct(s, datalo, datahi, - addrlo, index, offset, seg, is64, opc); - } + tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, + is64, opc); #endif } @@ -2144,28 +2135,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); #else - { - int32_t offset = guest_base; - int index = -1; - int seg = 0; - - /* - * Recall we store 32-bit values zero-extended. No need for - * further manual extension or an addr32 (0x67) prefix. - */ - if (guest_base == 0 || guest_base_flags) { - seg = guest_base_flags; - offset = 0; - } else if (TCG_TARGET_REG_BITS == 64 && offset != guest_base) { - /* ??? Note that we require L0 free for bswap. */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, guest_base); - index = TCG_REG_L1; - offset = 0; - } - - tcg_out_qemu_st_direct(s, datalo, datahi, - addrlo, index, offset, seg, opc); - } + tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, + x86_guest_base_offset, x86_guest_base_seg, opc); #endif } @@ -3412,6 +3383,21 @@ static void tcg_target_qemu_prologue(TCGContext *s) (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else +# ifndef CONFIG_SOFTMMU + if (guest_base) { + int seg = setup_guest_base_seg(); + if (seg != 0) { + x86_guest_base_seg = seg; + } else if (guest_base == (int32_t)guest_base) { + x86_guest_base_offset = guest_base; + } else { + /* Choose R12 because, as a base, it requires a SIB byte. */ + x86_guest_base_index = TCG_REG_R12; + tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + } + } +# endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ @@ -3437,13 +3423,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_pop(s, tcg_target_callee_save_regs[i]); } tcg_out_opc(s, OPC_RET, 0, 0, 0); - -#if !defined(CONFIG_SOFTMMU) - /* Try to set up a segment register to point to guest_base. */ - if (guest_base) { - setup_guest_base_seg(); - } -#endif } static void tcg_out_nop_fill(tcg_insn_unit *p, int count) From patchwork Mon Dec 3 16:08:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 152710 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp7033831ljp; Mon, 3 Dec 2018 08:54:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/U0uXszhZGOTpr/BgE8jzA2cqaJlrts3TwyOSSlIIGEXS7mRhqoEL3pv3NyRh2PvtySqMzT X-Received: by 2002:a37:1bd3:: with SMTP id m80mr15047413qkh.259.1543856066233; Mon, 03 Dec 2018 08:54:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543856066; cv=none; d=google.com; s=arc-20160816; b=q4SJWgxe5XPSePrcFPnLSKh/gnQg1pDi1soVIQISYYKi34T5A0UDMIs91cehDISdge GwGMuMabKn+uHg6MCNQnKu9anzNKNuU1wrYlEmn34sU0CMjQfSXdfDhWGth5kmK/SStB hffTLdCrhcE2V+1UcaLqigk7t0XaBeb4AofrtVyPUJzg/4y5x9NhRnwNHX8zNXUMwJpF Y0BRCtrMbe75B/HLrL2Rbx9d32/OhVBn+6JrW5DMjfvo6CUEr8JjQUiDyUo7knIB5Wz3 GVdzWlmJr2ShyScOVeevbMz2Kti1zEAboxP9B5OHcwv3sHfWlmb/3KOV1N6c0jLMWj5U Vlyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=F6DluLGLSO9afKjowSYnD+gDl6Isk/WNzD0i4/fr9zg=; b=em07M93e2X5VgFOW2qpi0GUZETXH3CtTd9LBB/QqfMWuldkFsd3tjRGjBxCw37LEoL /W/SFrhc09HAfPbVhqE+my2zq9+EpW1QdHTjZ+UFhbzUdfsEiNqvDnCIvECw2j8hlIzB 3E/o98y3+s6oWY67U1MKG1z0jeQabHBsP1IZnzeyV2MOo/mevmfcDE6WzoO5X8++UV7F IB+VByI8l+c2q6a/RrGeNGNaqWgLuQrVFyJ5g6jKcjf14FYRsf3nBoSqHPPdXGXyapsD dM3Ig/bx2bilkRymoiED8mq1fV8tvs9jbqwxhDqGCmjpqltdqOHA3PLsFEYsaanSZcZs r1wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dHOypX6v; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id c19sm6338165otl.16.2018.12.03.08.08.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 08:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 10:08:40 -0600 Message-Id: <20181203160840.15115-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203160840.15115-1-richard.henderson@linaro.org> References: <20181203160840.15115-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH for-4.0 5/5] tcg/i386: Add setup_guest_base_seg for FreeBSD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.2 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index b8d2dd5ba3..3a39b51685 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1873,6 +1873,15 @@ static inline int setup_guest_base_seg(void) } return 0; } +# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) +# include +static inline int setup_guest_base_seg(void) +{ + if (sysarch(AMD64_SET_GSBASE, &guest_base) == 0) { + return P_GS; + } + return 0; +} # else static inline int setup_guest_base_seg(void) {