From patchwork Wed Mar 2 22:07:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 547752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A26DC4332F for ; Wed, 2 Mar 2022 22:09:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243711AbiCBWK1 (ORCPT ); Wed, 2 Mar 2022 17:10:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239783AbiCBWKY (ORCPT ); Wed, 2 Mar 2022 17:10:24 -0500 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2082.outbound.protection.outlook.com [40.107.244.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2427AC9A1E; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 22:09:20.2499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b88c5a6b-ed1e-45de-7831-08d9fc994d18 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3524 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Switches might not have a uid set if the DROM read failed during initialization previously. Normally upon resume the uid is re-read to confirm it's the same device connected. * If the DROM read failed during init but then succeeded during resume it could either be a new device or faulty device * If the DROM read failed during init and also failed during resume it might be a different device plugged in all together. Detect this situation and prevent re-using the same configuration in these cirucmstances. Signed-off-by: Mario Limonciello --- drivers/thunderbolt/switch.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index b5fb3e76ed09..294518af4ee4 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -2980,6 +2980,10 @@ int tb_switch_resume(struct tb_switch *sw) return err; } + /* We don't have any way to confirm this was the same device */ + if (!sw->uid) + return -ENODEV; + if (tb_switch_is_usb4(sw)) err = usb4_switch_read_uid(sw, &uid); else From patchwork Wed Mar 2 22:07:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 547751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE8DBC4332F for ; Wed, 2 Mar 2022 22:09:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245341AbiCBWK3 (ORCPT ); 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Wed, 2 Mar 2022 16:09:20 -0600 From: Mario Limonciello To: Mika Westerberg CC: "open list:THUNDERBOLT DRIVER" , , , Mario Limonciello Subject: [PATCH 5/5] drivers/thunderbolt: Rename EEPROM handling bits to match USB4 spec Date: Wed, 2 Mar 2022 16:07:09 -0600 Message-ID: <20220302220709.3138846-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220302220709.3138846-1-mario.limonciello@amd.com> References: <20220302220709.3138846-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 41470ac5-a27c-4248-86ae-08d9fc994e93 X-MS-TrafficTypeDiagnostic: DM6PR12MB3947:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PYmb9m0mf8Jjh1GHdDDx6QW7UGDr2Kxx3rHB7GujOY9m3s8YEx0kIgatQS7hOeKiJk/91tOblrFuhiloM/+wH+6Z8AxpELidJplC/eb6tRwl+PKRPdo//EExsR/WB7g66g4mToizKOQE2FUyQDMR+SDOkWmm3emKmYM/xdGm42E8INp9l8MEK00q1TrnH64qEBzj1u0JwvypMIVxtwRBoH/xmpeEmuM3XaqXjzVA/mi5fAKN62dMoZ808UK23331/HQb4E42IcF/gFTCtie0bynaXV5KSTg+pGCOwNDkXv1pqd+1dhW2+RGfTcgCK8l6dX76xnmkYea5+1NJtNhhqnAwDgAdZe8wA+yzDRzXlUtoZkAJF/3QB2O6liIHE9ZnQldM8mnu5I9Bw1H+FUhD/3m3lweR0dgVtju80RsK1/knG56TJ8cjWUlyRNNgWZbxnApXT8ApDDkNIj+SDIWT4crNT1BCLBke+rGy49Azi3K4qBAcpNJ1zMRe1UFSGUgYY6eq1Xi1w5PGmmDXzNJBR3HU4Dhzt3BY689NnIK3K6lOOezgf9LdnYB0kQ+OXhKzcnfcYlIro6vQE7458+H74xuzJ+meVHhS9n0Jusan5bcEmoOwxvGuXM57iv614G0Qdp4oVkIT5N1WLsvZypXpL+MRxdXbsroqMNtNvAjUBnH9LA3DZaqWyCfsOJvWpOnq8umakHre9Exvtm1no5LSzw6KS1u9B/w1ch9MtpzGlNCtYoJQ4AUzeYFLzHf1J4XKCF+8M9pdwb/DnVI/L6qCCsRlA9O/EFMl/i7cn/caAog= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(66574015)(47076005)(70206006)(4326008)(70586007)(316002)(2906002)(86362001)(36756003)(36860700001)(6916009)(54906003)(44832011)(82310400004)(8676002)(8936002)(356005)(81166007)(5660300002)(6666004)(1076003)(2616005)(508600001)(186003)(16526019)(26005)(966005)(336012)(426003)(40460700003)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 22:09:22.7497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41470ac5-a27c-4248-86ae-08d9fc994e93 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3947 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The structure `tb_eeprom_ctl` is used to show the bits accessed when reading/writing EEPROM. As this structure detail is specified in VSC_CS_4 on page 510 of the USB4 specification in table 13-14, update the names and use of members to match the specification. This should not change anything functionally. Link: https://www.usb.org/sites/default/files/USB4%20Specification%2020211116.zip Signed-off-by: Mario Limonciello --- drivers/thunderbolt/eeprom.c | 24 ++++++++++++------------ drivers/thunderbolt/tb_regs.h | 10 +++++----- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c index 10cdbcb55df9..c90d22f56d4e 100644 --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c @@ -17,7 +17,7 @@ */ static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) { - return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); + return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); } /* @@ -25,7 +25,7 @@ static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) */ static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) { - return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); + return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); } enum tb_eeprom_transfer { @@ -46,18 +46,18 @@ static int tb_eeprom_active(struct tb_switch *sw, bool enable) if (res) return res; if (enable) { - ctl.access_high = 1; + ctl.bit_banging_enable = 1; res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res; - ctl.access_low = 0; + ctl.fl_cs = 0; return tb_eeprom_ctl_write(sw, &ctl); } else { - ctl.access_low = 1; + ctl.fl_cs = 1; res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res; - ctl.access_high = 0; + ctl.bit_banging_enable = 0; return tb_eeprom_ctl_write(sw, &ctl); } } @@ -65,8 +65,8 @@ static int tb_eeprom_active(struct tb_switch *sw, bool enable) /* * tb_eeprom_transfer - transfer one bit * - * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in. - * If TB_EEPROM_OUT is passed, then ctl->data_out will be written. + * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do. + * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written. */ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, enum tb_eeprom_transfer direction) @@ -77,7 +77,7 @@ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, if (res) return res; } - ctl->clock = 1; + ctl->fl_sk = 1; res = tb_eeprom_ctl_write(sw, ctl); if (res) return res; @@ -86,7 +86,7 @@ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, if (res) return res; } - ctl->clock = 0; + ctl->fl_sk = 0; return tb_eeprom_ctl_write(sw, ctl); } @@ -101,7 +101,7 @@ static int tb_eeprom_out(struct tb_switch *sw, u8 val) if (res) return res; for (i = 0; i < 8; i++) { - ctl.data_out = val & 0x80; + ctl.fl_di = val & 0x80; res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT); if (res) return res; @@ -126,7 +126,7 @@ static int tb_eeprom_in(struct tb_switch *sw, u8 *val) res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN); if (res) return res; - *val |= ctl.data_in; + *val |= ctl.fl_do; } return 0; } diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index 8c42f8bc679e..872d8977d5e9 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -133,11 +133,11 @@ struct tb_cap_phy { } __packed; struct tb_eeprom_ctl { - bool clock:1; /* send pulse to transfer one bit */ - bool access_low:1; /* set to 0 before access */ - bool data_out:1; /* to eeprom */ - bool data_in:1; /* from eeprom */ - bool access_high:1; /* set to 1 before access */ + bool fl_sk:1; /* send pulse to transfer one bit */ + bool fl_cs:1; /* set to 0 before access */ + bool fl_di:1; /* to eeprom */ + bool fl_do:1; /* from eeprom */ + bool bit_banging_enable:1; /* set to 1 before access */ bool not_present:1; /* should be 0 */ bool unknown1:1; bool present:1; /* should be 1 */