From patchwork Wed Mar 16 23:41:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 552804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15F1CC4332F for ; Wed, 16 Mar 2022 23:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242323AbiCPXnF (ORCPT ); Wed, 16 Mar 2022 19:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351592AbiCPXnD (ORCPT ); Wed, 16 Mar 2022 19:43:03 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B62D01A833 for ; Wed, 16 Mar 2022 16:41:46 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 0F4DA2C0C1E; Wed, 16 Mar 2022 23:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647474104; bh=nVcp3cB00aWvtsu3vJBxU+P4/JWMysUbwbvfhFJcak4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tdGmLkb5X2uMoGAv163MveTWgjZ3PlY160oswvBI1jLqnmNnVurmmyQYrY7YfxXVE EyXA15/svaomRHT88e6H/lyEfsYkEYJMo8ZMrU62pR+DJBwkZJUlq+LNWigqzt6ugM hXEuPVVN7yUoBF2PnudJXiKdyD4LIb7C+XiyULm2kfTx1WJnySrhrMuW/ImyveoKi+ 99OPKSKzB9CEFnsltn/ayyvfpQ0WQz2Qp4SmgZxYfoLXWWvwQEWKV13szez/wZLMZG 8d1muaJYjUMv1m4MXXwXO2NTQWFfZ6Kvt6DG6pZ8erWwyLYcQd3Kzqwh97M9ce2E0t 5UxcsAo8lTV6A== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Thu, 17 Mar 2022 12:41:43 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id BB0EF13EE3F; Thu, 17 Mar 2022 12:41:43 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 46EE62A004D; Thu, 17 Mar 2022 12:41:41 +1300 (NZDT) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH 1/2] dt-bindings: hwmon: Document adt7475 pin-function properties Date: Thu, 17 Mar 2022 12:41:33 +1300 Message-Id: <20220316234134.290492-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316234134.290492-1-chris.packham@alliedtelesis.co.nz> References: <20220316234134.290492-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=XrEdriJqPTbsqx2b3kgA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The adt7473, adt7475, adt7476 and adt7490 have pins that can be used for different functions. Add bindings so that it is possible to describe what pin functions are intended by the hardware design. Signed-off-by: Chris Packham --- .../devicetree/bindings/hwmon/adt7475.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/adt7475.yaml b/Documentation/devicetree/bindings/hwmon/adt7475.yaml index 7d9c083632b9..22beb37f1bf1 100644 --- a/Documentation/devicetree/bindings/hwmon/adt7475.yaml +++ b/Documentation/devicetree/bindings/hwmon/adt7475.yaml @@ -61,6 +61,26 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] + "adi,pin(5|10)-function": + description: | + Configures the function for pin 5 on the adi,adt7473 and adi,adt7475. Or + pin 10 on the adi,adt7476 and adi,adt7490. + $ref: /schemas/types.yaml#/definitions/string + enum: + - pwm2 + - smbalert# + + "adi,pin(9|14)-function": + description: | + Configures the function for pin 9 on the adi,adt7473 and adi,adt7475. Or + pin 14 on the adi,adt7476 and adi,adt7490 + $ref: /schemas/types.yaml#/definitions/string + enum: + - tach4 + - therm# + - smbalert# + - gpio + required: - compatible - reg @@ -79,6 +99,8 @@ examples: adi,bypass-attenuator-in0 = <1>; adi,bypass-attenuator-in1 = <0>; adi,pwm-active-state = <1 0 1>; + adi,pin10-function = "smbalert#"; + adi,pin14-function = "tach4"; }; }; From patchwork Wed Mar 16 23:41:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 551939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF8A2C43219 for ; Wed, 16 Mar 2022 23:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343972AbiCPXnF (ORCPT ); Wed, 16 Mar 2022 19:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351867AbiCPXnD (ORCPT ); Wed, 16 Mar 2022 19:43:03 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B654B1A837 for ; Wed, 16 Mar 2022 16:41:46 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 060842C0A90; Wed, 16 Mar 2022 23:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1647474104; bh=DPntaLupexbSQuqCHUpqy2bxzZx7cg0xC2Rn5t8ogeI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xgWa+h/9AdxzYDO9JbrJWh8pbvVonG+yUGEBtv0g+ef8oTr6jJgEjRk4WW/carfCa Tb0KCgyBamMiaZvAXv1H0fls5RKjxuSF8kq90p6z+0PRQuJwbP+Q0eVrwDAn+XVrc2 xFzxyZ0q5jpeXFnEksUAWChNp/7QrOpGmZ0AWs0HV8yxlh27kSGDZStKbQ+LO8mA+0 8Xyl8uUMXE9HVRJ527Hc0U3mE3UQsrE+BBSJmhubi6Hrx7UmdXb96Bu83Dfa/3UJ7f ZFkL71sM/yn/J5ORlohp3iioVY6I2/brIgJwm9ADSVoJUnQE4xnmtfwRLbUtOZwMls iOUS9Jcg4zNpQ== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Thu, 17 Mar 2022 12:41:43 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id BC07F13EE43; Thu, 17 Mar 2022 12:41:43 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 4AB8E2A267B; Thu, 17 Mar 2022 12:41:41 +1300 (NZDT) From: Chris Packham To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH 2/2] hwmon: (adt7475) Add support for pin configuration Date: Thu, 17 Mar 2022 12:41:34 +1300 Message-Id: <20220316234134.290492-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316234134.290492-1-chris.packham@alliedtelesis.co.nz> References: <20220316234134.290492-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=Cfh2G4jl c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=o8Y5sQTvuykA:10 a=3Y0ZRzig23Q1LHC3s8QA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The adt7473, adt7475, adt7476 and adt7490 have pins that can be used for different functions. On the adt7473 and adt7475 this is pins 5 and 9. On the adt7476 and adt7490 this is pins 10 and 14. The first pin can either be PWM2(default) or SMBALERT#. The second pin can be TACH4(default), THERM#, SMBALERT# or GPIO. The adt7475 driver has always been able to detect the configuration if it had been done by an earlier boot stage. Add support for configuring the pins based on the hardware description in the device tree. Signed-off-by: Chris Packham --- drivers/hwmon/adt7475.c | 95 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 9d5b019651f2..ad5e5a7a844b 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -112,6 +112,8 @@ #define CONFIG3_THERM 0x02 #define CONFIG4_PINFUNC 0x03 +#define CONFIG4_THERM 0x01 +#define CONFIG4_SMBALERT 0x02 #define CONFIG4_MAXDUTY 0x08 #define CONFIG4_ATTN_IN10 0x30 #define CONFIG4_ATTN_IN43 0xC0 @@ -1460,6 +1462,95 @@ static int adt7475_update_limits(struct i2c_client *client) return 0; } +static int load_pin10_config(const struct i2c_client *client, const char *propname) +{ + const char *function; + u8 config3; + int err; + + err = of_property_read_string(client->dev.of_node, propname, &function); + if (!err) { + config3 = adt7475_read(REG_CONFIG3); + + if (!strcmp("pwm2", function)) + config3 &= ~CONFIG3_SMBALERT; + else if (!strcmp("smbalert#", function)) + config3 |= CONFIG3_SMBALERT; + else + return -EINVAL; + + return i2c_smbus_write_byte_data(client, REG_CONFIG3, config3); + } + + return 0; +} + +static int load_pin14_config(const struct i2c_client *client, const char *propname) +{ + const char *function; + u8 config4; + int err; + + err = of_property_read_string(client->dev.of_node, propname, &function); + if (!err) { + config4 = adt7475_read(REG_CONFIG4); + config4 &= ~CONFIG4_PINFUNC; + + if (!strcmp("tach4", function)) + ; + else if (!strcmp("therm#", function)) + config4 |= CONFIG4_THERM; + else if (!strcmp("smbalert#", function)) + config4 |= CONFIG4_SMBALERT; + else if (!strcmp("gpio", function)) + config4 |= CONFIG4_PINFUNC; + else + return -EINVAL; + + return i2c_smbus_write_byte_data(client, REG_CONFIG4, config4); + } + + return 0; +} + +static int load_config(const struct i2c_client *client, int chip) +{ + int err; + const char *conf_prop1, *conf_prop2; + + switch (chip) { + case adt7473: + case adt7475: + conf_prop1 = "adi,pin5-function"; + conf_prop2 = "adi,pin9-function"; + break; + case adt7476: + case adt7490: + conf_prop1 = "adi,pin10-function"; + conf_prop2 = "adi,pin14-function"; + break; + default: + return -EINVAL; + } + + if (chip != adt7476 && chip != adt7490) + return 0; + + err = load_pin10_config(client, conf_prop1); + if (err) { + dev_err(&client->dev, "failed to configure PIN10\n"); + return err; + } + + err = load_pin14_config(client, conf_prop2); + if (err) { + dev_err(&client->dev, "failed to configure PIN14\n"); + return err; + } + + return 0; +} + static int set_property_bit(const struct i2c_client *client, char *property, u8 *config, u8 bit_index) { @@ -1585,6 +1676,10 @@ static int adt7475_probe(struct i2c_client *client) revision = adt7475_read(REG_DEVID2) & 0x07; } + ret = load_config(client, chip); + if (ret) + return ret; + config3 = adt7475_read(REG_CONFIG3); /* Pin PWM2 may alternatively be used for ALERT output */ if (!(config3 & CONFIG3_SMBALERT))