From patchwork Sat Mar 19 20:46:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F140C4321E for ; Sat, 19 Mar 2022 20:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244185AbiCSUsU (ORCPT ); Sat, 19 Mar 2022 16:48:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244176AbiCSUsT (ORCPT ); Sat, 19 Mar 2022 16:48:19 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 997E9264828; Sat, 19 Mar 2022 13:46:57 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A254E2223E; Sat, 19 Mar 2022 21:46:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zxa+5cyhBT+v7MQr5Kc7DgMng+Ktl8wb4jNAKcCd1XA=; b=f03elNsWnDbCoB5YagG7aupXK9jwbTRLOmLTR4dea7DimkHro3/lBe+Io5X9/NSNGdQSPe IpNepJZ7bXc8TCnWz/fAxCBIMuTjsqAxLNl18AIgqw2zKezWy069lzqi5eFQkOcieDCpWC ikfpXkOBTNALXMMjh2p08zX2B1pLoVA= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 1/6] MIPS: mscc: jaguar2: rename pinctrl nodes Date: Sat, 19 Mar 2022 21:46:23 +0100 Message-Id: <20220319204628.1759635-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle --- arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +++++----- arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +++++----- arch/mips/boot/dts/mscc/jaguar2_pcb118.dts | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts index d80cd6842b2a..0ea7bc5b5746 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts @@ -180,27 +180,27 @@ synce_builtin_pins: synce-builtin-pins { pins = "GPIO_49"; function = "si"; }; - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts index 813c5e16013c..05d8c6a96dc4 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts @@ -79,27 +79,27 @@ cpld_fifo_pins: synce-builtin-pins { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_18"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts index 27c644f2d17f..cf2cf591a211 100644 --- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts +++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts @@ -39,17 +39,17 @@ i2c151: i2c@1 { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_17", "GPIO_16"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; From patchwork Sat Mar 19 20:46:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E551C433F5 for ; Sat, 19 Mar 2022 20:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244189AbiCSUsV (ORCPT ); Sat, 19 Mar 2022 16:48:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244187AbiCSUsU (ORCPT ); Sat, 19 Mar 2022 16:48:20 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2A5E25F659; Sat, 19 Mar 2022 13:46:58 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 3A2B1223F0; Sat, 19 Mar 2022 21:46:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722816; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AKolvVJkdV9GMASWo5gbLFGE9fn7Q2dVVjR7W2uh8EY=; b=dsMgvpPMMTA9HA2/BjxLUzONeG+rQU3Feyrv2J8zPtFH0m0hzPQHfMXax7pkEQW9nfJZJi eOcNGbRHR+6r0fPXc5Va0jWkJQtti3YXIczHuWg86Uk7ErakpWyyBK6r4s9GNLd1EP+AA5 17LJLqOYz77kFUZAjzZbZ5N4ASZBAPA= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 2/6] MIPS: mscc: ocelot: rename pinctrl nodes Date: Sat, 19 Mar 2022 21:46:24 +0100 Message-Id: <20220319204628.1759635-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle --- arch/mips/boot/dts/mscc/ocelot.dtsi | 4 ++-- arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index e51db651af13..cfc219a72bdd 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -225,7 +225,7 @@ uart2_pins: uart2-pins { function = "uart2"; }; - miim1: miim1 { + miim1_pins: miim1-pins { pins = "GPIO_14", "GPIO_15"; function = "miim"; }; @@ -261,7 +261,7 @@ mdio1: mdio@10700c0 { reg = <0x10700c0 0x24>; interrupts = <15>; pinctrl-names = "default"; - pinctrl-0 = <&miim1>; + pinctrl-0 = <&miim1_pins>; status = "disabled"; }; diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts index bd240690cb37..d348742c233d 100644 --- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts +++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts @@ -22,12 +22,12 @@ memory@0 { }; &gpio { - phy_int_pins: phy_int_pins { + phy_int_pins: phy-int-pins { pins = "GPIO_4"; function = "gpio"; }; - phy_load_save_pins: phy_load_save_pins { + phy_load_save_pins: phy-load-save-pins { pins = "GPIO_10"; function = "ptp2"; }; @@ -40,7 +40,7 @@ &mdio0 { &mdio1 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>; + pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>; phy7: ethernet-phy@0 { reg = <0>; From patchwork Sat Mar 19 20:46:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D59D6C433FE for ; Sat, 19 Mar 2022 20:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244223AbiCSUs0 (ORCPT ); Sat, 19 Mar 2022 16:48:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244198AbiCSUsX (ORCPT ); Sat, 19 Mar 2022 16:48:23 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11BFA25F659; Sat, 19 Mar 2022 13:47:00 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 0183A223F7; Sat, 19 Mar 2022 21:46:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZVsJ/nky1D7q5dVEHn2yK6pFAX9Hr6zPq4c1Y4piQNM=; b=IZVJgxuOwnY4TXVG44fb5ah7HtBmd5eOoULgTsVByFXlOADe4prNbKNKg5hPn81isXLaFJ TTe+tYvtLRcOcYJU1sJrleDJas/HEUSL3AqHxY2YO7hnzjRML2S2tlRj0Cj3hUxqxqbqX1 iZh1/8Mu0qccX6FUK5Ghs68dCijOdPY= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 3/6] MIPS: mscc: serval: rename pinctrl nodes Date: Sat, 19 Mar 2022 21:46:25 +0100 Message-Id: <20220319204628.1759635-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle --- arch/mips/boot/dts/mscc/serval_common.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi index 5b404836db5e..0893de420e27 100644 --- a/arch/mips/boot/dts/mscc/serval_common.dtsi +++ b/arch/mips/boot/dts/mscc/serval_common.dtsi @@ -82,38 +82,38 @@ i2c_pins: i2c-pins { pins = "GPIO_7"; /* No "default" scl for i2c0 */ function = "twi"; }; - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_11"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_12"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_21"; function = "twi_scl_m"; output-high; From patchwork Sat Mar 19 20:46:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0864C41535 for ; Sat, 19 Mar 2022 20:47:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244210AbiCSUsZ (ORCPT ); Sat, 19 Mar 2022 16:48:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244197AbiCSUsX (ORCPT ); Sat, 19 Mar 2022 16:48:23 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 460B5264828; Sat, 19 Mar 2022 13:47:00 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id E026922438; Sat, 19 Mar 2022 21:46:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ATuFVnlVSTv5vBpDhKHuTqAId/TAl0VhsC8BKMw2kS8=; b=AJJEGCDTP/6ty4hd/WxICeEmHHDMtFAy1HnFpqt9zhI6UAOAYvgMj8HHczNROBTaQoPWXg El+0sQbMvwN1WWjCmpWVW2IkVU8vgkU1S6ZhQ5F3QgHyrdPB4+65CMTJcOy9ecuwV6vqOU rn4cTf0d9lm/SrHCzQfzFM4OjykGjJo= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes Date: Sat, 19 Mar 2022 21:46:26 +0100 Message-Id: <20220319204628.1759635-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle --- .../dts/microchip/sparx5_pcb134_board.dtsi | 26 +++++++++---------- .../dts/microchip/sparx5_pcb135_board.dtsi | 10 +++---- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 33faf1f3264f..6f488e774215 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -325,69 +325,69 @@ &sgpio2 { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_22"; function = "twi_scl_m"; output-high; }; - i2cmux_6: i2cmux-6 { + i2cmux_6: i2cmux-6-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_7: i2cmux-7 { + i2cmux_7: i2cmux-7-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_8: i2cmux-8 { + i2cmux_8: i2cmux-8-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_9: i2cmux-9 { + i2cmux_9: i2cmux-9-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; }; - i2cmux_10: i2cmux-10 { + i2cmux_10: i2cmux-10-pins { pins = "GPIO_56"; function = "twi_scl_m"; output-high; }; - i2cmux_11: i2cmux-11 { + i2cmux_11: i2cmux-11-pins { pins = "GPIO_57"; function = "twi_scl_m"; output-high; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index ef96e6d8c6b3..d9e519bfbf68 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -59,28 +59,28 @@ led@7 { }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_35", "GPIO_36", "GPIO_50", "GPIO_51"; function = "twi_scl_m"; output-low; }; - i2cmux_s29: i2cmux-0 { + i2cmux_s29: i2cmux-0-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_s30: i2cmux-1 { + i2cmux_s30: i2cmux-1-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_s31: i2cmux-2 { + i2cmux_s31: i2cmux-2-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_s32: i2cmux-3 { + i2cmux_s32: i2cmux-3-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; From patchwork Sat Mar 19 20:46:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD3DC4332F for ; Sat, 19 Mar 2022 20:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244217AbiCSUsZ (ORCPT ); Sat, 19 Mar 2022 16:48:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244200AbiCSUsY (ORCPT ); Sat, 19 Mar 2022 16:48:24 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2563C26483A; Sat, 19 Mar 2022 13:47:01 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id EA0802244E; Sat, 19 Mar 2022 21:46:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722819; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gJKCVpoR4FBJ8+A4tQuZpuVlftctKas2Drjo6g8NXic=; b=EeRNtYEP5oBVmi0AEe9jRj1m/RJBWASF2cGcUEwzr7Q1nhZxAEnbuZ4OIKCqA3gc+EEeEg p0V3PdzkOEJu/VL940jftcupnZu28nDMyWZev7XcyzNeDDbdVxIS+4a2q1+qRSYyEVFKJm /DrxgSrhMYbPB4NmnGv1IcIohfiqEhc= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes Date: Sat, 19 Mar 2022 21:46:27 +0100 Message-Id: <20220319204628.1759635-6-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle Acked-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts index 3281af90ac6d..3c7e3a7d6f14 100644 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins { function = "fc3_b"; }; - can0_b_pins: can0_b_pins { + can0_b_pins: can0-b-pins { /* RX, TX */ pins = "GPIO_35", "GPIO_36"; function = "can0_b"; From patchwork Sat Mar 19 20:46:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56BEDC433EF for ; Sat, 19 Mar 2022 20:47:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244212AbiCSUsa (ORCPT ); Sat, 19 Mar 2022 16:48:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244205AbiCSUsY (ORCPT ); Sat, 19 Mar 2022 16:48:24 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F199C264F54; Sat, 19 Mar 2022 13:47:01 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 8D2E422450; Sat, 19 Mar 2022 21:46:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647722819; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xEf5Qdy2CZeKPC3PR1yIdltyKRL+/rUuvVCQ5taspNg=; b=EC8mOIwEdpG6mVzMc3/1mn5D5CdVRIZ1Ze3UZVxGWgMNVJK67buWy9yGT17eWNxZYKiS2l 7I5/7LwSjZXNmHhR2jGwqwiO3tBG4hL3BtovkBlHMELZnv5zS2OaCLz9XbrEfPMxSfS2FJ pdU8ajepRCBPPpwRpmSlrKC5yt5xUSo= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Thomas Bogendoerfer , Gregory CLEMENT , Paul Burton , Quentin Schulz , Antoine Tenart , Kavyasree Kotagiri , Nicolas Ferre Cc: "David S . Miller" , UNGLinuxDriver@microchip.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Michael Walle Subject: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format Date: Sat, 19 Mar 2022 21:46:28 +0100 Message-Id: <20220319204628.1759635-7-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220319204628.1759635-1-michael@walle.cc> References: <20220319204628.1759635-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert the ocelot-pinctrl device tree binding to the new YAML format. Additionally to the original binding documentation, add interrupt properties which are optional and already used on several SoCs like SparX-5, Luton, Ocelot and LAN966x but were not documented before. Also, on the sparx5 and the lan966x SoCs there are two items for the reg property. Signed-off-by: Michael Walle Reviewed-by: Krzysztof Kozlowski Acked-by: Linus Walleij --- .../bindings/pinctrl/mscc,ocelot-pinctrl.txt | 42 ------- .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++ 2 files changed, 108 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index 5d84fd299ccf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,42 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl", - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - . - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000000..7149a6655623 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller + +maintainers: + - Alexandre Belloni + - Lars Povlsen + +properties: + compatible: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + + reg: + items: + - description: Base address + - description: Extended pin configuration registers + minItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + + properties: + function: true + pins: true + output-high: true + output-low: true + drive-strength: true + + required: + - function + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +...