From patchwork Sat Mar 26 12:09:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 554458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE93DC4332F for ; Sat, 26 Mar 2022 12:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbiCZMLa (ORCPT ); Sat, 26 Mar 2022 08:11:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232776AbiCZML3 (ORCPT ); Sat, 26 Mar 2022 08:11:29 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEDA062A02; Sat, 26 Mar 2022 05:09:50 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id x34so11893257ede.8; Sat, 26 Mar 2022 05:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rkpQ2CvLx5/YOytL3DUt1U7LW03Ve0SSyCtKDL1HKQY=; b=cv/OXQ3kn0vZd+oalJeNtX7VyFKKTOQdKzR0MzowDFH69xIOlKBGmPW2QBt1H/awLB EfkUgZd/oiK1dD+SvmSCVlRvuPGdppO/QDzvov6XSX5FJ+IRDdS1qUXWRhD6T8XZjdKk 6nk4WYC5TIux739Y2eK1mrP8sdzSJm6UsaVasewRQ5EXUxCUUP0o1Bcwe+BVluvUhOq6 8BlGcxm0jF0GfC6wDwuxntMb+hdGR0EXizhlJqgmbL2oFcTJSpoDl1kEczjrzfmIuqi8 gSeWetQE8MRzsSit53Ow9rQ4PKfzDQIJJQL/8iSJemCBUX1XYnabzSKBDEJdDULFjKHS nkAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rkpQ2CvLx5/YOytL3DUt1U7LW03Ve0SSyCtKDL1HKQY=; b=YIYc8IfnSE0T6gOVKv5eY/lefSezzeIPK29SEGxdFxfoQ5DVvzDmbFdAGUNz4Sp/W9 AvJ0TrAKPqkU+X6eW/qDhIfkHqr4iYlmoSQDFnMcF80T8+Di6qOmxocH/WPVSSOMwIhC MgzTcUiZlIgVmKUY8Ne9OhHQlU2+GjxndNWAqgj9SdhGbb8P72odihLiR8QRIeVJ+Dl0 usWl2B3npaKlTB0PE2BQvuskc1Na+htRWXmIrzeuVdxwjbL4HIVRPxfxUfVFuNpp56ke 9HwICZh1GSVeJwfgsT+omB9iJpxBU+ClWQWxnXi6tnsVQErepuh7ByxSvdJmkZW3XmXo abew== X-Gm-Message-State: AOAM5305d3g5Uin+CqZEpmle00tbxErKzci1WD7PATnT6ulocvEphjqs qi+Y6qjr9VUowqOmfx8uz89btNGksws= X-Google-Smtp-Source: ABdhPJzTrzjvLOcgoh8sDDfmO2EFpSX8kVF9ThptSc0DTR0uV/5q6FdEiwo6Fc8Q/a0EnUykuXUzPQ== X-Received: by 2002:aa7:c056:0:b0:418:e8d7:52a3 with SMTP id k22-20020aa7c056000000b00418e8d752a3mr3983658edo.301.1648296589084; Sat, 26 Mar 2022 05:09:49 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id cr19-20020a170906d55300b006df6b316e29sm3559920ejc.208.2022.03.26.05.09.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Mar 2022 05:09:48 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: clock: convert rockchip, rk3288-cru.txt to YAML Date: Sat, 26 Mar 2022 13:09:41 +0100 Message-Id: <20220326120942.24008-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Current dts files with RK3288 'cru' nodes are manually verified. In order to automate this process rockchip,rk3288-cru.txt has to be converted to YAML. Changed: Add properties to fix notifications by clocks.yaml for example: clocks clock-names Signed-off-by: Johan Jonker Reviewed-by: Rob Herring --- .../bindings/clock/rockchip,rk3288-cru.txt | 67 --------------- .../bindings/clock/rockchip,rk3288-cru.yaml | 83 +++++++++++++++++++ 2 files changed, 83 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index bf3a9ec19..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -A revision of this SoC is available: rk3288w. The clock tree is a bit -different so another dt-compatible is available. Noticed that it is only -setting the difference but there is no automatic revision detection. This -should be performed by bootloaders. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in - case of this revision of Rockchip rk3288. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml new file mode 100644 index 000000000..e5f89a78e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3288 Clock and Reset Unit (CRU) + +maintainers: + - Heiko Stuebner + +description: | + The RK3288 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + + A revision of this SoC is available: rk3288w. The clock tree is a bit + different so another dt-compatible is available. Noticed that it is only + setting the difference but there is no automatic revision detection. This + should be performed by bootloaders. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_edp_24m" - external display port clock - optional, + - "ext_vip" - external VIP clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + +properties: + compatible: + enum: + - rockchip,rk3288-cru + - rockchip,rk3288w-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files", + if missing pll rates are not changeable, due to the missing pll lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Mar 26 12:09:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 554711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA1DC433EF for ; Sat, 26 Mar 2022 12:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232783AbiCZMLa (ORCPT ); Sat, 26 Mar 2022 08:11:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232032AbiCZML3 (ORCPT ); Sat, 26 Mar 2022 08:11:29 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B408B62A1E; Sat, 26 Mar 2022 05:09:51 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id c62so11906633edf.5; Sat, 26 Mar 2022 05:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M61AFRbLUdMV7oXCOaCCHm47RW/KqcD8CWFb8D1XXr8=; b=OjI0mWSkh8IF18F/TSsJ8MJss9uNPfHXlbT1L61y23JeWnLf2gAJCMA7VsFeGKVXx/ kouG/ev3S77WOrCw2HAnmKAVgFOWnawYlFbbIsH4DOmTtb50+DfTgxCNs3po2rx+gWCL tZv8w6uJOSkH+iq7F2o9zwUU00c1Ghw8ASeERc6XfqqLBxfWBYHpUDHuexfxotmoR8Mo jyXGT1jtq+wanQ6Aw7wikR//M+kyJ3cN07GVbAtUqAnAFaO02hIVEP4tYq60W3+SiAfh s/xMKKNwntvuqRLMwMf2f1jiRMw+2vOoVtehrD/XERWsagWg3w0bZhmMaYfnMcgHSxFM 36vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M61AFRbLUdMV7oXCOaCCHm47RW/KqcD8CWFb8D1XXr8=; b=0jV9nSyM52Cc7RkIutK8MauRw4bsgCvhCzLI6JlQ5Ncrar4lBFhKQZM4BsU75SFmBl /mNrbfQLEECj9kkmpW8cH7RKrt9gCiK+wU4FjNmp1dSDtJDIfSNtzP2hKcTr2y+rhIXa Z1XqQmWbYpmtHVCLK8KLpN+JKIrYpvhrlNd/PJyXlN7xBiy+EuNcSl/1MFh/+zQj6VJr g9W4R05dfZDcC8bEOs4ybqmgED6RIyL+zsZZRdiDXZHNBGmfUc9rM4SlLixVG/thW7Ni Beqwgd5OUt+dr/iltYMUyNwacbHBZP1lFPyxt3Y6Yb8vZ6bdcU/p24z0lXqsnMMROWOP TW2g== X-Gm-Message-State: AOAM531MI5yRiYmiHsZWzxh5gJLkw+EsDqFpu3KXIP+bMo5WYbgsLgBE UF995T26A/EokJ3sp0nemH0= X-Google-Smtp-Source: ABdhPJxZ7fNDA9cRLndFfVEfAHwP3Hdtn2XRwJWm9oe/0TWDoVGrU/0hP95piDM/ll+gLVzl/M5M+w== X-Received: by 2002:aa7:dbd6:0:b0:408:4a31:97a5 with SMTP id v22-20020aa7dbd6000000b004084a3197a5mr4159348edt.186.1648296589901; Sat, 26 Mar 2022 05:09:49 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id cr19-20020a170906d55300b006df6b316e29sm3559920ejc.208.2022.03.26.05.09.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Mar 2022 05:09:49 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] ARM: dts: rockchip: add clocks property to cru node rk3288 Date: Sat, 26 Mar 2022 13:09:42 +0100 Message-Id: <20220326120942.24008-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220326120942.24008-1-jbx6244@gmail.com> References: <20220326120942.24008-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add clocks property to rk3288 cru node to fix warnings like: 'clocks' is a dependency of 'assigned-clocks'. Signed-off-by: Johan Jonker --- arch/arm/boot/dts/rk3288.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 26b9bbe31..487b0e03d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -862,6 +862,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3288-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>;