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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id d77si13384929pfj.124.2018.12.11.07.02.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Dw8z57OO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BA5A92194D3AE; Tue, 11 Dec 2018 07:02:45 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::341; helo=mail-wm1-x341.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1CD302119926B for ; Tue, 11 Dec 2018 07:02:43 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id n190so2574851wmd.0 for ; Tue, 11 Dec 2018 07:02:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Z88tCHknS8aexAglNIO+B+I6EdkSp3Pd9aCug1Axak=; b=Dw8z57OOa/lqzDbumlENL/JRjxu5A+/3c+TFzqtus9JVnKYz5tDU7I0fOAvKtQsgi8 tjjrMTdLUp6U20EYoBb1kTnENmpbiy4XYf2OMAGfmIBe4sFuzunGQnOK51mQim0JfojB iq1ZwcZVCOgWayT2bpG5/0xiJsyUTnLHywkV8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Z88tCHknS8aexAglNIO+B+I6EdkSp3Pd9aCug1Axak=; b=IFo4jmBDTdpd5kPiP6CaQnuwWRY1DamlxgYv6wo64ABiLTQwFyG1ab1/QUUHvhHu0g Ks0QyegSlZd+h6gzUGN7d76/7hwZ8wSjZaosB8VZ+igUtWLFwd1MPrBwiwOu/0yrdAFU 9qvQUjC1Go9/npLKvHtvtzNQ4atylqlWK+sWxdjKvj9thOrf9yY2j++7rEZ/zRbj7F04 rYtHrSUQVn8R7LWYiFiPZIxrqNvxAnovyi3zCPwpssuZ7ky6AIIIm6MKDXwvdSwGi5Y2 FIdBRBQQ8L75BYGZO2x7Ny7IM2zQ7stO5w5KtmqoyPMFkufbiN3itK978DzzgJg4Oq9+ ynlw== X-Gm-Message-State: AA+aEWaM+q5CRDKE+GQ6UZpwNlg1HiEvTGv79+ozW+/k8oDZr8GI+79v XPNAWLy6+VX/kPUOGiOAEP0fvvhPivf3Pg== X-Received: by 2002:a1c:81ca:: with SMTP id c193mr2820744wmd.66.1544540562137; Tue, 11 Dec 2018 07:02:42 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:41 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:32 +0100 Message-Id: <20181211150237.32275-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 1/6] Platform/AMD/OverdriveBoard: fix byte order of default MAC addresses X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The PCDs containing the default MAC addresses are of type UINT64, and so the byte order needs to be inverted. As they are currently, both default MAC addresses are invalid since they have the multicast bit set. For readability, let's switch to a VOID* type PCD while at it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AmdStyx.dec | 4 ++-- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 4 ++-- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 9 ++++---- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 24 ++++++++++++-------- Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 8 +++---- 5 files changed, 26 insertions(+), 23 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index 902259dd7267..c2e691cb5ea4 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -42,8 +42,8 @@ gAmdStyxTokenSpaceGuid.PcdSocCoreCount|1|UINT32|0x00000100 gAmdStyxTokenSpaceGuid.PcdSocCpuId|1|UINT32|0x00000101 - gAmdStyxTokenSpaceGuid.PcdEthMacA|0|UINT64|0x000d0001 - gAmdStyxTokenSpaceGuid.PcdEthMacB|0|UINT64|0x000d0002 + gAmdStyxTokenSpaceGuid.PcdEthMacA|{0x0,0x0,0x0,0x0,0x0,0x0}|VOID*|0x000d0001 + gAmdStyxTokenSpaceGuid.PcdEthMacB|{0x0,0x0,0x0,0x0,0x0,0x0}|VOID*|0x000d0002 [PcdsFixedAtBuild] # CPUID Register diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index ce909982c39b..3b9d70de2751 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -468,8 +468,8 @@ DEFINE DO_CAPSULE = FALSE gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1 [PcdsDynamicDefault.common] - gAmdStyxTokenSpaceGuid.PcdEthMacA|0x02A1A2A3A4A5 - gAmdStyxTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5 + gAmdStyxTokenSpaceGuid.PcdEthMacA|{0x2,0xA1,0xA2,0xA3,0xA4,0xA5} + gAmdStyxTokenSpaceGuid.PcdEthMacB|{0x2,0xB1,0xB2,0xB3,0xB4,0xB5} [PcdsPatchableInModule] gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|TRUE diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index f1223ada2444..9c17c38a04bf 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -60,15 +60,14 @@ STATIC VOID SetPackageAddress ( UINT8 *Package, - UINT64 MacAddress, + UINT8 *MacAddress, UINTN Size ) { UINTN Index; for (Index = PACKAGE_MAC_OFFSET; Index < Size; Index += PACKAGE_MAC_INCR) { - Package[Index] = (UINT8)MacAddress; - MacAddress >>= 8; + Package[Index] = *MacAddress++; } } @@ -165,11 +164,11 @@ InstallSystemDescriptionTables ( // CopyMem (MacPackage, mDefaultMacPackageA, sizeof (MacPackage)); - SetPackageAddress (MacPackage, PcdGet64 (PcdEthMacA), sizeof (MacPackage)); + SetPackageAddress (MacPackage, PcdGetPtr (PcdEthMacA), sizeof (MacPackage)); PatchAmlPackage (mDefaultMacPackageA, MacPackage, sizeof (MacPackage), (UINT8 *)Table, TableSize); - SetPackageAddress (MacPackage, PcdGet64 (PcdEthMacB), sizeof (MacPackage)); + SetPackageAddress (MacPackage, PcdGetPtr (PcdEthMacB), sizeof (MacPackage)); PatchAmlPackage (mDefaultMacPackageB, MacPackage, sizeof (MacPackage), (UINT8 *)Table, TableSize); diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 4ea1dd4b3577..3cd650eee36b 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -123,7 +123,7 @@ PlatInitPeiEntryPoint ( ISCP_CPU_RESET_INFO CpuResetInfo = {0}; #if DO_XGBE == 1 ISCP_MAC_INFO MacAddrInfo = {0}; - UINT64 MacAddr0, MacAddr1; + UINTN MacSize; #endif UINTN CpuCoreCount, CpuMap, CpuMapSize; UINTN Index, CoreNum; @@ -223,16 +223,20 @@ PlatInitPeiEntryPoint ( PeiServices, &MacAddrInfo ); ASSERT_EFI_ERROR (Status); - MacAddr0 = MacAddr1 = 0; - for (Index = 0; Index < 6; ++Index) { - MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8); - MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8); - } - PcdSet64 (PcdEthMacA, MacAddr0); - PcdSet64 (PcdEthMacB, MacAddr1); + MacSize = sizeof(MacAddrInfo.MacAddress0); + Status = PcdSetPtrS (PcdEthMacA, &MacSize, MacAddrInfo.MacAddress0); + ASSERT_EFI_ERROR (Status); + Status = PcdSetPtrS (PcdEthMacB, &MacSize, MacAddrInfo.MacAddress1); + ASSERT_EFI_ERROR (Status); - DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA))); - DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB))); + DEBUG ((EFI_D_ERROR, "EthMacA = %02x:%02x:%02x:%02x:%02x:%02x\n", + ((UINT8 *)PcdGetPtr (PcdEthMacA))[0], ((UINT8 *)PcdGetPtr (PcdEthMacA))[1], + ((UINT8 *)PcdGetPtr (PcdEthMacA))[2], ((UINT8 *)PcdGetPtr (PcdEthMacA))[3], + ((UINT8 *)PcdGetPtr (PcdEthMacA))[4], ((UINT8 *)PcdGetPtr (PcdEthMacA))[5])); + DEBUG ((EFI_D_ERROR, "EthMacB = %02x:%02x:%02x:%02x:%02x:%02x\n", + ((UINT8 *)PcdGetPtr (PcdEthMacB))[0], ((UINT8 *)PcdGetPtr (PcdEthMacB))[1], + ((UINT8 *)PcdGetPtr (PcdEthMacB))[2], ((UINT8 *)PcdGetPtr (PcdEthMacB))[3], + ((UINT8 *)PcdGetPtr (PcdEthMacB))[4], ((UINT8 *)PcdGetPtr (PcdEthMacB))[5])); #endif // Let other PEI modules know we're done! diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index b9dfa2367ab2..4ca5d9bebed6 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -168,7 +168,7 @@ VOID SetMacAddress ( IN VOID *Fdt, IN CONST CHAR8 *Device, - IN UINT64 MacAddress + IN UINT8 *MacAddress ) { INT32 Node; @@ -179,7 +179,7 @@ SetMacAddress ( if (Node >= 0) { SubNode = fdt_subnode_offset (Fdt, Node, Device); if (SubNode >= 0) { - Rc = fdt_setprop (Fdt, SubNode, "mac-address", (VOID *)&MacAddress, + Rc = fdt_setprop (Fdt, SubNode, "mac-address", MacAddress, MAC_ADDRESS_BYTES); if (Rc) { DEBUG ((DEBUG_ERROR, @@ -289,8 +289,8 @@ SetXgbeStatus ( SetDeviceStatus (Fdt, "xgmac@e0900000", TRUE); SetDeviceStatus (Fdt, "phy@e1240c00", TRUE); - SetMacAddress (Fdt, "xgmac@e0700000", PcdGet64 (PcdEthMacA)); - SetMacAddress (Fdt, "xgmac@e0900000", PcdGet64 (PcdEthMacB)); + SetMacAddress (Fdt, "xgmac@e0700000", PcdGetPtr (PcdEthMacA)); + SetMacAddress (Fdt, "xgmac@e0900000", PcdGetPtr (PcdEthMacB)); #else SetDeviceStatus (Fdt, "xgmac@e0700000", FALSE); SetDeviceStatus (Fdt, "phy@e1240800", FALSE); From patchwork Tue Dec 11 15:02:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 153470 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp716330ljp; Tue, 11 Dec 2018 07:02:52 -0800 (PST) X-Google-Smtp-Source: AFSGD/Xol7B/4T89Y4q68KVFjS/unFZCEZuAL62Wkl9fDDKog2d27oYcU17E8iOeBvPEqAc3RniO X-Received: by 2002:a62:870e:: with SMTP id i14mr17055937pfe.41.1544540571878; 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[198.145.21.10]) by mx.google.com with ESMTPS id w24si12144722plp.304.2018.12.11.07.02.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YXrX0cWY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0142821199B3E; Tue, 11 Dec 2018 07:02:47 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3548021199539 for ; Tue, 11 Dec 2018 07:02:46 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id y1so2534798wmi.3 for ; Tue, 11 Dec 2018 07:02:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9q9xw+RZi0Rq4s3x7ACklVnt+F41m4B82wsORlKqTHY=; b=YXrX0cWYZ48TTOU+UYZuondzNdCMcaI816zwUtGdzaLxVqW6oSvT3yz1fKWXMSfmib Q/6pkurE2AOKniYWzXDGpOkmO8+iF1VcDycgg8x8cXzLFsGnsNwSSwb4ku1BS1w6tM4y Ocv/vgtNJYsXFo3P807OeeRoBhy8n2yl8Hvuc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9q9xw+RZi0Rq4s3x7ACklVnt+F41m4B82wsORlKqTHY=; b=encjZ3nX+cmkTT1ZyX/6VCGLczzmixB0wj1RuyrUrZYSkADdbr0EIuIs38hvF/q4cZ C2ru9kxklJOe/O1SJr79ey0vaQjAfo9pPz5XJYhOFt/33csFLEOgEZABxHk4GxUgXTn/ VHQOmnODY8RxHVVH4Cha7v83WlVspjdSW92weJWEwXSGbnN3tYlrw/Jy+JnTbkR5HNoC ds2p2B0Oa1JEYBfFiTQRmZn4ACWn8XYAGVWYrJrF/nNhbSWRfmF5oK6NzwVBm+mAr62Q bWTlmI5nm66njce/XyaT7oE29arynknFT/IGm+A/P+CwJY27/m7QIAvQEWEB8578B7e5 aX+A== X-Gm-Message-State: AA+aEWYBo4wbYizvMysyT1BFBZ07YFI8IBtMWImWaCiFWHiwAYwHHTE9 ru0J8QrGdF4CX8zUpIG9Jmlmz6wgobHlJw== X-Received: by 2002:a1c:8acd:: with SMTP id m196mr2716604wmd.120.1544540564297; Tue, 11 Dec 2018 07:02:44 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:42 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:33 +0100 Message-Id: <20181211150237.32275-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 2/6] Silicon/Styx: drop ARM_CPU_AARCH64 define X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The define ARM_CPU_AARCH64 is only tested once, in the SMBIOS driver, to decide whether to emit 'v8' or 'v7' as processor architecture. However, this platform has no 32-bit addressable DRAM, and so it cannot be built or executed in 32-bit mode anyway, making the test rather pointless. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 4 ++-- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 4 ++-- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 4 ++-- Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 4 ---- 4 files changed, 6 insertions(+), 10 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 3b9d70de2751..9172c82fdeba 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -268,8 +268,8 @@ DEFINE DO_CAPSULE = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 29e740695366..f556591b9e25 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -260,8 +260,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index f342cf82d251..5abf1d52f916 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -258,8 +258,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) -DARM_CPU_AARCH64 + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index bcb6e020a5fd..8fe806c18ac3 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -309,11 +309,7 @@ STATIC SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { STATIC CHAR8 CONST * CONST mProcessorInfoType4Strings[] = { "Socket", "ARM", -#ifdef ARM_CPU_AARCH64 "v8", -#else - "v7", -#endif "1.0", "1.0", "1.0", From patchwork Tue Dec 11 15:02:34 2018 Content-Type: text/plain; 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w17si11411760pgl.6.2018.12.11.07.02.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gGEEVUtJ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2DD832119955F; Tue, 11 Dec 2018 07:02:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3469121199539 for ; Tue, 11 Dec 2018 07:02:48 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id a62so2553960wmh.4 for ; Tue, 11 Dec 2018 07:02:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z6kr7v+j7MK4EvibR24pT6/uaEiR9kc0U6Zb6kPUkb0=; b=gGEEVUtJwXmIfEC5+1vKxr/glw5FXJCX61d/+DImcALsd7fhD7Axim3Z9qT+kVmjKL jiaPVGSJikiaJqwXMJxLHyb6xw5lh5qT7jD+gMhEm9o9nLTKhywxZwTXoQVeB9AWwJKZ 5sZ4yYE/mcq6byyjQE4zUnCPgTNbn7cTtah+M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z6kr7v+j7MK4EvibR24pT6/uaEiR9kc0U6Zb6kPUkb0=; b=ENGaMxTks5BviDpSKQ3eg5kYDuHaCXoz8y6EG/JVGbVEAq9XGJNkJdvqf1wbeIJsYy 3XmeNhEAPCM6uSMFYFTa40RiPUrgWH9Hz72/kfZteiyTRFA0yZg3GA+IoALs6z4S4ubK FZGnm4L6ZxDX1St1QRoed0yNel0eReIX3M0R4smVcoruieVqAckL2CLLcURzFmTYs3I4 CTNNrT5G194q00QJs5iFv46qbcDsPKnIzQEsCMpM6SdXZ9HBGQTL/LBuh2kyiMkMd2kO Mt9241lC8VtaR9Z6+qHt6JUKglLqtVAMjHU09UHc0hft5O+xoKGeAJKHi6FDRAh6nx44 ULDQ== X-Gm-Message-State: AA+aEWYhd2TiVp522CO3tC87V5Pkp7BYdxYmJ8wxMd48hq1NGj7uh+az 0IcFJ3iTN+dprpNhTA+6ISMKNCKptyGdlA== X-Received: by 2002:a1c:6a16:: with SMTP id f22mr1947905wmc.25.1544540565791; Tue, 11 Dec 2018 07:02:45 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:44 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:34 +0100 Message-Id: <20181211150237.32275-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 3/6] Silicon/Styx: get rid of NUM_CORES preprocessor define on command line X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of relying on the compiler command line to pass the value of NUM_CORES as a preprocessor define, use the value of the PcdCoreCount PCD that we already set in the platform .DSC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 4 ++-- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 4 ++-- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 4 ++-- Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 ++ Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf | 2 ++ Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 2 ++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl | 2 ++ Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc | 2 ++ 8 files changed, 16 insertions(+), 6 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 9172c82fdeba..696090cfb2dd 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -268,8 +268,8 @@ DEFINE DO_CAPSULE = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_XGBE=$(DO_XGBE) -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index f556591b9e25..5056122aa681 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -260,8 +260,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 5abf1d52f916..8187e799a6fc 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -258,8 +258,8 @@ DEFINE DO_FLASHER = FALSE *_*_*_ASLPP_FLAGS = $(ARCHCC_FLAGS) *_*_*_ASLCC_FLAGS = $(ARCHCC_FLAGS) - GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) - GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) -DNUM_CORES=$(NUM_CORES) + GCC:*_*_AARCH64_ARCHCC_FLAGS = -DDO_KCS=$(DO_KCS) + GCC:*_*_AARCH64_PP_FLAGS = -DDO_KCS=$(DO_KCS) [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf index 2a42d76d4883..be885d6aea90 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -42,6 +42,7 @@ SsdtXgbe.asl [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -84,6 +85,7 @@ gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf index 3f36799f5df1..87cdcb3e6b25 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.inf @@ -24,6 +24,7 @@ StyxDtbLoaderLib.c [Packages] + ArmPlatformPkg/ArmPlatformPkg.dec ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec @@ -49,6 +50,7 @@ gArmTokenSpaceGuid.PcdSystemMemoryBase [FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment gAmdStyxTokenSpaceGuid.PcdSata1PortCount diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index 4ca5d9bebed6..b1e4984d3fd0 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -33,6 +33,8 @@ #define PMU_INT_FLAG_SPI 0 #define PMU_INT_TYPE_HIGH_LEVEL 4 +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + // // PMU interrupts per core // diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl index c1417e7e1cd7..60288114aeab 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Dsdt.asl @@ -21,6 +21,8 @@ **/ +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + DefinitionBlock ("DSDT.aml", "DSDT", 2, "AMDINC", "SEATTLE ", 3) { Scope (_SB) diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc index 64a6cda7fd87..031307fa3c36 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/Pptt.aslc @@ -18,6 +18,8 @@ #define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) +#define NUM_CORES FixedPcdGet32 (PcdCoreCount) + #pragma pack(1) typedef struct { EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR 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[198.145.21.10]) by mx.google.com with ESMTPS id a2si11750761pgm.154.2018.12.11.07.03.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:03:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=i8IGHGDs; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5F39E2119A455; Tue, 11 Dec 2018 07:02:50 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::343; helo=mail-wm1-x343.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4B9522119A455 for ; Tue, 11 Dec 2018 07:02:49 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id m22so2612089wml.3 for ; Tue, 11 Dec 2018 07:02:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nhIkD7RppHSowIcSk8rGbd96/rDHdAtG/WRUJHZFgCs=; b=i8IGHGDsDMAdGX7aKKAMl0VqXleR4h/MbECd/OjWTFIdPgECMIUsUg3fkfxMsgmzHl LB6vny17wcpTXIa3OszX+pIx7FjI2C7SkaUr22C4zmBD448enSoa3i/vCJxV47525D0k MP1LCQlkc0c1DI5bYmkedCRRi5+YEcwO3vCic= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nhIkD7RppHSowIcSk8rGbd96/rDHdAtG/WRUJHZFgCs=; b=hh9I9Z8gnDUFg/H/fqz3JCWwneLHrCrY8a7HjpVNklUhHW84iEsOyNSoyDJ5pZs0rP 5LMaOyiFZxf4TTun2lfjKVqJbTfOtDg5WoR+vgawyYzTAlFiyQoyye97PFzIlQr61zzr /ETAB/5dyxNrLOfoUPt1U92Q2Z/c69/sC0QvVeZu7X9hFD4Np0lTw5u7LTxGa52pkx6w Y5Tusn5W/S9JJbvzu1MZfMmbwKNCxwRJ6KRcOcwcPbVAQ7H8iNdVoRfKtLvKVd2fBdYq 4WIY2XGWUadm/xHCbxoma7r1ZpStF+pTgNrJ2Hg3egfWW7Z61bhJU8p6DZzbSl9CMuq8 UPJg== X-Gm-Message-State: AA+aEWZPqchLZRZzxWIhon4LFXxl/G1RQc6hNx2aZnFYCs+ZWQxecC3t rQYaU3EXtAX8QWFPq7nBsDiqMOkfaOfsYQ== X-Received: by 2002:a1c:1707:: with SMTP id 7mr2701252wmx.150.1544540567064; Tue, 11 Dec 2018 07:02:47 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:46 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:35 +0100 Message-Id: <20181211150237.32275-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 4/6] Silicon/Styx: switch to device path protocol driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Replace the default resolution of the DevicePathLib library with the version that invokes the DevicePathDxe protocol driver, which was created to avoid having to carry a copy of the entire library in each module. Note that this driver itself incorporates on the NULL PcdLib instance, to avoid creating a circular dependency on the PCD DXE driver. The driver itself nor the DXE core can depend on the protocol, so they keep using the library directly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 9 +++++++-- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 9 +++++++-- Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 9 +++++++-- 3 files changed, 21 insertions(+), 6 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 696090cfb2dd..4b7342b3e3ce 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -63,7 +63,7 @@ DEFINE DO_CAPSULE = FALSE UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf @@ -545,12 +545,18 @@ DEFINE DO_CAPSULE = FALSE # MdeModulePkg/Core/Dxe/DxeMain.inf { + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf } MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf } + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } # # Architectural Protocols @@ -703,7 +709,6 @@ DEFINE DO_CAPSULE = FALSE # # Bds # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 5056122aa681..37daef4f82e6 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -59,7 +59,7 @@ DEFINE DO_FLASHER = FALSE UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf @@ -498,12 +498,18 @@ DEFINE DO_FLASHER = FALSE # MdeModulePkg/Core/Dxe/DxeMain.inf { + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf } MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf } + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } # # Architectural Protocols @@ -633,7 +639,6 @@ DEFINE DO_FLASHER = FALSE # # Bds # - MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 8187e799a6fc..5264346a375c 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -59,7 +59,7 @@ DEFINE DO_FLASHER = FALSE UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf - DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf @@ -482,12 +482,18 @@ DEFINE DO_FLASHER = FALSE # MdeModulePkg/Core/Dxe/DxeMain.inf { + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf } MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf } + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } # # Architectural Protocols @@ -628,7 +634,6 @@ DEFINE DO_FLASHER = FALSE # # Bds # - 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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id o192si12449825pgo.129.2018.12.11.07.03.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:03:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PQ0ue3K9; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 959112119A461; Tue, 11 Dec 2018 07:02:52 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::335; helo=mail-wm1-x335.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3E73B21199539 for ; Tue, 11 Dec 2018 07:02:51 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id s14so2570832wmh.1 for ; Tue, 11 Dec 2018 07:02:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E6dCM0IanQF9IaZ7F/j/55OM4CmXi4Ijj8w2IoMmnBk=; b=PQ0ue3K9wPj9E2t45ROfksrgQigjptwtOkSR6FItLqt9rLkqBEli/1uHSdEwVjA5wL cJlbyRCzl3EUFMwZ3qDxkSsG/saObAFZW9E9XCNLlYpEgk+kTR1wVPZqAfRe1ZWR6ZeN 7JDZRxuIV0QDWNdJn2mrzCM6JDdzr38Ls7gnQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E6dCM0IanQF9IaZ7F/j/55OM4CmXi4Ijj8w2IoMmnBk=; b=WLZDm3Cfo80TvihmwQSjXwuHcgM63UjoyiN9sjoxb4Ek1GLfd/nEobmDf8FI+qGqoR lYT5sz0C3xkAnDjCW9aEq52e9OeVY8awq9jAhO0Z1LWZcbiBOk2Xz74jpTGoIZEtXYnI g8EvtW5toLKZVjBktavKn5s+/hFsjFKTtukOHqiWr2DReES2SNWqofvI0ooMAhz1YVZ9 3n4ThtS7XNQktOUNyuXPlcxHEB67ES/mFKgpG6w80r1ifjeNta/KOFmxZ8G1EoTpFeIN FuP92qC/iin7f69TKHgYj9/maS4OEYMwSO2Z+ojZo9TyN5O2ANn1evmrBuznR2hgMivW gikw== X-Gm-Message-State: AA+aEWa7UOff0q7qRTCFK56Wn1gtnaHgQmfbGHmgxrH2kV6p1qDu+kSL C8yvcGaHTgRujLsNOMG3JcI9lvN61vqWaw== X-Received: by 2002:a1c:70b:: with SMTP id 11mr2782045wmh.74.1544540568709; Tue, 11 Dec 2018 07:02:48 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:47 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:36 +0100 Message-Id: <20181211150237.32275-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 5/6] Platform/AMD/OverdriveBoard: enable support for IPv6 networking and HTTP boot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable the various bits and pieces that implement IPv6 networking and HTTP/HTTPS boot from UEFI. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 32 ++++++++++++++------ Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 19 +++++++++--- 2 files changed, 36 insertions(+), 15 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 4b7342b3e3ce..04d655440d5b 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -128,7 +128,6 @@ DEFINE DO_CAPSULE = FALSE DisplayUpdateProgressLib|MdeModulePkg/Library/DisplayUpdateProgressLibGraphics/DisplayUpdateProgressLibGraphics.inf !if $(DO_CAPSULE) == TRUE BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf @@ -136,6 +135,11 @@ DEFINE DO_CAPSULE = FALSE PlatformFlashAccessLib|Silicon/AMD/Styx/Library/StyxPlatformFlashAccessLib/StyxPlatformFlashAccessLib.inf !endif + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf @@ -459,6 +463,8 @@ DEFINE DO_CAPSULE = FALSE # map the stack as non-executable when entering the DXE phase gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE + !if $(DO_XGBE) gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|TRUE @@ -658,23 +664,29 @@ DEFINE DO_CAPSULE = FALSE # # Networking stack # - MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf -# MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf - MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 - } + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf - NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + NetworkPkg/Ip6Dxe/Ip6Dxe.inf NetworkPkg/TcpDxe/TcpDxe.inf -## Bug https://bugs.linaro.org/show_bug.cgi?id=2239 -# NetworkPkg/IScsiDxe/IScsiDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + NetworkPkg/IScsiDxe/IScsiDxe.inf + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf + NetworkPkg/TlsDxe/TlsDxe.inf + NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf # # Core Info diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf index c7e27e20ad4a..5dcf67d819f6 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.fdf @@ -195,20 +195,29 @@ READ_LOCK_STATUS = TRUE # # Networking stack # - INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf -# INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf - INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf INF NetworkPkg/TcpDxe/TcpDxe.inf -## Bug https://bugs.linaro.org/show_bug.cgi?id=2239 -# INF NetworkPkg/IScsiDxe/IScsiDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/IScsiDxe/IScsiDxe.inf + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf + INF NetworkPkg/TlsDxe/TlsDxe.inf + INF NetworkPkg/TlsAuthConfigDxe/TlsAuthConfigDxe.inf + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf # # Core Info From patchwork Tue Dec 11 15:02:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 153474 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp716759ljp; Tue, 11 Dec 2018 07:03:10 -0800 (PST) X-Google-Smtp-Source: AFSGD/XokkRph/7/U55kgQPrs464DDpkKWfsCy83yK2K049F77dyQXxZIXGGBXdTkl/Pou8TQGRN X-Received: by 2002:a63:6ac5:: with SMTP id f188mr15000125pgc.165.1544540589918; Tue, 11 Dec 2018 07:03:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544540589; cv=none; d=google.com; s=arc-20160816; b=wDuiP9/zWWBy2spBIHl1QHHa/Gl22+uNZ+Xwsgpgt0q176u6bJFF8KD7Zd6zH7s1hH P+upyDbXW5P86BCWBtJIIV+2eOBF4QPYmtWFeIEFJ1AtdN5O0SE7kHMIgFREN7xgJGj/ Qrpkq2xlQpmOWP18vWJTZ622DQqFtYmdmKewLO63XbnZUOYfPG0c0kEWextTVEIAppX+ 4XOOaoZViKrSRznTwC8FabFICozdtMd9vVTysavWtQJVQpItRvWFfKsp2F9QHM/VgxO2 GtVjdhD5QIwwtHsox11FElE4pkfZRCrpf31rcG6PqCc1LMkIQpZVqa6YTNnvDJMWByK+ b/XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:subject:mime-version:references:in-reply-to:message-id :date:to:from:dkim-signature:delivered-to; bh=otmC0+V5H9XlleKrhG3hDnrm7ikRPw3PWyQR11YJNuo=; b=oV0/xdY493G0xqUbju+fxQCXL+Eru/s/otsmOQhuIYiBhgIW89psnfZaSfUxbKyXK9 iDuZogQbTMZRPtsUSaWkzMo4fMsrG7Z6fv+NUZX/hpPT95nf23yFfQXwQka6cMU+sPyP ogGUW6YDXMFIkJsQowKnojai1ny5iVuk+c3SiBjhGy4odNmVmjiDATSnF033Xg3ohH3D 3WRMk8oov4FzIkx23jPaIDpMjMTDC4XRjB0ewQ9cosEi+7kl0/1xf64hUKLSzKiOP4wj c6rplNVdlRw/aEUTMUXoGYhbP5auGwUlDPfj7BUaaSPI5TRMjwb8+GEfOUnNg1RMt6Ma KG8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=h6T7T5st; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id h9si13092209plb.180.2018.12.11.07.03.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:03:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=h6T7T5st; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C75012119A468; Tue, 11 Dec 2018 07:02:53 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::341; helo=mail-wm1-x341.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B5A492119A463 for ; Tue, 11 Dec 2018 07:02:52 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id s14so2570952wmh.1 for ; Tue, 11 Dec 2018 07:02:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uX/MFtY34yzjH1xeIMnGAFWHl/nXb40goBQ/ge3jsQs=; b=h6T7T5stOzJaWNQUMj7H7jOdhUj6LGxY6Wf17mIHUZnLR74o3lsCtKMwZylVGxh0uW vc27Du18oTSop10usKVZIgn9uo8n7p1OKK430rVSZNjL//duNX3ti28dPiljsh1GKkSN SGsAYsY7YL63hByMBIfh/Uy88LNfcg6vAkExg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uX/MFtY34yzjH1xeIMnGAFWHl/nXb40goBQ/ge3jsQs=; b=iVwyclv+TPOS5qG1pvXtulqDe93B04E8nKRDGS0VucPL0xPOCjU8ZKcxLDtgJ2lKy4 VpeSgF5gBcOLw0CyIQkLBohfQ27odmETmMb5RsNar2bwYDDU3MnIOpOAtbyJK5i9xY2W MAcZeUuVLWA12hSVNPh5mzpffstOyQ+SvGdOo8G4DWZPEGfEM3DRWxy4JIjWh07CwGC8 pwhs3fpJGLqc61QzNnk4UKMcTtDMsbYbPu7NQmwhnxzzpA4WST4RjSlqV2I/cEW80C+u uXQBZsvCS8/+wVisRF4gFCJlJdre4S+XiXeHLTKz4wdzkrGl2DGB8okyRjI0IlI5/Gr4 Hx+A== X-Gm-Message-State: AA+aEWZWGAzlc8DVRr6rQGp+4nmnrRtWHspTeZTyRvP2/6Q5KYXbUOqk KzRriCUbz21UUCHvy4eComoSD4dnOgnJOA== X-Received: by 2002:a1c:9692:: with SMTP id y140mr2749471wmd.67.1544540570442; Tue, 11 Dec 2018 07:02:50 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8c3:6b9d:cbc9:58c6]) by smtp.gmail.com with ESMTPSA id o9sm285793wmh.3.2018.12.11.07.02.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Dec 2018 07:02:49 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 11 Dec 2018 16:02:37 +0100 Message-Id: <20181211150237.32275-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181211150237.32275-1-ard.biesheuvel@linaro.org> References: <20181211150237.32275-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH edk2-platforms 6/6] Platform/AMD/OverdriveBoard: build device tree from source X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alan@softiron.co.uk Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of incorporating the prebuilt device tree binary as a FREEFORM FFS file into the build, define a module that contains the source so that the device tree compiler is invoked at build time. The original .dts file is moved into the new module, and cleaned up a little so that explicit phandle properties are dropped, and unused clocks and other redudant pieces are removed as well. The existing prebuilt binary is deleted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 1 + Platform/LeMaker/CelloBoard/CelloBoard.dsc | 1 + Platform/AMD/OverdriveBoard/OverdriveBoard.fdf | 10 +- Platform/LeMaker/CelloBoard/CelloBoard.fdf | 9 +- Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.inf | 28 ++++ Platform/AMD/OverdriveBoard/{FdtBlob/styx-overdrive.dts => DeviceTree/OverdriveBoard.dts} | 140 ++++++-------------- Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 9357 -> 0 bytes 7 files changed, 81 insertions(+), 108 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platform/AMD/OverdriveBoard/FdtBlob/styx-overdrive.dtb deleted file mode 100644 index c8e5fd980bce305186214aab10a7d399faa22500..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9357 zcmdT~O>7-k6`rw)A*6q4AOZx68>b{vrSMPo6pFwcq`#}(#4}ym-;d%e>`K#U!qCFXYpJ__@2FbM7^7V1BMQld1p?MBm$Ds5ad}xfF@t2T|YT2sY7j8RrH{5Pg!KMhmsiH-m1D>f)@g2B zC)A(B#<;AXkD6N65u@he-XM6Je%P=3JpPc!zt`~+r^>r970j>+rm8eAG81*zDyl_K zf5%a1ulRL-Q6>>8dFK8Flok<=P?%(^n0fiil_g0n+i)DGmeWnsi;`@ZtkO{9yhs70 z@~;m3dt2rE!CZ@b**ttMS*NVB`Gao$u?55tm9*bioTJYidIe1x7kLb>B}u_BzE8;? z=}9)xLAS`eVR3Ls@Yw+(}+P@)w!Oj3qdVBsIigokDv< z98Q7#=hcfNdF|!WT`x@2pScB@C+BV}&V7G>`KrSw{mIiRVSlVsx@_hY^NMxT$jmEc z&8wTQx7S~9zH@rl}uQ?56u3PRQpzw?M;hG0EytcUxC9zN@y@8^2#Lh8Qnb;}& z*pq!@e+3>$d&B+(SSohq70<1(bDpRzu~W9#u_lrC`4)EeZK@g+)tTN#62&V?3I&Kh zM!9zbCEjcu$4hgafG1v!`xf|d`9+)X0O}Z%bPUDE)@xzIc^KZ)ORKn>nVz(;G4_V} zRo8+UxDj&~y8U3bUOdd{T!LE=L9E$f|9RrOe3~ll4>sb`M6iW=XHMk=pmubo`Z?uB z*2dSYXNleEV878NB)<0?dyAtW#37cpe(bM8w`=Umlxdu?>(Y5`&$TCKdy#c!XXVbT zC~^EJCd<@@!6Xseb{#+*8~<~t(D=Ob;Cy0kwH(I0IKn*$8&D7z-6fuCs3+O^R22j$ zdyG{}TOZ@x+^sOulTd>ZQph<=9Dcq&4_Wc@>f_}cK5`R`vL4ZfM8EsP$QDAk#P}r4 z_Jfh0VIQ8wm80ckxrg#)*{Eq#^%6WBEOx+?XwUgNmFG!>vm&apVa*DV`bw;*a<~xA zMp}(o;r{CT7(mU$s79$Gnn1B22 z=KwBlyPw_ydguD7qc+;F0D0fzncqo2y$3m>xwCQOt}1j#{`h>;j_WwvOT{Y5c)cb zGKIQmWmwgbN#Z=}n*q+e1Qj6Ku+PUGuQK;R`c?TNc-<#~IQ$!Al0`ql4qxGQ#A6-X za^HKM0*Lo-&R_T@c+E9^Bq)IzTBl+Qb^^Q4+pJc4HyHQ{w@`<9gX42VL}Jl2x^UX+ zcGyYI8WUl{hsM|uZ`&Vp1>FvR>`U8j#_ITp(GYFgb|Z6Qo7?9bK$Bfatg-XXHthdv zD2zjy`=LIMJO!Thpip^jbDc^Q%A_|?w2seyTuLevJ7vM1B!k7yrjc#f-F4Hh!H)W9 zp>qx@Y0q{Eg@5n|>Y9(-QSZTyMZ*L9144GJ|$91B!QFXvt?5jxy z=%a@MXSW-6=!2=W$kPZ7=>$Z-*t^2()QiUInp|$VKA?^#SR3DS&?!FnpXkuf(oX-x zy$Cyc(tbP%p6%>7XRGd=jr2`p?D^fE_s-`1@Of>skC#JuKItssEs_7`rim}_aM5qY zBl|w(7M@wCnm*qJJVjmXj%TWchjI(g++D>pd-MFbGfc*b>ymN{&-`7+bJP6j{NubK z9?F8JShg}>$F--g1SQx$!B8ZIhWxNx z_;ZOrkpIIghz2@;b-#Js)1!XkYcvEoyNLum*M_b%)pL!qe=Ir{*c&FEhm3deQg|S% z{g1)(oe2x;RsRdeQ`R*|KYxO(#C)=z__-$|ca6+C$~$w7H*(OC*zPXon%f_#$@Ntc zgWwXc$n}4nJTBK4P^Wra|1WZ_V@2G|HD$@QJG&p<_t||39!PdZ>A3E8c7F+$j13Bv z*EZLoBo@k~_Stkd&g(MYyX}B zZ?h7F-}3lxd;E7CPd}iEE&PzjSu*kF#EU=u+0S2sWOYQq_htuB^z3;6A&&6WeC7E@m@FFxK+!nR9}448{48J?4-nGyjx#dguf79_U7p?sN`sLsJ_II$bdC>fGZzs<-d&$4< z7kkY==QXLFf38Ix59XgT^DkqN;9=bGEs?ds9H0EqBly$zkufi$wM|haZYqdhd9LTZ zGWAjCtb6_27`fP!C#yVR9F2W2ANEX!yW+fv>lA-P1f!1;3cTAN)WJ;L>*3b9iukU( z3TCSGigEnNcJ$#wFym>ZMQQpYuT@aSgTASPEFG+Eo+(!1K@U;$D)l~o2(T(5XE!7N zH@kqA$DRDMYi5vK4y-&}tBbWd8sMLP;Ol3@Zk$C83aHW{AH6Jox=w~GM*1f0t3c|j zpsM2<|EXK2)*D~#dVL$L%c(0w0CgP61{S z^vrsin5Fu1VFG+KU_naC-4HjqqB%;nIvOzXfFX409huq$v4%4u5T=NebkMh-#1sY} z3sk0dAIOwFQ$^iuBk|>=R{~9Kd|mNuRIQo~Uxh5hdEsk%%O; + interrupt-parent = <&gic>; #address-cells = <0x2>; #size-cells = <0x2>; - interrupt-controller@e1101000 { + gic: interrupt-controller@e1101000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <0x3>; @@ -35,15 +35,11 @@ <0x0 0xe1160000 0x0 0x2000>; interrupts = <0x1 0x9 0xf04>; ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>; - linux,phandle = <0x1>; - phandle = <0x1>; - v2m@e0080000 { + msi: v2m@e0080000 { compatible = "arm,gic-v2m-frame"; msi-controller; reg = <0x0 0x80000 0x0 0x1000>; - linux,phandle = <0x4>; - phandle = <0x4>; }; }; @@ -67,59 +63,25 @@ */ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - clk100mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - clk375mhz { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - clk333mhz { + sata_clk: clk333mhz { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <333000000>; clock-output-names = "sataclk_333mhz"; - linux,phandle = <0x2>; - phandle = <0x2>; }; - clk500mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0x0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - clk250mhz_4 { + i2c_clk: clk250mhz_4 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <250000000>; clock-output-names = "miscclk_250mhz"; - linux,phandle = <0xd>; - phandle = <0xd>; }; - clk100mhz_1 { + apb_clk: clk100mhz_1 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; clock-output-names = "uartspiclk_100mhz"; - linux,phandle = <0x3>; - phandle = <0x3>; }; sata0_smmu: smmu@e0200000 { @@ -152,7 +114,7 @@ compatible = "snps,dwc-ahci"; reg = <0x0 0xe0300000 0x0 0xf0000>; interrupts = <0x0 0x163 0x4>; - clocks = <0x2>; + clocks = <&sata_clk>; dma-coherent; iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ }; @@ -162,7 +124,7 @@ compatible = "snps,dwc-ahci"; reg = <0x0 0xe0d00000 0x0 0xf0000>; interrupts = <0x0 0x162 0x4>; - clocks = <0x2>; + clocks = <&sata_clk>; dma-coherent; iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ }; @@ -171,21 +133,21 @@ compatible = "snps,designware-i2c"; reg = <0x0 0xe1000000 0x0 0x1000>; interrupts = <0x0 0x165 0x4>; - clocks = <0xd>; + clocks = <&i2c_clk>; }; i2c@e0050000 { compatible = "snps,designware-i2c"; reg = <0x0 0xe0050000 0x0 0x1000>; interrupts = <0x0 0x154 0x4>; - clocks = <0xd>; + clocks = <&i2c_clk>; }; serial@e1010000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xe1010000 0x0 0x1000>; interrupts = <0x0 0x148 0x4>; - clocks = <0x3 0x3>; + clocks = <&apb_clk &apb_clk>; clock-names = "uartclk", "apb_pclk"; }; @@ -194,7 +156,7 @@ reg = <0x0 0xe1020000 0x0 0x1000>; spi-controller; interrupts = <0x0 0x14a 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; }; @@ -203,7 +165,7 @@ reg = <0x0 0xe1030000 0x0 0x1000>; spi-controller; interrupts = <0x0 0x149 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; num-cs = <0x1>; #address-cells = <0x1>; @@ -230,7 +192,7 @@ interrupt-controller; #interrupt-cells = <0x2>; interrupts = <0x0 0x166 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; }; @@ -243,7 +205,7 @@ interrupt-controller; #interrupt-cells = <0x2>; interrupts = <0x0 0x16e 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; }; @@ -256,7 +218,7 @@ interrupt-controller; #interrupt-cells = <0x2>; interrupts = <0x0 0x16d 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; }; @@ -268,7 +230,7 @@ interrupt-controller; #interrupt-cells = <0x2>; interrupts = <0x0 0x169 0x4>; - clocks = <0x3>; + clocks = <&apb_clk>; clock-names = "apb_pclk"; }; @@ -288,23 +250,23 @@ iommu-map = <0x0 &pcie_smmu 0x0 0x10000>; device_type = "pci"; bus-range = <0x0 0x7f>; - msi-parent = <0x4>; + msi-parent = <&msi>; reg = <0x0 0xf0000000 0x0 0x10000000>; interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, - <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, - <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, - <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, + interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x120 0x1>, + <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x121 0x1>, + <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x122 0x1>, + <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x123 0x1>, - <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, - <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, - <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, - <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, + <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x124 0x1>, + <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x125 0x1>, + <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x126 0x1>, + <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x127 0x1>, - <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, - <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, - <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, - <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; + <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x128 0x1>, + <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x129 0x1>, + <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12a 0x1>, + <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x12b 0x1>; dma-coherent; dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */ @@ -352,43 +314,35 @@ reg-spacing = <4>; }; - clk250mhz_0 { + xgmacclk0_dma: clk250mhz_0 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <250000000>; clock-output-names = "xgmacclk0_dma_250mhz"; - linux,phandle = <0x5>; - phandle = <0x5>; }; - clk250mhz_1 { + xgmacclk0_ptp: clk250mhz_1 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <250000000>; clock-output-names = "xgmacclk0_ptp_250mhz"; - linux,phandle = <0x6>; - phandle = <0x6>; }; - clk250mhz_2 { + xgmacclk1_dma: clk250mhz_2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <250000000>; clock-output-names = "xgmacclk1_dma_250mhz"; - linux,phandle = <0x7>; - phandle = <0x7>; }; - clk250mhz_3 { + xgmacclk1_ptp: clk250mhz_3 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <250000000>; clock-output-names = "xgmacclk1_ptp_250mhz"; - linux,phandle = <0x8>; - phandle = <0x8>; }; - phy@e1240800 { + xgmac0_phy: phy@e1240800 { status = "disabled"; compatible = "amd,xgbe-phy-seattle-v1a"; reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */ @@ -402,11 +356,9 @@ amd,serdes-tx-amp = <0xf 0xf 0xa>; amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0x9>; - phandle = <0x9>; }; - phy@e1240c00 { + xgmac1_phy: phy@e1240c00 { status = "disabled"; compatible = "amd,xgbe-phy-seattle-v1a"; reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */ @@ -420,8 +372,6 @@ amd,serdes-tx-amp = <0xf 0xf 0xa>; amd,serdes-dfe-tap-config = <0x3 0x3 0x1>; amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>; - linux,phandle = <0xa>; - phandle = <0xa>; }; xgmac0_smmu: smmu@e0600000 { @@ -461,14 +411,12 @@ <0x0 0x15d 0x1>; amd,per-channel-interrupt; mac-address = [02 a1 a2 a3 a4 a5]; - clocks = <0x5 0x6>; + clocks = <&xgmacclk0_dma &xgmacclk0_ptp>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0x9>; + phy-handle = <&xgmac0_phy>; phy-mode = "xgmii"; dma-coherent; iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xb>; - phandle = <0xb>; }; xgmac@e0900000 { @@ -482,25 +430,17 @@ <0x0 0x158 0x1>; amd,per-channel-interrupt; mac-address = [02 b1 b2 b3 b4 b5]; - clocks = <0x7 0x8>; + clocks = <&xgmacclk1_dma &xgmacclk1_ptp>; clock-names = "dma_clk", "ptp_clk"; - phy-handle = <0xa>; + phy-handle = <&xgmac1_phy>; phy-mode = "xgmii"; dma-coherent; iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ - linux,phandle = <0xc>; - phandle = <0xc>; }; }; chosen { stdout-path = "/smb/serial@e1010000"; - /* Note: - * Linux support for pci-probe-only DT is not - * stable. Disable this for now and let Linux - * take care of the resource assignment. - */ - // linux,pci-probe-only; }; psci {