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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id c7sm20315823wre.64.2018.12.21.07.08.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 07:08:51 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 21 Dec 2018 16:08:48 +0100 Message-Id: <20181221150848.4783-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Subject: [edk2] [PATCH] ArmPkg/ArmGicV3Dxe: use correct value for ARM_GICD_IROUTER X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Use the correct value for ARM_GICD_IROUTER as per the GIC spec, and fix the code that relies on the value being skewed by 32 x 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmGicLib.h | 2 +- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index 5775905ca91b..b52b77628ae1 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -43,7 +43,7 @@ #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register // GICv3 specific registers -#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers +#define ARM_GICD_IROUTER 0x6000 // Interrupt Routing Registers // GICD_CTLR bits #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db31713a..7d891873ba82 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -466,7 +466,7 @@ GicV3DxeInitialize ( } // Route the SPIs to the primary CPU. SPIs start at the INTID 32 - for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { + for (Index = 32; Index < mGicNumInterrupts; Index++) { MmioWrite32 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget