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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:31 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Rob Herring Subject: [PATCH v3 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Date: Sun, 1 May 2022 20:25:53 +0100 Message-Id: <20220501192557.2631936-3-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley The MPFS system controller has no registers of its own, so move it out of the soc node to avoid dtbs_check warnings: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'} Reported-by: Palmer Dabbelt Suggested-by: Rob Herring Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 746c4d4e7686..bf21a2edd180 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -146,6 +146,11 @@ refclk: mssrefclk { #clock-cells = <0>; }; + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -446,10 +451,5 @@ mbox: mailbox@37020000 { #mbox-cells = <1>; status = "disabled"; }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - mboxes = <&mbox 0>; - }; }; }; From patchwork Sun May 1 19:25:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D9E5C4332F for ; Sun, 1 May 2022 19:26:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353895AbiEATaL (ORCPT ); Sun, 1 May 2022 15:30:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352999AbiEATaD (ORCPT ); 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:32 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Sun, 1 May 2022 20:25:54 +0100 Message-Id: <20220501192557.2631936-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" / { #address-cells = <2>; From patchwork Sun May 1 19:25:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6CC1C433EF for ; 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:34 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 5/8] riscv: dts: microchip: make the fabric dtsi board specific Date: Sun, 1 May 2022 20:25:56 +0100 Message-Id: <20220501192557.2631936-6-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine currently since there is only one board with this SoC upstream. However if another board was added, it would include the fabric contents of the Icicle Kit's reference design. To avoid this, rename mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts rather than mpfs.dtsi. Signed-off-by: Conor Dooley --- .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++ arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 - 3 files changed, 3 insertions(+), 1 deletion(-) rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%) diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi similarity index 91% rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index ccaac3371cf9..0d28858b83f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { + compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs"; + core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x41000000 0x0 0xF0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 84b0015dfd47..739dfa52bed1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index cc3386068c2d..695c4e2807f5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,6 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "mpfs-fabric.dtsi" / { #address-cells = <2>; From patchwork Sun May 1 19:25:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E1B0C433EF for ; Sun, 1 May 2022 19:26:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353403AbiEATaJ (ORCPT ); Sun, 1 May 2022 15:30:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353859AbiEATaH (ORCPT ); Sun, 1 May 2022 15:30:07 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C582C2CE07 for ; Sun, 1 May 2022 12:26:39 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id e24so17192979wrc.9 for ; Sun, 01 May 2022 12:26:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rfHaik7/2US1P/NFRRn4iUnlONPLqG6WILHOUefbBUo=; b=mVdv9kcwOOIpX2quM/vp3HTG42F5lFQfkJxhE6lBERhLVc7FEwAM/Tn4kD+7r62ie8 nvlAX46+VaiPTnF/vylOd4xI+lScf0samo6C4eeA/GEJ3KrbWWyOJe7OmoW+Vwii6HqG rWf8UXEHyGB2/s4ROjXXjewRBx1w/DyfWoz+chilBzG6ESM3ictgX6QuwAPWgZtrAMQt FBKns7Y1C/TbqWVRqL+8qkARg7ZrKNKNotJc+/nTWOdUs1fWwCOXM1WFnsji800uqj9Z YYMK7gooIH4sy+NV0qHp8CYytcOcOL/cVgfLYrvALtxEAKAJgLccYTYoodR9xMVbF2ES Y6vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rfHaik7/2US1P/NFRRn4iUnlONPLqG6WILHOUefbBUo=; b=PxIx0+8kNIUB/hq0r54v5bJVy/TwriSTL9QRTTSHyyAY7SeqrfB8ohDoyivYcHl9QT eMXaQ7FQdgmCVxMnmz8LVo8iyutxJyM0LD8DbpPxMkPIhNR+wztoRNW0QdY7s5qRufpM DooCYMl/eLMO5w4W/ED0+Jb+8U8aofhk93DLduF04FSu+FE6nH7sj+oOD045UlkzSwdH 1W5+O3sNLF4Kf83q7THjUyHn8ai2b7NrVRhUixqrtYTWpnep/uUP37khrKib8F7JlkXy fPQIGVa//Vc5zyinMSpR1nVOhvzkQJEE5suoJMWFr9t0SCvqyeSpIOU6U4uVb/oMzjuf 5Yog== X-Gm-Message-State: AOAM532kwR6gjZBZv7If8LNCmByMbIEFwdeYlCaU3SLRgzHmeqE9HfOc mM0qP7qc1XCRfpv2oiyd4HsMDQ== X-Google-Smtp-Source: ABdhPJx2i0mes1PmcgvFU5xWJ4TRUZY/DT1oIlVE5UY3f+NAzTWLdIkcmmjjxXaExuxvVcYoCFsCag== X-Received: by 2002:a5d:5012:0:b0:20a:d9a9:44dc with SMTP id e18-20020a5d5012000000b0020ad9a944dcmr7113624wrt.627.1651433198331; Sun, 01 May 2022 12:26:38 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id i14-20020adfa50e000000b0020c5253d8c6sm6448105wrb.18.2022.05.01.12.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 12:26:37 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v3 8/8] riscv: dts: microchip: add the sundance polarberry Date: Sun, 1 May 2022 20:25:59 +0100 Message-Id: <20220501192557.2631936-9-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220501192557.2631936-1-mail@conchuod.ie> References: <20220501192557.2631936-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..96ec589d1571 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Sundance PolarBerry"; + compatible = "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + ethernet0 = &mac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + status = "okay"; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; +}; + +&mac0 { + status = "disabled"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&rtc { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +};